if_ale.c revision 217542
1/*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/ale/if_ale.c 217542 2011-01-18 16:27:40Z jhb $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/kernel.h> 38#include <sys/malloc.h> 39#include <sys/mbuf.h> 40#include <sys/module.h> 41#include <sys/rman.h> 42#include <sys/queue.h> 43#include <sys/socket.h> 44#include <sys/sockio.h> 45#include <sys/sysctl.h> 46#include <sys/taskqueue.h> 47 48#include <net/bpf.h> 49#include <net/if.h> 50#include <net/if_arp.h> 51#include <net/ethernet.h> 52#include <net/if_dl.h> 53#include <net/if_llc.h> 54#include <net/if_media.h> 55#include <net/if_types.h> 56#include <net/if_vlan_var.h> 57 58#include <netinet/in.h> 59#include <netinet/in_systm.h> 60#include <netinet/ip.h> 61#include <netinet/tcp.h> 62 63#include <dev/mii/mii.h> 64#include <dev/mii/miivar.h> 65 66#include <dev/pci/pcireg.h> 67#include <dev/pci/pcivar.h> 68 69#include <machine/bus.h> 70#include <machine/in_cksum.h> 71 72#include <dev/ale/if_alereg.h> 73#include <dev/ale/if_alevar.h> 74 75/* "device miibus" required. See GENERIC if you get errors here. */ 76#include "miibus_if.h" 77 78/* For more information about Tx checksum offload issues see ale_encap(). */ 79#define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 80 81MODULE_DEPEND(ale, pci, 1, 1, 1); 82MODULE_DEPEND(ale, ether, 1, 1, 1); 83MODULE_DEPEND(ale, miibus, 1, 1, 1); 84 85/* Tunables. */ 86static int msi_disable = 0; 87static int msix_disable = 0; 88TUNABLE_INT("hw.ale.msi_disable", &msi_disable); 89TUNABLE_INT("hw.ale.msix_disable", &msix_disable); 90 91/* 92 * Devices supported by this driver. 93 */ 94static struct ale_dev { 95 uint16_t ale_vendorid; 96 uint16_t ale_deviceid; 97 const char *ale_name; 98} ale_devs[] = { 99 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX, 100 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" }, 101}; 102 103static int ale_attach(device_t); 104static int ale_check_boundary(struct ale_softc *); 105static int ale_detach(device_t); 106static int ale_dma_alloc(struct ale_softc *); 107static void ale_dma_free(struct ale_softc *); 108static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int); 109static int ale_encap(struct ale_softc *, struct mbuf **); 110static void ale_get_macaddr(struct ale_softc *); 111static void ale_init(void *); 112static void ale_init_locked(struct ale_softc *); 113static void ale_init_rx_pages(struct ale_softc *); 114static void ale_init_tx_ring(struct ale_softc *); 115static void ale_int_task(void *, int); 116static int ale_intr(void *); 117static int ale_ioctl(struct ifnet *, u_long, caddr_t); 118static void ale_link_task(void *, int); 119static void ale_mac_config(struct ale_softc *); 120static int ale_miibus_readreg(device_t, int, int); 121static void ale_miibus_statchg(device_t); 122static int ale_miibus_writereg(device_t, int, int, int); 123static int ale_mediachange(struct ifnet *); 124static void ale_mediastatus(struct ifnet *, struct ifmediareq *); 125static void ale_phy_reset(struct ale_softc *); 126static int ale_probe(device_t); 127static void ale_reset(struct ale_softc *); 128static int ale_resume(device_t); 129static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 130 uint32_t, uint32_t *); 131static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 132static int ale_rxeof(struct ale_softc *sc, int); 133static void ale_rxfilter(struct ale_softc *); 134static void ale_rxvlan(struct ale_softc *); 135static void ale_setlinkspeed(struct ale_softc *); 136static void ale_setwol(struct ale_softc *); 137static int ale_shutdown(device_t); 138static void ale_start(struct ifnet *); 139static void ale_start_locked(struct ifnet *); 140static void ale_stats_clear(struct ale_softc *); 141static void ale_stats_update(struct ale_softc *); 142static void ale_stop(struct ale_softc *); 143static void ale_stop_mac(struct ale_softc *); 144static int ale_suspend(device_t); 145static void ale_sysctl_node(struct ale_softc *); 146static void ale_tick(void *); 147static void ale_txeof(struct ale_softc *); 148static void ale_watchdog(struct ale_softc *); 149static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 150static int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS); 151static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS); 152 153static device_method_t ale_methods[] = { 154 /* Device interface. */ 155 DEVMETHOD(device_probe, ale_probe), 156 DEVMETHOD(device_attach, ale_attach), 157 DEVMETHOD(device_detach, ale_detach), 158 DEVMETHOD(device_shutdown, ale_shutdown), 159 DEVMETHOD(device_suspend, ale_suspend), 160 DEVMETHOD(device_resume, ale_resume), 161 162 /* MII interface. */ 163 DEVMETHOD(miibus_readreg, ale_miibus_readreg), 164 DEVMETHOD(miibus_writereg, ale_miibus_writereg), 165 DEVMETHOD(miibus_statchg, ale_miibus_statchg), 166 167 { NULL, NULL } 168}; 169 170static driver_t ale_driver = { 171 "ale", 172 ale_methods, 173 sizeof(struct ale_softc) 174}; 175 176static devclass_t ale_devclass; 177 178DRIVER_MODULE(ale, pci, ale_driver, ale_devclass, 0, 0); 179DRIVER_MODULE(miibus, ale, miibus_driver, miibus_devclass, 0, 0); 180 181static struct resource_spec ale_res_spec_mem[] = { 182 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 183 { -1, 0, 0 } 184}; 185 186static struct resource_spec ale_irq_spec_legacy[] = { 187 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 188 { -1, 0, 0 } 189}; 190 191static struct resource_spec ale_irq_spec_msi[] = { 192 { SYS_RES_IRQ, 1, RF_ACTIVE }, 193 { -1, 0, 0 } 194}; 195 196static struct resource_spec ale_irq_spec_msix[] = { 197 { SYS_RES_IRQ, 1, RF_ACTIVE }, 198 { -1, 0, 0 } 199}; 200 201static int 202ale_miibus_readreg(device_t dev, int phy, int reg) 203{ 204 struct ale_softc *sc; 205 uint32_t v; 206 int i; 207 208 sc = device_get_softc(dev); 209 210 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 211 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 212 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 213 DELAY(5); 214 v = CSR_READ_4(sc, ALE_MDIO); 215 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 216 break; 217 } 218 219 if (i == 0) { 220 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg); 221 return (0); 222 } 223 224 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 225} 226 227static int 228ale_miibus_writereg(device_t dev, int phy, int reg, int val) 229{ 230 struct ale_softc *sc; 231 uint32_t v; 232 int i; 233 234 sc = device_get_softc(dev); 235 236 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 237 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 238 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 239 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 240 DELAY(5); 241 v = CSR_READ_4(sc, ALE_MDIO); 242 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 243 break; 244 } 245 246 if (i == 0) 247 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg); 248 249 return (0); 250} 251 252static void 253ale_miibus_statchg(device_t dev) 254{ 255 struct ale_softc *sc; 256 257 sc = device_get_softc(dev); 258 259 taskqueue_enqueue(taskqueue_swi, &sc->ale_link_task); 260} 261 262static void 263ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 264{ 265 struct ale_softc *sc; 266 struct mii_data *mii; 267 268 sc = ifp->if_softc; 269 ALE_LOCK(sc); 270 mii = device_get_softc(sc->ale_miibus); 271 272 mii_pollstat(mii); 273 ALE_UNLOCK(sc); 274 ifmr->ifm_status = mii->mii_media_status; 275 ifmr->ifm_active = mii->mii_media_active; 276} 277 278static int 279ale_mediachange(struct ifnet *ifp) 280{ 281 struct ale_softc *sc; 282 struct mii_data *mii; 283 struct mii_softc *miisc; 284 int error; 285 286 sc = ifp->if_softc; 287 ALE_LOCK(sc); 288 mii = device_get_softc(sc->ale_miibus); 289 if (mii->mii_instance != 0) { 290 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 291 mii_phy_reset(miisc); 292 } 293 error = mii_mediachg(mii); 294 ALE_UNLOCK(sc); 295 296 return (error); 297} 298 299static int 300ale_probe(device_t dev) 301{ 302 struct ale_dev *sp; 303 int i; 304 uint16_t vendor, devid; 305 306 vendor = pci_get_vendor(dev); 307 devid = pci_get_device(dev); 308 sp = ale_devs; 309 for (i = 0; i < sizeof(ale_devs) / sizeof(ale_devs[0]); i++) { 310 if (vendor == sp->ale_vendorid && 311 devid == sp->ale_deviceid) { 312 device_set_desc(dev, sp->ale_name); 313 return (BUS_PROBE_DEFAULT); 314 } 315 sp++; 316 } 317 318 return (ENXIO); 319} 320 321static void 322ale_get_macaddr(struct ale_softc *sc) 323{ 324 uint32_t ea[2], reg; 325 int i, vpdc; 326 327 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 328 if ((reg & SPI_VPD_ENB) != 0) { 329 reg &= ~SPI_VPD_ENB; 330 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 331 } 332 333 if (pci_find_extcap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) { 334 /* 335 * PCI VPD capability found, let TWSI reload EEPROM. 336 * This will set ethernet address of controller. 337 */ 338 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 339 TWSI_CTRL_SW_LD_START); 340 for (i = 100; i > 0; i--) { 341 DELAY(1000); 342 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 343 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 344 break; 345 } 346 if (i == 0) 347 device_printf(sc->ale_dev, 348 "reloading EEPROM timeout!\n"); 349 } else { 350 if (bootverbose) 351 device_printf(sc->ale_dev, 352 "PCI VPD capability not found!\n"); 353 } 354 355 ea[0] = CSR_READ_4(sc, ALE_PAR0); 356 ea[1] = CSR_READ_4(sc, ALE_PAR1); 357 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 358 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 359 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 360 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 361 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 362 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 363} 364 365static void 366ale_phy_reset(struct ale_softc *sc) 367{ 368 369 /* Reset magic from Linux. */ 370 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 371 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 372 GPHY_CTRL_PHY_PLL_ON); 373 DELAY(1000); 374 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 375 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 376 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 377 DELAY(1000); 378 379#define ATPHY_DBG_ADDR 0x1D 380#define ATPHY_DBG_DATA 0x1E 381 382 /* Enable hibernation mode. */ 383 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 384 ATPHY_DBG_ADDR, 0x0B); 385 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 386 ATPHY_DBG_DATA, 0xBC00); 387 /* Set Class A/B for all modes. */ 388 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 389 ATPHY_DBG_ADDR, 0x00); 390 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 391 ATPHY_DBG_DATA, 0x02EF); 392 /* Enable 10BT power saving. */ 393 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 394 ATPHY_DBG_ADDR, 0x12); 395 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 396 ATPHY_DBG_DATA, 0x4C04); 397 /* Adjust 1000T power. */ 398 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 399 ATPHY_DBG_ADDR, 0x04); 400 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 401 ATPHY_DBG_ADDR, 0x8BBB); 402 /* 10BT center tap voltage. */ 403 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 404 ATPHY_DBG_ADDR, 0x05); 405 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 406 ATPHY_DBG_ADDR, 0x2C46); 407 408#undef ATPHY_DBG_ADDR 409#undef ATPHY_DBG_DATA 410 DELAY(1000); 411} 412 413static int 414ale_attach(device_t dev) 415{ 416 struct ale_softc *sc; 417 struct ifnet *ifp; 418 uint16_t burst; 419 int error, i, msic, msixc, pmc; 420 uint32_t rxf_len, txf_len; 421 422 error = 0; 423 sc = device_get_softc(dev); 424 sc->ale_dev = dev; 425 426 mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 427 MTX_DEF); 428 callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0); 429 TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc); 430 TASK_INIT(&sc->ale_link_task, 0, ale_link_task, sc); 431 432 /* Map the device. */ 433 pci_enable_busmaster(dev); 434 sc->ale_res_spec = ale_res_spec_mem; 435 sc->ale_irq_spec = ale_irq_spec_legacy; 436 error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res); 437 if (error != 0) { 438 device_printf(dev, "cannot allocate memory resources.\n"); 439 goto fail; 440 } 441 442 /* Set PHY address. */ 443 sc->ale_phyaddr = ALE_PHY_ADDR; 444 445 /* Reset PHY. */ 446 ale_phy_reset(sc); 447 448 /* Reset the ethernet controller. */ 449 ale_reset(sc); 450 451 /* Get PCI and chip id/revision. */ 452 sc->ale_rev = pci_get_revid(dev); 453 if (sc->ale_rev >= 0xF0) { 454 /* L2E Rev. B. AR8114 */ 455 sc->ale_flags |= ALE_FLAG_FASTETHER; 456 } else { 457 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 458 /* L1E AR8121 */ 459 sc->ale_flags |= ALE_FLAG_JUMBO; 460 } else { 461 /* L2E Rev. A. AR8113 */ 462 sc->ale_flags |= ALE_FLAG_FASTETHER; 463 } 464 } 465 /* 466 * All known controllers seems to require 4 bytes alignment 467 * of Tx buffers to make Tx checksum offload with custom 468 * checksum generation method work. 469 */ 470 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 471 /* 472 * All known controllers seems to have issues on Rx checksum 473 * offload for fragmented IP datagrams. 474 */ 475 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 476 /* 477 * Don't use Tx CMB. It is known to cause RRS update failure 478 * under certain circumstances. Typical phenomenon of the 479 * issue would be unexpected sequence number encountered in 480 * Rx handler. 481 */ 482 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 483 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 484 MASTER_CHIP_REV_SHIFT; 485 if (bootverbose) { 486 device_printf(dev, "PCI device revision : 0x%04x\n", 487 sc->ale_rev); 488 device_printf(dev, "Chip id/revision : 0x%04x\n", 489 sc->ale_chip_rev); 490 } 491 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 492 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 493 /* 494 * Uninitialized hardware returns an invalid chip id/revision 495 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 496 */ 497 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 498 rxf_len == 0xFFFFFFF) { 499 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO " 500 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev, 501 txf_len, rxf_len); 502 error = ENXIO; 503 goto fail; 504 } 505 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len); 506 507 /* Allocate IRQ resources. */ 508 msixc = pci_msix_count(dev); 509 msic = pci_msi_count(dev); 510 if (bootverbose) { 511 device_printf(dev, "MSIX count : %d\n", msixc); 512 device_printf(dev, "MSI count : %d\n", msic); 513 } 514 515 /* Prefer MSIX over MSI. */ 516 if (msix_disable == 0 || msi_disable == 0) { 517 if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES && 518 pci_alloc_msix(dev, &msixc) == 0) { 519 if (msic == ALE_MSIX_MESSAGES) { 520 device_printf(dev, "Using %d MSIX messages.\n", 521 msixc); 522 sc->ale_flags |= ALE_FLAG_MSIX; 523 sc->ale_irq_spec = ale_irq_spec_msix; 524 } else 525 pci_release_msi(dev); 526 } 527 if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 && 528 msic == ALE_MSI_MESSAGES && 529 pci_alloc_msi(dev, &msic) == 0) { 530 if (msic == ALE_MSI_MESSAGES) { 531 device_printf(dev, "Using %d MSI messages.\n", 532 msic); 533 sc->ale_flags |= ALE_FLAG_MSI; 534 sc->ale_irq_spec = ale_irq_spec_msi; 535 } else 536 pci_release_msi(dev); 537 } 538 } 539 540 error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq); 541 if (error != 0) { 542 device_printf(dev, "cannot allocate IRQ resources.\n"); 543 goto fail; 544 } 545 546 /* Get DMA parameters from PCIe device control register. */ 547 if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) { 548 sc->ale_flags |= ALE_FLAG_PCIE; 549 burst = pci_read_config(dev, i + 0x08, 2); 550 /* Max read request size. */ 551 sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) << 552 DMA_CFG_RD_BURST_SHIFT; 553 /* Max payload size. */ 554 sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) << 555 DMA_CFG_WR_BURST_SHIFT; 556 if (bootverbose) { 557 device_printf(dev, "Read request size : %d bytes.\n", 558 128 << ((burst >> 12) & 0x07)); 559 device_printf(dev, "TLP payload size : %d bytes.\n", 560 128 << ((burst >> 5) & 0x07)); 561 } 562 } else { 563 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 564 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 565 } 566 567 /* Create device sysctl node. */ 568 ale_sysctl_node(sc); 569 570 if ((error = ale_dma_alloc(sc) != 0)) 571 goto fail; 572 573 /* Load station address. */ 574 ale_get_macaddr(sc); 575 576 ifp = sc->ale_ifp = if_alloc(IFT_ETHER); 577 if (ifp == NULL) { 578 device_printf(dev, "cannot allocate ifnet structure.\n"); 579 error = ENXIO; 580 goto fail; 581 } 582 583 ifp->if_softc = sc; 584 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 585 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 586 ifp->if_ioctl = ale_ioctl; 587 ifp->if_start = ale_start; 588 ifp->if_init = ale_init; 589 ifp->if_snd.ifq_drv_maxlen = ALE_TX_RING_CNT - 1; 590 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 591 IFQ_SET_READY(&ifp->if_snd); 592 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4; 593 ifp->if_hwassist = ALE_CSUM_FEATURES | CSUM_TSO; 594 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) { 595 sc->ale_flags |= ALE_FLAG_PMCAP; 596 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 597 } 598 ifp->if_capenable = ifp->if_capabilities; 599 600 /* Set up MII bus. */ 601 error = mii_attach(dev, &sc->ale_miibus, ifp, ale_mediachange, 602 ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY, 603 0); 604 if (error != 0) { 605 device_printf(dev, "attaching PHYs failed\n"); 606 goto fail; 607 } 608 609 ether_ifattach(ifp, sc->ale_eaddr); 610 611 /* VLAN capability setup. */ 612 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 613 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 614 ifp->if_capenable = ifp->if_capabilities; 615 /* 616 * Even though controllers supported by ale(3) have Rx checksum 617 * offload bug the workaround for fragmented frames seemed to 618 * work so far. However it seems Rx checksum offload does not 619 * work under certain conditions. So disable Rx checksum offload 620 * until I find more clue about it but allow users to override it. 621 */ 622 ifp->if_capenable &= ~IFCAP_RXCSUM; 623 624 /* Tell the upper layer(s) we support long frames. */ 625 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 626 627 /* Create local taskq. */ 628 sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK, 629 taskqueue_thread_enqueue, &sc->ale_tq); 630 if (sc->ale_tq == NULL) { 631 device_printf(dev, "could not create taskqueue.\n"); 632 ether_ifdetach(ifp); 633 error = ENXIO; 634 goto fail; 635 } 636 taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq", 637 device_get_nameunit(sc->ale_dev)); 638 639 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 640 msic = ALE_MSIX_MESSAGES; 641 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 642 msic = ALE_MSI_MESSAGES; 643 else 644 msic = 1; 645 for (i = 0; i < msic; i++) { 646 error = bus_setup_intr(dev, sc->ale_irq[i], 647 INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc, 648 &sc->ale_intrhand[i]); 649 if (error != 0) 650 break; 651 } 652 if (error != 0) { 653 device_printf(dev, "could not set up interrupt handler.\n"); 654 taskqueue_free(sc->ale_tq); 655 sc->ale_tq = NULL; 656 ether_ifdetach(ifp); 657 goto fail; 658 } 659 660fail: 661 if (error != 0) 662 ale_detach(dev); 663 664 return (error); 665} 666 667static int 668ale_detach(device_t dev) 669{ 670 struct ale_softc *sc; 671 struct ifnet *ifp; 672 int i, msic; 673 674 sc = device_get_softc(dev); 675 676 ifp = sc->ale_ifp; 677 if (device_is_attached(dev)) { 678 ether_ifdetach(ifp); 679 ALE_LOCK(sc); 680 ale_stop(sc); 681 ALE_UNLOCK(sc); 682 callout_drain(&sc->ale_tick_ch); 683 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 684 taskqueue_drain(taskqueue_swi, &sc->ale_link_task); 685 } 686 687 if (sc->ale_tq != NULL) { 688 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 689 taskqueue_free(sc->ale_tq); 690 sc->ale_tq = NULL; 691 } 692 693 if (sc->ale_miibus != NULL) { 694 device_delete_child(dev, sc->ale_miibus); 695 sc->ale_miibus = NULL; 696 } 697 bus_generic_detach(dev); 698 ale_dma_free(sc); 699 700 if (ifp != NULL) { 701 if_free(ifp); 702 sc->ale_ifp = NULL; 703 } 704 705 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 706 msic = ALE_MSIX_MESSAGES; 707 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 708 msic = ALE_MSI_MESSAGES; 709 else 710 msic = 1; 711 for (i = 0; i < msic; i++) { 712 if (sc->ale_intrhand[i] != NULL) { 713 bus_teardown_intr(dev, sc->ale_irq[i], 714 sc->ale_intrhand[i]); 715 sc->ale_intrhand[i] = NULL; 716 } 717 } 718 719 bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq); 720 if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0) 721 pci_release_msi(dev); 722 bus_release_resources(dev, sc->ale_res_spec, sc->ale_res); 723 mtx_destroy(&sc->ale_mtx); 724 725 return (0); 726} 727 728#define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 729 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 730 731#if __FreeBSD_version >= 900030 732#define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 733 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 734#elif __FreeBSD_version > 800000 735#define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 736 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 737#else 738#define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 739 SYSCTL_ADD_ULONG(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 740#endif 741 742static void 743ale_sysctl_node(struct ale_softc *sc) 744{ 745 struct sysctl_ctx_list *ctx; 746 struct sysctl_oid_list *child, *parent; 747 struct sysctl_oid *tree; 748 struct ale_hw_stats *stats; 749 int error; 750 751 stats = &sc->ale_stats; 752 ctx = device_get_sysctl_ctx(sc->ale_dev); 753 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev)); 754 755 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 756 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_rx_mod, 0, 757 sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation"); 758 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 759 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_tx_mod, 0, 760 sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation"); 761 /* Pull in device tunables. */ 762 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 763 error = resource_int_value(device_get_name(sc->ale_dev), 764 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod); 765 if (error == 0) { 766 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN || 767 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) { 768 device_printf(sc->ale_dev, "int_rx_mod value out of " 769 "range; using default: %d\n", 770 ALE_IM_RX_TIMER_DEFAULT); 771 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 772 } 773 } 774 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 775 error = resource_int_value(device_get_name(sc->ale_dev), 776 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod); 777 if (error == 0) { 778 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN || 779 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) { 780 device_printf(sc->ale_dev, "int_tx_mod value out of " 781 "range; using default: %d\n", 782 ALE_IM_TX_TIMER_DEFAULT); 783 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 784 } 785 } 786 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 787 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_process_limit, 0, 788 sysctl_hw_ale_proc_limit, "I", 789 "max number of Rx events to process"); 790 /* Pull in device tunables. */ 791 sc->ale_process_limit = ALE_PROC_DEFAULT; 792 error = resource_int_value(device_get_name(sc->ale_dev), 793 device_get_unit(sc->ale_dev), "process_limit", 794 &sc->ale_process_limit); 795 if (error == 0) { 796 if (sc->ale_process_limit < ALE_PROC_MIN || 797 sc->ale_process_limit > ALE_PROC_MAX) { 798 device_printf(sc->ale_dev, 799 "process_limit value out of range; " 800 "using default: %d\n", ALE_PROC_DEFAULT); 801 sc->ale_process_limit = ALE_PROC_DEFAULT; 802 } 803 } 804 805 /* Misc statistics. */ 806 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq", 807 &stats->reset_brk_seq, 808 "Controller resets due to broken Rx sequnce number"); 809 810 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 811 NULL, "ATE statistics"); 812 parent = SYSCTL_CHILDREN(tree); 813 814 /* Rx statistics. */ 815 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 816 NULL, "Rx MAC statistics"); 817 child = SYSCTL_CHILDREN(tree); 818 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 819 &stats->rx_frames, "Good frames"); 820 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 821 &stats->rx_bcast_frames, "Good broadcast frames"); 822 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 823 &stats->rx_mcast_frames, "Good multicast frames"); 824 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 825 &stats->rx_pause_frames, "Pause control frames"); 826 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 827 &stats->rx_control_frames, "Control frames"); 828 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 829 &stats->rx_crcerrs, "CRC errors"); 830 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 831 &stats->rx_lenerrs, "Frames with length mismatched"); 832 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 833 &stats->rx_bytes, "Good octets"); 834 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 835 &stats->rx_bcast_bytes, "Good broadcast octets"); 836 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 837 &stats->rx_mcast_bytes, "Good multicast octets"); 838 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts", 839 &stats->rx_runts, "Too short frames"); 840 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments", 841 &stats->rx_fragments, "Fragmented frames"); 842 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 843 &stats->rx_pkts_64, "64 bytes frames"); 844 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 845 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 846 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 847 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 848 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 849 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 850 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 851 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 852 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 853 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 854 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 855 &stats->rx_pkts_1519_max, "1519 to max frames"); 856 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 857 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 858 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 859 &stats->rx_fifo_oflows, "FIFO overflows"); 860 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 861 &stats->rx_rrs_errs, "Return status write-back errors"); 862 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 863 &stats->rx_alignerrs, "Alignment errors"); 864 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered", 865 &stats->rx_pkts_filtered, 866 "Frames dropped due to address filtering"); 867 868 /* Tx statistics. */ 869 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 870 NULL, "Tx MAC statistics"); 871 child = SYSCTL_CHILDREN(tree); 872 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 873 &stats->tx_frames, "Good frames"); 874 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 875 &stats->tx_bcast_frames, "Good broadcast frames"); 876 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 877 &stats->tx_mcast_frames, "Good multicast frames"); 878 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 879 &stats->tx_pause_frames, "Pause control frames"); 880 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 881 &stats->tx_control_frames, "Control frames"); 882 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 883 &stats->tx_excess_defer, "Frames with excessive derferrals"); 884 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers", 885 &stats->tx_excess_defer, "Frames with derferrals"); 886 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 887 &stats->tx_bytes, "Good octets"); 888 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 889 &stats->tx_bcast_bytes, "Good broadcast octets"); 890 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 891 &stats->tx_mcast_bytes, "Good multicast octets"); 892 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 893 &stats->tx_pkts_64, "64 bytes frames"); 894 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 895 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 896 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 897 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 898 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 899 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 900 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 901 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 902 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 903 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 904 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 905 &stats->tx_pkts_1519_max, "1519 to max frames"); 906 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 907 &stats->tx_single_colls, "Single collisions"); 908 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 909 &stats->tx_multi_colls, "Multiple collisions"); 910 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 911 &stats->tx_late_colls, "Late collisions"); 912 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 913 &stats->tx_excess_colls, "Excessive collisions"); 914 ALE_SYSCTL_STAT_ADD32(ctx, child, "abort", 915 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 916 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns", 917 &stats->tx_underrun, "FIFO underruns"); 918 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 919 &stats->tx_desc_underrun, "Descriptor write-back errors"); 920 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 921 &stats->tx_lenerrs, "Frames with length mismatched"); 922 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 923 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 924} 925 926#undef ALE_SYSCTL_STAT_ADD32 927#undef ALE_SYSCTL_STAT_ADD64 928 929struct ale_dmamap_arg { 930 bus_addr_t ale_busaddr; 931}; 932 933static void 934ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 935{ 936 struct ale_dmamap_arg *ctx; 937 938 if (error != 0) 939 return; 940 941 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 942 943 ctx = (struct ale_dmamap_arg *)arg; 944 ctx->ale_busaddr = segs[0].ds_addr; 945} 946 947/* 948 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register 949 * which specifies high address region of DMA blocks. Therefore these 950 * blocks should have the same high address of given 4GB address 951 * space(i.e. crossing 4GB boundary is not allowed). 952 */ 953static int 954ale_check_boundary(struct ale_softc *sc) 955{ 956 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end; 957 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end; 958 959 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr + 960 sc->ale_pagesize; 961 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr + 962 sc->ale_pagesize; 963 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ; 964 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ; 965 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ; 966 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ; 967 968 if ((ALE_ADDR_HI(tx_ring_end) != 969 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) || 970 (ALE_ADDR_HI(rx_page_end[0]) != 971 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) || 972 (ALE_ADDR_HI(rx_page_end[1]) != 973 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) || 974 (ALE_ADDR_HI(tx_cmb_end) != 975 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) || 976 (ALE_ADDR_HI(rx_cmb_end[0]) != 977 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) || 978 (ALE_ADDR_HI(rx_cmb_end[1]) != 979 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr))) 980 return (EFBIG); 981 982 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) || 983 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) || 984 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) || 985 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) || 986 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end))) 987 return (EFBIG); 988 989 return (0); 990} 991 992static int 993ale_dma_alloc(struct ale_softc *sc) 994{ 995 struct ale_txdesc *txd; 996 bus_addr_t lowaddr; 997 struct ale_dmamap_arg ctx; 998 int error, guard_size, i; 999 1000 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 1001 guard_size = ALE_JUMBO_FRAMELEN; 1002 else 1003 guard_size = ALE_MAX_FRAMELEN; 1004 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 1005 ALE_RX_PAGE_ALIGN); 1006 lowaddr = BUS_SPACE_MAXADDR; 1007again: 1008 /* Create parent DMA tag. */ 1009 error = bus_dma_tag_create( 1010 bus_get_dma_tag(sc->ale_dev), /* parent */ 1011 1, 0, /* alignment, boundary */ 1012 lowaddr, /* lowaddr */ 1013 BUS_SPACE_MAXADDR, /* highaddr */ 1014 NULL, NULL, /* filter, filterarg */ 1015 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1016 0, /* nsegments */ 1017 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1018 0, /* flags */ 1019 NULL, NULL, /* lockfunc, lockarg */ 1020 &sc->ale_cdata.ale_parent_tag); 1021 if (error != 0) { 1022 device_printf(sc->ale_dev, 1023 "could not create parent DMA tag.\n"); 1024 goto fail; 1025 } 1026 1027 /* Create DMA tag for Tx descriptor ring. */ 1028 error = bus_dma_tag_create( 1029 sc->ale_cdata.ale_parent_tag, /* parent */ 1030 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */ 1031 BUS_SPACE_MAXADDR, /* lowaddr */ 1032 BUS_SPACE_MAXADDR, /* highaddr */ 1033 NULL, NULL, /* filter, filterarg */ 1034 ALE_TX_RING_SZ, /* maxsize */ 1035 1, /* nsegments */ 1036 ALE_TX_RING_SZ, /* maxsegsize */ 1037 0, /* flags */ 1038 NULL, NULL, /* lockfunc, lockarg */ 1039 &sc->ale_cdata.ale_tx_ring_tag); 1040 if (error != 0) { 1041 device_printf(sc->ale_dev, 1042 "could not create Tx ring DMA tag.\n"); 1043 goto fail; 1044 } 1045 1046 /* Create DMA tag for Rx pages. */ 1047 for (i = 0; i < ALE_RX_PAGES; i++) { 1048 error = bus_dma_tag_create( 1049 sc->ale_cdata.ale_parent_tag, /* parent */ 1050 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */ 1051 BUS_SPACE_MAXADDR, /* lowaddr */ 1052 BUS_SPACE_MAXADDR, /* highaddr */ 1053 NULL, NULL, /* filter, filterarg */ 1054 sc->ale_pagesize, /* maxsize */ 1055 1, /* nsegments */ 1056 sc->ale_pagesize, /* maxsegsize */ 1057 0, /* flags */ 1058 NULL, NULL, /* lockfunc, lockarg */ 1059 &sc->ale_cdata.ale_rx_page[i].page_tag); 1060 if (error != 0) { 1061 device_printf(sc->ale_dev, 1062 "could not create Rx page %d DMA tag.\n", i); 1063 goto fail; 1064 } 1065 } 1066 1067 /* Create DMA tag for Tx coalescing message block. */ 1068 error = bus_dma_tag_create( 1069 sc->ale_cdata.ale_parent_tag, /* parent */ 1070 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1071 BUS_SPACE_MAXADDR, /* lowaddr */ 1072 BUS_SPACE_MAXADDR, /* highaddr */ 1073 NULL, NULL, /* filter, filterarg */ 1074 ALE_TX_CMB_SZ, /* maxsize */ 1075 1, /* nsegments */ 1076 ALE_TX_CMB_SZ, /* maxsegsize */ 1077 0, /* flags */ 1078 NULL, NULL, /* lockfunc, lockarg */ 1079 &sc->ale_cdata.ale_tx_cmb_tag); 1080 if (error != 0) { 1081 device_printf(sc->ale_dev, 1082 "could not create Tx CMB DMA tag.\n"); 1083 goto fail; 1084 } 1085 1086 /* Create DMA tag for Rx coalescing message block. */ 1087 for (i = 0; i < ALE_RX_PAGES; i++) { 1088 error = bus_dma_tag_create( 1089 sc->ale_cdata.ale_parent_tag, /* parent */ 1090 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1091 BUS_SPACE_MAXADDR, /* lowaddr */ 1092 BUS_SPACE_MAXADDR, /* highaddr */ 1093 NULL, NULL, /* filter, filterarg */ 1094 ALE_RX_CMB_SZ, /* maxsize */ 1095 1, /* nsegments */ 1096 ALE_RX_CMB_SZ, /* maxsegsize */ 1097 0, /* flags */ 1098 NULL, NULL, /* lockfunc, lockarg */ 1099 &sc->ale_cdata.ale_rx_page[i].cmb_tag); 1100 if (error != 0) { 1101 device_printf(sc->ale_dev, 1102 "could not create Rx page %d CMB DMA tag.\n", i); 1103 goto fail; 1104 } 1105 } 1106 1107 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1108 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag, 1109 (void **)&sc->ale_cdata.ale_tx_ring, 1110 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1111 &sc->ale_cdata.ale_tx_ring_map); 1112 if (error != 0) { 1113 device_printf(sc->ale_dev, 1114 "could not allocate DMA'able memory for Tx ring.\n"); 1115 goto fail; 1116 } 1117 ctx.ale_busaddr = 0; 1118 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag, 1119 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring, 1120 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0); 1121 if (error != 0 || ctx.ale_busaddr == 0) { 1122 device_printf(sc->ale_dev, 1123 "could not load DMA'able memory for Tx ring.\n"); 1124 goto fail; 1125 } 1126 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr; 1127 1128 /* Rx pages. */ 1129 for (i = 0; i < ALE_RX_PAGES; i++) { 1130 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag, 1131 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 1132 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1133 &sc->ale_cdata.ale_rx_page[i].page_map); 1134 if (error != 0) { 1135 device_printf(sc->ale_dev, 1136 "could not allocate DMA'able memory for " 1137 "Rx page %d.\n", i); 1138 goto fail; 1139 } 1140 ctx.ale_busaddr = 0; 1141 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag, 1142 sc->ale_cdata.ale_rx_page[i].page_map, 1143 sc->ale_cdata.ale_rx_page[i].page_addr, 1144 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0); 1145 if (error != 0 || ctx.ale_busaddr == 0) { 1146 device_printf(sc->ale_dev, 1147 "could not load DMA'able memory for " 1148 "Rx page %d.\n", i); 1149 goto fail; 1150 } 1151 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr; 1152 } 1153 1154 /* Tx CMB. */ 1155 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag, 1156 (void **)&sc->ale_cdata.ale_tx_cmb, 1157 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1158 &sc->ale_cdata.ale_tx_cmb_map); 1159 if (error != 0) { 1160 device_printf(sc->ale_dev, 1161 "could not allocate DMA'able memory for Tx CMB.\n"); 1162 goto fail; 1163 } 1164 ctx.ale_busaddr = 0; 1165 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag, 1166 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb, 1167 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1168 if (error != 0 || ctx.ale_busaddr == 0) { 1169 device_printf(sc->ale_dev, 1170 "could not load DMA'able memory for Tx CMB.\n"); 1171 goto fail; 1172 } 1173 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr; 1174 1175 /* Rx CMB. */ 1176 for (i = 0; i < ALE_RX_PAGES; i++) { 1177 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1178 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 1179 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1180 &sc->ale_cdata.ale_rx_page[i].cmb_map); 1181 if (error != 0) { 1182 device_printf(sc->ale_dev, "could not allocate " 1183 "DMA'able memory for Rx page %d CMB.\n", i); 1184 goto fail; 1185 } 1186 ctx.ale_busaddr = 0; 1187 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1188 sc->ale_cdata.ale_rx_page[i].cmb_map, 1189 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1190 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1191 if (error != 0 || ctx.ale_busaddr == 0) { 1192 device_printf(sc->ale_dev, "could not load DMA'able " 1193 "memory for Rx page %d CMB.\n", i); 1194 goto fail; 1195 } 1196 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr; 1197 } 1198 1199 /* 1200 * Tx descriptors/RXF0/CMB DMA blocks share the same 1201 * high address region of 64bit DMA address space. 1202 */ 1203 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1204 (error = ale_check_boundary(sc)) != 0) { 1205 device_printf(sc->ale_dev, "4GB boundary crossed, " 1206 "switching to 32bit DMA addressing mode.\n"); 1207 ale_dma_free(sc); 1208 /* 1209 * Limit max allowable DMA address space to 32bit 1210 * and try again. 1211 */ 1212 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1213 goto again; 1214 } 1215 1216 /* 1217 * Create Tx buffer parent tag. 1218 * AR81xx allows 64bit DMA addressing of Tx buffers so it 1219 * needs separate parent DMA tag as parent DMA address space 1220 * could be restricted to be within 32bit address space by 1221 * 4GB boundary crossing. 1222 */ 1223 error = bus_dma_tag_create( 1224 bus_get_dma_tag(sc->ale_dev), /* parent */ 1225 1, 0, /* alignment, boundary */ 1226 BUS_SPACE_MAXADDR, /* lowaddr */ 1227 BUS_SPACE_MAXADDR, /* highaddr */ 1228 NULL, NULL, /* filter, filterarg */ 1229 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1230 0, /* nsegments */ 1231 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1232 0, /* flags */ 1233 NULL, NULL, /* lockfunc, lockarg */ 1234 &sc->ale_cdata.ale_buffer_tag); 1235 if (error != 0) { 1236 device_printf(sc->ale_dev, 1237 "could not create parent buffer DMA tag.\n"); 1238 goto fail; 1239 } 1240 1241 /* Create DMA tag for Tx buffers. */ 1242 error = bus_dma_tag_create( 1243 sc->ale_cdata.ale_buffer_tag, /* parent */ 1244 1, 0, /* alignment, boundary */ 1245 BUS_SPACE_MAXADDR, /* lowaddr */ 1246 BUS_SPACE_MAXADDR, /* highaddr */ 1247 NULL, NULL, /* filter, filterarg */ 1248 ALE_TSO_MAXSIZE, /* maxsize */ 1249 ALE_MAXTXSEGS, /* nsegments */ 1250 ALE_TSO_MAXSEGSIZE, /* maxsegsize */ 1251 0, /* flags */ 1252 NULL, NULL, /* lockfunc, lockarg */ 1253 &sc->ale_cdata.ale_tx_tag); 1254 if (error != 0) { 1255 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n"); 1256 goto fail; 1257 } 1258 1259 /* Create DMA maps for Tx buffers. */ 1260 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1261 txd = &sc->ale_cdata.ale_txdesc[i]; 1262 txd->tx_m = NULL; 1263 txd->tx_dmamap = NULL; 1264 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0, 1265 &txd->tx_dmamap); 1266 if (error != 0) { 1267 device_printf(sc->ale_dev, 1268 "could not create Tx dmamap.\n"); 1269 goto fail; 1270 } 1271 } 1272 1273fail: 1274 return (error); 1275} 1276 1277static void 1278ale_dma_free(struct ale_softc *sc) 1279{ 1280 struct ale_txdesc *txd; 1281 int i; 1282 1283 /* Tx buffers. */ 1284 if (sc->ale_cdata.ale_tx_tag != NULL) { 1285 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1286 txd = &sc->ale_cdata.ale_txdesc[i]; 1287 if (txd->tx_dmamap != NULL) { 1288 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag, 1289 txd->tx_dmamap); 1290 txd->tx_dmamap = NULL; 1291 } 1292 } 1293 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag); 1294 sc->ale_cdata.ale_tx_tag = NULL; 1295 } 1296 /* Tx descriptor ring. */ 1297 if (sc->ale_cdata.ale_tx_ring_tag != NULL) { 1298 if (sc->ale_cdata.ale_tx_ring_map != NULL) 1299 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag, 1300 sc->ale_cdata.ale_tx_ring_map); 1301 if (sc->ale_cdata.ale_tx_ring_map != NULL && 1302 sc->ale_cdata.ale_tx_ring != NULL) 1303 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag, 1304 sc->ale_cdata.ale_tx_ring, 1305 sc->ale_cdata.ale_tx_ring_map); 1306 sc->ale_cdata.ale_tx_ring = NULL; 1307 sc->ale_cdata.ale_tx_ring_map = NULL; 1308 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag); 1309 sc->ale_cdata.ale_tx_ring_tag = NULL; 1310 } 1311 /* Rx page block. */ 1312 for (i = 0; i < ALE_RX_PAGES; i++) { 1313 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) { 1314 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL) 1315 bus_dmamap_unload( 1316 sc->ale_cdata.ale_rx_page[i].page_tag, 1317 sc->ale_cdata.ale_rx_page[i].page_map); 1318 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL && 1319 sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 1320 bus_dmamem_free( 1321 sc->ale_cdata.ale_rx_page[i].page_tag, 1322 sc->ale_cdata.ale_rx_page[i].page_addr, 1323 sc->ale_cdata.ale_rx_page[i].page_map); 1324 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 1325 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 1326 bus_dma_tag_destroy( 1327 sc->ale_cdata.ale_rx_page[i].page_tag); 1328 sc->ale_cdata.ale_rx_page[i].page_tag = NULL; 1329 } 1330 } 1331 /* Rx CMB. */ 1332 for (i = 0; i < ALE_RX_PAGES; i++) { 1333 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) { 1334 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL) 1335 bus_dmamap_unload( 1336 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1337 sc->ale_cdata.ale_rx_page[i].cmb_map); 1338 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL && 1339 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 1340 bus_dmamem_free( 1341 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1342 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1343 sc->ale_cdata.ale_rx_page[i].cmb_map); 1344 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 1345 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 1346 bus_dma_tag_destroy( 1347 sc->ale_cdata.ale_rx_page[i].cmb_tag); 1348 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL; 1349 } 1350 } 1351 /* Tx CMB. */ 1352 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) { 1353 if (sc->ale_cdata.ale_tx_cmb_map != NULL) 1354 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag, 1355 sc->ale_cdata.ale_tx_cmb_map); 1356 if (sc->ale_cdata.ale_tx_cmb_map != NULL && 1357 sc->ale_cdata.ale_tx_cmb != NULL) 1358 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag, 1359 sc->ale_cdata.ale_tx_cmb, 1360 sc->ale_cdata.ale_tx_cmb_map); 1361 sc->ale_cdata.ale_tx_cmb = NULL; 1362 sc->ale_cdata.ale_tx_cmb_map = NULL; 1363 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag); 1364 sc->ale_cdata.ale_tx_cmb_tag = NULL; 1365 } 1366 if (sc->ale_cdata.ale_buffer_tag != NULL) { 1367 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag); 1368 sc->ale_cdata.ale_buffer_tag = NULL; 1369 } 1370 if (sc->ale_cdata.ale_parent_tag != NULL) { 1371 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag); 1372 sc->ale_cdata.ale_parent_tag = NULL; 1373 } 1374} 1375 1376static int 1377ale_shutdown(device_t dev) 1378{ 1379 1380 return (ale_suspend(dev)); 1381} 1382 1383/* 1384 * Note, this driver resets the link speed to 10/100Mbps by 1385 * restarting auto-negotiation in suspend/shutdown phase but we 1386 * don't know whether that auto-negotiation would succeed or not 1387 * as driver has no control after powering off/suspend operation. 1388 * If the renegotiation fail WOL may not work. Running at 1Gbps 1389 * will draw more power than 375mA at 3.3V which is specified in 1390 * PCI specification and that would result in complete 1391 * shutdowning power to ethernet controller. 1392 * 1393 * TODO 1394 * Save current negotiated media speed/duplex/flow-control to 1395 * softc and restore the same link again after resuming. PHY 1396 * handling such as power down/resetting to 100Mbps may be better 1397 * handled in suspend method in phy driver. 1398 */ 1399static void 1400ale_setlinkspeed(struct ale_softc *sc) 1401{ 1402 struct mii_data *mii; 1403 int aneg, i; 1404 1405 mii = device_get_softc(sc->ale_miibus); 1406 mii_pollstat(mii); 1407 aneg = 0; 1408 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1409 (IFM_ACTIVE | IFM_AVALID)) { 1410 switch IFM_SUBTYPE(mii->mii_media_active) { 1411 case IFM_10_T: 1412 case IFM_100_TX: 1413 return; 1414 case IFM_1000_T: 1415 aneg++; 1416 break; 1417 default: 1418 break; 1419 } 1420 } 1421 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0); 1422 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1423 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1424 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1425 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1426 DELAY(1000); 1427 if (aneg != 0) { 1428 /* 1429 * Poll link state until ale(4) get a 10/100Mbps link. 1430 */ 1431 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1432 mii_pollstat(mii); 1433 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1434 == (IFM_ACTIVE | IFM_AVALID)) { 1435 switch (IFM_SUBTYPE( 1436 mii->mii_media_active)) { 1437 case IFM_10_T: 1438 case IFM_100_TX: 1439 ale_mac_config(sc); 1440 return; 1441 default: 1442 break; 1443 } 1444 } 1445 ALE_UNLOCK(sc); 1446 pause("alelnk", hz); 1447 ALE_LOCK(sc); 1448 } 1449 if (i == MII_ANEGTICKS_GIGE) 1450 device_printf(sc->ale_dev, 1451 "establishing a link failed, WOL may not work!"); 1452 } 1453 /* 1454 * No link, force MAC to have 100Mbps, full-duplex link. 1455 * This is the last resort and may/may not work. 1456 */ 1457 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1458 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1459 ale_mac_config(sc); 1460} 1461 1462static void 1463ale_setwol(struct ale_softc *sc) 1464{ 1465 struct ifnet *ifp; 1466 uint32_t reg, pmcs; 1467 uint16_t pmstat; 1468 int pmc; 1469 1470 ALE_LOCK_ASSERT(sc); 1471 1472 if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) != 0) { 1473 /* Disable WOL. */ 1474 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1475 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1476 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1477 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1478 /* Force PHY power down. */ 1479 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1480 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1481 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON | 1482 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ | 1483 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW); 1484 return; 1485 } 1486 1487 ifp = sc->ale_ifp; 1488 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1489 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 1490 ale_setlinkspeed(sc); 1491 } 1492 1493 pmcs = 0; 1494 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1495 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1496 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs); 1497 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1498 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1499 MAC_CFG_BCAST); 1500 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1501 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1502 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1503 reg |= MAC_CFG_RX_ENB; 1504 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1505 1506 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1507 /* WOL disabled, PHY power down. */ 1508 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1509 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1510 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1511 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1512 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1513 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 1514 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS | 1515 GPHY_CTRL_PWDOWN_HW); 1516 } 1517 /* Request PME. */ 1518 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2); 1519 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1520 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1521 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1522 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1523} 1524 1525static int 1526ale_suspend(device_t dev) 1527{ 1528 struct ale_softc *sc; 1529 1530 sc = device_get_softc(dev); 1531 1532 ALE_LOCK(sc); 1533 ale_stop(sc); 1534 ale_setwol(sc); 1535 ALE_UNLOCK(sc); 1536 1537 return (0); 1538} 1539 1540static int 1541ale_resume(device_t dev) 1542{ 1543 struct ale_softc *sc; 1544 struct ifnet *ifp; 1545 int pmc; 1546 uint16_t pmstat; 1547 1548 sc = device_get_softc(dev); 1549 1550 ALE_LOCK(sc); 1551 if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) == 0) { 1552 /* Disable PME and clear PME status. */ 1553 pmstat = pci_read_config(sc->ale_dev, 1554 pmc + PCIR_POWER_STATUS, 2); 1555 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1556 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1557 pci_write_config(sc->ale_dev, 1558 pmc + PCIR_POWER_STATUS, pmstat, 2); 1559 } 1560 } 1561 /* Reset PHY. */ 1562 ale_phy_reset(sc); 1563 ifp = sc->ale_ifp; 1564 if ((ifp->if_flags & IFF_UP) != 0) { 1565 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1566 ale_init_locked(sc); 1567 } 1568 ALE_UNLOCK(sc); 1569 1570 return (0); 1571} 1572 1573static int 1574ale_encap(struct ale_softc *sc, struct mbuf **m_head) 1575{ 1576 struct ale_txdesc *txd, *txd_last; 1577 struct tx_desc *desc; 1578 struct mbuf *m; 1579 struct ip *ip; 1580 struct tcphdr *tcp; 1581 bus_dma_segment_t txsegs[ALE_MAXTXSEGS]; 1582 bus_dmamap_t map; 1583 uint32_t cflags, hdrlen, ip_off, poff, vtag; 1584 int error, i, nsegs, prod, si; 1585 1586 ALE_LOCK_ASSERT(sc); 1587 1588 M_ASSERTPKTHDR((*m_head)); 1589 1590 m = *m_head; 1591 ip = NULL; 1592 tcp = NULL; 1593 cflags = vtag = 0; 1594 ip_off = poff = 0; 1595 if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1596 /* 1597 * AR81xx requires offset of TCP/UDP payload in its Tx 1598 * descriptor to perform hardware Tx checksum offload. 1599 * Additionally, TSO requires IP/TCP header size and 1600 * modification of IP/TCP header in order to make TSO 1601 * engine work. This kind of operation takes many CPU 1602 * cycles on FreeBSD so fast host CPU is required to 1603 * get smooth TSO performance. 1604 */ 1605 struct ether_header *eh; 1606 1607 if (M_WRITABLE(m) == 0) { 1608 /* Get a writable copy. */ 1609 m = m_dup(*m_head, M_DONTWAIT); 1610 /* Release original mbufs. */ 1611 m_freem(*m_head); 1612 if (m == NULL) { 1613 *m_head = NULL; 1614 return (ENOBUFS); 1615 } 1616 *m_head = m; 1617 } 1618 1619 /* 1620 * Buggy-controller requires 4 byte aligned Tx buffer 1621 * to make custom checksum offload work. 1622 */ 1623 if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 && 1624 (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 && 1625 (mtod(m, intptr_t) & 3) != 0) { 1626 m = m_defrag(*m_head, M_DONTWAIT); 1627 if (m == NULL) { 1628 *m_head = NULL; 1629 return (ENOBUFS); 1630 } 1631 *m_head = m; 1632 } 1633 1634 ip_off = sizeof(struct ether_header); 1635 m = m_pullup(m, ip_off); 1636 if (m == NULL) { 1637 *m_head = NULL; 1638 return (ENOBUFS); 1639 } 1640 eh = mtod(m, struct ether_header *); 1641 /* 1642 * Check if hardware VLAN insertion is off. 1643 * Additional check for LLC/SNAP frame? 1644 */ 1645 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1646 ip_off = sizeof(struct ether_vlan_header); 1647 m = m_pullup(m, ip_off); 1648 if (m == NULL) { 1649 *m_head = NULL; 1650 return (ENOBUFS); 1651 } 1652 } 1653 m = m_pullup(m, ip_off + sizeof(struct ip)); 1654 if (m == NULL) { 1655 *m_head = NULL; 1656 return (ENOBUFS); 1657 } 1658 ip = (struct ip *)(mtod(m, char *) + ip_off); 1659 poff = ip_off + (ip->ip_hl << 2); 1660 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1661 /* 1662 * XXX 1663 * AR81xx requires the first descriptor should 1664 * not include any TCP playload for TSO case. 1665 * (i.e. ethernet header + IP + TCP header only) 1666 * m_pullup(9) above will ensure this too. 1667 * However it's not correct if the first mbuf 1668 * of the chain does not use cluster. 1669 */ 1670 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1671 if (m == NULL) { 1672 *m_head = NULL; 1673 return (ENOBUFS); 1674 } 1675 ip = (struct ip *)(mtod(m, char *) + ip_off); 1676 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1677 m = m_pullup(m, poff + (tcp->th_off << 2)); 1678 if (m == NULL) { 1679 *m_head = NULL; 1680 return (ENOBUFS); 1681 } 1682 /* 1683 * AR81xx requires IP/TCP header size and offset as 1684 * well as TCP pseudo checksum which complicates 1685 * TSO configuration. I guess this comes from the 1686 * adherence to Microsoft NDIS Large Send 1687 * specification which requires insertion of 1688 * pseudo checksum by upper stack. The pseudo 1689 * checksum that NDIS refers to doesn't include 1690 * TCP payload length so ale(4) should recompute 1691 * the pseudo checksum here. Hopefully this wouldn't 1692 * be much burden on modern CPUs. 1693 * Reset IP checksum and recompute TCP pseudo 1694 * checksum as NDIS specification said. 1695 */ 1696 ip->ip_sum = 0; 1697 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1698 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1699 } 1700 *m_head = m; 1701 } 1702 1703 si = prod = sc->ale_cdata.ale_tx_prod; 1704 txd = &sc->ale_cdata.ale_txdesc[prod]; 1705 txd_last = txd; 1706 map = txd->tx_dmamap; 1707 1708 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1709 *m_head, txsegs, &nsegs, 0); 1710 if (error == EFBIG) { 1711 m = m_collapse(*m_head, M_DONTWAIT, ALE_MAXTXSEGS); 1712 if (m == NULL) { 1713 m_freem(*m_head); 1714 *m_head = NULL; 1715 return (ENOMEM); 1716 } 1717 *m_head = m; 1718 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1719 *m_head, txsegs, &nsegs, 0); 1720 if (error != 0) { 1721 m_freem(*m_head); 1722 *m_head = NULL; 1723 return (error); 1724 } 1725 } else if (error != 0) 1726 return (error); 1727 if (nsegs == 0) { 1728 m_freem(*m_head); 1729 *m_head = NULL; 1730 return (EIO); 1731 } 1732 1733 /* Check descriptor overrun. */ 1734 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 3) { 1735 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map); 1736 return (ENOBUFS); 1737 } 1738 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE); 1739 1740 m = *m_head; 1741 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1742 /* Request TSO and set MSS. */ 1743 cflags |= ALE_TD_TSO; 1744 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT); 1745 /* Set IP/TCP header size. */ 1746 cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT; 1747 cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT; 1748 } else if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 1749 /* 1750 * AR81xx supports Tx custom checksum offload feature 1751 * that offloads single 16bit checksum computation. 1752 * So you can choose one among IP, TCP and UDP. 1753 * Normally driver sets checksum start/insertion 1754 * position from the information of TCP/UDP frame as 1755 * TCP/UDP checksum takes more time than that of IP. 1756 * However it seems that custom checksum offload 1757 * requires 4 bytes aligned Tx buffers due to hardware 1758 * bug. 1759 * AR81xx also supports explicit Tx checksum computation 1760 * if it is told that the size of IP header and TCP 1761 * header(for UDP, the header size does not matter 1762 * because it's fixed length). However with this scheme 1763 * TSO does not work so you have to choose one either 1764 * TSO or explicit Tx checksum offload. I chosen TSO 1765 * plus custom checksum offload with work-around which 1766 * will cover most common usage for this consumer 1767 * ethernet controller. The work-around takes a lot of 1768 * CPU cycles if Tx buffer is not aligned on 4 bytes 1769 * boundary, though. 1770 */ 1771 cflags |= ALE_TD_CXSUM; 1772 /* Set checksum start offset. */ 1773 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 1774 /* Set checksum insertion position of TCP/UDP. */ 1775 cflags |= ((poff + m->m_pkthdr.csum_data) << 1776 ALE_TD_CSUM_XSUMOFFSET_SHIFT); 1777 } 1778 1779 /* Configure VLAN hardware tag insertion. */ 1780 if ((m->m_flags & M_VLANTAG) != 0) { 1781 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1782 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1783 cflags |= ALE_TD_INSERT_VLAN_TAG; 1784 } 1785 1786 i = 0; 1787 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1788 /* 1789 * Make sure the first fragment contains 1790 * only ethernet and IP/TCP header with options. 1791 */ 1792 hdrlen = poff + (tcp->th_off << 2); 1793 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1794 desc->addr = htole64(txsegs[i].ds_addr); 1795 desc->len = htole32(ALE_TX_BYTES(hdrlen) | vtag); 1796 desc->flags = htole32(cflags); 1797 sc->ale_cdata.ale_tx_cnt++; 1798 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1799 if (m->m_len - hdrlen > 0) { 1800 /* Handle remaining payload of the first fragment. */ 1801 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1802 desc->addr = htole64(txsegs[i].ds_addr + hdrlen); 1803 desc->len = htole32(ALE_TX_BYTES(m->m_len - hdrlen) | 1804 vtag); 1805 desc->flags = htole32(cflags); 1806 sc->ale_cdata.ale_tx_cnt++; 1807 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1808 } 1809 i = 1; 1810 } 1811 for (; i < nsegs; i++) { 1812 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1813 desc->addr = htole64(txsegs[i].ds_addr); 1814 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag); 1815 desc->flags = htole32(cflags); 1816 sc->ale_cdata.ale_tx_cnt++; 1817 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1818 } 1819 /* Update producer index. */ 1820 sc->ale_cdata.ale_tx_prod = prod; 1821 /* Set TSO header on the first descriptor. */ 1822 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1823 desc = &sc->ale_cdata.ale_tx_ring[si]; 1824 desc->flags |= htole32(ALE_TD_TSO_HDR); 1825 } 1826 1827 /* Finally set EOP on the last descriptor. */ 1828 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1829 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1830 desc->flags |= htole32(ALE_TD_EOP); 1831 1832 /* Swap dmamap of the first and the last. */ 1833 txd = &sc->ale_cdata.ale_txdesc[prod]; 1834 map = txd_last->tx_dmamap; 1835 txd_last->tx_dmamap = txd->tx_dmamap; 1836 txd->tx_dmamap = map; 1837 txd->tx_m = m; 1838 1839 /* Sync descriptors. */ 1840 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 1841 sc->ale_cdata.ale_tx_ring_map, 1842 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1843 1844 return (0); 1845} 1846 1847static void 1848ale_start(struct ifnet *ifp) 1849{ 1850 struct ale_softc *sc; 1851 1852 sc = ifp->if_softc; 1853 ALE_LOCK(sc); 1854 ale_start_locked(ifp); 1855 ALE_UNLOCK(sc); 1856} 1857 1858static void 1859ale_start_locked(struct ifnet *ifp) 1860{ 1861 struct ale_softc *sc; 1862 struct mbuf *m_head; 1863 int enq; 1864 1865 sc = ifp->if_softc; 1866 1867 ALE_LOCK_ASSERT(sc); 1868 1869 /* Reclaim transmitted frames. */ 1870 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1871 ale_txeof(sc); 1872 1873 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1874 IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0) 1875 return; 1876 1877 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1878 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1879 if (m_head == NULL) 1880 break; 1881 /* 1882 * Pack the data into the transmit ring. If we 1883 * don't have room, set the OACTIVE flag and wait 1884 * for the NIC to drain the ring. 1885 */ 1886 if (ale_encap(sc, &m_head)) { 1887 if (m_head == NULL) 1888 break; 1889 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1890 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1891 break; 1892 } 1893 1894 enq++; 1895 /* 1896 * If there's a BPF listener, bounce a copy of this frame 1897 * to him. 1898 */ 1899 ETHER_BPF_MTAP(ifp, m_head); 1900 } 1901 1902 if (enq > 0) { 1903 /* Kick. */ 1904 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1905 sc->ale_cdata.ale_tx_prod); 1906 /* Set a timeout in case the chip goes out to lunch. */ 1907 sc->ale_watchdog_timer = ALE_TX_TIMEOUT; 1908 } 1909} 1910 1911static void 1912ale_watchdog(struct ale_softc *sc) 1913{ 1914 struct ifnet *ifp; 1915 1916 ALE_LOCK_ASSERT(sc); 1917 1918 if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer) 1919 return; 1920 1921 ifp = sc->ale_ifp; 1922 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1923 if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n"); 1924 ifp->if_oerrors++; 1925 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1926 ale_init_locked(sc); 1927 return; 1928 } 1929 if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n"); 1930 ifp->if_oerrors++; 1931 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1932 ale_init_locked(sc); 1933 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1934 ale_start_locked(ifp); 1935} 1936 1937static int 1938ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1939{ 1940 struct ale_softc *sc; 1941 struct ifreq *ifr; 1942 struct mii_data *mii; 1943 int error, mask; 1944 1945 sc = ifp->if_softc; 1946 ifr = (struct ifreq *)data; 1947 error = 0; 1948 switch (cmd) { 1949 case SIOCSIFMTU: 1950 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU || 1951 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 && 1952 ifr->ifr_mtu > ETHERMTU)) 1953 error = EINVAL; 1954 else if (ifp->if_mtu != ifr->ifr_mtu) { 1955 ALE_LOCK(sc); 1956 ifp->if_mtu = ifr->ifr_mtu; 1957 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1958 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1959 ale_init_locked(sc); 1960 } 1961 ALE_UNLOCK(sc); 1962 } 1963 break; 1964 case SIOCSIFFLAGS: 1965 ALE_LOCK(sc); 1966 if ((ifp->if_flags & IFF_UP) != 0) { 1967 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1968 if (((ifp->if_flags ^ sc->ale_if_flags) 1969 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1970 ale_rxfilter(sc); 1971 } else { 1972 ale_init_locked(sc); 1973 } 1974 } else { 1975 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1976 ale_stop(sc); 1977 } 1978 sc->ale_if_flags = ifp->if_flags; 1979 ALE_UNLOCK(sc); 1980 break; 1981 case SIOCADDMULTI: 1982 case SIOCDELMULTI: 1983 ALE_LOCK(sc); 1984 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1985 ale_rxfilter(sc); 1986 ALE_UNLOCK(sc); 1987 break; 1988 case SIOCSIFMEDIA: 1989 case SIOCGIFMEDIA: 1990 mii = device_get_softc(sc->ale_miibus); 1991 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1992 break; 1993 case SIOCSIFCAP: 1994 ALE_LOCK(sc); 1995 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1996 if ((mask & IFCAP_TXCSUM) != 0 && 1997 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1998 ifp->if_capenable ^= IFCAP_TXCSUM; 1999 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2000 ifp->if_hwassist |= ALE_CSUM_FEATURES; 2001 else 2002 ifp->if_hwassist &= ~ALE_CSUM_FEATURES; 2003 } 2004 if ((mask & IFCAP_RXCSUM) != 0 && 2005 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 2006 ifp->if_capenable ^= IFCAP_RXCSUM; 2007 if ((mask & IFCAP_TSO4) != 0 && 2008 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2009 ifp->if_capenable ^= IFCAP_TSO4; 2010 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 2011 ifp->if_hwassist |= CSUM_TSO; 2012 else 2013 ifp->if_hwassist &= ~CSUM_TSO; 2014 } 2015 2016 if ((mask & IFCAP_WOL_MCAST) != 0 && 2017 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 2018 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2019 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2020 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2021 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2022 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2023 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2024 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2025 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2026 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2027 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2028 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2029 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2030 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2031 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2032 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 2033 ale_rxvlan(sc); 2034 } 2035 ALE_UNLOCK(sc); 2036 VLAN_CAPABILITIES(ifp); 2037 break; 2038 default: 2039 error = ether_ioctl(ifp, cmd, data); 2040 break; 2041 } 2042 2043 return (error); 2044} 2045 2046static void 2047ale_mac_config(struct ale_softc *sc) 2048{ 2049 struct mii_data *mii; 2050 uint32_t reg; 2051 2052 ALE_LOCK_ASSERT(sc); 2053 2054 mii = device_get_softc(sc->ale_miibus); 2055 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2056 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2057 MAC_CFG_SPEED_MASK); 2058 /* Reprogram MAC with resolved speed/duplex. */ 2059 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2060 case IFM_10_T: 2061 case IFM_100_TX: 2062 reg |= MAC_CFG_SPEED_10_100; 2063 break; 2064 case IFM_1000_T: 2065 reg |= MAC_CFG_SPEED_1000; 2066 break; 2067 } 2068 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2069 reg |= MAC_CFG_FULL_DUPLEX; 2070#ifdef notyet 2071 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2072 reg |= MAC_CFG_TX_FC; 2073 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2074 reg |= MAC_CFG_RX_FC; 2075#endif 2076 } 2077 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2078} 2079 2080static void 2081ale_link_task(void *arg, int pending) 2082{ 2083 struct ale_softc *sc; 2084 struct mii_data *mii; 2085 struct ifnet *ifp; 2086 uint32_t reg; 2087 2088 sc = (struct ale_softc *)arg; 2089 2090 ALE_LOCK(sc); 2091 mii = device_get_softc(sc->ale_miibus); 2092 ifp = sc->ale_ifp; 2093 if (mii == NULL || ifp == NULL || 2094 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2095 ALE_UNLOCK(sc); 2096 return; 2097 } 2098 2099 sc->ale_flags &= ~ALE_FLAG_LINK; 2100 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 2101 (IFM_ACTIVE | IFM_AVALID)) { 2102 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2103 case IFM_10_T: 2104 case IFM_100_TX: 2105 sc->ale_flags |= ALE_FLAG_LINK; 2106 break; 2107 case IFM_1000_T: 2108 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 2109 sc->ale_flags |= ALE_FLAG_LINK; 2110 break; 2111 default: 2112 break; 2113 } 2114 } 2115 2116 /* Stop Rx/Tx MACs. */ 2117 ale_stop_mac(sc); 2118 2119 /* Program MACs with resolved speed/duplex/flow-control. */ 2120 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 2121 ale_mac_config(sc); 2122 /* Reenable Tx/Rx MACs. */ 2123 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2124 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 2125 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2126 } 2127 2128 ALE_UNLOCK(sc); 2129} 2130 2131static void 2132ale_stats_clear(struct ale_softc *sc) 2133{ 2134 struct smb sb; 2135 uint32_t *reg; 2136 int i; 2137 2138 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2139 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2140 i += sizeof(uint32_t); 2141 } 2142 /* Read Tx statistics. */ 2143 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2144 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2145 i += sizeof(uint32_t); 2146 } 2147} 2148 2149static void 2150ale_stats_update(struct ale_softc *sc) 2151{ 2152 struct ale_hw_stats *stat; 2153 struct smb sb, *smb; 2154 struct ifnet *ifp; 2155 uint32_t *reg; 2156 int i; 2157 2158 ALE_LOCK_ASSERT(sc); 2159 2160 ifp = sc->ale_ifp; 2161 stat = &sc->ale_stats; 2162 smb = &sb; 2163 2164 /* Read Rx statistics. */ 2165 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2166 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2167 i += sizeof(uint32_t); 2168 } 2169 /* Read Tx statistics. */ 2170 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2171 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2172 i += sizeof(uint32_t); 2173 } 2174 2175 /* Rx stats. */ 2176 stat->rx_frames += smb->rx_frames; 2177 stat->rx_bcast_frames += smb->rx_bcast_frames; 2178 stat->rx_mcast_frames += smb->rx_mcast_frames; 2179 stat->rx_pause_frames += smb->rx_pause_frames; 2180 stat->rx_control_frames += smb->rx_control_frames; 2181 stat->rx_crcerrs += smb->rx_crcerrs; 2182 stat->rx_lenerrs += smb->rx_lenerrs; 2183 stat->rx_bytes += smb->rx_bytes; 2184 stat->rx_runts += smb->rx_runts; 2185 stat->rx_fragments += smb->rx_fragments; 2186 stat->rx_pkts_64 += smb->rx_pkts_64; 2187 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2188 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2189 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2190 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2191 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2192 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2193 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2194 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2195 stat->rx_rrs_errs += smb->rx_rrs_errs; 2196 stat->rx_alignerrs += smb->rx_alignerrs; 2197 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2198 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2199 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2200 2201 /* Tx stats. */ 2202 stat->tx_frames += smb->tx_frames; 2203 stat->tx_bcast_frames += smb->tx_bcast_frames; 2204 stat->tx_mcast_frames += smb->tx_mcast_frames; 2205 stat->tx_pause_frames += smb->tx_pause_frames; 2206 stat->tx_excess_defer += smb->tx_excess_defer; 2207 stat->tx_control_frames += smb->tx_control_frames; 2208 stat->tx_deferred += smb->tx_deferred; 2209 stat->tx_bytes += smb->tx_bytes; 2210 stat->tx_pkts_64 += smb->tx_pkts_64; 2211 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2212 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2213 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2214 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2215 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2216 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2217 stat->tx_single_colls += smb->tx_single_colls; 2218 stat->tx_multi_colls += smb->tx_multi_colls; 2219 stat->tx_late_colls += smb->tx_late_colls; 2220 stat->tx_excess_colls += smb->tx_excess_colls; 2221 stat->tx_abort += smb->tx_abort; 2222 stat->tx_underrun += smb->tx_underrun; 2223 stat->tx_desc_underrun += smb->tx_desc_underrun; 2224 stat->tx_lenerrs += smb->tx_lenerrs; 2225 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2226 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2227 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2228 2229 /* Update counters in ifnet. */ 2230 ifp->if_opackets += smb->tx_frames; 2231 2232 ifp->if_collisions += smb->tx_single_colls + 2233 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2234 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 2235 2236 /* 2237 * XXX 2238 * tx_pkts_truncated counter looks suspicious. It constantly 2239 * increments with no sign of Tx errors. This may indicate 2240 * the counter name is not correct one so I've removed the 2241 * counter in output errors. 2242 */ 2243 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 2244 smb->tx_underrun; 2245 2246 ifp->if_ipackets += smb->rx_frames; 2247 2248 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2249 smb->rx_runts + smb->rx_pkts_truncated + 2250 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2251 smb->rx_alignerrs; 2252} 2253 2254static int 2255ale_intr(void *arg) 2256{ 2257 struct ale_softc *sc; 2258 uint32_t status; 2259 2260 sc = (struct ale_softc *)arg; 2261 2262 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2263 if ((status & ALE_INTRS) == 0) 2264 return (FILTER_STRAY); 2265 /* Disable interrupts. */ 2266 CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT); 2267 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2268 2269 return (FILTER_HANDLED); 2270} 2271 2272static void 2273ale_int_task(void *arg, int pending) 2274{ 2275 struct ale_softc *sc; 2276 struct ifnet *ifp; 2277 uint32_t status; 2278 int more; 2279 2280 sc = (struct ale_softc *)arg; 2281 2282 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2283 ALE_LOCK(sc); 2284 if (sc->ale_morework != 0) 2285 status |= INTR_RX_PKT; 2286 if ((status & ALE_INTRS) == 0) 2287 goto done; 2288 2289 /* Acknowledge interrupts but still disable interrupts. */ 2290 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 2291 2292 ifp = sc->ale_ifp; 2293 more = 0; 2294 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2295 more = ale_rxeof(sc, sc->ale_process_limit); 2296 if (more == EAGAIN) 2297 sc->ale_morework = 1; 2298 else if (more == EIO) { 2299 sc->ale_stats.reset_brk_seq++; 2300 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2301 ale_init_locked(sc); 2302 ALE_UNLOCK(sc); 2303 return; 2304 } 2305 2306 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2307 if ((status & INTR_DMA_RD_TO_RST) != 0) 2308 device_printf(sc->ale_dev, 2309 "DMA read error! -- resetting\n"); 2310 if ((status & INTR_DMA_WR_TO_RST) != 0) 2311 device_printf(sc->ale_dev, 2312 "DMA write error! -- resetting\n"); 2313 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2314 ale_init_locked(sc); 2315 ALE_UNLOCK(sc); 2316 return; 2317 } 2318 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2319 ale_start_locked(ifp); 2320 } 2321 2322 if (more == EAGAIN || 2323 (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) { 2324 ALE_UNLOCK(sc); 2325 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2326 return; 2327 } 2328 2329done: 2330 ALE_UNLOCK(sc); 2331 2332 /* Re-enable interrupts. */ 2333 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 2334} 2335 2336static void 2337ale_txeof(struct ale_softc *sc) 2338{ 2339 struct ifnet *ifp; 2340 struct ale_txdesc *txd; 2341 uint32_t cons, prod; 2342 int prog; 2343 2344 ALE_LOCK_ASSERT(sc); 2345 2346 ifp = sc->ale_ifp; 2347 2348 if (sc->ale_cdata.ale_tx_cnt == 0) 2349 return; 2350 2351 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2352 sc->ale_cdata.ale_tx_ring_map, 2353 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2354 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 2355 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2356 sc->ale_cdata.ale_tx_cmb_map, 2357 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2358 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 2359 } else 2360 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 2361 cons = sc->ale_cdata.ale_tx_cons; 2362 /* 2363 * Go through our Tx list and free mbufs for those 2364 * frames which have been transmitted. 2365 */ 2366 for (prog = 0; cons != prod; prog++, 2367 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 2368 if (sc->ale_cdata.ale_tx_cnt <= 0) 2369 break; 2370 prog++; 2371 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2372 sc->ale_cdata.ale_tx_cnt--; 2373 txd = &sc->ale_cdata.ale_txdesc[cons]; 2374 if (txd->tx_m != NULL) { 2375 /* Reclaim transmitted mbufs. */ 2376 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2377 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2378 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2379 txd->tx_dmamap); 2380 m_freem(txd->tx_m); 2381 txd->tx_m = NULL; 2382 } 2383 } 2384 2385 if (prog > 0) { 2386 sc->ale_cdata.ale_tx_cons = cons; 2387 /* 2388 * Unarm watchdog timer only when there is no pending 2389 * Tx descriptors in queue. 2390 */ 2391 if (sc->ale_cdata.ale_tx_cnt == 0) 2392 sc->ale_watchdog_timer = 0; 2393 } 2394} 2395 2396static void 2397ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 2398 uint32_t length, uint32_t *prod) 2399{ 2400 struct ale_rx_page *rx_page; 2401 2402 rx_page = *page; 2403 /* Update consumer position. */ 2404 rx_page->cons += roundup(length + sizeof(struct rx_rs), 2405 ALE_RX_PAGE_ALIGN); 2406 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 2407 /* 2408 * End of Rx page reached, let hardware reuse 2409 * this page. 2410 */ 2411 rx_page->cons = 0; 2412 *rx_page->cmb_addr = 0; 2413 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2414 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2415 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 2416 RXF_VALID); 2417 /* Switch to alternate Rx page. */ 2418 sc->ale_cdata.ale_rx_curp ^= 1; 2419 rx_page = *page = 2420 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2421 /* Page flipped, sync CMB and Rx page. */ 2422 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2423 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2424 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2425 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2426 /* Sync completed, cache updated producer index. */ 2427 *prod = *rx_page->cmb_addr; 2428 } 2429} 2430 2431 2432/* 2433 * It seems that AR81xx controller can compute partial checksum. 2434 * The partial checksum value can be used to accelerate checksum 2435 * computation for fragmented TCP/UDP packets. Upper network stack 2436 * already takes advantage of the partial checksum value in IP 2437 * reassembly stage. But I'm not sure the correctness of the 2438 * partial hardware checksum assistance due to lack of data sheet. 2439 * In addition, the Rx feature of controller that requires copying 2440 * for every frames effectively nullifies one of most nice offload 2441 * capability of controller. 2442 */ 2443static void 2444ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 2445{ 2446 struct ifnet *ifp; 2447 struct ip *ip; 2448 char *p; 2449 2450 ifp = sc->ale_ifp; 2451 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2452 if ((status & ALE_RD_IPCSUM_NOK) == 0) 2453 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2454 2455 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 2456 if (((status & ALE_RD_IPV4_FRAG) == 0) && 2457 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 2458 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) { 2459 m->m_pkthdr.csum_flags |= 2460 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2461 m->m_pkthdr.csum_data = 0xffff; 2462 } 2463 } else { 2464 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 && 2465 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) { 2466 p = mtod(m, char *); 2467 p += ETHER_HDR_LEN; 2468 if ((status & ALE_RD_802_3) != 0) 2469 p += LLC_SNAPFRAMELEN; 2470 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0 && 2471 (status & ALE_RD_VLAN) != 0) 2472 p += ETHER_VLAN_ENCAP_LEN; 2473 ip = (struct ip *)p; 2474 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0) 2475 return; 2476 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 2477 CSUM_PSEUDO_HDR; 2478 m->m_pkthdr.csum_data = 0xffff; 2479 } 2480 } 2481 /* 2482 * Don't mark bad checksum for TCP/UDP frames 2483 * as fragmented frames may always have set 2484 * bad checksummed bit of frame status. 2485 */ 2486} 2487 2488/* Process received frames. */ 2489static int 2490ale_rxeof(struct ale_softc *sc, int count) 2491{ 2492 struct ale_rx_page *rx_page; 2493 struct rx_rs *rs; 2494 struct ifnet *ifp; 2495 struct mbuf *m; 2496 uint32_t length, prod, seqno, status, vtags; 2497 int prog; 2498 2499 ifp = sc->ale_ifp; 2500 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2501 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2502 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2503 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2504 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2505 /* 2506 * Don't directly access producer index as hardware may 2507 * update it while Rx handler is in progress. It would 2508 * be even better if there is a way to let hardware 2509 * know how far driver processed its received frames. 2510 * Alternatively, hardware could provide a way to disable 2511 * CMB updates until driver acknowledges the end of CMB 2512 * access. 2513 */ 2514 prod = *rx_page->cmb_addr; 2515 for (prog = 0; prog < count; prog++) { 2516 if (rx_page->cons >= prod) 2517 break; 2518 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 2519 seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 2520 if (sc->ale_cdata.ale_rx_seqno != seqno) { 2521 /* 2522 * Normally I believe this should not happen unless 2523 * severe driver bug or corrupted memory. However 2524 * it seems to happen under certain conditions which 2525 * is triggered by abrupt Rx events such as initiation 2526 * of bulk transfer of remote host. It's not easy to 2527 * reproduce this and I doubt it could be related 2528 * with FIFO overflow of hardware or activity of Tx 2529 * CMB updates. I also remember similar behaviour 2530 * seen on RealTek 8139 which uses resembling Rx 2531 * scheme. 2532 */ 2533 if (bootverbose) 2534 device_printf(sc->ale_dev, 2535 "garbled seq: %u, expected: %u -- " 2536 "resetting!\n", seqno, 2537 sc->ale_cdata.ale_rx_seqno); 2538 return (EIO); 2539 } 2540 /* Frame received. */ 2541 sc->ale_cdata.ale_rx_seqno++; 2542 length = ALE_RX_BYTES(le32toh(rs->length)); 2543 status = le32toh(rs->flags); 2544 if ((status & ALE_RD_ERROR) != 0) { 2545 /* 2546 * We want to pass the following frames to upper 2547 * layer regardless of error status of Rx return 2548 * status. 2549 * 2550 * o IP/TCP/UDP checksum is bad. 2551 * o frame length and protocol specific length 2552 * does not match. 2553 */ 2554 if ((status & (ALE_RD_CRC | ALE_RD_CODE | 2555 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 2556 ALE_RD_TRUNC)) != 0) { 2557 ale_rx_update_page(sc, &rx_page, length, &prod); 2558 continue; 2559 } 2560 } 2561 /* 2562 * m_devget(9) is major bottle-neck of ale(4)(It comes 2563 * from hardware limitation). For jumbo frames we could 2564 * get a slightly better performance if driver use 2565 * m_getjcl(9) with proper buffer size argument. However 2566 * that would make code more complicated and I don't 2567 * think users would expect good Rx performance numbers 2568 * on these low-end consumer ethernet controller. 2569 */ 2570 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 2571 ETHER_ALIGN, ifp, NULL); 2572 if (m == NULL) { 2573 ifp->if_iqdrops++; 2574 ale_rx_update_page(sc, &rx_page, length, &prod); 2575 continue; 2576 } 2577 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2578 (status & ALE_RD_IPV4) != 0) 2579 ale_rxcsum(sc, m, status); 2580 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2581 (status & ALE_RD_VLAN) != 0) { 2582 vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 2583 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags); 2584 m->m_flags |= M_VLANTAG; 2585 } 2586 2587 /* Pass it to upper layer. */ 2588 ALE_UNLOCK(sc); 2589 (*ifp->if_input)(ifp, m); 2590 ALE_LOCK(sc); 2591 2592 ale_rx_update_page(sc, &rx_page, length, &prod); 2593 } 2594 2595 return (count > 0 ? 0 : EAGAIN); 2596} 2597 2598static void 2599ale_tick(void *arg) 2600{ 2601 struct ale_softc *sc; 2602 struct mii_data *mii; 2603 2604 sc = (struct ale_softc *)arg; 2605 2606 ALE_LOCK_ASSERT(sc); 2607 2608 mii = device_get_softc(sc->ale_miibus); 2609 mii_tick(mii); 2610 ale_stats_update(sc); 2611 /* 2612 * Reclaim Tx buffers that have been transferred. It's not 2613 * needed here but it would release allocated mbuf chains 2614 * faster and limit the maximum delay to a hz. 2615 */ 2616 ale_txeof(sc); 2617 ale_watchdog(sc); 2618 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2619} 2620 2621static void 2622ale_reset(struct ale_softc *sc) 2623{ 2624 uint32_t reg; 2625 int i; 2626 2627 /* Initialize PCIe module. From Linux. */ 2628 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2629 2630 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 2631 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2632 DELAY(10); 2633 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 2634 break; 2635 } 2636 if (i == 0) 2637 device_printf(sc->ale_dev, "master reset timeout!\n"); 2638 2639 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2640 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 2641 break; 2642 DELAY(10); 2643 } 2644 2645 if (i == 0) 2646 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg); 2647} 2648 2649static void 2650ale_init(void *xsc) 2651{ 2652 struct ale_softc *sc; 2653 2654 sc = (struct ale_softc *)xsc; 2655 ALE_LOCK(sc); 2656 ale_init_locked(sc); 2657 ALE_UNLOCK(sc); 2658} 2659 2660static void 2661ale_init_locked(struct ale_softc *sc) 2662{ 2663 struct ifnet *ifp; 2664 struct mii_data *mii; 2665 uint8_t eaddr[ETHER_ADDR_LEN]; 2666 bus_addr_t paddr; 2667 uint32_t reg, rxf_hi, rxf_lo; 2668 2669 ALE_LOCK_ASSERT(sc); 2670 2671 ifp = sc->ale_ifp; 2672 mii = device_get_softc(sc->ale_miibus); 2673 2674 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2675 return; 2676 /* 2677 * Cancel any pending I/O. 2678 */ 2679 ale_stop(sc); 2680 /* 2681 * Reset the chip to a known state. 2682 */ 2683 ale_reset(sc); 2684 /* Initialize Tx descriptors, DMA memory blocks. */ 2685 ale_init_rx_pages(sc); 2686 ale_init_tx_ring(sc); 2687 2688 /* Reprogram the station address. */ 2689 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2690 CSR_WRITE_4(sc, ALE_PAR0, 2691 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2692 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 2693 /* 2694 * Clear WOL status and disable all WOL feature as WOL 2695 * would interfere Rx operation under normal environments. 2696 */ 2697 CSR_READ_4(sc, ALE_WOL_CFG); 2698 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 2699 /* 2700 * Set Tx descriptor/RXF0/CMB base addresses. They share 2701 * the same high address part of DMAable region. 2702 */ 2703 paddr = sc->ale_cdata.ale_tx_ring_paddr; 2704 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 2705 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 2706 CSR_WRITE_4(sc, ALE_TPD_CNT, 2707 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 2708 /* Set Rx page base address, note we use single queue. */ 2709 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 2710 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 2711 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 2712 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 2713 /* Set Tx/Rx CMB addresses. */ 2714 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 2715 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 2716 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 2717 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 2718 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 2719 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 2720 /* Mark RXF0 is valid. */ 2721 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 2722 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 2723 /* 2724 * No need to initialize RFX1/RXF2/RXF3. We don't use 2725 * multi-queue yet. 2726 */ 2727 2728 /* Set Rx page size, excluding guard frame size. */ 2729 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 2730 /* Tell hardware that we're ready to load DMA blocks. */ 2731 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 2732 2733 /* Set Rx/Tx interrupt trigger threshold. */ 2734 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 2735 (4 << INT_TRIG_TX_THRESH_SHIFT)); 2736 /* 2737 * XXX 2738 * Set interrupt trigger timer, its purpose and relation 2739 * with interrupt moderation mechanism is not clear yet. 2740 */ 2741 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 2742 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 2743 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 2744 2745 /* Configure interrupt moderation timer. */ 2746 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 2747 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 2748 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 2749 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 2750 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 2751 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2752 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 2753 reg |= MASTER_IM_RX_TIMER_ENB; 2754 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 2755 reg |= MASTER_IM_TX_TIMER_ENB; 2756 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 2757 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 2758 2759 /* Set Maximum frame size of controller. */ 2760 if (ifp->if_mtu < ETHERMTU) 2761 sc->ale_max_frame_size = ETHERMTU; 2762 else 2763 sc->ale_max_frame_size = ifp->if_mtu; 2764 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2765 ETHER_CRC_LEN; 2766 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 2767 /* Configure IPG/IFG parameters. */ 2768 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 2769 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 2770 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2771 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2772 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 2773 /* Set parameters for half-duplex media. */ 2774 CSR_WRITE_4(sc, ALE_HDPX_CFG, 2775 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2776 HDPX_CFG_LCOL_MASK) | 2777 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2778 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2779 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2780 HDPX_CFG_ABEBT_MASK) | 2781 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2782 HDPX_CFG_JAMIPG_MASK)); 2783 2784 /* Configure Tx jumbo frame parameters. */ 2785 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2786 if (ifp->if_mtu < ETHERMTU) 2787 reg = sc->ale_max_frame_size; 2788 else if (ifp->if_mtu < 6 * 1024) 2789 reg = (sc->ale_max_frame_size * 2) / 3; 2790 else 2791 reg = sc->ale_max_frame_size / 2; 2792 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 2793 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 2794 TX_JUMBO_THRESH_UNIT_SHIFT); 2795 } 2796 /* Configure TxQ. */ 2797 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 2798 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 2799 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2800 TXQ_CFG_TPD_BURST_MASK; 2801 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 2802 2803 /* Configure Rx jumbo frame & flow control parameters. */ 2804 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2805 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 2806 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 2807 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 2808 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 2809 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 2810 RX_JUMBO_LKAH_MASK)); 2811 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 2812 rxf_hi = (reg * 7) / 10; 2813 rxf_lo = (reg * 3)/ 10; 2814 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 2815 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2816 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2817 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2818 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2819 } 2820 2821 /* Disable RSS. */ 2822 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 2823 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 2824 2825 /* Configure RxQ. */ 2826 CSR_WRITE_4(sc, ALE_RXQ_CFG, 2827 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2828 2829 /* Configure DMA parameters. */ 2830 reg = 0; 2831 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 2832 reg |= DMA_CFG_TXCMB_ENB; 2833 CSR_WRITE_4(sc, ALE_DMA_CFG, 2834 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 2835 sc->ale_dma_rd_burst | reg | 2836 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 2837 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2838 DMA_CFG_RD_DELAY_CNT_MASK) | 2839 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2840 DMA_CFG_WR_DELAY_CNT_MASK)); 2841 2842 /* 2843 * Hardware can be configured to issue SMB interrupt based 2844 * on programmed interval. Since there is a callout that is 2845 * invoked for every hz in driver we use that instead of 2846 * relying on periodic SMB interrupt. 2847 */ 2848 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 2849 /* Clear MAC statistics. */ 2850 ale_stats_clear(sc); 2851 2852 /* 2853 * Configure Tx/Rx MACs. 2854 * - Auto-padding for short frames. 2855 * - Enable CRC generation. 2856 * Actual reconfiguration of MAC for resolved speed/duplex 2857 * is followed after detection of link establishment. 2858 * AR81xx always does checksum computation regardless of 2859 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 2860 * cause Rx handling issue for fragmented IP datagrams due 2861 * to silicon bug. 2862 */ 2863 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2864 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2865 MAC_CFG_PREAMBLE_MASK); 2866 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 2867 reg |= MAC_CFG_SPEED_10_100; 2868 else 2869 reg |= MAC_CFG_SPEED_1000; 2870 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2871 2872 /* Set up the receive filter. */ 2873 ale_rxfilter(sc); 2874 ale_rxvlan(sc); 2875 2876 /* Acknowledge all pending interrupts and clear it. */ 2877 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 2878 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2879 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 2880 2881 sc->ale_flags &= ~ALE_FLAG_LINK; 2882 /* Switch to the current media. */ 2883 mii_mediachg(mii); 2884 2885 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2886 2887 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2888 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2889} 2890 2891static void 2892ale_stop(struct ale_softc *sc) 2893{ 2894 struct ifnet *ifp; 2895 struct ale_txdesc *txd; 2896 uint32_t reg; 2897 int i; 2898 2899 ALE_LOCK_ASSERT(sc); 2900 /* 2901 * Mark the interface down and cancel the watchdog timer. 2902 */ 2903 ifp = sc->ale_ifp; 2904 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2905 sc->ale_flags &= ~ALE_FLAG_LINK; 2906 callout_stop(&sc->ale_tick_ch); 2907 sc->ale_watchdog_timer = 0; 2908 ale_stats_update(sc); 2909 /* Disable interrupts. */ 2910 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 2911 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2912 /* Disable queue processing and DMA. */ 2913 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 2914 reg &= ~TXQ_CFG_ENB; 2915 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 2916 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 2917 reg &= ~RXQ_CFG_ENB; 2918 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 2919 reg = CSR_READ_4(sc, ALE_DMA_CFG); 2920 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 2921 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 2922 DELAY(1000); 2923 /* Stop Rx/Tx MACs. */ 2924 ale_stop_mac(sc); 2925 /* Disable interrupts which might be touched in taskq handler. */ 2926 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2927 2928 /* 2929 * Free TX mbufs still in the queues. 2930 */ 2931 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2932 txd = &sc->ale_cdata.ale_txdesc[i]; 2933 if (txd->tx_m != NULL) { 2934 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2935 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2936 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2937 txd->tx_dmamap); 2938 m_freem(txd->tx_m); 2939 txd->tx_m = NULL; 2940 } 2941 } 2942} 2943 2944static void 2945ale_stop_mac(struct ale_softc *sc) 2946{ 2947 uint32_t reg; 2948 int i; 2949 2950 ALE_LOCK_ASSERT(sc); 2951 2952 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2953 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2954 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 2955 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2956 } 2957 2958 for (i = ALE_TIMEOUT; i > 0; i--) { 2959 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 2960 if (reg == 0) 2961 break; 2962 DELAY(10); 2963 } 2964 if (i == 0) 2965 device_printf(sc->ale_dev, 2966 "could not disable Tx/Rx MAC(0x%08x)!\n", reg); 2967} 2968 2969static void 2970ale_init_tx_ring(struct ale_softc *sc) 2971{ 2972 struct ale_txdesc *txd; 2973 int i; 2974 2975 ALE_LOCK_ASSERT(sc); 2976 2977 sc->ale_cdata.ale_tx_prod = 0; 2978 sc->ale_cdata.ale_tx_cons = 0; 2979 sc->ale_cdata.ale_tx_cnt = 0; 2980 2981 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); 2982 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); 2983 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2984 txd = &sc->ale_cdata.ale_txdesc[i]; 2985 txd->tx_m = NULL; 2986 } 2987 *sc->ale_cdata.ale_tx_cmb = 0; 2988 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2989 sc->ale_cdata.ale_tx_cmb_map, 2990 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2991 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2992 sc->ale_cdata.ale_tx_ring_map, 2993 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2994} 2995 2996static void 2997ale_init_rx_pages(struct ale_softc *sc) 2998{ 2999 struct ale_rx_page *rx_page; 3000 int i; 3001 3002 ALE_LOCK_ASSERT(sc); 3003 3004 sc->ale_morework = 0; 3005 sc->ale_cdata.ale_rx_seqno = 0; 3006 sc->ale_cdata.ale_rx_curp = 0; 3007 3008 for (i = 0; i < ALE_RX_PAGES; i++) { 3009 rx_page = &sc->ale_cdata.ale_rx_page[i]; 3010 bzero(rx_page->page_addr, sc->ale_pagesize); 3011 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ); 3012 rx_page->cons = 0; 3013 *rx_page->cmb_addr = 0; 3014 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 3015 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3016 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 3017 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3018 } 3019} 3020 3021static void 3022ale_rxvlan(struct ale_softc *sc) 3023{ 3024 struct ifnet *ifp; 3025 uint32_t reg; 3026 3027 ALE_LOCK_ASSERT(sc); 3028 3029 ifp = sc->ale_ifp; 3030 reg = CSR_READ_4(sc, ALE_MAC_CFG); 3031 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3032 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3033 reg |= MAC_CFG_VLAN_TAG_STRIP; 3034 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 3035} 3036 3037static void 3038ale_rxfilter(struct ale_softc *sc) 3039{ 3040 struct ifnet *ifp; 3041 struct ifmultiaddr *ifma; 3042 uint32_t crc; 3043 uint32_t mchash[2]; 3044 uint32_t rxcfg; 3045 3046 ALE_LOCK_ASSERT(sc); 3047 3048 ifp = sc->ale_ifp; 3049 3050 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 3051 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3052 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3053 rxcfg |= MAC_CFG_BCAST; 3054 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3055 if ((ifp->if_flags & IFF_PROMISC) != 0) 3056 rxcfg |= MAC_CFG_PROMISC; 3057 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3058 rxcfg |= MAC_CFG_ALLMULTI; 3059 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF); 3060 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF); 3061 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3062 return; 3063 } 3064 3065 /* Program new filter. */ 3066 bzero(mchash, sizeof(mchash)); 3067 3068 if_maddr_rlock(ifp); 3069 TAILQ_FOREACH(ifma, &sc->ale_ifp->if_multiaddrs, ifma_link) { 3070 if (ifma->ifma_addr->sa_family != AF_LINK) 3071 continue; 3072 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3073 ifma->ifma_addr), ETHER_ADDR_LEN); 3074 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3075 } 3076 if_maddr_runlock(ifp); 3077 3078 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 3079 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 3080 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3081} 3082 3083static int 3084sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3085{ 3086 int error, value; 3087 3088 if (arg1 == NULL) 3089 return (EINVAL); 3090 value = *(int *)arg1; 3091 error = sysctl_handle_int(oidp, &value, 0, req); 3092 if (error || req->newptr == NULL) 3093 return (error); 3094 if (value < low || value > high) 3095 return (EINVAL); 3096 *(int *)arg1 = value; 3097 3098 return (0); 3099} 3100 3101static int 3102sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS) 3103{ 3104 return (sysctl_int_range(oidp, arg1, arg2, req, 3105 ALE_PROC_MIN, ALE_PROC_MAX)); 3106} 3107 3108static int 3109sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS) 3110{ 3111 3112 return (sysctl_int_range(oidp, arg1, arg2, req, 3113 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX)); 3114} 3115