aic7xxx_93cx6.c revision 76634 
1/*
2 * Interface for the 93C66/56/46/26/06 serial eeprom parts.
3 *
4 * Copyright (c) 1995, 1996 Daniel M. Eischen
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions, and the following disclaimer,
12 *    without modification.
13 * 2. The name of the author may not be used to endorse or promote products
14 *    derived from this software without specific prior written permission.
15 *
16 * Alternatively, this software may be distributed under the terms of the
17 * GNU Public License ("GPL").
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * $Id: //depot/src/aic7xxx/aic7xxx_93cx6.c#7 $
32 *
33 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx_93cx6.c 76634 2001-05-15 19:41:12Z gibbs $
34 */
35
36/*
37 *   The instruction set of the 93C66/56/46/26/06 chips are as follows:
38 *
39 *               Start  OP	    *
40 *     Function   Bit  Code  Address**  Data     Description
41 *     -------------------------------------------------------------------
42 *     READ        1    10   A5 - A0             Reads data stored in memory,
43 *                                               starting at specified address
44 *     EWEN        1    00   11XXXX              Write enable must precede
45 *                                               all programming modes
46 *     ERASE       1    11   A5 - A0             Erase register A5A4A3A2A1A0
47 *     WRITE       1    01   A5 - A0   D15 - D0  Writes register
48 *     ERAL        1    00   10XXXX              Erase all registers
49 *     WRAL        1    00   01XXXX    D15 - D0  Writes to all registers
50 *     EWDS        1    00   00XXXX              Disables all programming
51 *                                               instructions
52 *     *Note: A value of X for address is a don't care condition.
53 *    **Note: There are 8 address bits for the 93C56/66 chips unlike
54 *	      the 93C46/26/06 chips which have 6 address bits.
55 *
56 *   The 93C46 has a four wire interface: clock, chip select, data in, and
57 *   data out.  In order to perform one of the above functions, you need
58 *   to enable the chip select for a clock period (typically a minimum of
59 *   1 usec, with the clock high and low a minimum of 750 and 250 nsec
60 *   respectively).  While the chip select remains high, you can clock in
61 *   the instructions (above) starting with the start bit, followed by the
62 *   OP code, Address, and Data (if needed).  For the READ instruction, the
63 *   requested 16-bit register contents is read from the data out line but
64 *   is preceded by an initial zero (leading 0, followed by 16-bits, MSB
65 *   first).  The clock cycling from low to high initiates the next data
66 *   bit to be sent from the chip.
67 *
68 */
69
70#include <dev/aic7xxx/aic7xxx_freebsd.h>
71#include <dev/aic7xxx/aic7xxx_inline.h>
72#include <dev/aic7xxx/aic7xxx_93cx6.h>
73
74/*
75 * Right now, we only have to read the SEEPROM.  But we make it easier to
76 * add other 93Cx6 functions.
77 */
78static struct seeprom_cmd {
79  	uint8_t len;
80 	uint8_t bits[3];
81} seeprom_read = {3, {1, 1, 0}};
82
83/*
84 * Wait for the SEERDY to go high; about 800 ns.
85 */
86#define CLOCK_PULSE(sd, rdy)				\
87	while ((SEEPROM_STATUS_INB(sd) & rdy) == 0) {	\
88		;  /* Do nothing */			\
89	}						\
90	(void)SEEPROM_INB(sd);	/* Clear clock */
91
92/*
93 * Read the serial EEPROM and returns 1 if successful and 0 if
94 * not successful.
95 */
96int
97read_seeprom(sd, buf, start_addr, count)
98	struct seeprom_descriptor *sd;
99	uint16_t *buf;
100	u_int start_addr;
101	u_int count;
102{
103	int i = 0;
104	u_int k = 0;
105	uint16_t v;
106	uint8_t temp;
107
108	/*
109	 * Read the requested registers of the seeprom.  The loop
110	 * will range from 0 to count-1.
111	 */
112	for (k = start_addr; k < count + start_addr; k++) {
113		/* Send chip select for one clock cycle. */
114		temp = sd->sd_MS ^ sd->sd_CS;
115		SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
116		CLOCK_PULSE(sd, sd->sd_RDY);
117
118		/*
119		 * Now we're ready to send the read command followed by the
120		 * address of the 16-bit register we want to read.
121		 */
122		for (i = 0; i < seeprom_read.len; i++) {
123			if (seeprom_read.bits[i] != 0)
124				temp ^= sd->sd_DO;
125			SEEPROM_OUTB(sd, temp);
126			CLOCK_PULSE(sd, sd->sd_RDY);
127			SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
128			CLOCK_PULSE(sd, sd->sd_RDY);
129			if (seeprom_read.bits[i] != 0)
130				temp ^= sd->sd_DO;
131		}
132		/* Send the 6 or 8 bit address (MSB first, LSB last). */
133		for (i = (sd->sd_chip - 1); i >= 0; i--) {
134			if ((k & (1 << i)) != 0)
135				temp ^= sd->sd_DO;
136			SEEPROM_OUTB(sd, temp);
137			CLOCK_PULSE(sd, sd->sd_RDY);
138			SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
139			CLOCK_PULSE(sd, sd->sd_RDY);
140			if ((k & (1 << i)) != 0)
141				temp ^= sd->sd_DO;
142		}
143
144		/*
145		 * Now read the 16 bit register.  An initial 0 precedes the
146		 * register contents which begins with bit 15 (MSB) and ends
147		 * with bit 0 (LSB).  The initial 0 will be shifted off the
148		 * top of our word as we let the loop run from 0 to 16.
149		 */
150		v = 0;
151		for (i = 16; i >= 0; i--) {
152			SEEPROM_OUTB(sd, temp);
153			CLOCK_PULSE(sd, sd->sd_RDY);
154			v <<= 1;
155			if (SEEPROM_DATA_INB(sd) & sd->sd_DI)
156				v |= 1;
157			SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
158			CLOCK_PULSE(sd, sd->sd_RDY);
159		}
160
161		buf[k - start_addr] = v;
162
163		/* Reset the chip select for the next command cycle. */
164		temp = sd->sd_MS;
165		SEEPROM_OUTB(sd, temp);
166		CLOCK_PULSE(sd, sd->sd_RDY);
167		SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
168		CLOCK_PULSE(sd, sd->sd_RDY);
169		SEEPROM_OUTB(sd, temp);
170		CLOCK_PULSE(sd, sd->sd_RDY);
171	}
172#ifdef AHC_DUMP_EEPROM
173	printf("\nSerial EEPROM:\n\t");
174	for (k = 0; k < count; k = k + 1) {
175		if (((k % 8) == 0) && (k != 0)) {
176			printf ("\n\t");
177		}
178		printf (" 0x%x", buf[k]);
179	}
180	printf ("\n");
181#endif
182	return (1);
183}
184
185int
186verify_cksum(struct seeprom_config *sc)
187{
188	int i;
189	int maxaddr;
190	uint32_t checksum;
191	uint16_t *scarray;
192
193	maxaddr = (sizeof(*sc)/2) - 1;
194	checksum = 0;
195	scarray = (uint16_t *)sc;
196
197	for (i = 0; i < maxaddr; i++)
198		checksum = checksum + scarray[i];
199	if (checksum == 0
200	 || (checksum & 0xFFFF) != sc->checksum) {
201		return (0);
202	} else {
203		return(1);
204	}
205}
206