aic7xxx_93cx6.c revision 66269
1238384Sjkim/* 2238384Sjkim * Interface for the 93C66/56/46/26/06 serial eeprom parts. 3238384Sjkim * 4238384Sjkim * Copyright (c) 1995, 1996 Daniel M. Eischen 5238384Sjkim * All rights reserved. 6238384Sjkim * 7238384Sjkim * Redistribution and use in source and binary forms, with or without 8238384Sjkim * modification, are permitted provided that the following conditions 9238384Sjkim * are met: 10238384Sjkim * 1. Redistributions of source code must retain the above copyright 11238384Sjkim * notice, this list of conditions, and the following disclaimer, 12238384Sjkim * without modification. 13238384Sjkim * 2. The name of the author may not be used to endorse or promote products 14238384Sjkim * derived from this software without specific prior written permission. 15238384Sjkim * 16238384Sjkim * Alternatively, this software may be distributed under the terms of the 17238384Sjkim * GNU Public License ("GPL"). 18238384Sjkim * 19238384Sjkim * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20238384Sjkim * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21238384Sjkim * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22238384Sjkim * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 23238384Sjkim * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24238384Sjkim * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25238384Sjkim * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26238384Sjkim * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27238384Sjkim * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28238384Sjkim * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29238384Sjkim * SUCH DAMAGE. 30238384Sjkim * 31238384Sjkim * $Id: //depot/src/aic7xxx/aic7xxx_93cx6.c#3 $ 32238384Sjkim * 33238384Sjkim * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx_93cx6.c 66269 2000-09-22 22:18:05Z gibbs $ 34238384Sjkim */ 35238384Sjkim 36238384Sjkim/* 37238384Sjkim * The instruction set of the 93C66/56/46/26/06 chips are as follows: 38238384Sjkim * 39238384Sjkim * Start OP * 40238384Sjkim * Function Bit Code Address** Data Description 41238384Sjkim * ------------------------------------------------------------------- 42238384Sjkim * READ 1 10 A5 - A0 Reads data stored in memory, 43238384Sjkim * starting at specified address 44238384Sjkim * EWEN 1 00 11XXXX Write enable must preceed 45238384Sjkim * all programming modes 46238384Sjkim * ERASE 1 11 A5 - A0 Erase register A5A4A3A2A1A0 47238384Sjkim * WRITE 1 01 A5 - A0 D15 - D0 Writes register 48238384Sjkim * ERAL 1 00 10XXXX Erase all registers 49238384Sjkim * WRAL 1 00 01XXXX D15 - D0 Writes to all registers 50238384Sjkim * EWDS 1 00 00XXXX Disables all programming 51238384Sjkim * instructions 52238384Sjkim * *Note: A value of X for address is a don't care condition. 53238384Sjkim * **Note: There are 8 address bits for the 93C56/66 chips unlike 54238384Sjkim * the 93C46/26/06 chips which have 6 address bits. 55238384Sjkim * 56238384Sjkim * The 93C46 has a four wire interface: clock, chip select, data in, and 57238384Sjkim * data out. In order to perform one of the above functions, you need 58238384Sjkim * to enable the chip select for a clock period (typically a minimum of 59238384Sjkim * 1 usec, with the clock high and low a minimum of 750 and 250 nsec 60238384Sjkim * respectively). While the chip select remains high, you can clock in 61238384Sjkim * the instructions (above) starting with the start bit, followed by the 62238384Sjkim * OP code, Address, and Data (if needed). For the READ instruction, the 63238384Sjkim * requested 16-bit register contents is read from the data out line but 64238384Sjkim * is preceded by an initial zero (leading 0, followed by 16-bits, MSB 65238384Sjkim * first). The clock cycling from low to high initiates the next data 66238384Sjkim * bit to be sent from the chip. 67238384Sjkim * 68238384Sjkim */ 69238384Sjkim 70238384Sjkim#ifdef __linux__ 71238384Sjkim#include "aic7xxx_linux.h" 72238384Sjkim#include "aic7xxx_inline.h" 73238384Sjkim#include "aic7xxx_93cx6.h" 74238384Sjkim#endif 75238384Sjkim 76#ifdef __FreeBSD__ 77#include <dev/aic7xxx/aic7xxx_freebsd.h> 78#include <dev/aic7xxx/aic7xxx_inline.h> 79#include <dev/aic7xxx/aic7xxx_93cx6.h> 80#endif 81 82/* 83 * Right now, we only have to read the SEEPROM. But we make it easier to 84 * add other 93Cx6 functions. 85 */ 86static struct seeprom_cmd { 87 uint8_t len; 88 uint8_t bits[3]; 89} seeprom_read = {3, {1, 1, 0}}; 90 91/* 92 * Wait for the SEERDY to go high; about 800 ns. 93 */ 94#define CLOCK_PULSE(sd, rdy) \ 95 while ((SEEPROM_STATUS_INB(sd) & rdy) == 0) { \ 96 ; /* Do nothing */ \ 97 } \ 98 (void)SEEPROM_INB(sd); /* Clear clock */ 99 100/* 101 * Read the serial EEPROM and returns 1 if successful and 0 if 102 * not successful. 103 */ 104int 105read_seeprom(sd, buf, start_addr, count) 106 struct seeprom_descriptor *sd; 107 uint16_t *buf; 108 u_int start_addr; 109 u_int count; 110{ 111 int i = 0; 112 u_int k = 0; 113 uint16_t v; 114 uint8_t temp; 115 116 /* 117 * Read the requested registers of the seeprom. The loop 118 * will range from 0 to count-1. 119 */ 120 for (k = start_addr; k < count + start_addr; k++) { 121 /* Send chip select for one clock cycle. */ 122 temp = sd->sd_MS ^ sd->sd_CS; 123 SEEPROM_OUTB(sd, temp ^ sd->sd_CK); 124 CLOCK_PULSE(sd, sd->sd_RDY); 125 126 /* 127 * Now we're ready to send the read command followed by the 128 * address of the 16-bit register we want to read. 129 */ 130 for (i = 0; i < seeprom_read.len; i++) { 131 if (seeprom_read.bits[i] != 0) 132 temp ^= sd->sd_DO; 133 SEEPROM_OUTB(sd, temp); 134 CLOCK_PULSE(sd, sd->sd_RDY); 135 SEEPROM_OUTB(sd, temp ^ sd->sd_CK); 136 CLOCK_PULSE(sd, sd->sd_RDY); 137 if (seeprom_read.bits[i] != 0) 138 temp ^= sd->sd_DO; 139 } 140 /* Send the 6 or 8 bit address (MSB first, LSB last). */ 141 for (i = (sd->sd_chip - 1); i >= 0; i--) { 142 if ((k & (1 << i)) != 0) 143 temp ^= sd->sd_DO; 144 SEEPROM_OUTB(sd, temp); 145 CLOCK_PULSE(sd, sd->sd_RDY); 146 SEEPROM_OUTB(sd, temp ^ sd->sd_CK); 147 CLOCK_PULSE(sd, sd->sd_RDY); 148 if ((k & (1 << i)) != 0) 149 temp ^= sd->sd_DO; 150 } 151 152 /* 153 * Now read the 16 bit register. An initial 0 precedes the 154 * register contents which begins with bit 15 (MSB) and ends 155 * with bit 0 (LSB). The initial 0 will be shifted off the 156 * top of our word as we let the loop run from 0 to 16. 157 */ 158 v = 0; 159 for (i = 16; i >= 0; i--) { 160 SEEPROM_OUTB(sd, temp); 161 CLOCK_PULSE(sd, sd->sd_RDY); 162 v <<= 1; 163 if (SEEPROM_DATA_INB(sd) & sd->sd_DI) 164 v |= 1; 165 SEEPROM_OUTB(sd, temp ^ sd->sd_CK); 166 CLOCK_PULSE(sd, sd->sd_RDY); 167 } 168 169 buf[k - start_addr] = v; 170 171 /* Reset the chip select for the next command cycle. */ 172 temp = sd->sd_MS; 173 SEEPROM_OUTB(sd, temp); 174 CLOCK_PULSE(sd, sd->sd_RDY); 175 SEEPROM_OUTB(sd, temp ^ sd->sd_CK); 176 CLOCK_PULSE(sd, sd->sd_RDY); 177 SEEPROM_OUTB(sd, temp); 178 CLOCK_PULSE(sd, sd->sd_RDY); 179 } 180#ifdef AHC_DUMP_EEPROM 181 printf("\nSerial EEPROM:\n\t"); 182 for (k = 0; k < count; k = k + 1) { 183 if (((k % 8) == 0) && (k != 0)) { 184 printf ("\n\t"); 185 } 186 printf (" 0x%x", buf[k]); 187 } 188 printf ("\n"); 189#endif 190 return (1); 191} 192 193int 194verify_cksum(struct seeprom_config *sc) 195{ 196 int i; 197 int maxaddr; 198 uint32_t checksum; 199 uint16_t *scarray; 200 201 maxaddr = (sizeof(*sc)/2) - 1; 202 checksum = 0; 203 scarray = (uint16_t *)sc; 204 205 for (i = 0; i < maxaddr; i++) 206 checksum = checksum + scarray[i]; 207 if (checksum == 0 208 || (checksum & 0xFFFF) != sc->checksum) { 209 return (0); 210 } else { 211 return(1); 212 } 213} 214