aic7xxx.seq revision 74094
1/* 2 * Adaptec 274x/284x/294x device driver firmware for Linux and FreeBSD. 3 * 4 * Copyright (c) 1994-2001 Justin Gibbs. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * Alternatively, this software may be distributed under the terms of the 17 * GNU Public License ("GPL"). 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $Id: //depot/src/aic7xxx/aic7xxx.seq#23 $ 32 * 33 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.seq 74094 2001-03-11 06:34:17Z gibbs $ 34 */ 35 36#include "aic7xxx.reg" 37#include "scsi_message.h" 38 39/* 40 * A few words on the waiting SCB list: 41 * After starting the selection hardware, we check for reconnecting targets 42 * as well as for our selection to complete just in case the reselection wins 43 * bus arbitration. The problem with this is that we must keep track of the 44 * SCB that we've already pulled from the QINFIFO and started the selection 45 * on just in case the reselection wins so that we can retry the selection at 46 * a later time. This problem cannot be resolved by holding a single entry 47 * in scratch ram since a reconnecting target can request sense and this will 48 * create yet another SCB waiting for selection. The solution used here is to 49 * use byte 27 of the SCB as a psuedo-next pointer and to thread a list 50 * of SCBs that are awaiting selection. Since 0-0xfe are valid SCB indexes, 51 * SCB_LIST_NULL is 0xff which is out of range. An entry is also added to 52 * this list everytime a request sense occurs or after completing a non-tagged 53 * command for which a second SCB has been queued. The sequencer will 54 * automatically consume the entries. 55 */ 56 57bus_free_sel: 58 /* 59 * Turn off the selection hardware. We need to reset the 60 * selection request in order to perform a new selection. 61 */ 62 and SCSISEQ, TEMODE|ENSELI|ENRSELI|ENAUTOATNP, SCSISEQ; 63 and SIMODE1, ~ENBUSFREE; 64poll_for_work: 65 call clear_target_state; 66 and SXFRCTL0, ~SPIOEN; 67 if ((ahc->features & AHC_ULTRA2) != 0) { 68 clr SCSIBUSL; 69 } 70 test SCSISEQ, ENSELO jnz poll_for_selection; 71 if ((ahc->features & AHC_TWIN) != 0) { 72 xor SBLKCTL,SELBUSB; /* Toggle to the other bus */ 73 test SCSISEQ, ENSELO jnz poll_for_selection; 74 } 75 cmp WAITING_SCBH,SCB_LIST_NULL jne start_waiting; 76poll_for_work_loop: 77 if ((ahc->features & AHC_TWIN) != 0) { 78 xor SBLKCTL,SELBUSB; /* Toggle to the other bus */ 79 } 80 test SSTAT0, SELDO|SELDI jnz selection; 81test_queue: 82 /* Has the driver posted any work for us? */ 83BEGIN_CRITICAL 84 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 85 test QOFF_CTLSTA, SCB_AVAIL jz poll_for_work_loop; 86 } else { 87 mov A, QINPOS; 88 cmp KERNEL_QINPOS, A je poll_for_work_loop; 89 } 90 mov ARG_1, NEXT_QUEUED_SCB; 91 92 /* 93 * We have at least one queued SCB now and we don't have any 94 * SCBs in the list of SCBs awaiting selection. Allocate a 95 * card SCB for the host's SCB and get to work on it. 96 */ 97 if ((ahc->flags & AHC_PAGESCBS) != 0) { 98 mov ALLZEROS call get_free_or_disc_scb; 99 } else { 100 /* In the non-paging case, the SCBID == hardware SCB index */ 101 mov SCBPTR, ARG_1; 102 } 103 or SEQ_FLAGS2, SCB_DMA; 104END_CRITICAL 105dma_queued_scb: 106 /* 107 * DMA the SCB from host ram into the current SCB location. 108 */ 109 mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET; 110 mov ARG_1 call dma_scb; 111 /* 112 * Check one last time to see if this SCB was canceled 113 * before we completed the DMA operation. If it was, 114 * the QINFIFO next pointer will not match our saved 115 * value. 116 */ 117 mov A, ARG_1; 118BEGIN_CRITICAL 119 cmp NEXT_QUEUED_SCB, A jne abort_qinscb; 120 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 121 cmp SCB_TAG, A je . + 2; 122 mvi SCB_MISMATCH call set_seqint; 123 } 124 mov NEXT_QUEUED_SCB, SCB_NEXT; 125 mov SCB_NEXT,WAITING_SCBH; 126 mov WAITING_SCBH, SCBPTR; 127 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 128 mov NONE, SNSCB_QOFF; 129 } else { 130 inc QINPOS; 131 } 132 and SEQ_FLAGS2, ~SCB_DMA; 133END_CRITICAL 134start_waiting: 135 /* 136 * Start the first entry on the waiting SCB list. 137 */ 138 mov SCBPTR, WAITING_SCBH; 139 call start_selection; 140 141poll_for_selection: 142 /* 143 * Twin channel devices cannot handle things like SELTO 144 * interrupts on the "background" channel. So, while 145 * selecting, keep polling the current channel until 146 * either a selection or reselection occurs. 147 */ 148 test SSTAT0, SELDO|SELDI jz poll_for_selection; 149 150selection: 151 /* 152 * We aren't expecting a bus free, so interrupt 153 * the kernel driver if it happens. 154 */ 155 mvi CLRSINT1,CLRBUSFREE; 156 or SIMODE1, ENBUSFREE; 157 158 /* 159 * Guard against a bus free after (re)selection 160 * but prior to enabling the busfree interrupt. SELDI 161 * and SELDO will be cleared in that case. 162 */ 163 test SSTAT0, SELDI|SELDO jz bus_free_sel; 164 test SSTAT0,SELDO jnz select_out; 165select_in: 166 if ((ahc->flags & AHC_TARGETROLE) != 0) { 167 if ((ahc->flags & AHC_INITIATORROLE) != 0) { 168 test SSTAT0, TARGET jz initiator_reselect; 169 } 170 mvi CLRSINT0, CLRSELDI; 171 172 /* 173 * We've just been selected. Assert BSY and 174 * setup the phase for receiving messages 175 * from the target. 176 * 177 * If bus reset interrupts have been disabled (from a 178 * previous reset), re-enable them now. Resets are only 179 * of interest when we have outstanding transactions, so 180 * we can safely defer re-enabling the interrupt until, 181 * as a target, we start receiving transactions again. 182 */ 183 test SIMODE1, ENSCSIRST jnz . + 3; 184 mvi CLRSINT1, CLRSCSIRSTI; 185 or SIMODE1, ENSCSIRST; 186 mvi SCSISIGO, P_MESGOUT|BSYO; 187 188 /* 189 * Setup the DMA for sending the identify and 190 * command information. 191 */ 192 or SEQ_FLAGS, CMDPHASE_PENDING; 193 194 mov A, TQINPOS; 195 if ((ahc->features & AHC_CMD_CHAN) != 0) { 196 mvi DINDEX, CCHADDR; 197 mvi SHARED_DATA_ADDR call set_32byte_addr; 198 mvi CCSCBCTL, CCSCBRESET; 199 } else { 200 mvi DINDEX, HADDR; 201 mvi SHARED_DATA_ADDR call set_32byte_addr; 202 mvi DFCNTRL, FIFORESET; 203 } 204 205 /* Initiator that selected us */ 206 and SAVED_SCSIID, SELID_MASK, SELID; 207 /* The Target ID we were selected at */ 208 if ((ahc->features & AHC_MULTI_TID) != 0) { 209 and A, OID, TARGIDIN; 210 } else if ((ahc->features & AHC_ULTRA2) != 0) { 211 and A, OID, SCSIID_ULTRA2; 212 } else { 213 and A, OID, SCSIID; 214 } 215 or SAVED_SCSIID, A; 216 if ((ahc->features & AHC_TWIN) != 0) { 217 test SBLKCTL, SELBUSB jz . + 2; 218 or SAVED_SCSIID, TWIN_CHNLB; 219 } 220 if ((ahc->features & AHC_CMD_CHAN) != 0) { 221 mov CCSCBRAM, SAVED_SCSIID; 222 } else { 223 mov DFDAT, SAVED_SCSIID; 224 } 225 226 /* 227 * If ATN isn't asserted, the target isn't interested 228 * in talking to us. Go directly to bus free. 229 * XXX SCSI-1 may require us to assume lun 0 if 230 * ATN is false. 231 */ 232 test SCSISIGI, ATNI jz target_busfree; 233 234 /* 235 * Watch ATN closely now as we pull in messages from the 236 * initiator. We follow the guidlines from section 6.5 237 * of the SCSI-2 spec for what messages are allowed when. 238 */ 239 call target_inb; 240 241 /* 242 * Our first message must be one of IDENTIFY, ABORT, or 243 * BUS_DEVICE_RESET. 244 */ 245 test DINDEX, MSG_IDENTIFYFLAG jz host_target_message_loop; 246 /* Store for host */ 247 if ((ahc->features & AHC_CMD_CHAN) != 0) { 248 mov CCSCBRAM, DINDEX; 249 } else { 250 mov DFDAT, DINDEX; 251 } 252 253 /* Remember for disconnection decision */ 254 test DINDEX, MSG_IDENTIFY_DISCFLAG jnz . + 2; 255 /* XXX Honor per target settings too */ 256 or SEQ_FLAGS, NO_DISCONNECT; 257 258 test SCSISIGI, ATNI jz ident_messages_done; 259 call target_inb; 260 /* 261 * If this is a tagged request, the tagged message must 262 * immediately follow the identify. We test for a valid 263 * tag message by seeing if it is >= MSG_SIMPLE_Q_TAG and 264 * < MSG_IGN_WIDE_RESIDUE. 265 */ 266 add A, -MSG_SIMPLE_Q_TAG, DINDEX; 267 jnc ident_messages_done; 268 add A, -MSG_IGN_WIDE_RESIDUE, DINDEX; 269 jc ident_messages_done; 270 /* Store for host */ 271 if ((ahc->features & AHC_CMD_CHAN) != 0) { 272 mov CCSCBRAM, DINDEX; 273 } else { 274 mov DFDAT, DINDEX; 275 } 276 277 /* 278 * If the initiator doesn't feel like providing a tag number, 279 * we've got a failed selection and must transition to bus 280 * free. 281 */ 282 test SCSISIGI, ATNI jz target_busfree; 283 284 /* 285 * Store the tag for the host. 286 */ 287 call target_inb; 288 if ((ahc->features & AHC_CMD_CHAN) != 0) { 289 mov CCSCBRAM, DINDEX; 290 } else { 291 mov DFDAT, DINDEX; 292 } 293 mov INITIATOR_TAG, DINDEX; 294 or SEQ_FLAGS, TARGET_CMD_IS_TAGGED; 295 test SCSISIGI, ATNI jz . + 2; 296 /* Initiator still wants to give us messages */ 297 call target_inb; 298 jmp ident_messages_done; 299 300 /* 301 * Pushed message loop to allow the kernel to 302 * run it's own target mode message state engine. 303 */ 304host_target_message_loop: 305 mvi HOST_MSG_LOOP call set_seqint; 306 cmp RETURN_1, EXIT_MSG_LOOP je target_ITloop; 307 test SSTAT0, SPIORDY jz .; 308 jmp host_target_message_loop; 309 310ident_messages_done: 311 /* If ring buffer is full, return busy or queue full */ 312 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 313 and A, HOST_TQINPOS, HS_MAILBOX; 314 } else { 315 mov A, KERNEL_TQINPOS; 316 } 317 cmp TQINPOS, A jne tqinfifo_has_space; 318 mvi P_STATUS|BSYO call change_phase; 319 test SEQ_FLAGS, TARGET_CMD_IS_TAGGED jz . + 3; 320 mvi STATUS_QUEUE_FULL call target_outb; 321 jmp target_busfree_wait; 322 mvi STATUS_BUSY call target_outb; 323 jmp target_busfree_wait; 324tqinfifo_has_space: 325 /* Terminate the ident list */ 326 if ((ahc->features & AHC_CMD_CHAN) != 0) { 327 mvi CCSCBRAM, SCB_LIST_NULL; 328 } else { 329 mvi DFDAT, SCB_LIST_NULL; 330 } 331 or SEQ_FLAGS, TARG_CMD_PENDING|IDENTIFY_SEEN; 332 test SCSISIGI, ATNI jnz target_mesgout_pending; 333 jmp target_ITloop; 334 } 335 336if ((ahc->flags & AHC_INITIATORROLE) != 0) { 337/* 338 * Reselection has been initiated by a target. Make a note that we've been 339 * reselected, but haven't seen an IDENTIFY message from the target yet. 340 */ 341initiator_reselect: 342 /* XXX test for and handle ONE BIT condition */ 343 or SXFRCTL0, SPIOEN|CLRSTCNT|CLRCHN; 344 and SAVED_SCSIID, SELID_MASK, SELID; 345 if ((ahc->features & AHC_ULTRA2) != 0) { 346 and A, OID, SCSIID_ULTRA2; 347 } else { 348 and A, OID, SCSIID; 349 } 350 or SAVED_SCSIID, A; 351 if ((ahc->features & AHC_TWIN) != 0) { 352 test SBLKCTL, SELBUSB jz . + 2; 353 or SAVED_SCSIID, TWIN_CHNLB; 354 } 355 mvi CLRSINT0, CLRSELDI; 356 jmp ITloop; 357} 358 359abort_qinscb: 360 call add_scb_to_free_list; 361 jmp poll_for_work_loop; 362 363start_selection: 364 /* 365 * If bus reset interrupts have been disabled (from a previous 366 * reset), re-enable them now. Resets are only of interest 367 * when we have outstanding transactions, so we can safely 368 * defer re-enabling the interrupt until, as an initiator, 369 * we start sending out transactions again. 370 */ 371 test SIMODE1, ENSCSIRST jnz . + 3; 372 mvi CLRSINT1, CLRSCSIRSTI; 373 or SIMODE1, ENSCSIRST; 374 if ((ahc->features & AHC_TWIN) != 0) { 375 and SINDEX,~SELBUSB,SBLKCTL;/* Clear channel select bit */ 376 test SCB_SCSIID, TWIN_CHNLB jz . + 2; 377 or SINDEX, SELBUSB; 378 mov SBLKCTL,SINDEX; /* select channel */ 379 } 380initialize_scsiid: 381 if ((ahc->features & AHC_ULTRA2) != 0) { 382 mov SCSIID_ULTRA2, SCB_SCSIID; 383 } else if ((ahc->features & AHC_TWIN) != 0) { 384 and SCSIID, TWIN_TID|OID, SCB_SCSIID; 385 } else { 386 mov SCSIID, SCB_SCSIID; 387 } 388 if ((ahc->flags & AHC_TARGETROLE) != 0) { 389 mov SINDEX, SCSISEQ_TEMPLATE; 390 test SCB_CONTROL, TARGET_SCB jz . + 2; 391 or SINDEX, TEMODE; 392 mov SCSISEQ, SINDEX ret; 393 } else { 394 mov SCSISEQ, SCSISEQ_TEMPLATE ret; 395 } 396 397/* 398 * Initialize transfer settings and clear the SCSI channel. 399 * SINDEX should contain any additional bit's the client wants 400 * set in SXFRCTL0. We also assume that the current SCB is 401 * a valid SCB for the target we wish to talk to. 402 */ 403initialize_channel: 404 or SXFRCTL0, SPIOEN|CLRSTCNT|CLRCHN; 405set_transfer_settings: 406 if ((ahc->features & AHC_ULTRA) != 0) { 407 test SCB_CONTROL, ULTRAENB jz . + 2; 408 or SXFRCTL0, FAST20; 409 } 410 /* 411 * Initialize SCSIRATE with the appropriate value for this target. 412 */ 413 if ((ahc->features & AHC_ULTRA2) != 0) { 414 bmov SCSIRATE, SCB_SCSIRATE, 2 ret; 415 } else { 416 mov SCSIRATE, SCB_SCSIRATE ret; 417 } 418 419if ((ahc->flags & AHC_TARGETROLE) != 0) { 420/* 421 * We carefully toggle SPIOEN to allow us to return the 422 * message byte we receive so it can be checked prior to 423 * driving REQ on the bus for the next byte. 424 */ 425target_inb: 426 /* 427 * Drive REQ on the bus by enabling SCSI PIO. 428 */ 429 or SXFRCTL0, SPIOEN; 430 /* Wait for the byte */ 431 test SSTAT0, SPIORDY jz .; 432 /* Prevent our read from triggering another REQ */ 433 and SXFRCTL0, ~SPIOEN; 434 /* Save latched contents */ 435 mov DINDEX, SCSIDATL ret; 436} 437 438/* 439 * After the selection, remove this SCB from the "waiting SCB" 440 * list. This is achieved by simply moving our "next" pointer into 441 * WAITING_SCBH. Our next pointer will be set to null the next time this 442 * SCB is used, so don't bother with it now. 443 */ 444select_out: 445 /* Turn off the selection hardware */ 446 and SCSISEQ, TEMODE|ENSELI|ENRSELI|ENAUTOATNP, SCSISEQ; 447 mvi CLRSINT0, CLRSELDO; 448 mov SCBPTR, WAITING_SCBH; 449 mov WAITING_SCBH,SCB_NEXT; 450 mov SAVED_SCSIID, SCB_SCSIID; 451 mov SAVED_LUN, SCB_LUN; 452 call initialize_channel; 453 if ((ahc->flags & AHC_TARGETROLE) != 0) { 454 test SSTAT0, TARGET jz initiator_select; 455 456 /* 457 * We've just re-selected an initiator. 458 * Assert BSY and setup the phase for 459 * sending our identify messages. 460 */ 461 mvi P_MESGIN|BSYO call change_phase; 462 463 /* 464 * Start out with a simple identify message. 465 */ 466 or SCB_LUN, MSG_IDENTIFYFLAG call target_outb; 467 468 /* 469 * If we are the result of a tagged command, send 470 * a simple Q tag and the tag id. 471 */ 472 test SCB_CONTROL, TAG_ENB jz . + 3; 473 mvi MSG_SIMPLE_Q_TAG call target_outb; 474 mov SCB_TARGET_INFO[SCB_INITIATOR_TAG] call target_outb; 475target_synccmd: 476 /* 477 * Now determine what phases the host wants us 478 * to go through. 479 */ 480 mov SEQ_FLAGS, SCB_TARGET_INFO[SCB_TARGET_PHASES]; 481 482target_ITloop: 483 /* 484 * Start honoring ATN signals now that 485 * we properly identified ourselves. 486 */ 487 test SCSISIGI, ATNI jnz target_mesgout; 488 test SEQ_FLAGS, CMDPHASE_PENDING jnz target_cmdphase; 489 test SEQ_FLAGS, DPHASE_PENDING jnz target_dphase; 490 test SEQ_FLAGS, SPHASE_PENDING jnz target_sphase; 491 492 /* 493 * No more work to do. Either disconnect or not depending 494 * on the state of NO_DISCONNECT. 495 */ 496 test SEQ_FLAGS, NO_DISCONNECT jz target_disconnect; 497 if ((ahc->flags & AHC_PAGESCBS) != 0) { 498 mov ALLZEROS call get_free_or_disc_scb; 499 } 500 mov RETURN_1, ALLZEROS; 501 call complete_target_cmd; 502 cmp RETURN_1, CONT_MSG_LOOP jne .; 503 mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET; 504 mov SCB_TAG call dma_scb; 505 jmp target_synccmd; 506 507target_mesgout: 508 mvi SCSISIGO, P_MESGOUT|BSYO; 509target_mesgout_continue: 510 call target_inb; 511target_mesgout_pending: 512 /* Local Processing goes here... */ 513 jmp host_target_message_loop; 514 515target_disconnect: 516 mvi P_MESGIN|BSYO call change_phase; 517 test SEQ_FLAGS, DPHASE jz . + 2; 518 mvi MSG_SAVEDATAPOINTER call target_outb; 519 mvi MSG_DISCONNECT call target_outb; 520 521target_busfree_wait: 522 /* Wait for preceding I/O session to complete. */ 523 test SCSISIGI, ACKI jnz .; 524target_busfree: 525 and SIMODE1, ~ENBUSFREE; 526 if ((ahc->features & AHC_ULTRA2) != 0) { 527 clr SCSIBUSL; 528 } 529 clr SCSISIGO; 530 mvi LASTPHASE, P_BUSFREE; 531 call complete_target_cmd; 532 jmp poll_for_work; 533 534target_cmdphase: 535 mvi P_COMMAND|BSYO call change_phase; 536 call target_inb; 537 mov A, DINDEX; 538 /* Store for host */ 539 if ((ahc->features & AHC_CMD_CHAN) != 0) { 540 mov CCSCBRAM, A; 541 } else { 542 mov DFDAT, A; 543 } 544 545 /* 546 * Determine the number of bytes to read 547 * based on the command group code via table lookup. 548 * We reuse the first 8 bytes of the TARG_SCSIRATE 549 * BIOS array for this table. Count is one less than 550 * the total for the command since we've already fetched 551 * the first byte. 552 */ 553 shr A, CMD_GROUP_CODE_SHIFT; 554 add SINDEX, CMDSIZE_TABLE, A; 555 mov A, SINDIR; 556 557 test A, 0xFF jz command_phase_done; 558 or SXFRCTL0, SPIOEN; 559command_loop: 560 test SSTAT0, SPIORDY jz .; 561 cmp A, 1 jne . + 2; 562 and SXFRCTL0, ~SPIOEN; /* Last Byte */ 563 if ((ahc->features & AHC_CMD_CHAN) != 0) { 564 mov CCSCBRAM, SCSIDATL; 565 } else { 566 mov DFDAT, SCSIDATL; 567 } 568 dec A; 569 test A, 0xFF jnz command_loop; 570 571command_phase_done: 572 and SEQ_FLAGS, ~CMDPHASE_PENDING; 573 jmp target_ITloop; 574 575target_dphase: 576 /* 577 * Data phases on the bus are from the 578 * perspective of the initiator. The dma 579 * code looks at LASTPHASE to determine the 580 * data direction of the DMA. Toggle it for 581 * target transfers. 582 */ 583 xor LASTPHASE, IOI, SCB_TARGET_INFO[SCB_TARGET_DATA_DIR]; 584 or SCB_TARGET_INFO[SCB_TARGET_DATA_DIR], BSYO 585 call change_phase; 586 jmp p_data; 587 588target_sphase: 589 mvi P_STATUS|BSYO call change_phase; 590 mvi LASTPHASE, P_STATUS; 591 mov SCB_TARGET_INFO[SCB_TARGET_STATUS] call target_outb; 592 /* XXX Watch for ATN or parity errors??? */ 593 mvi SCSISIGO, P_MESGIN|BSYO; 594 /* MSG_CMDCMPLT is 0, but we can't do an immediate of 0 */ 595 mov ALLZEROS call target_outb; 596 jmp target_busfree_wait; 597 598complete_target_cmd: 599 test SEQ_FLAGS, TARG_CMD_PENDING jnz . + 2; 600 mov SCB_TAG jmp complete_post; 601 if ((ahc->features & AHC_CMD_CHAN) != 0) { 602 /* Set the valid byte */ 603 mvi CCSCBADDR, 24; 604 mov CCSCBRAM, ALLONES; 605 mvi CCHCNT, 28; 606 or CCSCBCTL, CCSCBEN|CCSCBRESET; 607 test CCSCBCTL, CCSCBDONE jz .; 608 clr CCSCBCTL; 609 } else { 610 /* Set the valid byte */ 611 or DFCNTRL, FIFORESET; 612 mvi DFWADDR, 3; /* Third 64bit word or byte 24 */ 613 mov DFDAT, ALLONES; 614 mvi 28 call set_hcnt; 615 or DFCNTRL, HDMAEN|FIFOFLUSH; 616 call dma_finish; 617 } 618 inc TQINPOS; 619 mvi INTSTAT,CMDCMPLT ret; 620 } 621 622if ((ahc->flags & AHC_INITIATORROLE) != 0) { 623initiator_select: 624 /* 625 * As soon as we get a successful selection, the target 626 * should go into the message out phase since we have ATN 627 * asserted. 628 */ 629 mvi MSG_OUT, MSG_IDENTIFYFLAG; 630 or SEQ_FLAGS, IDENTIFY_SEEN; 631 632 /* 633 * Main loop for information transfer phases. Wait for the 634 * target to assert REQ before checking MSG, C/D and I/O for 635 * the bus phase. 636 */ 637mesgin_phasemis: 638ITloop: 639 call phase_lock; 640 641 mov A, LASTPHASE; 642 643 test A, ~P_DATAIN jz p_data; 644 cmp A,P_COMMAND je p_command; 645 cmp A,P_MESGOUT je p_mesgout; 646 cmp A,P_STATUS je p_status; 647 cmp A,P_MESGIN je p_mesgin; 648 649 mvi BAD_PHASE call set_seqint; 650 jmp ITloop; /* Try reading the bus again. */ 651 652await_busfree: 653 and SIMODE1, ~ENBUSFREE; 654 mov NONE, SCSIDATL; /* Ack the last byte */ 655 if ((ahc->features & AHC_ULTRA2) != 0) { 656 clr SCSIBUSL; /* Prevent bit leakage durint SELTO */ 657 } 658 and SXFRCTL0, ~SPIOEN; 659 test SSTAT1,REQINIT|BUSFREE jz .; 660 test SSTAT1, BUSFREE jnz poll_for_work; 661 mvi MISSED_BUSFREE call set_seqint; 662} 663 664clear_target_state: 665 /* 666 * We assume that the kernel driver may reset us 667 * at any time, even in the middle of a DMA, so 668 * clear DFCNTRL too. 669 */ 670 clr DFCNTRL; 671 or SXFRCTL0, CLRSTCNT|CLRCHN; 672 673 /* 674 * We don't know the target we will connect to, 675 * so default to narrow transfers to avoid 676 * parity problems. 677 */ 678 if ((ahc->features & AHC_ULTRA2) != 0) { 679 bmov SCSIRATE, ALLZEROS, 2; 680 } else { 681 clr SCSIRATE; 682 if ((ahc->features & AHC_ULTRA) != 0) { 683 and SXFRCTL0, ~(FAST20); 684 } 685 } 686 mvi LASTPHASE, P_BUSFREE; 687 /* clear target specific flags */ 688 clr SEQ_FLAGS ret; 689 690sg_advance: 691 clr A; /* add sizeof(struct scatter) */ 692 add SCB_RESIDUAL_SGPTR[0],SG_SIZEOF; 693 adc SCB_RESIDUAL_SGPTR[1],A; 694 adc SCB_RESIDUAL_SGPTR[2],A; 695 adc SCB_RESIDUAL_SGPTR[3],A ret; 696 697if ((ahc->features & AHC_CMD_CHAN) != 0) { 698disable_ccsgen: 699 test CCSGCTL, CCSGEN jz return; 700 test CCSGCTL, CCSGDONE jz .; 701disable_ccsgen_fetch_done: 702 clr CCSGCTL; 703 test CCSGCTL, CCSGEN jnz .; 704 ret; 705idle_loop: 706 /* Did we just finish fetching segs? */ 707 cmp CCSGCTL, CCSGEN|CCSGDONE je idle_sgfetch_complete; 708 709 /* Are we actively fetching segments? */ 710 test CCSGCTL, CCSGEN jnz return; 711 712 /* 713 * Do we need any more segments? 714 */ 715 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jnz return; 716 717 /* 718 * Do we have any prefetch left??? 719 */ 720 cmp CCSGADDR, SG_PREFETCH_CNT jne idle_sg_avail; 721 722 /* 723 * Need to fetch segments, but we can only do that 724 * if the command channel is completely idle. Make 725 * sure we don't have an SCB prefetch going on. 726 */ 727 test CCSCBCTL, CCSCBEN jnz return; 728 729 /* 730 * We fetch a "cacheline aligned" and sized amount of data 731 * so we don't end up referencing a non-existant page. 732 * Cacheline aligned is in quotes because the kernel will 733 * set the prefetch amount to a reasonable level if the 734 * cacheline size is unknown. 735 */ 736 mvi CCHCNT, SG_PREFETCH_CNT; 737 and CCHADDR[0], SG_PREFETCH_ALIGN_MASK, SCB_RESIDUAL_SGPTR; 738 bmov CCHADDR[1], SCB_RESIDUAL_SGPTR[1], 3; 739 mvi CCSGCTL, CCSGEN|CCSGRESET ret; 740idle_sgfetch_complete: 741 call disable_ccsgen_fetch_done; 742 and CCSGADDR, SG_PREFETCH_ADDR_MASK, SCB_RESIDUAL_SGPTR; 743idle_sg_avail: 744 if ((ahc->features & AHC_ULTRA2) != 0) { 745 /* Does the hardware have space for another SG entry? */ 746 test DFSTATUS, PRELOAD_AVAIL jz return; 747 bmov HADDR, CCSGRAM, 4; 748 bmov SINDEX, CCSGRAM, 1; 749 test SINDEX, 0x1 jz . + 2; 750 xor DATA_COUNT_ODD, 0x1; 751 bmov HCNT[0], SINDEX, 1; 752 bmov HCNT[1], CCSGRAM, 2; 753 bmov SCB_RESIDUAL_DATACNT[3], CCSGRAM, 1; 754 call sg_advance; 755 mov SINDEX, SCB_RESIDUAL_SGPTR[0]; 756 test DATA_COUNT_ODD, 0x1 jz . + 2; 757 or SINDEX, ODD_SEG; 758 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 2; 759 or SINDEX, LAST_SEG; 760 mov SG_CACHE_PRE, SINDEX; 761 /* Load the segment by writing DFCNTRL again */ 762 mov DFCNTRL, DMAPARAMS; 763 } 764 ret; 765} 766 767if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0) { 768/* 769 * Calculate the trailing portion of this S/G segment that cannot 770 * be transferred using memory write and invalidate PCI transactions. 771 * XXX Can we optimize this for PCI writes only??? 772 */ 773calc_mwi_residual: 774 /* 775 * If the ending address is on a cacheline boundary, 776 * there is no need for an extra segment. 777 */ 778 mov A, HCNT[0]; 779 add A, A, HADDR[0]; 780 and A, CACHESIZE_MASK; 781 test A, 0xFF jz return; 782 783 /* 784 * If the transfer is less than a cachline, 785 * there is no need for an extra segment. 786 */ 787 test HCNT[1], 0xFF jnz calc_mwi_residual_final; 788 test HCNT[2], 0xFF jnz calc_mwi_residual_final; 789 add NONE, INVERTED_CACHESIZE_MASK, HCNT[0]; 790 jnc return; 791 792calc_mwi_residual_final: 793 mov MWI_RESIDUAL, A; 794 not A; 795 inc A; 796 add HCNT[0], A; 797 adc HCNT[1], -1; 798 adc HCNT[2], -1 ret; 799} 800 801/* 802 * If we re-enter the data phase after going through another phase, the 803 * STCNT may have been cleared, so restore it from the residual field. 804 */ 805data_phase_reinit: 806 if ((ahc->features & AHC_ULTRA2) != 0) { 807 /* 808 * The preload circuitry requires us to 809 * reload the address too, so pull it from 810 * the shaddow address. 811 */ 812 bmov HADDR, SHADDR, 4; 813 bmov HCNT, SCB_RESIDUAL_DATACNT, 3; 814 } else if ((ahc->features & AHC_CMD_CHAN) != 0) { 815 bmov STCNT, SCB_RESIDUAL_DATACNT, 3; 816 } else { 817 mvi DINDEX, STCNT; 818 mvi SCB_RESIDUAL_DATACNT call bcopy_3; 819 } 820 and DATA_COUNT_ODD, 0x1, SCB_RESIDUAL_DATACNT[0]; 821 jmp data_phase_loop; 822 823p_data: 824 if ((ahc->features & AHC_ULTRA2) != 0) { 825 mvi DMAPARAMS, PRELOADEN|SCSIEN|HDMAEN; 826 } else { 827 mvi DMAPARAMS, WIDEODD|SCSIEN|SDMAEN|HDMAEN|FIFORESET; 828 } 829 test LASTPHASE, IOI jnz . + 2; 830 or DMAPARAMS, DIRECTION; 831 call assert; /* 832 * Ensure entering a data 833 * phase is okay - seen identify, etc. 834 */ 835 if ((ahc->features & AHC_CMD_CHAN) != 0) { 836 /* We don't have any valid S/G elements */ 837 mvi CCSGADDR, SG_PREFETCH_CNT; 838 } 839 test SEQ_FLAGS, DPHASE jnz data_phase_reinit; 840 841 /* We have seen a data phase */ 842 or SEQ_FLAGS, DPHASE; 843 844 /* 845 * Initialize the DMA address and counter from the SCB. 846 * Also set SCB_RESIDUAL_SGPTR, including the LAST_SEG 847 * flag in the highest byte of the data count. We cannot 848 * modify the saved values in the SCB until we see a save 849 * data pointers message. 850 */ 851 if ((ahc->features & AHC_CMD_CHAN) != 0) { 852 bmov HADDR, SCB_DATAPTR, 7; 853 bmov SCB_RESIDUAL_DATACNT[3], SCB_DATACNT[3], 5; 854 } else { 855 mvi DINDEX, HADDR; 856 mvi SCB_DATAPTR call bcopy_7; 857 mvi DINDEX, SCB_RESIDUAL_DATACNT + 3; 858 mvi SCB_DATACNT + 3 call bcopy_5; 859 } 860 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0) { 861 call calc_mwi_residual; 862 } 863 and SCB_RESIDUAL_SGPTR[0], ~SG_FULL_RESID; 864 and DATA_COUNT_ODD, 0x1, HCNT[0]; 865 866 if ((ahc->features & AHC_ULTRA2) == 0) { 867 if ((ahc->features & AHC_CMD_CHAN) != 0) { 868 bmov STCNT, HCNT, 3; 869 } else { 870 call set_stcnt_from_hcnt; 871 } 872 } 873 874data_phase_loop: 875 /* Guard against overruns */ 876 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz data_phase_inbounds; 877 878 /* 879 * Turn on `Bit Bucket' mode, wait until the target takes 880 * us to another phase, and then notify the host. 881 */ 882 and DMAPARAMS, DIRECTION; 883 mov DFCNTRL, DMAPARAMS; 884 or SXFRCTL1,BITBUCKET; 885 test SSTAT1,PHASEMIS jz .; 886 and SXFRCTL1, ~BITBUCKET; 887 mvi DATA_OVERRUN call set_seqint; 888 jmp ITloop; 889 890data_phase_inbounds: 891 if ((ahc->features & AHC_ULTRA2) != 0) { 892 mov SINDEX, SCB_RESIDUAL_SGPTR[0]; 893 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 2; 894 or SINDEX, LAST_SEG; 895 test DATA_COUNT_ODD, 0x1 jz . + 2; 896 or SINDEX, ODD_SEG; 897 mov SG_CACHE_PRE, SINDEX; 898 mov DFCNTRL, DMAPARAMS; 899ultra2_dma_loop: 900 call idle_loop; 901 /* 902 * The transfer is complete if either the last segment 903 * completes or the target changes phase. 904 */ 905 test SG_CACHE_SHADOW, LAST_SEG_DONE jnz ultra2_dmafinish; 906 if ((ahc->flags & AHC_TARGETROLE) != 0) { 907 /* 908 * As a target, we control the phases, 909 * so ignore PHASEMIS. 910 */ 911 test SSTAT0, TARGET jnz ultra2_dma_loop; 912 } 913 if ((ahc->flags & AHC_INITIATORROLE) != 0) { 914 test SSTAT1,PHASEMIS jz ultra2_dma_loop; 915 } 916 917ultra2_dmafinish: 918 test DFCNTRL, DIRECTION jnz ultra2_dmafifoempty; 919 if ((ahc->features & AHC_DT) == 0) { 920 and DFCNTRL, ~SCSIEN; 921 test DFCNTRL, SCSIEN jnz .; 922 } 923ultra2_dmafifoflush: 924 if ((ahc->bugs & AHC_AUTOFLUSH_BUG) != 0) { 925 /* 926 * On Rev A of the aic7890, the autoflush 927 * features doesn't function correctly. 928 * Perform an explicit manual flush. During 929 * a manual flush, the FIFOEMP bit becomes 930 * true every time the PCI FIFO empties 931 * regardless of the state of the SCSI FIFO. 932 * It can take up to 4 clock cycles for the 933 * SCSI FIFO to get data into the PCI FIFO 934 * and for FIFOEMP to de-assert. Here we 935 * guard against this condition by making 936 * sure the FIFOEMP bit stays on for 5 full 937 * clock cycles. 938 */ 939 or DFCNTRL, FIFOFLUSH; 940 test DFSTATUS, FIFOEMP jz ultra2_dmafifoflush; 941 test DFSTATUS, FIFOEMP jz ultra2_dmafifoflush; 942 test DFSTATUS, FIFOEMP jz ultra2_dmafifoflush; 943 test DFSTATUS, FIFOEMP jz ultra2_dmafifoflush; 944 } 945 test DFSTATUS, FIFOEMP jz ultra2_dmafifoflush; 946ultra2_dmafifoempty: 947 /* Don't clobber an inprogress host data transfer */ 948 test DFSTATUS, MREQPEND jnz ultra2_dmafifoempty; 949ultra2_dmahalt: 950 and DFCNTRL, ~(SCSIEN|HDMAEN); 951 test DFCNTRL, HDMAEN jnz .; 952 953 /* 954 * If, by chance, we stopped before being able 955 * to fetch additional segments for this transfer, 956 * yet the last S/G was completely exhausted, 957 * call our idle loop until it is able to load 958 * another segment. This will allow us to immediately 959 * pickup on the next segment on the next data phase. 960 * 961 * If we happened to stop on the last segment, then 962 * our residual information is still correct from 963 * the idle loop and there is no need to perform 964 * any fixups. Just jump to data_phase_finish. 965 */ 966ultra2_ensure_sg: 967 test SG_CACHE_SHADOW, LAST_SEG jz ultra2_shvalid; 968 /* Record if we've consumed all S/G entries */ 969 test SG_CACHE_SHADOW, LAST_SEG_DONE jz data_phase_finish; 970 or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL; 971 jmp data_phase_finish; 972 973ultra2_shvalid: 974 test SSTAT2, SHVALID jnz sgptr_fixup; 975 call idle_loop; 976 jmp ultra2_ensure_sg; 977 978sgptr_fixup: 979 /* 980 * Fixup the residual next S/G pointer. The S/G preload 981 * feature of the chip allows us to load two elements 982 * in addition to the currently active element. We 983 * store the bottom byte of the next S/G pointer in 984 * the SG_CACEPTR register so we can restore the 985 * correct value when the DMA completes. If the next 986 * sg ptr value has advanced to the point where higher 987 * bytes in the address have been affected, fix them 988 * too. 989 */ 990 test SG_CACHE_SHADOW, 0x80 jz sgptr_fixup_done; 991 test SCB_RESIDUAL_SGPTR[0], 0x80 jnz sgptr_fixup_done; 992 add SCB_RESIDUAL_SGPTR[1], -1; 993 adc SCB_RESIDUAL_SGPTR[2], -1; 994 adc SCB_RESIDUAL_SGPTR[3], -1; 995sgptr_fixup_done: 996 and SCB_RESIDUAL_SGPTR[0], SG_ADDR_MASK, SG_CACHE_SHADOW; 997 clr DATA_COUNT_ODD; 998 test SG_CACHE_SHADOW, ODD_SEG jz . + 2; 999 or DATA_COUNT_ODD, 0x1; 1000 clr SCB_RESIDUAL_DATACNT[3]; /* We are not the last seg */ 1001 } else { 1002 /* If we are the last SG block, tell the hardware. */ 1003 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 1004 && ahc->pci_cachesize != 0) { 1005 test MWI_RESIDUAL, 0xFF jnz dma_mid_sg; 1006 } 1007 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz dma_mid_sg; 1008 if ((ahc->flags & AHC_TARGETROLE) != 0) { 1009 test SSTAT0, TARGET jz dma_last_sg; 1010 if ((ahc->flags & AHC_TMODE_WIDEODD_BUG) != 0) { 1011 test DMAPARAMS, DIRECTION jz dma_mid_sg; 1012 } 1013 } 1014dma_last_sg: 1015 and DMAPARAMS, ~WIDEODD; 1016dma_mid_sg: 1017 /* Start DMA data transfer. */ 1018 mov DFCNTRL, DMAPARAMS; 1019dma_loop: 1020 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1021 call idle_loop; 1022 } 1023 test SSTAT0,DMADONE jnz dma_dmadone; 1024 test SSTAT1,PHASEMIS jz dma_loop; /* ie. underrun */ 1025dma_phasemis: 1026 /* 1027 * We will be "done" DMAing when the transfer count goes to 1028 * zero, or the target changes the phase (in light of this, 1029 * it makes sense that the DMA circuitry doesn't ACK when 1030 * PHASEMIS is active). If we are doing a SCSI->Host transfer, 1031 * the data FIFO should be flushed auto-magically on STCNT=0 1032 * or a phase change, so just wait for FIFO empty status. 1033 */ 1034dma_checkfifo: 1035 test DFCNTRL,DIRECTION jnz dma_fifoempty; 1036dma_fifoflush: 1037 test DFSTATUS,FIFOEMP jz dma_fifoflush; 1038dma_fifoempty: 1039 /* Don't clobber an inprogress host data transfer */ 1040 test DFSTATUS, MREQPEND jnz dma_fifoempty; 1041 1042 /* 1043 * Now shut off the DMA and make sure that the DMA 1044 * hardware has actually stopped. Touching the DMA 1045 * counters, etc. while a DMA is active will result 1046 * in an ILLSADDR exception. 1047 */ 1048dma_dmadone: 1049 and DFCNTRL, ~(SCSIEN|SDMAEN|HDMAEN); 1050dma_halt: 1051 /* 1052 * Some revisions of the aic78XX have a problem where, if the 1053 * data fifo is full, but the PCI input latch is not empty, 1054 * HDMAEN cannot be cleared. The fix used here is to drain 1055 * the prefetched but unused data from the data fifo until 1056 * there is space for the input latch to drain. 1057 */ 1058 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0) { 1059 mov NONE, DFDAT; 1060 } 1061 test DFCNTRL, (SCSIEN|SDMAEN|HDMAEN) jnz dma_halt; 1062 1063 /* See if we have completed this last segment */ 1064 test STCNT[0], 0xff jnz data_phase_finish; 1065 test STCNT[1], 0xff jnz data_phase_finish; 1066 test STCNT[2], 0xff jnz data_phase_finish; 1067 1068 /* 1069 * Advance the scatter-gather pointers if needed 1070 */ 1071 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 1072 && ahc->pci_cachesize != 0) { 1073 test MWI_RESIDUAL, 0xFF jz no_mwi_resid; 1074 /* 1075 * Reload HADDR from SHADDR and setup the 1076 * count to be the size of our residual. 1077 */ 1078 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1079 bmov HADDR, SHADDR, 4; 1080 mov HCNT, MWI_RESIDUAL; 1081 bmov HCNT[1], ALLZEROS, 2; 1082 } else { 1083 mvi DINDEX, HADDR; 1084 mvi SHADDR call bcopy_4; 1085 mov MWI_RESIDUAL call set_hcnt; 1086 } 1087 clr MWI_RESIDUAL; 1088 jmp sg_load_done; 1089no_mwi_resid: 1090 } 1091 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz sg_load; 1092 or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL; 1093 jmp data_phase_finish; 1094sg_load: 1095 /* 1096 * Load the next SG element's data address and length 1097 * into the DMA engine. If we don't have hardware 1098 * to perform a prefetch, we'll have to fetch the 1099 * segment from host memory first. 1100 */ 1101 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1102 /* Wait for the idle loop to complete */ 1103 test CCSGCTL, CCSGEN jz . + 3; 1104 call idle_loop; 1105 test CCSGCTL, CCSGEN jnz . - 1; 1106 bmov HADDR, CCSGRAM, 7; 1107 test CCSGRAM, SG_LAST_SEG jz . + 2; 1108 or SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG; 1109 } else { 1110 mvi DINDEX, HADDR; 1111 mvi SCB_RESIDUAL_SGPTR call bcopy_4; 1112 1113 mvi SG_SIZEOF call set_hcnt; 1114 1115 or DFCNTRL, HDMAEN|DIRECTION|FIFORESET; 1116 1117 call dma_finish; 1118 1119 mvi DINDEX, HADDR; 1120 call dfdat_in_7; 1121 mov SCB_RESIDUAL_DATACNT[3], DFDAT; 1122 } 1123 1124 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 1125 && ahc->pci_cachesize != 0) { 1126 call calc_mwi_residual; 1127 } 1128 1129 /* Point to the new next sg in memory */ 1130 call sg_advance; 1131 1132sg_load_done: 1133 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1134 bmov STCNT, HCNT, 3; 1135 } else { 1136 call set_stcnt_from_hcnt; 1137 } 1138 /* Track odd'ness */ 1139 test HCNT[0], 0x1 jz . + 2; 1140 xor DATA_COUNT_ODD, 0x1; 1141 1142 if ((ahc->flags & AHC_TARGETROLE) != 0) { 1143 test SSTAT0, TARGET jnz data_phase_loop; 1144 } 1145 } 1146data_phase_finish: 1147 /* 1148 * If the target has left us in data phase, loop through 1149 * the dma code again. In the case of ULTRA2 adapters, 1150 * we should only loop if there is a data overrun. For 1151 * all other adapters, we'll loop after each S/G element 1152 * is loaded as well as if there is an overrun. 1153 */ 1154 if ((ahc->flags & AHC_TARGETROLE) != 0) { 1155 test SSTAT0, TARGET jnz data_phase_done; 1156 } 1157 if ((ahc->flags & AHC_INITIATORROLE) != 0) { 1158 test SSTAT1, REQINIT jz .; 1159 test SSTAT1,PHASEMIS jz data_phase_loop; 1160 } 1161 1162data_phase_done: 1163 /* 1164 * After a DMA finishes, save the SG and STCNT residuals back into 1165 * the SCB. We use STCNT instead of HCNT, since it's a reflection 1166 * of how many bytes were transferred on the SCSI (as opposed to the 1167 * host) bus. 1168 */ 1169 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1170 /* Kill off any pending prefetch */ 1171 call disable_ccsgen; 1172 } 1173 1174 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 1175 && ahc->pci_cachesize != 0) { 1176 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1177 test MWI_RESIDUAL, 0xFF jz bmov_resid; 1178 } 1179 mov A, MWI_RESIDUAL; 1180 add SCB_RESIDUAL_DATACNT[0], A, STCNT[0]; 1181 clr A; 1182 adc SCB_RESIDUAL_DATACNT[1], A, STCNT[1]; 1183 adc SCB_RESIDUAL_DATACNT[2], A, STCNT[2]; 1184 clr MWI_RESIDUAL; 1185 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1186 jmp . + 2; 1187bmov_resid: 1188 bmov SCB_RESIDUAL_DATACNT, STCNT, 3; 1189 } 1190 } else if ((ahc->features & AHC_CMD_CHAN) != 0) { 1191 bmov SCB_RESIDUAL_DATACNT, STCNT, 3; 1192 } else { 1193 mov SCB_RESIDUAL_DATACNT[0], STCNT[0]; 1194 mov SCB_RESIDUAL_DATACNT[1], STCNT[1]; 1195 mov SCB_RESIDUAL_DATACNT[2], STCNT[2]; 1196 } 1197 1198 /* 1199 * Since we've been through a data phase, the SCB_RESID* fields 1200 * are now initialized. Clear the full residual flag. 1201 */ 1202 and SCB_SGPTR[0], ~SG_FULL_RESID; 1203 1204 if ((ahc->features & AHC_ULTRA2) != 0) { 1205 /* Clear the channel in case we return to data phase later */ 1206 or SXFRCTL0, CLRSTCNT|CLRCHN; 1207 or SXFRCTL0, CLRSTCNT|CLRCHN; 1208 } 1209 1210 if ((ahc->flags & AHC_TARGETROLE) != 0) { 1211 test SEQ_FLAGS, DPHASE_PENDING jz ITloop; 1212 and SEQ_FLAGS, ~DPHASE_PENDING; 1213 /* 1214 * For data-in phases, wait for any pending acks from the 1215 * initiator before changing phase. 1216 */ 1217 test DFCNTRL, DIRECTION jz target_ITloop; 1218 test SSTAT1, REQINIT jnz .; 1219 jmp target_ITloop; 1220 } else { 1221 jmp ITloop; 1222 } 1223 1224if ((ahc->flags & AHC_INITIATORROLE) != 0) { 1225/* 1226 * Command phase. Set up the DMA registers and let 'er rip. 1227 */ 1228p_command: 1229 call assert; 1230 1231 if ((ahc->features & AHC_ULTRA2) != 0) { 1232 bmov HCNT[0], SCB_CDB_LEN, 1; 1233 bmov HCNT[1], ALLZEROS, 2; 1234 mvi SG_CACHE_PRE, LAST_SEG; 1235 } else if ((ahc->features & AHC_CMD_CHAN) != 0) { 1236 bmov STCNT[0], SCB_CDB_LEN, 1; 1237 bmov STCNT[1], ALLZEROS, 2; 1238 } else { 1239 mov STCNT[0], SCB_CDB_LEN; 1240 clr STCNT[1]; 1241 clr STCNT[2]; 1242 } 1243 add NONE, -13, SCB_CDB_LEN; 1244 mvi SCB_CDB_STORE jnc p_command_embedded; 1245p_command_from_host: 1246 if ((ahc->features & AHC_ULTRA2) != 0) { 1247 bmov HADDR[0], SCB_CDB_PTR, 4; 1248 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN|DIRECTION); 1249 } else { 1250 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1251 bmov HADDR[0], SCB_CDB_PTR, 4; 1252 bmov HCNT, STCNT, 3; 1253 } else { 1254 mvi DINDEX, HADDR; 1255 mvi SCB_CDB_PTR call bcopy_4; 1256 mov SCB_CDB_LEN call set_hcnt; 1257 } 1258 mvi DFCNTRL, (SCSIEN|SDMAEN|HDMAEN|DIRECTION|FIFORESET); 1259 } 1260 jmp p_command_loop; 1261p_command_embedded: 1262 /* 1263 * The data fifo seems to require 4 byte alligned 1264 * transfers from the sequencer. Force this to 1265 * be the case by clearing HADDR[0] even though 1266 * we aren't going to touch host memeory. 1267 */ 1268 clr HADDR[0]; 1269 if ((ahc->features & AHC_ULTRA2) != 0) { 1270 mvi DFCNTRL, (PRELOADEN|SCSIEN|DIRECTION); 1271 bmov DFDAT, SCB_CDB_STORE, 12; 1272 } else if ((ahc->features & AHC_CMD_CHAN) != 0) { 1273 if ((ahc->flags & AHC_SCB_BTT) != 0) { 1274 /* 1275 * On the 7895 the data FIFO will 1276 * get corrupted if you try to dump 1277 * data from external SCB memory into 1278 * the FIFO while it is enabled. So, 1279 * fill the fifo and then enable SCSI 1280 * transfers. 1281 */ 1282 mvi DFCNTRL, (DIRECTION|FIFORESET); 1283 } else { 1284 mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFORESET); 1285 } 1286 bmov DFDAT, SCB_CDB_STORE, 12; 1287 if ((ahc->flags & AHC_SCB_BTT) != 0) { 1288 mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFOFLUSH); 1289 } else { 1290 or DFCNTRL, FIFOFLUSH; 1291 } 1292 } else { 1293 mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFORESET); 1294 call copy_to_fifo_6; 1295 call copy_to_fifo_6; 1296 or DFCNTRL, FIFOFLUSH; 1297 } 1298p_command_loop: 1299 test SSTAT0, SDONE jnz . + 2; 1300 test SSTAT1, PHASEMIS jz p_command_loop; 1301 /* 1302 * Wait for our ACK to go-away on it's own 1303 * instead of being killed by SCSIEN getting cleared. 1304 */ 1305 test SCSISIGI, ACKI jnz .; 1306 and DFCNTRL, ~(SCSIEN|SDMAEN|HDMAEN); 1307 test DFCNTRL, (SCSIEN|SDMAEN|HDMAEN) jnz .; 1308 if ((ahc->features & AHC_ULTRA2) != 0) { 1309 /* Drop any residual from the S/G Preload queue */ 1310 or SXFRCTL0, CLRSTCNT; 1311 } 1312 jmp ITloop; 1313 1314/* 1315 * Status phase. Wait for the data byte to appear, then read it 1316 * and store it into the SCB. 1317 */ 1318p_status: 1319 call assert; 1320 1321 mov SCB_SCSI_STATUS, SCSIDATL; 1322 jmp ITloop; 1323 1324/* 1325 * Message out phase. If MSG_OUT is MSG_IDENTIFYFLAG, build a full 1326 * indentify message sequence and send it to the target. The host may 1327 * override this behavior by setting the MK_MESSAGE bit in the SCB 1328 * control byte. This will cause us to interrupt the host and allow 1329 * it to handle the message phase completely on its own. If the bit 1330 * associated with this target is set, we will also interrupt the host, 1331 * thereby allowing it to send a message on the next selection regardless 1332 * of the transaction being sent. 1333 * 1334 * If MSG_OUT is == HOST_MSG, also interrupt the host and take a message. 1335 * This is done to allow the host to send messages outside of an identify 1336 * sequence while protecting the seqencer from testing the MK_MESSAGE bit 1337 * on an SCB that might not be for the current nexus. (For example, a 1338 * BDR message in responce to a bad reselection would leave us pointed to 1339 * an SCB that doesn't have anything to do with the current target). 1340 * 1341 * Otherwise, treat MSG_OUT as a 1 byte message to send (abort, abort tag, 1342 * bus device reset). 1343 * 1344 * When there are no messages to send, MSG_OUT should be set to MSG_NOOP, 1345 * in case the target decides to put us in this phase for some strange 1346 * reason. 1347 */ 1348p_mesgout_retry: 1349 or SCSISIGO,ATNO,LASTPHASE;/* turn on ATN for the retry */ 1350p_mesgout: 1351 mov SINDEX, MSG_OUT; 1352 cmp SINDEX, MSG_IDENTIFYFLAG jne p_mesgout_from_host; 1353 test SCB_CONTROL,MK_MESSAGE jnz host_message_loop; 1354 mov FUNCTION1, SCB_SCSIID; 1355 mov A, FUNCTION1; 1356 mov SINDEX, TARGET_MSG_REQUEST[0]; 1357 if ((ahc->features & AHC_TWIN) != 0) { 1358 /* Second Channel uses high byte bits */ 1359 test SCB_SCSIID, TWIN_CHNLB jz . + 2; 1360 mov SINDEX, TARGET_MSG_REQUEST[1]; 1361 } else if ((ahc->features & AHC_WIDE) != 0) { 1362 test SCB_SCSIID, 0x80 jz . + 2; /* target > 7 */ 1363 mov SINDEX, TARGET_MSG_REQUEST[1]; 1364 } 1365 test SINDEX, A jnz host_message_loop; 1366p_mesgout_identify: 1367 or SINDEX, MSG_IDENTIFYFLAG|DISCENB, SCB_LUN; 1368 test SCB_CONTROL, DISCENB jnz . + 2; 1369 and SINDEX, ~DISCENB; 1370/* 1371 * Send a tag message if TAG_ENB is set in the SCB control block. 1372 * Use SCB_TAG (the position in the kernel's SCB array) as the tag value. 1373 */ 1374p_mesgout_tag: 1375 test SCB_CONTROL,TAG_ENB jz p_mesgout_onebyte; 1376 mov SCSIDATL, SINDEX; /* Send the identify message */ 1377 call phase_lock; 1378 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done; 1379 and SCSIDATL,TAG_ENB|SCB_TAG_TYPE,SCB_CONTROL; 1380 call phase_lock; 1381 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done; 1382 mov SCB_TAG jmp p_mesgout_onebyte; 1383/* 1384 * Interrupt the driver, and allow it to handle this message 1385 * phase and any required retries. 1386 */ 1387p_mesgout_from_host: 1388 cmp SINDEX, HOST_MSG jne p_mesgout_onebyte; 1389 jmp host_message_loop; 1390 1391p_mesgout_onebyte: 1392 mvi CLRSINT1, CLRATNO; 1393 mov SCSIDATL, SINDEX; 1394 1395/* 1396 * If the next bus phase after ATN drops is message out, it means 1397 * that the target is requesting that the last message(s) be resent. 1398 */ 1399 call phase_lock; 1400 cmp LASTPHASE, P_MESGOUT je p_mesgout_retry; 1401 1402p_mesgout_done: 1403 mvi CLRSINT1,CLRATNO; /* Be sure to turn ATNO off */ 1404 mov LAST_MSG, MSG_OUT; 1405 mvi MSG_OUT, MSG_NOOP; /* No message left */ 1406 jmp ITloop; 1407 1408/* 1409 * Message in phase. Bytes are read using Automatic PIO mode. 1410 */ 1411p_mesgin: 1412 mvi ACCUM call inb_first; /* read the 1st message byte */ 1413 1414 test A,MSG_IDENTIFYFLAG jnz mesgin_identify; 1415 cmp A,MSG_DISCONNECT je mesgin_disconnect; 1416 cmp A,MSG_SAVEDATAPOINTER je mesgin_sdptrs; 1417 cmp ALLZEROS,A je mesgin_complete; 1418 cmp A,MSG_RESTOREPOINTERS je mesgin_rdptrs; 1419 cmp A,MSG_IGN_WIDE_RESIDUE je mesgin_ign_wide_residue; 1420 cmp A,MSG_NOOP je mesgin_done; 1421 1422/* 1423 * Pushed message loop to allow the kernel to 1424 * run it's own message state engine. To avoid an 1425 * extra nop instruction after signaling the kernel, 1426 * we perform the phase_lock before checking to see 1427 * if we should exit the loop and skip the phase_lock 1428 * in the ITloop. Performing back to back phase_locks 1429 * shouldn't hurt, but why do it twice... 1430 */ 1431host_message_loop: 1432 mvi HOST_MSG_LOOP call set_seqint; 1433 call phase_lock; 1434 cmp RETURN_1, EXIT_MSG_LOOP je ITloop + 1; 1435 jmp host_message_loop; 1436 1437mesgin_ign_wide_residue: 1438if ((ahc->features & AHC_WIDE) != 0) { 1439 test SCSIRATE, WIDEXFER jz mesgin_reject; 1440 /* Pull the residue byte */ 1441 mvi ARG_1 call inb_next; 1442 cmp ARG_1, 0x01 jne mesgin_reject; 1443 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz . + 2; 1444 test DATA_COUNT_ODD, 0x1 jz mesgin_done; 1445 mvi IGN_WIDE_RES call set_seqint; 1446 jmp mesgin_done; 1447} 1448 1449mesgin_reject: 1450 mvi MSG_MESSAGE_REJECT call mk_mesg; 1451mesgin_done: 1452 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/ 1453 jmp ITloop; 1454 1455mesgin_complete: 1456/* 1457 * We received a "command complete" message. Put the SCB_TAG into the QOUTFIFO, 1458 * and trigger a completion interrupt. Before doing so, check to see if there 1459 * is a residual or the status byte is something other than STATUS_GOOD (0). 1460 * In either of these conditions, we upload the SCB back to the host so it can 1461 * process this information. In the case of a non zero status byte, we 1462 * additionally interrupt the kernel driver synchronously, allowing it to 1463 * decide if sense should be retrieved. If the kernel driver wishes to request 1464 * sense, it will fill the kernel SCB with a request sense command, requeue 1465 * it to the QINFIFO and tell us not to post to the QOUTFIFO by setting 1466 * RETURN_1 to SEND_SENSE. 1467 */ 1468 1469/* 1470 * If ATN is raised, we still want to give the target a message. 1471 * Perhaps there was a parity error on this last message byte. 1472 * Either way, the target should take us to message out phase 1473 * and then attempt to complete the command again. We should use a 1474 * critical section here to guard against a timeout triggering 1475 * for this command and setting ATN while we are still processing 1476 * the completion. 1477 test SCSISIGI, ATNI jnz mesgin_done; 1478 */ 1479 1480/* 1481 * See if we attempted to deliver a message but the target ingnored us. 1482 */ 1483 test SCB_CONTROL, MK_MESSAGE jz . + 2; 1484 mvi MKMSG_FAILED call set_seqint; 1485 1486/* 1487 * Check for residuals 1488 */ 1489 test SCB_SGPTR, SG_LIST_NULL jnz check_status;/* No xfer */ 1490 test SCB_SGPTR, SG_FULL_RESID jnz upload_scb;/* Never xfered */ 1491 test SCB_RESIDUAL_SGPTR, SG_LIST_NULL jz upload_scb; 1492check_status: 1493 test SCB_SCSI_STATUS,0xff jz complete; /* Good Status? */ 1494upload_scb: 1495 or SCB_SGPTR, SG_RESID_VALID; 1496 mvi DMAPARAMS, FIFORESET; 1497 mov SCB_TAG call dma_scb; 1498 test SCB_SCSI_STATUS, 0xff jz complete; /* Just a residual? */ 1499 mvi BAD_STATUS call set_seqint; /* let driver know */ 1500 cmp RETURN_1, SEND_SENSE jne complete; 1501 call add_scb_to_free_list; 1502 jmp await_busfree; 1503complete: 1504 mov SCB_TAG call complete_post; 1505 jmp await_busfree; 1506} 1507 1508complete_post: 1509 /* Post the SCBID in SINDEX and issue an interrupt */ 1510 call add_scb_to_free_list; 1511 mov ARG_1, SINDEX; 1512 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 1513 mov A, SDSCB_QOFF; 1514 } else { 1515 mov A, QOUTPOS; 1516 } 1517 mvi QOUTFIFO_OFFSET call post_byte_setup; 1518 mov ARG_1 call post_byte; 1519 if ((ahc->features & AHC_QUEUE_REGS) == 0) { 1520 inc QOUTPOS; 1521 } 1522 mvi INTSTAT,CMDCMPLT ret; 1523 1524if ((ahc->flags & AHC_INITIATORROLE) != 0) { 1525/* 1526 * Is it a disconnect message? Set a flag in the SCB to remind us 1527 * and await the bus going free. If this is an untagged transaction 1528 * store the SCB id for it in our untagged target table for lookup on 1529 * a reselction. 1530 */ 1531mesgin_disconnect: 1532 /* 1533 * If ATN is raised, we still want to give the target a message. 1534 * Perhaps there was a parity error on this last message byte 1535 * or we want to abort this command. Either way, the target 1536 * should take us to message out phase and then attempt to 1537 * disconnect again. 1538 * XXX - Wait for more testing. 1539 test SCSISIGI, ATNI jnz mesgin_done; 1540 */ 1541 1542 or SCB_CONTROL,DISCONNECTED; 1543 if ((ahc->flags & AHC_PAGESCBS) != 0) { 1544 call add_scb_to_disc_list; 1545 } 1546 test SCB_CONTROL, TAG_ENB jnz await_busfree; 1547 mov ARG_1, SCB_TAG; 1548 mov SAVED_LUN, SCB_LUN; 1549 mov SCB_SCSIID call set_busy_target; 1550 jmp await_busfree; 1551 1552/* 1553 * Save data pointers message: 1554 * Copying RAM values back to SCB, for Save Data Pointers message, but 1555 * only if we've actually been into a data phase to change them. This 1556 * protects against bogus data in scratch ram and the residual counts 1557 * since they are only initialized when we go into data_in or data_out. 1558 */ 1559mesgin_sdptrs: 1560 test SEQ_FLAGS, DPHASE jz mesgin_done; 1561 1562 /* 1563 * The SCB_SGPTR becomes the next one we'll download, 1564 * and the SCB_DATAPTR becomes the current SHADDR. 1565 * Use the residual number since STCNT is corrupted by 1566 * any message transfer. 1567 */ 1568 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1569 bmov SCB_DATAPTR, SHADDR, 4; 1570 bmov SCB_DATACNT, SCB_RESIDUAL_DATACNT, 8; 1571 } else { 1572 mvi DINDEX, SCB_DATAPTR; 1573 mvi SHADDR call bcopy_4; 1574 mvi SCB_RESIDUAL_DATACNT call bcopy_8; 1575 } 1576 jmp mesgin_done; 1577 1578/* 1579 * Restore pointers message? Data pointers are recopied from the 1580 * SCB anytime we enter a data phase for the first time, so all 1581 * we need to do is clear the DPHASE flag and let the data phase 1582 * code do the rest. 1583 */ 1584mesgin_rdptrs: 1585 and SEQ_FLAGS, ~DPHASE; /* 1586 * We'll reload them 1587 * the next time through 1588 * the dataphase. 1589 */ 1590 jmp mesgin_done; 1591 1592/* 1593 * Index into our Busy Target table. SINDEX and DINDEX are modified 1594 * upon return. SCBPTR may be modified by this action. 1595 */ 1596set_busy_target: 1597 shr DINDEX, 4, SINDEX; 1598 if ((ahc->flags & AHC_SCB_BTT) != 0) { 1599 mov SCBPTR, SAVED_LUN; 1600 add DINDEX, SCB_64_BTT; 1601 } else { 1602 add DINDEX, BUSY_TARGETS; 1603 } 1604 mov DINDIR, ARG_1 ret; 1605 1606/* 1607 * Identify message? For a reconnecting target, this tells us the lun 1608 * that the reconnection is for - find the correct SCB and switch to it, 1609 * clearing the "disconnected" bit so we don't "find" it by accident later. 1610 */ 1611mesgin_identify: 1612 /* 1613 * Determine whether a target is using tagged or non-tagged 1614 * transactions by first looking at the transaction stored in 1615 * the busy target array. If there is no untagged transaction 1616 * for this target or the transaction is for a different lun, then 1617 * this must be an untagged transaction. 1618 */ 1619 shr SINDEX, 4, SAVED_SCSIID; 1620 and SAVED_LUN, MSG_IDENTIFY_LUNMASK, A; 1621 if ((ahc->flags & AHC_SCB_BTT) != 0) { 1622 add SINDEX, SCB_64_BTT; 1623 mov SCBPTR, SAVED_LUN; 1624 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 1625 add NONE, -SCB_64_BTT, SINDEX; 1626 jc . + 2; 1627 mvi INTSTAT, OUT_OF_RANGE; 1628 nop; 1629 add NONE, -(SCB_64_BTT + 16), SINDEX; 1630 jnc . + 2; 1631 mvi INTSTAT, OUT_OF_RANGE; 1632 nop; 1633 } 1634 } else { 1635 add SINDEX, BUSY_TARGETS; 1636 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 1637 add NONE, -BUSY_TARGETS, SINDEX; 1638 jc . + 2; 1639 mvi INTSTAT, OUT_OF_RANGE; 1640 nop; 1641 add NONE, -(BUSY_TARGETS + 16), SINDEX; 1642 jnc . + 2; 1643 mvi INTSTAT, OUT_OF_RANGE; 1644 nop; 1645 } 1646 } 1647 mov ARG_1, SINDIR; 1648 cmp ARG_1, SCB_LIST_NULL je snoop_tag; 1649 if ((ahc->flags & AHC_PAGESCBS) != 0) { 1650 mov ARG_1 call findSCB; 1651 } else { 1652 mov SCBPTR, ARG_1; 1653 } 1654 if ((ahc->flags & AHC_SCB_BTT) != 0) { 1655 jmp setup_SCB_id_lun_okay; 1656 } else { 1657 /* 1658 * We only allow one untagged command per-target 1659 * at a time. So, if the lun doesn't match, look 1660 * for a tag message. 1661 */ 1662 mov A, SCB_LUN; 1663 cmp SAVED_LUN, A je setup_SCB_id_lun_okay; 1664 if ((ahc->flags & AHC_PAGESCBS) != 0) { 1665 /* 1666 * findSCB removes the SCB from the 1667 * disconnected list, so we must replace 1668 * it there should this SCB be for another 1669 * lun. 1670 */ 1671 call cleanup_scb; 1672 } 1673 } 1674 1675/* 1676 * Here we "snoop" the bus looking for a SIMPLE QUEUE TAG message. 1677 * If we get one, we use the tag returned to find the proper 1678 * SCB. With SCB paging, we must search for non-tagged 1679 * transactions since the SCB may exist in any slot. If we're not 1680 * using SCB paging, we can use the tag as the direct index to the 1681 * SCB. 1682 */ 1683snoop_tag: 1684 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 1685 or SEQ_FLAGS, 0x80; 1686 } 1687 mov NONE,SCSIDATL; /* ACK Identify MSG */ 1688 call phase_lock; 1689 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 1690 or SEQ_FLAGS, 0x1; 1691 } 1692 cmp LASTPHASE, P_MESGIN jne not_found; 1693 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 1694 or SEQ_FLAGS, 0x2; 1695 } 1696 cmp SCSIBUSL,MSG_SIMPLE_Q_TAG jne not_found; 1697get_tag: 1698 if ((ahc->flags & AHC_PAGESCBS) != 0) { 1699 mvi ARG_1 call inb_next; /* tag value */ 1700 mov ARG_1 call findSCB; 1701 } else { 1702 mvi ARG_1 call inb_next; /* tag value */ 1703 mov SCBPTR, ARG_1; 1704 } 1705 1706/* 1707 * Ensure that the SCB the tag points to is for 1708 * an SCB transaction to the reconnecting target. 1709 */ 1710setup_SCB: 1711 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 1712 or SEQ_FLAGS, 0x4; 1713 } 1714 mov A, SCB_SCSIID; 1715 cmp SAVED_SCSIID, A jne not_found_cleanup_scb; 1716 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 1717 or SEQ_FLAGS, 0x8; 1718 } 1719setup_SCB_id_okay: 1720 mov A, SCB_LUN; 1721 cmp SAVED_LUN, A jne not_found_cleanup_scb; 1722setup_SCB_id_lun_okay: 1723 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 1724 or SEQ_FLAGS, 0x10; 1725 } 1726 test SCB_CONTROL,DISCONNECTED jz not_found_cleanup_scb; 1727 and SCB_CONTROL,~DISCONNECTED; 1728 test SCB_CONTROL, TAG_ENB jnz setup_SCB_tagged; 1729 if ((ahc->flags & AHC_SCB_BTT) != 0) { 1730 mov A, SCBPTR; 1731 } 1732 mvi ARG_1, SCB_LIST_NULL; 1733 mov SAVED_SCSIID call set_busy_target; 1734 if ((ahc->flags & AHC_SCB_BTT) != 0) { 1735 mov SCBPTR, A; 1736 } 1737setup_SCB_tagged: 1738 mvi SEQ_FLAGS,IDENTIFY_SEEN; /* make note of IDENTIFY */ 1739 call set_transfer_settings; 1740 /* See if the host wants to send a message upon reconnection */ 1741 test SCB_CONTROL, MK_MESSAGE jz mesgin_done; 1742 mvi HOST_MSG call mk_mesg; 1743 jmp mesgin_done; 1744 1745not_found_cleanup_scb: 1746 if ((ahc->flags & AHC_PAGESCBS) != 0) { 1747 call cleanup_scb; 1748 } 1749not_found: 1750 mvi NO_MATCH call set_seqint; 1751 jmp mesgin_done; 1752 1753mk_mesg: 1754 or SCSISIGO,ATNO,LASTPHASE;/* turn on ATNO */ 1755 mov MSG_OUT,SINDEX ret; 1756 1757/* 1758 * Functions to read data in Automatic PIO mode. 1759 * 1760 * According to Adaptec's documentation, an ACK is not sent on input from 1761 * the target until SCSIDATL is read from. So we wait until SCSIDATL is 1762 * latched (the usual way), then read the data byte directly off the bus 1763 * using SCSIBUSL. When we have pulled the ATN line, or we just want to 1764 * acknowledge the byte, then we do a dummy read from SCISDATL. The SCSI 1765 * spec guarantees that the target will hold the data byte on the bus until 1766 * we send our ACK. 1767 * 1768 * The assumption here is that these are called in a particular sequence, 1769 * and that REQ is already set when inb_first is called. inb_{first,next} 1770 * use the same calling convention as inb. 1771 */ 1772inb_next_wait_perr: 1773 mvi PERR_DETECTED call set_seqint; 1774 jmp inb_next_wait; 1775inb_next: 1776 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/ 1777inb_next_wait: 1778 /* 1779 * If there is a parity error, wait for the kernel to 1780 * see the interrupt and prepare our message response 1781 * before continuing. 1782 */ 1783 test SSTAT1, REQINIT jz inb_next_wait; 1784 test SSTAT1, SCSIPERR jnz inb_next_wait_perr; 1785inb_next_check_phase: 1786 and LASTPHASE, PHASE_MASK, SCSISIGI; 1787 cmp LASTPHASE, P_MESGIN jne mesgin_phasemis; 1788inb_first: 1789 mov DINDEX,SINDEX; 1790 mov DINDIR,SCSIBUSL ret; /*read byte directly from bus*/ 1791inb_last: 1792 mov NONE,SCSIDATL ret; /*dummy read from latch to ACK*/ 1793} 1794 1795if ((ahc->flags & AHC_TARGETROLE) != 0) { 1796/* 1797 * Change to a new phase. If we are changing the state of the I/O signal, 1798 * from out to in, wait an additional data release delay before continuing. 1799 */ 1800change_phase: 1801 /* Wait for preceding I/O session to complete. */ 1802 test SCSISIGI, ACKI jnz .; 1803 1804 /* Change the phase */ 1805 and DINDEX, IOI, SCSISIGI; 1806 mov SCSISIGO, SINDEX; 1807 and A, IOI, SINDEX; 1808 1809 /* 1810 * If the data direction has changed, from 1811 * out (initiator driving) to in (target driving), 1812 * we must wait at least a data release delay plus 1813 * the normal bus settle delay. [SCSI III SPI 10.11.0] 1814 */ 1815 cmp DINDEX, A je change_phase_wait; 1816 test SINDEX, IOI jz change_phase_wait; 1817 call change_phase_wait; 1818change_phase_wait: 1819 nop; 1820 nop; 1821 nop; 1822 nop ret; 1823 1824/* 1825 * Send a byte to an initiator in Automatic PIO mode. 1826 */ 1827target_outb: 1828 or SXFRCTL0, SPIOEN; 1829 test SSTAT0, SPIORDY jz .; 1830 mov SCSIDATL, SINDEX; 1831 test SSTAT0, SPIORDY jz .; 1832 and SXFRCTL0, ~SPIOEN ret; 1833} 1834 1835 1836/* 1837 * Assert that if we've been reselected, then we've seen an IDENTIFY 1838 * message. 1839 */ 1840assert: 1841 test SEQ_FLAGS,IDENTIFY_SEEN jnz return; /* seen IDENTIFY? */ 1842 1843 mvi NO_IDENT jmp set_seqint; /* no - tell the kernel */ 1844 1845/* 1846 * Locate a disconnected SCB by SCBID. Upon return, SCBPTR and SINDEX will 1847 * be set to the position of the SCB. If the SCB cannot be found locally, 1848 * it will be paged in from host memory. RETURN_2 stores the address of the 1849 * preceding SCB in the disconnected list which can be used to speed up 1850 * removal of the found SCB from the disconnected list. 1851 */ 1852if ((ahc->flags & AHC_PAGESCBS) != 0) { 1853BEGIN_CRITICAL 1854findSCB: 1855 mov A, SINDEX; /* Tag passed in SINDEX */ 1856 cmp DISCONNECTED_SCBH, SCB_LIST_NULL je findSCB_notFound; 1857 mov SCBPTR, DISCONNECTED_SCBH; /* Initialize SCBPTR */ 1858 mvi ARG_2, SCB_LIST_NULL; /* Head of list */ 1859 jmp findSCB_loop; 1860findSCB_next: 1861 cmp SCB_NEXT, SCB_LIST_NULL je findSCB_notFound; 1862 mov ARG_2, SCBPTR; 1863 mov SCBPTR,SCB_NEXT; 1864findSCB_loop: 1865 cmp SCB_TAG, A jne findSCB_next; 1866rem_scb_from_disc_list: 1867 cmp ARG_2, SCB_LIST_NULL je rHead; 1868 mov DINDEX, SCB_NEXT; 1869 mov SINDEX, SCBPTR; 1870 mov SCBPTR, ARG_2; 1871 mov SCB_NEXT, DINDEX; 1872 mov SCBPTR, SINDEX ret; 1873rHead: 1874 mov DISCONNECTED_SCBH,SCB_NEXT ret; 1875END_CRITICAL 1876findSCB_notFound: 1877 /* 1878 * We didn't find it. Page in the SCB. 1879 */ 1880 mov ARG_1, A; /* Save tag */ 1881 mov ALLZEROS call get_free_or_disc_scb; 1882 mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET; 1883 mov ARG_1 jmp dma_scb; 1884} 1885 1886/* 1887 * Prepare the hardware to post a byte to host memory given an 1888 * index of (A + (256 * SINDEX)) and a base address of SHARED_DATA_ADDR. 1889 */ 1890post_byte_setup: 1891 mov ARG_2, SINDEX; 1892 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1893 mvi DINDEX, CCHADDR; 1894 mvi SHARED_DATA_ADDR call set_1byte_addr; 1895 mvi CCHCNT, 1; 1896 mvi CCSCBCTL, CCSCBRESET ret; 1897 } else { 1898 mvi DINDEX, HADDR; 1899 mvi SHARED_DATA_ADDR call set_1byte_addr; 1900 mvi 1 call set_hcnt; 1901 mvi DFCNTRL, FIFORESET ret; 1902 } 1903 1904post_byte: 1905 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1906 bmov CCSCBRAM, SINDEX, 1; 1907 or CCSCBCTL, CCSCBEN|CCSCBRESET; 1908 test CCSCBCTL, CCSCBDONE jz .; 1909 clr CCSCBCTL ret; 1910 } else { 1911 mov DFDAT, SINDEX; 1912 or DFCNTRL, HDMAEN|FIFOFLUSH; 1913 jmp dma_finish; 1914 } 1915 1916phase_lock_perr: 1917 mvi PERR_DETECTED call set_seqint; 1918phase_lock: 1919 /* 1920 * If there is a parity error, wait for the kernel to 1921 * see the interrupt and prepare our message response 1922 * before continuing. 1923 */ 1924 test SSTAT1, REQINIT jz phase_lock; 1925 test SSTAT1, SCSIPERR jnz phase_lock_perr; 1926phase_lock_latch_phase: 1927 and SCSISIGO, PHASE_MASK, SCSISIGI; 1928 and LASTPHASE, PHASE_MASK, SCSISIGI ret; 1929 1930if ((ahc->features & AHC_CMD_CHAN) == 0) { 1931set_hcnt: 1932 mov HCNT[0], SINDEX; 1933clear_hcnt: 1934 clr HCNT[1]; 1935 clr HCNT[2] ret; 1936 1937set_stcnt_from_hcnt: 1938 mov STCNT[0], HCNT[0]; 1939 mov STCNT[1], HCNT[1]; 1940 mov STCNT[2], HCNT[2] ret; 1941 1942bcopy_8: 1943 mov DINDIR, SINDIR; 1944bcopy_7: 1945 mov DINDIR, SINDIR; 1946 mov DINDIR, SINDIR; 1947bcopy_5: 1948 mov DINDIR, SINDIR; 1949bcopy_4: 1950 mov DINDIR, SINDIR; 1951bcopy_3: 1952 mov DINDIR, SINDIR; 1953 mov DINDIR, SINDIR; 1954 mov DINDIR, SINDIR ret; 1955} 1956 1957if ((ahc->flags & AHC_TARGETROLE) != 0) { 1958/* 1959 * Setup addr assuming that A is an index into 1960 * an array of 32byte objects, SINDEX contains 1961 * the base address of that array, and DINDEX 1962 * contains the base address of the location 1963 * to store the indexed address. 1964 */ 1965set_32byte_addr: 1966 shr ARG_2, 3, A; 1967 shl A, 5; 1968 jmp set_1byte_addr; 1969} 1970 1971/* 1972 * Setup addr assuming that A is an index into 1973 * an array of 64byte objects, SINDEX contains 1974 * the base address of that array, and DINDEX 1975 * contains the base address of the location 1976 * to store the indexed address. 1977 */ 1978set_64byte_addr: 1979 shr ARG_2, 2, A; 1980 shl A, 6; 1981 1982/* 1983 * Setup addr assuming that A + (ARG_2 * 256) is an 1984 * index into an array of 1byte objects, SINDEX contains 1985 * the base address of that array, and DINDEX contains 1986 * the base address of the location to store the computed 1987 * address. 1988 */ 1989set_1byte_addr: 1990 add DINDIR, A, SINDIR; 1991 mov A, ARG_2; 1992 adc DINDIR, A, SINDIR; 1993 clr A; 1994 adc DINDIR, A, SINDIR; 1995 adc DINDIR, A, SINDIR ret; 1996 1997/* 1998 * Either post or fetch and SCB from host memory based on the 1999 * DIRECTION bit in DMAPARAMS. The host SCB index is in SINDEX. 2000 */ 2001dma_scb: 2002 mov A, SINDEX; 2003 if ((ahc->features & AHC_CMD_CHAN) != 0) { 2004 mvi DINDEX, CCHADDR; 2005 mvi HSCB_ADDR call set_64byte_addr; 2006 mov CCSCBPTR, SCBPTR; 2007 test DMAPARAMS, DIRECTION jz dma_scb_tohost; 2008 if ((ahc->flags & AHC_SCB_BTT) != 0) { 2009 mvi CCHCNT, SCB_DOWNLOAD_SIZE_64; 2010 } else { 2011 mvi CCHCNT, SCB_DOWNLOAD_SIZE; 2012 } 2013 mvi CCSCBCTL, CCARREN|CCSCBEN|CCSCBDIR|CCSCBRESET; 2014 cmp CCSCBCTL, CCSCBDONE|ARRDONE|CCARREN|CCSCBEN|CCSCBDIR jne .; 2015 jmp dma_scb_finish; 2016dma_scb_tohost: 2017 mvi CCHCNT, SCB_UPLOAD_SIZE; 2018 if ((ahc->features & AHC_ULTRA2) == 0) { 2019 mvi CCSCBCTL, CCSCBRESET; 2020 bmov CCSCBRAM, SCB_BASE, SCB_UPLOAD_SIZE; 2021 or CCSCBCTL, CCSCBEN|CCSCBRESET; 2022 test CCSCBCTL, CCSCBDONE jz .; 2023 } else if ((ahc->bugs & AHC_SCBCHAN_UPLOAD_BUG) != 0) { 2024 mvi CCSCBCTL, CCARREN|CCSCBRESET; 2025 cmp CCSCBCTL, ARRDONE|CCARREN jne .; 2026 mvi CCHCNT, SCB_UPLOAD_SIZE; 2027 mvi CCSCBCTL, CCSCBEN|CCSCBRESET; 2028 cmp CCSCBCTL, CCSCBDONE|CCSCBEN jne .; 2029 } else { 2030 mvi CCSCBCTL, CCARREN|CCSCBEN|CCSCBRESET; 2031 cmp CCSCBCTL, CCSCBDONE|ARRDONE|CCARREN|CCSCBEN jne .; 2032 } 2033dma_scb_finish: 2034 clr CCSCBCTL; 2035 test CCSCBCTL, CCARREN|CCSCBEN jnz .; 2036 ret; 2037 } else { 2038 mvi DINDEX, HADDR; 2039 mvi HSCB_ADDR call set_64byte_addr; 2040 mvi SCB_DOWNLOAD_SIZE call set_hcnt; 2041 mov DFCNTRL, DMAPARAMS; 2042 test DMAPARAMS, DIRECTION jnz dma_scb_fromhost; 2043 /* Fill it with the SCB data */ 2044copy_scb_tofifo: 2045 mvi SINDEX, SCB_BASE; 2046 add A, SCB_DOWNLOAD_SIZE, SINDEX; 2047copy_scb_tofifo_loop: 2048 call copy_to_fifo_8; 2049 cmp SINDEX, A jne copy_scb_tofifo_loop; 2050 or DFCNTRL, HDMAEN|FIFOFLUSH; 2051 jmp dma_finish; 2052dma_scb_fromhost: 2053 mvi DINDEX, SCB_BASE; 2054 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0) { 2055 /* 2056 * The PCI module will only issue a PCI 2057 * retry if the data FIFO is empty. If the 2058 * host disconnects in the middle of a 2059 * transfer, we must empty the fifo of all 2060 * available data to force the chip to 2061 * continue the transfer. This does not 2062 * happen for SCSI transfers as the SCSI module 2063 * will drain the FIFO as data is made available. 2064 * When the hang occurs, we know that a multiple 2065 * of 8 bytes are in the FIFO because the PCI 2066 * module has an 8 byte input latch that only 2067 * dumps to the FIFO when HCNT == 0 or the 2068 * latch is full. 2069 */ 2070 clr A; 2071 /* Wait for some data to arrive. */ 2072dma_scb_hang_fifo: 2073 test DFSTATUS, FIFOEMP jnz dma_scb_hang_fifo; 2074dma_scb_hang_wait: 2075 test DFSTATUS, MREQPEND jnz dma_scb_hang_wait; 2076 test DFSTATUS, HDONE jnz dma_scb_hang_dma_done; 2077 test DFSTATUS, HDONE jnz dma_scb_hang_dma_done; 2078 test DFSTATUS, HDONE jnz dma_scb_hang_dma_done; 2079 test DFSTATUS, HDONE jnz dma_scb_hang_dma_done; 2080 /* 2081 * The PCI module no longer intends to perform 2082 * a PCI transaction and HDONE has not come true. 2083 * We are hung. Drain the fifo. 2084 */ 2085dma_scb_hang_empty_fifo: 2086 /* 2087 * Skip lines not yet transfered into the FIFO. 2088 */ 2089 add SINDEX, 7, HCNT; 2090 shr SINDEX, 3; 2091 2092 /* 2093 * Skip lines already copied out of the FIFO. 2094 */ 2095 add A, A, SINDEX; 2096 2097 call dma_scb_hang_dma_drain_fifo; 2098 2099 /* 2100 * Set the lines transferred to all but 2101 * those yet to reach the FIFO. 2102 */ 2103 not SINDEX; 2104 add A, 5, SINDEX; 2105 jmp dma_scb_hang_fifo; 2106dma_scb_hang_dma_done: 2107 and DFCNTRL, ~HDMAEN; 2108 test DFCNTRL, HDMAEN jnz .; 2109dma_scb_hang_dma_drain_fifo: 2110 add SEQADDR0, A; 2111 } else { 2112 call dma_finish; 2113 } 2114 /* If we were putting the SCB, we are done */ 2115 call dfdat_in_8; 2116 call dfdat_in_8; 2117 call dfdat_in_8; 2118dfdat_in_8: 2119 mov DINDIR,DFDAT; 2120dfdat_in_7: 2121 mov DINDIR,DFDAT; 2122 mov DINDIR,DFDAT; 2123 mov DINDIR,DFDAT; 2124 mov DINDIR,DFDAT; 2125 mov DINDIR,DFDAT; 2126dfdat_in_2: 2127 mov DINDIR,DFDAT; 2128 mov DINDIR,DFDAT ret; 2129 } 2130 2131copy_to_fifo_8: 2132 mov DFDAT,SINDIR; 2133 mov DFDAT,SINDIR; 2134copy_to_fifo_6: 2135 mov DFDAT,SINDIR; 2136copy_to_fifo_5: 2137 mov DFDAT,SINDIR; 2138copy_to_fifo_4: 2139 mov DFDAT,SINDIR; 2140 mov DFDAT,SINDIR; 2141 mov DFDAT,SINDIR; 2142 mov DFDAT,SINDIR ret; 2143 2144/* 2145 * Wait for DMA from host memory to data FIFO to complete, then disable 2146 * DMA and wait for it to acknowledge that it's off. 2147 */ 2148dma_finish: 2149 test DFSTATUS,HDONE jz dma_finish; 2150 /* Turn off DMA */ 2151 and DFCNTRL, ~HDMAEN; 2152 test DFCNTRL, HDMAEN jnz .; 2153 ret; 2154 2155/* 2156 * Restore an SCB that failed to match an incoming reselection 2157 * to the correct/safe state. If the SCB is for a disconnected 2158 * transaction, it must be returned to the disconnected list. 2159 * If it is not in the disconnected state, it must be free. 2160 */ 2161cleanup_scb: 2162 if ((ahc->flags & AHC_PAGESCBS) != 0) { 2163 test SCB_CONTROL,DISCONNECTED jnz add_scb_to_disc_list; 2164 } 2165add_scb_to_free_list: 2166 if ((ahc->flags & AHC_PAGESCBS) != 0) { 2167BEGIN_CRITICAL 2168 mov SCB_NEXT, FREE_SCBH; 2169 mvi SCB_TAG, SCB_LIST_NULL; 2170 mov FREE_SCBH, SCBPTR ret; 2171END_CRITICAL 2172 } else { 2173 mvi SCB_TAG, SCB_LIST_NULL ret; 2174 } 2175 2176if ((ahc->flags & AHC_PAGESCBS) != 0) { 2177get_free_or_disc_scb: 2178BEGIN_CRITICAL 2179 cmp FREE_SCBH, SCB_LIST_NULL jne dequeue_free_scb; 2180 cmp DISCONNECTED_SCBH, SCB_LIST_NULL jne dequeue_disc_scb; 2181return_error: 2182 mvi NO_FREE_SCB call set_seqint; 2183 mvi SINDEX, SCB_LIST_NULL ret; 2184dequeue_disc_scb: 2185 mov SCBPTR, DISCONNECTED_SCBH; 2186 mov DISCONNECTED_SCBH, SCB_NEXT; 2187END_CRITICAL 2188 mvi DMAPARAMS, FIFORESET; 2189 mov SCB_TAG jmp dma_scb; 2190BEGIN_CRITICAL 2191dequeue_free_scb: 2192 mov SCBPTR, FREE_SCBH; 2193 mov FREE_SCBH, SCB_NEXT ret; 2194END_CRITICAL 2195 2196add_scb_to_disc_list: 2197/* 2198 * Link this SCB into the DISCONNECTED list. This list holds the 2199 * candidates for paging out an SCB if one is needed for a new command. 2200 * Modifying the disconnected list is a critical(pause dissabled) section. 2201 */ 2202BEGIN_CRITICAL 2203 mov SCB_NEXT, DISCONNECTED_SCBH; 2204 mov DISCONNECTED_SCBH, SCBPTR ret; 2205END_CRITICAL 2206} 2207set_seqint: 2208 mov INTSTAT, SINDEX; 2209 nop; 2210return: 2211 ret; 2212