aic7xxx.seq revision 71717
1/* 2 * Adaptec 274x/284x/294x device driver firmware for Linux and FreeBSD. 3 * 4 * Copyright (c) 1994-2001 Justin Gibbs. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * Alternatively, this software may be distributed under the terms of the 17 * GNU Public License ("GPL"). 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $Id: //depot/src/aic7xxx/aic7xxx.seq#16 $ 32 * 33 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.seq 71717 2001-01-27 20:54:24Z gibbs $ 34 */ 35 36#include "aic7xxx.reg" 37#include "scsi_message.h" 38 39/* 40 * A few words on the waiting SCB list: 41 * After starting the selection hardware, we check for reconnecting targets 42 * as well as for our selection to complete just in case the reselection wins 43 * bus arbitration. The problem with this is that we must keep track of the 44 * SCB that we've already pulled from the QINFIFO and started the selection 45 * on just in case the reselection wins so that we can retry the selection at 46 * a later time. This problem cannot be resolved by holding a single entry 47 * in scratch ram since a reconnecting target can request sense and this will 48 * create yet another SCB waiting for selection. The solution used here is to 49 * use byte 27 of the SCB as a psuedo-next pointer and to thread a list 50 * of SCBs that are awaiting selection. Since 0-0xfe are valid SCB indexes, 51 * SCB_LIST_NULL is 0xff which is out of range. An entry is also added to 52 * this list everytime a request sense occurs or after completing a non-tagged 53 * command for which a second SCB has been queued. The sequencer will 54 * automatically consume the entries. 55 */ 56 57bus_free_sel: 58 /* 59 * Turn off the selection hardware. We need to reset the 60 * selection request in order to perform a new selection. 61 */ 62 and SCSISEQ, TEMODE|ENSELI|ENRSELI|ENAUTOATNP, SCSISEQ; 63 and SIMODE1, ~ENBUSFREE; 64poll_for_work: 65 call clear_target_state; 66 and SXFRCTL0, ~SPIOEN; 67 if ((ahc->features & AHC_ULTRA2) != 0) { 68 clr SCSIBUSL; 69 } 70poll_for_work_loop: 71 test SSTAT0, SELDO|SELDI jnz selection; 72 test SCSISEQ, ENSELO jnz poll_for_work_loop; 73 if ((ahc->features & AHC_TWIN) != 0) { 74 /* 75 * Twin channel devices cannot handle things like SELTO 76 * interrupts on the "background" channel. So, if we 77 * are selecting, keep polling the current channel util 78 * either a selection or reselection occurs. 79 */ 80 xor SBLKCTL,SELBUSB; /* Toggle to the other bus */ 81 test SSTAT0, SELDO|SELDI jnz selection; 82 xor SBLKCTL,SELBUSB; /* Toggle back */ 83 } 84 cmp WAITING_SCBH,SCB_LIST_NULL jne start_waiting; 85test_queue: 86 /* Has the driver posted any work for us? */ 87BEGIN_CRITICAL 88 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 89 test QOFF_CTLSTA, SCB_AVAIL jz poll_for_work_loop; 90 } else { 91 mov A, QINPOS; 92 cmp KERNEL_QINPOS, A je poll_for_work_loop; 93 } 94 mov ARG_1, NEXT_QUEUED_SCB; 95END_CRITICAL 96 97 /* 98 * We have at least one queued SCB now and we don't have any 99 * SCBs in the list of SCBs awaiting selection. Allocate a 100 * card SCB for the host's SCB and get to work on it. 101 */ 102 if ((ahc->flags & AHC_PAGESCBS) != 0) { 103 mov ALLZEROS call get_free_or_disc_scb; 104 } else { 105 /* In the non-paging case, the SCBID == hardware SCB index */ 106 mov SCBPTR, ARG_1; 107 } 108dma_queued_scb: 109 /* 110 * DMA the SCB from host ram into the current SCB location. 111 */ 112 mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET; 113 mov ARG_1 call dma_scb; 114 /* 115 * Check one last time to see if this SCB was canceled 116 * before we completed the DMA operation. If it was, 117 * the QINFIFO next pointer will not match our saved 118 * value. 119 */ 120 mov A, ARG_1; 121BEGIN_CRITICAL 122 cmp NEXT_QUEUED_SCB, A jne abort_qinscb; 123 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 124 cmp SCB_TAG, A je . + 2; 125 mvi SCB_MISMATCH call set_seqint; 126 } 127 mov NEXT_QUEUED_SCB, SCB_NEXT; 128 mov SCB_NEXT,WAITING_SCBH; 129 mov WAITING_SCBH, SCBPTR; 130 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 131 mov NONE, SNSCB_QOFF; 132 } else { 133 inc QINPOS; 134 } 135END_CRITICAL 136start_waiting: 137 /* 138 * Start the first entry on the waiting SCB list. 139 */ 140 mov SCBPTR, WAITING_SCBH; 141 call start_selection; 142 jmp poll_for_work_loop; 143 144abort_qinscb: 145 call add_scb_to_free_list; 146 jmp poll_for_work_loop; 147 148start_selection: 149 /* 150 * If bus reset interrupts have been disabled (from a previous 151 * reset), re-enable them now. Resets are only of interest 152 * when we have outstanding transactions, so we can safely 153 * defer re-enabling the interrupt until, as an initiator, 154 * we start sending out transactions again. 155 */ 156 test SIMODE1, ENSCSIRST jnz . + 3; 157 mvi CLRSINT1, CLRSCSIRSTI; 158 or SIMODE1, ENSCSIRST; 159 if ((ahc->features & AHC_TWIN) != 0) { 160 and SINDEX,~SELBUSB,SBLKCTL;/* Clear channel select bit */ 161 test SCB_SCSIID, TWIN_CHNLB jz . + 2; 162 or SINDEX, SELBUSB; 163 mov SBLKCTL,SINDEX; /* select channel */ 164 } 165initialize_scsiid: 166 if ((ahc->features & AHC_ULTRA2) != 0) { 167 mov SCSIID_ULTRA2, SCB_SCSIID; 168 } else if ((ahc->features & AHC_TWIN) != 0) { 169 and SCSIID, TWIN_TID|OID, SCB_SCSIID; 170 } else { 171 mov SCSIID, SCB_SCSIID; 172 } 173 if ((ahc->flags & AHC_TARGETROLE) != 0) { 174 mov SINDEX, SCSISEQ_TEMPLATE; 175 test SCB_CONTROL, TARGET_SCB jz . + 2; 176 or SINDEX, TEMODE; 177 mov SCSISEQ, SINDEX ret; 178 } else { 179 mov SCSISEQ, SCSISEQ_TEMPLATE ret; 180 } 181 182/* 183 * Initialize transfer settings and clear the SCSI channel. 184 * SINDEX should contain any additional bit's the client wants 185 * set in SXFRCTL0. We also assume that the current SCB is 186 * a valid SCB for the target we wish to talk to. 187 */ 188initialize_channel: 189 or SXFRCTL0, SPIOEN|CLRSTCNT|CLRCHN; 190set_transfer_settings: 191 if ((ahc->features & AHC_ULTRA) != 0) { 192 test SCB_CONTROL, ULTRAENB jz . + 2; 193 or SXFRCTL0, FAST20; 194 } 195 /* 196 * Initialize SCSIRATE with the appropriate value for this target. 197 */ 198 if ((ahc->features & AHC_ULTRA2) != 0) { 199 bmov SCSIRATE, SCB_SCSIRATE, 2 ret; 200 } else { 201 mov SCSIRATE, SCB_SCSIRATE ret; 202 } 203 204selection: 205 /* 206 * We aren't expecting a bus free, so interrupt 207 * the kernel driver if it happens. 208 */ 209 mvi CLRSINT1,CLRBUSFREE; 210 or SIMODE1, ENBUSFREE; 211 212 /* 213 * Guard against a bus free after (re)selection 214 * but prior to enabling the busfree interrupt. SELDI 215 * and SELDO will be cleared in that case. 216 */ 217 test SSTAT0, SELDI|SELDO jz bus_free_sel; 218 test SSTAT0,SELDO jnz select_out; 219select_in: 220 if ((ahc->flags & AHC_TARGETROLE) != 0) { 221 if ((ahc->flags & AHC_INITIATORROLE) != 0) { 222 test SSTAT0, TARGET jz initiator_reselect; 223 } 224 mvi CLRSINT0, CLRSELDI; 225 226 /* 227 * We've just been selected. Assert BSY and 228 * setup the phase for receiving messages 229 * from the target. 230 * 231 * If bus reset interrupts have been disabled (from a 232 * previous reset), re-enable them now. Resets are only 233 * of interest when we have outstanding transactions, so 234 * we can safely defer re-enabling the interrupt until, 235 * as a target, we start receiving transactions again. 236 */ 237 test SIMODE1, ENSCSIRST jnz . + 3; 238 mvi CLRSINT1, CLRSCSIRSTI; 239 or SIMODE1, ENSCSIRST; 240 mvi SCSISIGO, P_MESGOUT|BSYO; 241 242 /* 243 * Setup the DMA for sending the identify and 244 * command information. 245 */ 246 or SEQ_FLAGS, CMDPHASE_PENDING; 247 248 mov A, TQINPOS; 249 if ((ahc->features & AHC_CMD_CHAN) != 0) { 250 mvi DINDEX, CCHADDR; 251 mvi SHARED_DATA_ADDR call set_32byte_addr; 252 mvi CCSCBCTL, CCSCBRESET; 253 } else { 254 mvi DINDEX, HADDR; 255 mvi SHARED_DATA_ADDR call set_32byte_addr; 256 mvi DFCNTRL, FIFORESET; 257 } 258 259 /* Initiator that selected us */ 260 and SAVED_SCSIID, SELID_MASK, SELID; 261 /* The Target ID we were selected at */ 262 if ((ahc->features & AHC_MULTI_TID) != 0) { 263 and A, OID, TARGIDIN; 264 } else if ((ahc->features & AHC_ULTRA2) != 0) { 265 and A, OID, SCSIID_ULTRA2; 266 } else { 267 and A, OID, SCSIID; 268 } 269 or SAVED_SCSIID, A; 270 if ((ahc->features & AHC_TWIN) != 0) { 271 test SBLKCTL, SELBUSB jz . + 2; 272 or SAVED_SCSIID, TWIN_CHNLB; 273 } 274 if ((ahc->features & AHC_CMD_CHAN) != 0) { 275 mov CCSCBRAM, SAVED_SCSIID; 276 } else { 277 mov DFDAT, SAVED_SCSIID; 278 } 279 280 /* 281 * If ATN isn't asserted, the target isn't interested 282 * in talking to us. Go directly to bus free. 283 * XXX SCSI-1 may require us to assume lun 0 if 284 * ATN is false. 285 */ 286 test SCSISIGI, ATNI jz target_busfree; 287 288 /* 289 * Watch ATN closely now as we pull in messages from the 290 * initiator. We follow the guidlines from section 6.5 291 * of the SCSI-2 spec for what messages are allowed when. 292 */ 293 call target_inb; 294 295 /* 296 * Our first message must be one of IDENTIFY, ABORT, or 297 * BUS_DEVICE_RESET. 298 */ 299 test DINDEX, MSG_IDENTIFYFLAG jz host_target_message_loop; 300 /* Store for host */ 301 if ((ahc->features & AHC_CMD_CHAN) != 0) { 302 mov CCSCBRAM, DINDEX; 303 } else { 304 mov DFDAT, DINDEX; 305 } 306 307 /* Remember for disconnection decision */ 308 test DINDEX, MSG_IDENTIFY_DISCFLAG jnz . + 2; 309 /* XXX Honor per target settings too */ 310 or SEQ_FLAGS, NO_DISCONNECT; 311 312 test SCSISIGI, ATNI jz ident_messages_done; 313 call target_inb; 314 /* 315 * If this is a tagged request, the tagged message must 316 * immediately follow the identify. We test for a valid 317 * tag message by seeing if it is >= MSG_SIMPLE_Q_TAG and 318 * < MSG_IGN_WIDE_RESIDUE. 319 */ 320 add A, -MSG_SIMPLE_Q_TAG, DINDEX; 321 jnc ident_messages_done; 322 add A, -MSG_IGN_WIDE_RESIDUE, DINDEX; 323 jc ident_messages_done; 324 /* Store for host */ 325 if ((ahc->features & AHC_CMD_CHAN) != 0) { 326 mov CCSCBRAM, DINDEX; 327 } else { 328 mov DFDAT, DINDEX; 329 } 330 331 /* 332 * If the initiator doesn't feel like providing a tag number, 333 * we've got a failed selection and must transition to bus 334 * free. 335 */ 336 test SCSISIGI, ATNI jz target_busfree; 337 338 /* 339 * Store the tag for the host. 340 */ 341 call target_inb; 342 if ((ahc->features & AHC_CMD_CHAN) != 0) { 343 mov CCSCBRAM, DINDEX; 344 } else { 345 mov DFDAT, DINDEX; 346 } 347 mov INITIATOR_TAG, DINDEX; 348 or SEQ_FLAGS, TARGET_CMD_IS_TAGGED; 349 test SCSISIGI, ATNI jz . + 2; 350 /* Initiator still wants to give us messages */ 351 call target_inb; 352 jmp ident_messages_done; 353 354 /* 355 * Pushed message loop to allow the kernel to 356 * run it's own target mode message state engine. 357 */ 358host_target_message_loop: 359 mvi HOST_MSG_LOOP call set_seqint; 360 cmp RETURN_1, EXIT_MSG_LOOP je target_ITloop; 361 test SSTAT0, SPIORDY jz .; 362 jmp host_target_message_loop; 363 364ident_messages_done: 365 /* If ring buffer is full, return busy or queue full */ 366 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 367 and A, HOST_TQINPOS, HS_MAILBOX; 368 } else { 369 mov A, KERNEL_TQINPOS; 370 } 371 cmp TQINPOS, A jne tqinfifo_has_space; 372 mvi P_STATUS|BSYO call change_phase; 373 test SEQ_FLAGS, TARGET_CMD_IS_TAGGED jz . + 3; 374 mvi STATUS_QUEUE_FULL call target_outb; 375 jmp target_busfree_wait; 376 mvi STATUS_BUSY call target_outb; 377 jmp target_busfree_wait; 378tqinfifo_has_space: 379 /* Terminate the ident list */ 380 if ((ahc->features & AHC_CMD_CHAN) != 0) { 381 mvi CCSCBRAM, SCB_LIST_NULL; 382 } else { 383 mvi DFDAT, SCB_LIST_NULL; 384 } 385 or SEQ_FLAGS, TARG_CMD_PENDING|IDENTIFY_SEEN; 386 test SCSISIGI, ATNI jnz target_mesgout_pending; 387 jmp target_ITloop; 388 389/* 390 * We carefully toggle SPIOEN to allow us to return the 391 * message byte we receive so it can be checked prior to 392 * driving REQ on the bus for the next byte. 393 */ 394target_inb: 395 /* 396 * Drive REQ on the bus by enabling SCSI PIO. 397 */ 398 or SXFRCTL0, SPIOEN; 399 /* Wait for the byte */ 400 test SSTAT0, SPIORDY jz .; 401 /* Prevent our read from triggering another REQ */ 402 and SXFRCTL0, ~SPIOEN; 403 /* Save latched contents */ 404 mov DINDEX, SCSIDATL ret; 405 } 406 407if ((ahc->flags & AHC_INITIATORROLE) != 0) { 408/* 409 * Reselection has been initiated by a target. Make a note that we've been 410 * reselected, but haven't seen an IDENTIFY message from the target yet. 411 */ 412initiator_reselect: 413 /* XXX test for and handle ONE BIT condition */ 414 or SXFRCTL0, SPIOEN|CLRSTCNT|CLRCHN; 415 and SAVED_SCSIID, SELID_MASK, SELID; 416 if ((ahc->features & AHC_ULTRA2) != 0) { 417 and A, OID, SCSIID_ULTRA2; 418 } else { 419 and A, OID, SCSIID; 420 } 421 or SAVED_SCSIID, A; 422 if ((ahc->features & AHC_TWIN) != 0) { 423 test SBLKCTL, SELBUSB jz . + 2; 424 or SAVED_SCSIID, TWIN_CHNLB; 425 } 426 mvi CLRSINT0, CLRSELDI; 427 jmp ITloop; 428} 429 430/* 431 * After the selection, remove this SCB from the "waiting SCB" 432 * list. This is achieved by simply moving our "next" pointer into 433 * WAITING_SCBH. Our next pointer will be set to null the next time this 434 * SCB is used, so don't bother with it now. 435 */ 436select_out: 437 /* Turn off the selection hardware */ 438 and SCSISEQ, TEMODE|ENSELI|ENRSELI|ENAUTOATNP, SCSISEQ; 439 mvi CLRSINT0, CLRSELDO; 440 mov SCBPTR, WAITING_SCBH; 441 mov WAITING_SCBH,SCB_NEXT; 442 mov SAVED_SCSIID, SCB_SCSIID; 443 mov SAVED_LUN, SCB_LUN; 444 call initialize_channel; 445 if ((ahc->flags & AHC_TARGETROLE) != 0) { 446 test SSTAT0, TARGET jz initiator_select; 447 448 /* 449 * We've just re-selected an initiator. 450 * Assert BSY and setup the phase for 451 * sending our identify messages. 452 */ 453 mvi P_MESGIN|BSYO call change_phase; 454 455 /* 456 * Start out with a simple identify message. 457 */ 458 or SCB_LUN, MSG_IDENTIFYFLAG call target_outb; 459 460 /* 461 * If we are the result of a tagged command, send 462 * a simple Q tag and the tag id. 463 */ 464 test SCB_CONTROL, TAG_ENB jz . + 3; 465 mvi MSG_SIMPLE_Q_TAG call target_outb; 466 mov SCB_TARGET_INFO[SCB_INITIATOR_TAG] call target_outb; 467target_synccmd: 468 /* 469 * Now determine what phases the host wants us 470 * to go through. 471 */ 472 mov SEQ_FLAGS, SCB_TARGET_INFO[SCB_TARGET_PHASES]; 473 474target_ITloop: 475 /* 476 * Start honoring ATN signals now that 477 * we properly identified ourselves. 478 */ 479 test SCSISIGI, ATNI jnz target_mesgout; 480 test SEQ_FLAGS, CMDPHASE_PENDING jnz target_cmdphase; 481 test SEQ_FLAGS, DPHASE_PENDING jnz target_dphase; 482 test SEQ_FLAGS, SPHASE_PENDING jnz target_sphase; 483 484 /* 485 * No more work to do. Either disconnect or not depending 486 * on the state of NO_DISCONNECT. 487 */ 488 test SEQ_FLAGS, NO_DISCONNECT jz target_disconnect; 489 if ((ahc->flags & AHC_PAGESCBS) != 0) { 490 mov ALLZEROS call get_free_or_disc_scb; 491 } 492 mov RETURN_1, ALLZEROS; 493 call complete_target_cmd; 494 cmp RETURN_1, CONT_MSG_LOOP jne .; 495 mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET; 496 mov SCB_TAG call dma_scb; 497 jmp target_synccmd; 498 499target_mesgout: 500 mvi SCSISIGO, P_MESGOUT|BSYO; 501target_mesgout_continue: 502 call target_inb; 503target_mesgout_pending: 504 /* Local Processing goes here... */ 505 jmp host_target_message_loop; 506 507target_disconnect: 508 mvi P_MESGIN|BSYO call change_phase; 509 test SEQ_FLAGS, DPHASE jz . + 2; 510 mvi MSG_SAVEDATAPOINTER call target_outb; 511 mvi MSG_DISCONNECT call target_outb; 512 513target_busfree_wait: 514 /* Wait for preceeding I/O session to complete. */ 515 test SCSISIGI, ACKI jnz .; 516target_busfree: 517 and SIMODE1, ~ENBUSFREE; 518 if ((ahc->features & AHC_ULTRA2) != 0) { 519 clr SCSIBUSL; 520 } 521 clr SCSISIGO; 522 mvi LASTPHASE, P_BUSFREE; 523 call complete_target_cmd; 524 jmp poll_for_work; 525 526target_cmdphase: 527 mvi P_COMMAND|BSYO call change_phase; 528 call target_inb; 529 mov A, DINDEX; 530 /* Store for host */ 531 if ((ahc->features & AHC_CMD_CHAN) != 0) { 532 mov CCSCBRAM, A; 533 } else { 534 mov DFDAT, A; 535 } 536 537 /* 538 * Determine the number of bytes to read 539 * based on the command group code via table lookup. 540 * We reuse the first 8 bytes of the TARG_SCSIRATE 541 * BIOS array for this table. Count is one less than 542 * the total for the command since we've already fetched 543 * the first byte. 544 */ 545 shr A, CMD_GROUP_CODE_SHIFT; 546 add SINDEX, CMDSIZE_TABLE, A; 547 mov A, SINDIR; 548 549 test A, 0xFF jz command_phase_done; 550 or SXFRCTL0, SPIOEN; 551command_loop: 552 test SSTAT0, SPIORDY jz .; 553 cmp A, 1 jne . + 2; 554 and SXFRCTL0, ~SPIOEN; /* Last Byte */ 555 if ((ahc->features & AHC_CMD_CHAN) != 0) { 556 mov CCSCBRAM, SCSIDATL; 557 } else { 558 mov DFDAT, SCSIDATL; 559 } 560 dec A; 561 test A, 0xFF jnz command_loop; 562 563command_phase_done: 564 and SEQ_FLAGS, ~CMDPHASE_PENDING; 565 jmp target_ITloop; 566 567target_dphase: 568 /* 569 * Data phases on the bus are from the 570 * perspective of the initiator. The dma 571 * code looks at LASTPHASE to determine the 572 * data direction of the DMA. Toggle it for 573 * target transfers. 574 */ 575 xor LASTPHASE, IOI, SCB_TARGET_INFO[SCB_TARGET_DATA_DIR]; 576 or SCB_TARGET_INFO[SCB_TARGET_DATA_DIR], BSYO 577 call change_phase; 578 jmp p_data; 579 580target_sphase: 581 mvi P_STATUS|BSYO call change_phase; 582 mvi LASTPHASE, P_STATUS; 583 mov SCB_TARGET_INFO[SCB_TARGET_STATUS] call target_outb; 584 /* XXX Watch for ATN or parity errors??? */ 585 mvi SCSISIGO, P_MESGIN|BSYO; 586 /* MSG_CMDCMPLT is 0, but we can't do an immediate of 0 */ 587 mov ALLZEROS call target_outb; 588 jmp target_busfree_wait; 589 590complete_target_cmd: 591 test SEQ_FLAGS, TARG_CMD_PENDING jnz . + 2; 592 mov SCB_TAG jmp complete_post; 593 if ((ahc->features & AHC_CMD_CHAN) != 0) { 594 /* Set the valid byte */ 595 mvi CCSCBADDR, 24; 596 mov CCSCBRAM, ALLONES; 597 mvi CCHCNT, 28; 598 or CCSCBCTL, CCSCBEN|CCSCBRESET; 599 test CCSCBCTL, CCSCBDONE jz .; 600 clr CCSCBCTL; 601 } else { 602 /* Set the valid byte */ 603 or DFCNTRL, FIFORESET; 604 mvi DFWADDR, 3; /* Third 64bit word or byte 24 */ 605 mov DFDAT, ALLONES; 606 mvi 28 call set_hcnt; 607 or DFCNTRL, HDMAEN|FIFOFLUSH; 608 call dma_finish; 609 } 610 inc TQINPOS; 611 mvi INTSTAT,CMDCMPLT ret; 612 } 613 614if ((ahc->flags & AHC_INITIATORROLE) != 0) { 615initiator_select: 616 /* 617 * As soon as we get a successful selection, the target 618 * should go into the message out phase since we have ATN 619 * asserted. 620 */ 621 mvi MSG_OUT, MSG_IDENTIFYFLAG; 622 or SEQ_FLAGS, IDENTIFY_SEEN; 623 624 /* 625 * Main loop for information transfer phases. Wait for the 626 * target to assert REQ before checking MSG, C/D and I/O for 627 * the bus phase. 628 */ 629mesgin_phasemis: 630ITloop: 631 call phase_lock; 632 633 mov A, LASTPHASE; 634 635 test A, ~P_DATAIN jz p_data; 636 cmp A,P_COMMAND je p_command; 637 cmp A,P_MESGOUT je p_mesgout; 638 cmp A,P_STATUS je p_status; 639 cmp A,P_MESGIN je p_mesgin; 640 641 mvi BAD_PHASE call set_seqint; 642 jmp ITloop; /* Try reading the bus again. */ 643 644await_busfree: 645 and SIMODE1, ~ENBUSFREE; 646 mov NONE, SCSIDATL; /* Ack the last byte */ 647 if ((ahc->features & AHC_ULTRA2) != 0) { 648 clr SCSIBUSL; /* Prevent bit leakage durint SELTO */ 649 } 650 and SXFRCTL0, ~SPIOEN; 651 test SSTAT1,REQINIT|BUSFREE jz .; 652 test SSTAT1, BUSFREE jnz poll_for_work; 653 mvi MISSED_BUSFREE call set_seqint; 654} 655 656clear_target_state: 657 /* 658 * We assume that the kernel driver may reset us 659 * at any time, even in the middle of a DMA, so 660 * clear DFCNTRL too. 661 */ 662 clr DFCNTRL; 663 or SXFRCTL0, CLRSTCNT|CLRCHN; 664 665 /* 666 * We don't know the target we will connect to, 667 * so default to narrow transfers to avoid 668 * parity problems. 669 */ 670 if ((ahc->features & AHC_ULTRA2) != 0) { 671 bmov SCSIRATE, ALLZEROS, 2; 672 } else { 673 clr SCSIRATE; 674 if ((ahc->features & AHC_ULTRA) != 0) { 675 and SXFRCTL0, ~(FAST20); 676 } 677 } 678 mvi LASTPHASE, P_BUSFREE; 679 /* clear target specific flags */ 680 clr SEQ_FLAGS ret; 681 682sg_advance: 683 clr A; /* add sizeof(struct scatter) */ 684 add SCB_RESIDUAL_SGPTR[0],SG_SIZEOF; 685 adc SCB_RESIDUAL_SGPTR[1],A; 686 adc SCB_RESIDUAL_SGPTR[2],A; 687 adc SCB_RESIDUAL_SGPTR[3],A ret; 688 689idle_loop: 690 if ((ahc->features & AHC_CMD_CHAN) != 0) { 691 /* Did we just finish fetching segs? */ 692 cmp CCSGCTL, CCSGEN|CCSGDONE je idle_sgfetch_complete; 693 694 /* Are we actively fetching segments? */ 695 test CCSGCTL, CCSGEN jnz return; 696 697 /* 698 * Do we need any more segments? 699 */ 700 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jnz return; 701 702 /* 703 * Do we have any prefetch left??? 704 */ 705 cmp CCSGADDR, SG_PREFETCH_CNT jne idle_sg_avail; 706 707 /* 708 * Need to fetch segments, but we can only do that 709 * if the command channel is completely idle. Make 710 * sure we don't have an SCB prefetch going on. 711 */ 712 test CCSCBCTL, CCSCBEN jnz return; 713 714 /* 715 * We fetch a "cacheline aligned" and sized amount of data 716 * so we don't end up referencing a non-existant page. 717 * Cacheline aligned is in quotes because the kernel will 718 * set the prefetch amount to a reasonable level if the 719 * cacheline size is unknown. 720 */ 721 mvi CCHCNT, SG_PREFETCH_CNT; 722 and CCHADDR[0], SG_PREFETCH_ALIGN_MASK, SCB_RESIDUAL_SGPTR; 723 bmov CCHADDR[1], SCB_RESIDUAL_SGPTR[1], 3; 724 mvi CCSGCTL, CCSGEN|CCSGRESET ret; 725idle_sgfetch_complete: 726 clr CCSGCTL; 727 test CCSGCTL, CCSGEN jnz .; 728 and CCSGADDR, SG_PREFETCH_ADDR_MASK, SCB_RESIDUAL_SGPTR; 729idle_sg_avail: 730 if ((ahc->features & AHC_ULTRA2) != 0) { 731 /* Does the hardware have space for another SG entry? */ 732 test DFSTATUS, PRELOAD_AVAIL jz return; 733 bmov HADDR, CCSGRAM, 4; 734 bmov SINDEX, CCSGRAM, 1; 735 test SINDEX, 0x1 jz . + 2; 736 xor DATA_COUNT_ODD, 0x1; 737 bmov HCNT[0], SINDEX, 1; 738 bmov HCNT[1], CCSGRAM, 2; 739 bmov SCB_RESIDUAL_DATACNT[3], CCSGRAM, 1; 740 call sg_advance; 741 mov SINDEX, SCB_RESIDUAL_SGPTR[0]; 742 test DATA_COUNT_ODD, 0x1 jz . + 2; 743 or SINDEX, ODD_SEG; 744 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 2; 745 or SINDEX, LAST_SEG; 746 mov SG_CACHE_PRE, SINDEX; 747 /* Load the segment by writing DFCNTRL again */ 748 mov DFCNTRL, DMAPARAMS; 749 } 750 ret; 751 } 752 753if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0) { 754/* 755 * Calculate the trailing portion of this S/G segment that cannot 756 * be transferred using memory write and invalidate PCI transactions. 757 * XXX Can we optimize this for PCI writes only??? 758 */ 759calc_mwi_residual: 760 /* 761 * If the ending address is on a cacheline boundary, 762 * there is no need for an extra segment. 763 */ 764 mov A, HCNT[0]; 765 add A, A, HADDR[0]; 766 and A, CACHESIZE_MASK; 767 test A, 0xFF jz return; 768 769 /* 770 * If the transfer is less than a cachline, 771 * there is no need for an extra segment. 772 */ 773 test HCNT[1], 0xFF jnz calc_mwi_residual_final; 774 test HCNT[2], 0xFF jnz calc_mwi_residual_final; 775 add NONE, INVERTED_CACHESIZE_MASK, HCNT[0]; 776 jnc return; 777 778calc_mwi_residual_final: 779 mov MWI_RESIDUAL, A; 780 not A; 781 inc A; 782 add HCNT[0], A; 783 adc HCNT[1], -1; 784 adc HCNT[2], -1 ret; 785} 786 787/* 788 * If we re-enter the data phase after going through another phase, the 789 * STCNT may have been cleared, so restore it from the residual field. 790 */ 791data_phase_reinit: 792 if ((ahc->features & AHC_ULTRA2) != 0) { 793 /* 794 * The preload circuitry requires us to 795 * reload the address too, so pull it from 796 * the shaddow address. 797 */ 798 bmov HADDR, SHADDR, 4; 799 bmov HCNT, SCB_RESIDUAL_DATACNT, 3; 800 } else if ((ahc->features & AHC_CMD_CHAN) != 0) { 801 bmov STCNT, SCB_RESIDUAL_DATACNT, 3; 802 } else { 803 mvi DINDEX, STCNT; 804 mvi SCB_RESIDUAL_DATACNT call bcopy_3; 805 } 806 and DATA_COUNT_ODD, 0x1, SCB_RESIDUAL_DATACNT[0]; 807 jmp data_phase_loop; 808 809p_data: 810 if ((ahc->features & AHC_ULTRA2) != 0) { 811 mvi DMAPARAMS, PRELOADEN|SCSIEN|HDMAEN; 812 } else { 813 mvi DMAPARAMS, WIDEODD|SCSIEN|SDMAEN|HDMAEN|FIFORESET; 814 } 815 test LASTPHASE, IOI jnz . + 2; 816 or DMAPARAMS, DIRECTION; 817 call assert; /* 818 * Ensure entering a data 819 * phase is okay - seen identify, etc. 820 */ 821 if ((ahc->features & AHC_CMD_CHAN) != 0) { 822 /* We don't have any valid S/G elements */ 823 mvi CCSGADDR, SG_PREFETCH_CNT; 824 } 825 test SEQ_FLAGS, DPHASE jnz data_phase_reinit; 826 827 /* We have seen a data phase */ 828 or SEQ_FLAGS, DPHASE; 829 830 /* 831 * Initialize the DMA address and counter from the SCB. 832 * Also set SCB_RESIDUAL_SGPTR, including the LAST_SEG 833 * flag in the highest byte of the data count. We cannot 834 * modify the saved values in the SCB until we see a save 835 * data pointers message. 836 */ 837 if ((ahc->features & AHC_CMD_CHAN) != 0) { 838 bmov HADDR, SCB_DATAPTR, 7; 839 bmov SCB_RESIDUAL_DATACNT[3], SCB_DATACNT[3], 5; 840 } else { 841 mvi DINDEX, HADDR; 842 mvi SCB_DATAPTR call bcopy_7; 843 mvi DINDEX, SCB_RESIDUAL_DATACNT + 3; 844 mvi SCB_DATACNT + 3 call bcopy_5; 845 } 846 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0) { 847 call calc_mwi_residual; 848 } 849 and SCB_RESIDUAL_SGPTR[0], ~SG_FULL_RESID; 850 and DATA_COUNT_ODD, 0x1, HCNT[0]; 851 852 if ((ahc->features & AHC_ULTRA2) == 0) { 853 if ((ahc->features & AHC_CMD_CHAN) != 0) { 854 bmov STCNT, HCNT, 3; 855 } else { 856 call set_stcnt_from_hcnt; 857 } 858 } 859 860data_phase_loop: 861 /* Guard against overruns */ 862 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz data_phase_inbounds; 863 864 /* 865 * Turn on `Bit Bucket' mode, wait until the target takes 866 * us to another phase, and then notify the host. 867 */ 868 and DMAPARAMS, DIRECTION; 869 mov DFCNTRL, DMAPARAMS; 870 or SXFRCTL1,BITBUCKET; 871 test SSTAT1,PHASEMIS jz .; 872 and SXFRCTL1, ~BITBUCKET; 873 mvi DATA_OVERRUN call set_seqint; 874 jmp ITloop; 875 876data_phase_inbounds: 877 if ((ahc->features & AHC_ULTRA2) != 0) { 878 mov SINDEX, SCB_RESIDUAL_SGPTR[0]; 879 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 2; 880 or SINDEX, LAST_SEG; 881 test DATA_COUNT_ODD, 0x1 jz . + 2; 882 or SINDEX, ODD_SEG; 883 mov SG_CACHE_PRE, SINDEX; 884 mov DFCNTRL, DMAPARAMS; 885ultra2_dma_loop: 886 call idle_loop; 887 /* 888 * The transfer is complete if either the last segment 889 * completes or the target changes phase. 890 */ 891 test SG_CACHE_SHADOW, LAST_SEG_DONE jnz ultra2_dmafinish; 892 if ((ahc->flags & AHC_TARGETROLE) != 0) { 893 /* 894 * As a target, we control the phases, 895 * so ignore PHASEMIS. 896 */ 897 test SSTAT0, TARGET jnz ultra2_dma_loop; 898 } 899 if ((ahc->flags & AHC_INITIATORROLE) != 0) { 900 test SSTAT1,PHASEMIS jz ultra2_dma_loop; 901 } 902 903ultra2_dmafinish: 904 test DFCNTRL, DIRECTION jnz ultra2_dmafifoempty; 905 and DFCNTRL, ~SCSIEN; 906 test DFCNTRL, SCSIEN jnz .; 907 if ((ahc->bugs & AHC_AUTOFLUSH_BUG) != 0) { 908 test DFSTATUS, FIFOEMP jnz ultra2_dmafifoempty; 909 } 910ultra2_dmafifoflush: 911 if ((ahc->bugs & AHC_AUTOFLUSH_BUG) != 0) { 912 /* 913 * On Rev A of the aic7890, the autoflush 914 * features doesn't function correctly. 915 * Perform an explicit manual flush. During 916 * a manual flush, the FIFOEMP bit becomes 917 * true every time the PCI FIFO empties 918 * regardless of the state of the SCSI FIFO. 919 * It can take up to 4 clock cycles for the 920 * SCSI FIFO to get data into the PCI FIFO 921 * and for FIFOEMP to de-assert. Here we 922 * guard against this condition by making 923 * sure the FIFOEMP bit stays on for 5 full 924 * clock cycles. 925 */ 926 or DFCNTRL, FIFOFLUSH; 927 test DFSTATUS, FIFOEMP jz ultra2_dmafifoflush; 928 test DFSTATUS, FIFOEMP jz ultra2_dmafifoflush; 929 test DFSTATUS, FIFOEMP jz ultra2_dmafifoflush; 930 test DFSTATUS, FIFOEMP jz ultra2_dmafifoflush; 931 } 932 test DFSTATUS, FIFOEMP jz ultra2_dmafifoflush; 933ultra2_dmafifoempty: 934 /* Don't clobber an inprogress host data transfer */ 935 test DFSTATUS, MREQPEND jnz ultra2_dmafifoempty; 936ultra2_dmahalt: 937 and DFCNTRL, ~(SCSIEN|HDMAEN); 938 test DFCNTRL, HDMAEN jnz .; 939 940 /* 941 * If, by chance, we stopped before being able 942 * to fetch additional segments for this transfer, 943 * yet the last S/G was completely exhausted, 944 * call our idle loop until it is able to load 945 * another segment. This will allow us to immediately 946 * pickup on the next segment on the next data phase. 947 * 948 * If we happened to stop on the last segment, then 949 * our residual information is still correct from 950 * the idle loop and there is no need to perform 951 * any fixups. Just jump to data_phase_finish. 952 */ 953ultra2_ensure_sg: 954 test SG_CACHE_SHADOW, LAST_SEG jz ultra2_shvalid; 955 /* Record if we've consumed all S/G entries */ 956 test SG_CACHE_SHADOW, LAST_SEG_DONE jz data_phase_finish; 957 or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL; 958 jmp data_phase_finish; 959 960ultra2_shvalid: 961 test SSTAT2, SHVALID jnz sgptr_fixup; 962 call idle_loop; 963 jmp ultra2_ensure_sg; 964 965sgptr_fixup: 966 /* 967 * Fixup the residual next S/G pointer. The S/G preload 968 * feature of the chip allows us to load two elements 969 * in addition to the currently active element. We 970 * store the bottom byte of the next S/G pointer in 971 * the SG_CACEPTR register so we can restore the 972 * correct value when the DMA completes. If the next 973 * sg ptr value has advanced to the point where higher 974 * bytes in the address have been affected, fix them 975 * too. 976 */ 977 test SG_CACHE_SHADOW, 0x80 jz sgptr_fixup_done; 978 test SCB_RESIDUAL_SGPTR[0], 0x80 jnz sgptr_fixup_done; 979 add SCB_RESIDUAL_SGPTR[1], -1; 980 adc SCB_RESIDUAL_SGPTR[2], -1; 981 adc SCB_RESIDUAL_SGPTR[3], -1; 982sgptr_fixup_done: 983 and SCB_RESIDUAL_SGPTR[0], SG_ADDR_MASK, SG_CACHE_SHADOW; 984 clr DATA_COUNT_ODD; 985 test SG_CACHE_SHADOW, ODD_SEG jz . + 2; 986 or DATA_COUNT_ODD, 0x1; 987 clr SCB_RESIDUAL_DATACNT[3]; /* We are not the last seg */ 988 } else { 989 /* If we are the last SG block, tell the hardware. */ 990 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 991 && ahc->pci_cachesize != 0) { 992 test MWI_RESIDUAL, 0xFF jnz dma_mid_sg; 993 } 994 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz dma_mid_sg; 995 if ((ahc->flags & AHC_TARGETROLE) != 0) { 996 test SSTAT0, TARGET jz dma_last_sg; 997 if ((ahc->flags & AHC_TMODE_WIDEODD_BUG) != 0) { 998 test DMAPARAMS, DIRECTION jz dma_mid_sg; 999 } 1000 } 1001dma_last_sg: 1002 and DMAPARAMS, ~WIDEODD; 1003dma_mid_sg: 1004 /* Start DMA data transfer. */ 1005 mov DFCNTRL, DMAPARAMS; 1006dma_loop: 1007 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1008 call idle_loop; 1009 } 1010 test SSTAT0,DMADONE jnz dma_dmadone; 1011 test SSTAT1,PHASEMIS jz dma_loop; /* ie. underrun */ 1012dma_phasemis: 1013 /* 1014 * We will be "done" DMAing when the transfer count goes to 1015 * zero, or the target changes the phase (in light of this, 1016 * it makes sense that the DMA circuitry doesn't ACK when 1017 * PHASEMIS is active). If we are doing a SCSI->Host transfer, 1018 * the data FIFO should be flushed auto-magically on STCNT=0 1019 * or a phase change, so just wait for FIFO empty status. 1020 */ 1021dma_checkfifo: 1022 test DFCNTRL,DIRECTION jnz dma_fifoempty; 1023dma_fifoflush: 1024 test DFSTATUS,FIFOEMP jz dma_fifoflush; 1025dma_fifoempty: 1026 /* Don't clobber an inprogress host data transfer */ 1027 test DFSTATUS, MREQPEND jnz dma_fifoempty; 1028 1029 /* 1030 * Now shut off the DMA and make sure that the DMA 1031 * hardware has actually stopped. Touching the DMA 1032 * counters, etc. while a DMA is active will result 1033 * in an ILLSADDR exception. 1034 */ 1035dma_dmadone: 1036 and DFCNTRL, ~(SCSIEN|SDMAEN|HDMAEN); 1037dma_halt: 1038 /* 1039 * Some revisions of the aic78XX have a problem where, if the 1040 * data fifo is full, but the PCI input latch is not empty, 1041 * HDMAEN cannot be cleared. The fix used here is to drain 1042 * the prefetched but unused data from the data fifo until 1043 * there is space for the input latch to drain. 1044 */ 1045 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0) { 1046 mov NONE, DFDAT; 1047 } 1048 test DFCNTRL, (SCSIEN|SDMAEN|HDMAEN) jnz dma_halt; 1049 1050 /* See if we have completed this last segment */ 1051 test STCNT[0], 0xff jnz data_phase_finish; 1052 test STCNT[1], 0xff jnz data_phase_finish; 1053 test STCNT[2], 0xff jnz data_phase_finish; 1054 1055 /* 1056 * Advance the scatter-gather pointers if needed 1057 */ 1058 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 1059 && ahc->pci_cachesize != 0) { 1060 test MWI_RESIDUAL, 0xFF jz no_mwi_resid; 1061 /* 1062 * Reload HADDR from SHADDR and setup the 1063 * count to be the size of our residual. 1064 */ 1065 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1066 bmov HADDR, SHADDR, 4; 1067 mov HCNT, MWI_RESIDUAL; 1068 bmov HCNT[1], ALLZEROS, 2; 1069 } else { 1070 mvi DINDEX, HADDR; 1071 mvi SHADDR call bcopy_4; 1072 mov MWI_RESIDUAL call set_hcnt; 1073 } 1074 clr MWI_RESIDUAL; 1075 jmp sg_load_done; 1076no_mwi_resid: 1077 } 1078 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz sg_load; 1079 or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL; 1080 jmp data_phase_finish; 1081sg_load: 1082 /* 1083 * Load the next SG element's data address and length 1084 * into the DMA engine. If we don't have hardware 1085 * to perform a prefetch, we'll have to fetch the 1086 * segment from host memory first. 1087 */ 1088 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1089 /* Wait for the idle loop to complete */ 1090 test CCSGCTL, CCSGEN jz . + 3; 1091 call idle_loop; 1092 test CCSGCTL, CCSGEN jnz . - 1; 1093 bmov HADDR, CCSGRAM, 7; 1094 test CCSGRAM, SG_LAST_SEG jz . + 2; 1095 or SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG; 1096 } else { 1097 mvi DINDEX, HADDR; 1098 mvi SCB_RESIDUAL_SGPTR call bcopy_4; 1099 1100 mvi SG_SIZEOF call set_hcnt; 1101 1102 or DFCNTRL, HDMAEN|DIRECTION|FIFORESET; 1103 1104 call dma_finish; 1105 1106 mvi DINDEX, HADDR; 1107 call dfdat_in_7; 1108 mov SCB_RESIDUAL_DATACNT[3], DFDAT; 1109 } 1110 1111 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 1112 && ahc->pci_cachesize != 0) { 1113 call calc_mwi_residual; 1114 } 1115 1116 /* Point to the new next sg in memory */ 1117 call sg_advance; 1118 1119sg_load_done: 1120 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1121 bmov STCNT, HCNT, 3; 1122 } else { 1123 call set_stcnt_from_hcnt; 1124 } 1125 /* Track odd'ness */ 1126 test HCNT[0], 0x1 jz . + 2; 1127 xor DATA_COUNT_ODD, 0x1; 1128 1129 if ((ahc->flags & AHC_TARGETROLE) != 0) { 1130 test SSTAT0, TARGET jnz data_phase_loop; 1131 } 1132 } 1133data_phase_finish: 1134 /* 1135 * If the target has left us in data phase, loop through 1136 * the dma code again. In the case of ULTRA2 adapters, 1137 * we should only loop if there is a data overrun. For 1138 * all other adapters, we'll loop after each S/G element 1139 * is loaded as well as if there is an overrun. 1140 */ 1141 if ((ahc->flags & AHC_TARGETROLE) != 0) { 1142 test SSTAT0, TARGET jnz data_phase_done; 1143 } 1144 if ((ahc->flags & AHC_INITIATORROLE) != 0) { 1145 test SSTAT1, REQINIT jz .; 1146 test SSTAT1,PHASEMIS jz data_phase_loop; 1147 1148 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1149 /* Kill off any pending prefetch */ 1150 clr CCSGCTL; 1151 test CCSGCTL, CCSGEN jnz .; 1152 } 1153 } 1154 1155data_phase_done: 1156 /* 1157 * After a DMA finishes, save the SG and STCNT residuals back into 1158 * the SCB. We use STCNT instead of HCNT, since it's a reflection 1159 * of how many bytes were transferred on the SCSI (as opposed to the 1160 * host) bus. 1161 */ 1162 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1163 /* Kill off any pending prefetch */ 1164 clr CCSGCTL; 1165 test CCSGCTL, CCSGEN jnz .; 1166 } 1167 1168 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 1169 && ahc->pci_cachesize != 0) { 1170 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1171 test MWI_RESIDUAL, 0xFF jz bmov_resid; 1172 } 1173 mov A, MWI_RESIDUAL; 1174 add SCB_RESIDUAL_DATACNT[0], A, STCNT[0]; 1175 clr A; 1176 adc SCB_RESIDUAL_DATACNT[1], A, STCNT[1]; 1177 adc SCB_RESIDUAL_DATACNT[2], A, STCNT[2]; 1178 clr MWI_RESIDUAL; 1179 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1180 jmp . + 2; 1181bmov_resid: 1182 bmov SCB_RESIDUAL_DATACNT, STCNT, 3; 1183 } 1184 } else if ((ahc->features & AHC_CMD_CHAN) != 0) { 1185 bmov SCB_RESIDUAL_DATACNT, STCNT, 3; 1186 } else { 1187 mov SCB_RESIDUAL_DATACNT[0], STCNT[0]; 1188 mov SCB_RESIDUAL_DATACNT[1], STCNT[1]; 1189 mov SCB_RESIDUAL_DATACNT[2], STCNT[2]; 1190 } 1191 1192 /* 1193 * Since we've been through a data phase, the SCB_RESID* fields 1194 * are now initialized. Clear the full residual flag. 1195 */ 1196 and SCB_SGPTR[0], ~SG_FULL_RESID; 1197 1198 if ((ahc->features & AHC_ULTRA2) != 0) { 1199 /* Clear the channel in case we return to data phase later */ 1200 or SXFRCTL0, CLRSTCNT|CLRCHN; 1201 or SXFRCTL0, CLRSTCNT|CLRCHN; 1202 } 1203 1204 if ((ahc->flags & AHC_TARGETROLE) != 0) { 1205 test SEQ_FLAGS, DPHASE_PENDING jz ITloop; 1206 and SEQ_FLAGS, ~DPHASE_PENDING; 1207 /* 1208 * For data-in phases, wait for any pending acks from the 1209 * initiator before changing phase. 1210 */ 1211 test DFCNTRL, DIRECTION jz target_ITloop; 1212 test SSTAT1, REQINIT jnz .; 1213 jmp target_ITloop; 1214 } else { 1215 jmp ITloop; 1216 } 1217 1218if ((ahc->flags & AHC_INITIATORROLE) != 0) { 1219/* 1220 * Command phase. Set up the DMA registers and let 'er rip. 1221 */ 1222p_command: 1223 call assert; 1224 1225 if ((ahc->features & AHC_ULTRA2) != 0) { 1226 bmov HCNT[0], SCB_CDB_LEN, 1; 1227 bmov HCNT[1], ALLZEROS, 2; 1228 mvi SG_CACHE_PRE, LAST_SEG; 1229 } else if ((ahc->features & AHC_CMD_CHAN) != 0) { 1230 bmov STCNT[0], SCB_CDB_LEN, 1; 1231 bmov STCNT[1], ALLZEROS, 2; 1232 } else { 1233 mov STCNT[0], SCB_CDB_LEN; 1234 clr STCNT[1]; 1235 clr STCNT[2]; 1236 } 1237 add NONE, -13, SCB_CDB_LEN; 1238 mvi SCB_CDB_STORE jnc p_command_embedded; 1239p_command_from_host: 1240 if ((ahc->features & AHC_ULTRA2) != 0) { 1241 bmov HADDR[0], SCB_CDB_PTR, 4; 1242 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN|DIRECTION); 1243 } else { 1244 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1245 bmov HADDR[0], SCB_CDB_PTR, 4; 1246 bmov HCNT, STCNT, 3; 1247 } else { 1248 mvi DINDEX, HADDR; 1249 mvi SCB_CDB_PTR call bcopy_4; 1250 mov SCB_CDB_LEN call set_hcnt; 1251 } 1252 mvi DFCNTRL, (SCSIEN|SDMAEN|HDMAEN|DIRECTION|FIFORESET); 1253 } 1254 jmp p_command_loop; 1255p_command_embedded: 1256 /* 1257 * The data fifo seems to require 4 byte alligned 1258 * transfers from the sequencer. Force this to 1259 * be the case by clearing HADDR[0] even though 1260 * we aren't going to touch host memeory. 1261 */ 1262 clr HADDR[0]; 1263 if ((ahc->features & AHC_ULTRA2) != 0) { 1264 mvi DFCNTRL, (PRELOADEN|SCSIEN|DIRECTION); 1265 bmov DFDAT, SCB_CDB_STORE, 12; 1266 } else if ((ahc->features & AHC_CMD_CHAN) != 0) { 1267 if ((ahc->flags & AHC_SCB_BTT) != 0) { 1268 /* 1269 * On the 7895 the data FIFO will 1270 * get corrupted if you try to dump 1271 * data from external SCB memory into 1272 * the FIFO while it is enabled. So, 1273 * fill the fifo and then enable SCSI 1274 * transfers. 1275 */ 1276 mvi DFCNTRL, (DIRECTION|FIFORESET); 1277 } else { 1278 mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFORESET); 1279 } 1280 bmov DFDAT, SCB_CDB_STORE, 12; 1281 if ((ahc->flags & AHC_SCB_BTT) != 0) { 1282 mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFOFLUSH); 1283 } else { 1284 or DFCNTRL, FIFOFLUSH; 1285 } 1286 } else { 1287 mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFORESET); 1288 call copy_to_fifo_6; 1289 call copy_to_fifo_6; 1290 or DFCNTRL, FIFOFLUSH; 1291 } 1292p_command_loop: 1293 test SSTAT0, SDONE jnz . + 2; 1294 test SSTAT1, PHASEMIS jz p_command_loop; 1295 /* 1296 * Wait for our ACK to go-away on it's own 1297 * instead of being killed by SCSIEN getting cleared. 1298 */ 1299 test SCSISIGI, ACKI jnz .; 1300 and DFCNTRL, ~(SCSIEN|SDMAEN|HDMAEN); 1301 test DFCNTRL, (SCSIEN|SDMAEN|HDMAEN) jnz .; 1302 if ((ahc->features & AHC_ULTRA2) != 0) { 1303 /* Drop any residual from the S/G Preload queue */ 1304 or SXFRCTL0, CLRSTCNT; 1305 } 1306 jmp ITloop; 1307 1308/* 1309 * Status phase. Wait for the data byte to appear, then read it 1310 * and store it into the SCB. 1311 */ 1312p_status: 1313 call assert; 1314 1315 mov SCB_SCSI_STATUS, SCSIDATL; 1316 jmp ITloop; 1317 1318/* 1319 * Message out phase. If MSG_OUT is MSG_IDENTIFYFLAG, build a full 1320 * indentify message sequence and send it to the target. The host may 1321 * override this behavior by setting the MK_MESSAGE bit in the SCB 1322 * control byte. This will cause us to interrupt the host and allow 1323 * it to handle the message phase completely on its own. If the bit 1324 * associated with this target is set, we will also interrupt the host, 1325 * thereby allowing it to send a message on the next selection regardless 1326 * of the transaction being sent. 1327 * 1328 * If MSG_OUT is == HOST_MSG, also interrupt the host and take a message. 1329 * This is done to allow the host to send messages outside of an identify 1330 * sequence while protecting the seqencer from testing the MK_MESSAGE bit 1331 * on an SCB that might not be for the current nexus. (For example, a 1332 * BDR message in responce to a bad reselection would leave us pointed to 1333 * an SCB that doesn't have anything to do with the current target). 1334 * 1335 * Otherwise, treat MSG_OUT as a 1 byte message to send (abort, abort tag, 1336 * bus device reset). 1337 * 1338 * When there are no messages to send, MSG_OUT should be set to MSG_NOOP, 1339 * in case the target decides to put us in this phase for some strange 1340 * reason. 1341 */ 1342p_mesgout_retry: 1343 or SCSISIGO,ATNO,LASTPHASE;/* turn on ATN for the retry */ 1344p_mesgout: 1345 mov SINDEX, MSG_OUT; 1346 cmp SINDEX, MSG_IDENTIFYFLAG jne p_mesgout_from_host; 1347 test SCB_CONTROL,MK_MESSAGE jnz host_message_loop; 1348 mov FUNCTION1, SCB_SCSIID; 1349 mov A, FUNCTION1; 1350 mov SINDEX, TARGET_MSG_REQUEST[0]; 1351 if ((ahc->features & AHC_TWIN) != 0) { 1352 /* Second Channel uses high byte bits */ 1353 test SCB_SCSIID, TWIN_CHNLB jz . + 2; 1354 mov SINDEX, TARGET_MSG_REQUEST[1]; 1355 } else if ((ahc->features & AHC_WIDE) != 0) { 1356 test SCB_SCSIID, 0x80 jz . + 2; /* target > 7 */ 1357 mov SINDEX, TARGET_MSG_REQUEST[1]; 1358 } 1359 test SINDEX, A jnz host_message_loop; 1360p_mesgout_identify: 1361 or SINDEX, MSG_IDENTIFYFLAG|DISCENB, SCB_LUN; 1362 test SCB_CONTROL, DISCENB jnz . + 2; 1363 and SINDEX, ~DISCENB; 1364/* 1365 * Send a tag message if TAG_ENB is set in the SCB control block. 1366 * Use SCB_TAG (the position in the kernel's SCB array) as the tag value. 1367 */ 1368p_mesgout_tag: 1369 test SCB_CONTROL,TAG_ENB jz p_mesgout_onebyte; 1370 mov SCSIDATL, SINDEX; /* Send the identify message */ 1371 call phase_lock; 1372 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done; 1373 and SCSIDATL,TAG_ENB|SCB_TAG_TYPE,SCB_CONTROL; 1374 call phase_lock; 1375 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done; 1376 mov SCB_TAG jmp p_mesgout_onebyte; 1377/* 1378 * Interrupt the driver, and allow it to handle this message 1379 * phase and any required retries. 1380 */ 1381p_mesgout_from_host: 1382 cmp SINDEX, HOST_MSG jne p_mesgout_onebyte; 1383 jmp host_message_loop; 1384 1385p_mesgout_onebyte: 1386 mvi CLRSINT1, CLRATNO; 1387 mov SCSIDATL, SINDEX; 1388 1389/* 1390 * If the next bus phase after ATN drops is message out, it means 1391 * that the target is requesting that the last message(s) be resent. 1392 */ 1393 call phase_lock; 1394 cmp LASTPHASE, P_MESGOUT je p_mesgout_retry; 1395 1396p_mesgout_done: 1397 mvi CLRSINT1,CLRATNO; /* Be sure to turn ATNO off */ 1398 mov LAST_MSG, MSG_OUT; 1399 mvi MSG_OUT, MSG_NOOP; /* No message left */ 1400 jmp ITloop; 1401 1402/* 1403 * Message in phase. Bytes are read using Automatic PIO mode. 1404 */ 1405p_mesgin: 1406 mvi ACCUM call inb_first; /* read the 1st message byte */ 1407 1408 test A,MSG_IDENTIFYFLAG jnz mesgin_identify; 1409 cmp A,MSG_DISCONNECT je mesgin_disconnect; 1410 cmp A,MSG_SAVEDATAPOINTER je mesgin_sdptrs; 1411 cmp ALLZEROS,A je mesgin_complete; 1412 cmp A,MSG_RESTOREPOINTERS je mesgin_rdptrs; 1413 cmp A,MSG_IGN_WIDE_RESIDUE je mesgin_ign_wide_residue; 1414 cmp A,MSG_NOOP je mesgin_done; 1415 1416/* 1417 * Pushed message loop to allow the kernel to 1418 * run it's own message state engine. To avoid an 1419 * extra nop instruction after signaling the kernel, 1420 * we perform the phase_lock before checking to see 1421 * if we should exit the loop and skip the phase_lock 1422 * in the ITloop. Performing back to back phase_locks 1423 * shouldn't hurt, but why do it twice... 1424 */ 1425host_message_loop: 1426 mvi HOST_MSG_LOOP call set_seqint; 1427 call phase_lock; 1428 cmp RETURN_1, EXIT_MSG_LOOP je ITloop + 1; 1429 jmp host_message_loop; 1430 1431mesgin_ign_wide_residue: 1432if ((ahc->features & AHC_WIDE) != 0) { 1433 test SCSIRATE, WIDEXFER jz mesgin_reject; 1434 /* Pull the residue byte */ 1435 mvi ARG_1 call inb_next; 1436 cmp ARG_1, 0x01 jne mesgin_reject; 1437 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz . + 2; 1438 test DATA_COUNT_ODD, 0x1 jz mesgin_done; 1439 mvi IGN_WIDE_RES call set_seqint; 1440 jmp mesgin_done; 1441} 1442 1443mesgin_reject: 1444 mvi MSG_MESSAGE_REJECT call mk_mesg; 1445mesgin_done: 1446 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/ 1447 jmp ITloop; 1448 1449mesgin_complete: 1450/* 1451 * We received a "command complete" message. Put the SCB_TAG into the QOUTFIFO, 1452 * and trigger a completion interrupt. Before doing so, check to see if there 1453 * is a residual or the status byte is something other than STATUS_GOOD (0). 1454 * In either of these conditions, we upload the SCB back to the host so it can 1455 * process this information. In the case of a non zero status byte, we 1456 * additionally interrupt the kernel driver synchronously, allowing it to 1457 * decide if sense should be retrieved. If the kernel driver wishes to request 1458 * sense, it will fill the kernel SCB with a request sense command, requeue 1459 * it to the QINFIFO and tell us not to post to the QOUTFIFO by setting 1460 * RETURN_1 to SEND_SENSE. 1461 */ 1462 1463/* 1464 * If ATN is raised, we still want to give the target a message. 1465 * Perhaps there was a parity error on this last message byte. 1466 * Either way, the target should take us to message out phase 1467 * and then attempt to complete the command again. 1468 * XXX - Need a critical section to do this corrctly. Wait until 1469 * we queue completions. 1470 test SCSISIGI, ATNI jnz mesgin_done; 1471 */ 1472 1473/* 1474 * See if we attempted to deliver a message but the target ingnored us. 1475 */ 1476 test SCB_CONTROL, MK_MESSAGE jz . + 2; 1477 mvi MKMSG_FAILED call set_seqint; 1478 1479/* 1480 * Check for residuals 1481 */ 1482 test SCB_SGPTR, SG_LIST_NULL jnz check_status;/* No xfer */ 1483 test SCB_SGPTR, SG_FULL_RESID jnz upload_scb;/* Never xfered */ 1484 test SCB_RESIDUAL_SGPTR, SG_LIST_NULL jz upload_scb; 1485check_status: 1486 test SCB_SCSI_STATUS,0xff jz complete; /* Good Status? */ 1487upload_scb: 1488 or SCB_SGPTR, SG_RESID_VALID; 1489 mvi DMAPARAMS, FIFORESET; 1490 mov SCB_TAG call dma_scb; 1491 test SCB_SCSI_STATUS, 0xff jz complete; /* Just a residual? */ 1492 mvi BAD_STATUS call set_seqint; /* let driver know */ 1493 cmp RETURN_1, SEND_SENSE jne complete; 1494 call add_scb_to_free_list; 1495 jmp await_busfree; 1496complete: 1497 mov SCB_TAG call complete_post; 1498 jmp await_busfree; 1499} 1500 1501complete_post: 1502 /* Post the SCBID in SINDEX and issue an interrupt */ 1503 call add_scb_to_free_list; 1504 mov ARG_1, SINDEX; 1505 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 1506 mov A, SDSCB_QOFF; 1507 } else { 1508 mov A, QOUTPOS; 1509 } 1510 mvi QOUTFIFO_OFFSET call post_byte_setup; 1511 mov ARG_1 call post_byte; 1512 if ((ahc->features & AHC_QUEUE_REGS) == 0) { 1513 inc QOUTPOS; 1514 } 1515 mvi INTSTAT,CMDCMPLT ret; 1516 1517if ((ahc->flags & AHC_INITIATORROLE) != 0) { 1518/* 1519 * Is it a disconnect message? Set a flag in the SCB to remind us 1520 * and await the bus going free. If this is an untagged transaction 1521 * store the SCB id for it in our untagged target table for lookup on 1522 * a reselction. 1523 */ 1524mesgin_disconnect: 1525 /* 1526 * If ATN is raised, we still want to give the target a message. 1527 * Perhaps there was a parity error on this last message byte 1528 * or we want to abort this command. Either way, the target 1529 * should take us to message out phase and then attempt to 1530 * disconnect again. 1531 * XXX - Wait for more testing. 1532 test SCSISIGI, ATNI jnz mesgin_done; 1533 */ 1534 1535 or SCB_CONTROL,DISCONNECTED; 1536 if ((ahc->flags & AHC_PAGESCBS) != 0) { 1537 call add_scb_to_disc_list; 1538 } 1539 test SCB_CONTROL, TAG_ENB jnz await_busfree; 1540 mov ARG_1, SCB_TAG; 1541 mov SAVED_LUN, SCB_LUN; 1542 mov SCB_SCSIID call set_busy_target; 1543 jmp await_busfree; 1544 1545/* 1546 * Save data pointers message: 1547 * Copying RAM values back to SCB, for Save Data Pointers message, but 1548 * only if we've actually been into a data phase to change them. This 1549 * protects against bogus data in scratch ram and the residual counts 1550 * since they are only initialized when we go into data_in or data_out. 1551 */ 1552mesgin_sdptrs: 1553 test SEQ_FLAGS, DPHASE jz mesgin_done; 1554 1555 /* 1556 * The SCB_SGPTR becomes the next one we'll download, 1557 * and the SCB_DATAPTR becomes the current SHADDR. 1558 * Use the residual number since STCNT is corrupted by 1559 * any message transfer. 1560 */ 1561 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1562 bmov SCB_DATAPTR, SHADDR, 4; 1563 bmov SCB_DATACNT, SCB_RESIDUAL_DATACNT, 8; 1564 } else { 1565 mvi DINDEX, SCB_DATAPTR; 1566 mvi SHADDR call bcopy_4; 1567 mvi SCB_RESIDUAL_DATACNT call bcopy_8; 1568 } 1569 jmp mesgin_done; 1570 1571/* 1572 * Restore pointers message? Data pointers are recopied from the 1573 * SCB anytime we enter a data phase for the first time, so all 1574 * we need to do is clear the DPHASE flag and let the data phase 1575 * code do the rest. 1576 */ 1577mesgin_rdptrs: 1578 and SEQ_FLAGS, ~DPHASE; /* 1579 * We'll reload them 1580 * the next time through 1581 * the dataphase. 1582 */ 1583 jmp mesgin_done; 1584 1585/* 1586 * Index into our Busy Target table. SINDEX and DINDEX are modified 1587 * upon return. SCBPTR may be modified by this action. 1588 */ 1589set_busy_target: 1590 shr DINDEX, 4, SINDEX; 1591 if ((ahc->flags & AHC_SCB_BTT) != 0) { 1592 mov SCBPTR, SAVED_LUN; 1593 add DINDEX, SCB_64_BTT; 1594 } else { 1595 add DINDEX, BUSY_TARGETS; 1596 } 1597 mov DINDIR, ARG_1 ret; 1598 1599/* 1600 * Identify message? For a reconnecting target, this tells us the lun 1601 * that the reconnection is for - find the correct SCB and switch to it, 1602 * clearing the "disconnected" bit so we don't "find" it by accident later. 1603 */ 1604mesgin_identify: 1605 /* 1606 * Determine whether a target is using tagged or non-tagged 1607 * transactions by first looking at the transaction stored in 1608 * the busy target array. If there is no untagged transaction 1609 * for this target or the transaction is for a different lun, then 1610 * this must be an untagged transaction. 1611 */ 1612 shr SINDEX, 4, SELID; 1613 and SAVED_LUN, MSG_IDENTIFY_LUNMASK, A; 1614 if ((ahc->flags & AHC_SCB_BTT) != 0) { 1615 add SINDEX, SCB_64_BTT; 1616 mov SCBPTR, SAVED_LUN; 1617 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 1618 add NONE, -SCB_64_BTT, SINDEX; 1619 jc . + 2; 1620 mvi INTSTAT, OUT_OF_RANGE; 1621 nop; 1622 add NONE, -(SCB_64_BTT + 16), SINDEX; 1623 jnc . + 2; 1624 mvi INTSTAT, OUT_OF_RANGE; 1625 nop; 1626 } 1627 } else { 1628 add SINDEX, BUSY_TARGETS; 1629 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 1630 add NONE, -BUSY_TARGETS, SINDEX; 1631 jc . + 2; 1632 mvi INTSTAT, OUT_OF_RANGE; 1633 nop; 1634 add NONE, -(BUSY_TARGETS + 16), SINDEX; 1635 jnc . + 2; 1636 mvi INTSTAT, OUT_OF_RANGE; 1637 nop; 1638 } 1639 } 1640 mov ARG_1, SINDIR; 1641 cmp ARG_1, SCB_LIST_NULL je snoop_tag; 1642 if ((ahc->flags & AHC_PAGESCBS) != 0) { 1643 mov ARG_1 call findSCB; 1644 } else { 1645 mov SCBPTR, RETURN_1; 1646 } 1647 if ((ahc->flags & AHC_SCB_BTT) != 0) { 1648 jmp setup_SCB_id_lun_okay; 1649 } else { 1650 jmp setup_SCB_id_okay; 1651 } 1652 1653/* 1654 * Here we "snoop" the bus looking for a SIMPLE QUEUE TAG message. 1655 * If we get one, we use the tag returned to find the proper 1656 * SCB. With SCB paging, we must search for non-tagged 1657 * transactions since the SCB may exist in any slot. If we're not 1658 * using SCB paging, we can use the tag as the direct index to the 1659 * SCB. 1660 */ 1661snoop_tag: 1662 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 1663 or SEQ_FLAGS, 0x80; 1664 } 1665 mov NONE,SCSIDATL; /* ACK Identify MSG */ 1666 call phase_lock; 1667 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 1668 or SEQ_FLAGS, 0x1; 1669 } 1670 cmp LASTPHASE, P_MESGIN jne not_found; 1671 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 1672 or SEQ_FLAGS, 0x2; 1673 } 1674 cmp SCSIBUSL,MSG_SIMPLE_Q_TAG jne not_found; 1675get_tag: 1676 if ((ahc->flags & AHC_PAGESCBS) != 0) { 1677 mvi ARG_1 call inb_next; /* tag value */ 1678 mov ARG_1 call findSCB; 1679 } else { 1680 mvi ARG_1 call inb_next; /* tag value */ 1681 mov SCBPTR, ARG_1; 1682 } 1683 1684/* 1685 * Ensure that the SCB the tag points to is for 1686 * an SCB transaction to the reconnecting target. 1687 */ 1688setup_SCB: 1689 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 1690 or SEQ_FLAGS, 0x4; 1691 } 1692 mov A, SCB_SCSIID; 1693 cmp SAVED_SCSIID, A jne not_found_cleanup_scb; 1694 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 1695 or SEQ_FLAGS, 0x8; 1696 } 1697setup_SCB_id_okay: 1698 mov A, SCB_LUN; 1699 cmp SAVED_LUN, A jne not_found_cleanup_scb; 1700setup_SCB_id_lun_okay: 1701 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 1702 or SEQ_FLAGS, 0x10; 1703 } 1704 test SCB_CONTROL,DISCONNECTED jz not_found_cleanup_scb; 1705 and SCB_CONTROL,~DISCONNECTED; 1706 test SCB_CONTROL, TAG_ENB jnz setup_SCB_tagged; 1707 mov A, SCBPTR; 1708 mvi ARG_1, SCB_LIST_NULL; 1709 mov SAVED_SCSIID call set_busy_target; 1710 mov SCBPTR, A; 1711setup_SCB_tagged: 1712 mvi SEQ_FLAGS,IDENTIFY_SEEN; /* make note of IDENTIFY */ 1713 call set_transfer_settings; 1714 /* See if the host wants to send a message upon reconnection */ 1715 test SCB_CONTROL, MK_MESSAGE jz mesgin_done; 1716 mvi HOST_MSG call mk_mesg; 1717 jmp mesgin_done; 1718 1719not_found_cleanup_scb: 1720 if ((ahc->flags & AHC_PAGESCBS) != 0) { 1721 call add_scb_to_free_list; 1722 } 1723not_found: 1724 mvi NO_MATCH call set_seqint; 1725 jmp mesgin_done; 1726 1727mk_mesg: 1728 or SCSISIGO,ATNO,LASTPHASE;/* turn on ATNO */ 1729 mov MSG_OUT,SINDEX ret; 1730 1731/* 1732 * Functions to read data in Automatic PIO mode. 1733 * 1734 * According to Adaptec's documentation, an ACK is not sent on input from 1735 * the target until SCSIDATL is read from. So we wait until SCSIDATL is 1736 * latched (the usual way), then read the data byte directly off the bus 1737 * using SCSIBUSL. When we have pulled the ATN line, or we just want to 1738 * acknowledge the byte, then we do a dummy read from SCISDATL. The SCSI 1739 * spec guarantees that the target will hold the data byte on the bus until 1740 * we send our ACK. 1741 * 1742 * The assumption here is that these are called in a particular sequence, 1743 * and that REQ is already set when inb_first is called. inb_{first,next} 1744 * use the same calling convention as inb. 1745 */ 1746inb_next_wait_perr: 1747 mvi PERR_DETECTED call set_seqint; 1748 jmp inb_next_wait; 1749inb_next: 1750 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/ 1751inb_next_wait: 1752 /* 1753 * If there is a parity error, wait for the kernel to 1754 * see the interrupt and prepare our message response 1755 * before continuing. 1756 */ 1757 test SSTAT1, REQINIT jz inb_next_wait; 1758 test SSTAT1, SCSIPERR jnz inb_next_wait_perr; 1759inb_next_check_phase: 1760 and LASTPHASE, PHASE_MASK, SCSISIGI; 1761 cmp LASTPHASE, P_MESGIN jne mesgin_phasemis; 1762inb_first: 1763 mov DINDEX,SINDEX; 1764 mov DINDIR,SCSIBUSL ret; /*read byte directly from bus*/ 1765inb_last: 1766 mov NONE,SCSIDATL ret; /*dummy read from latch to ACK*/ 1767} 1768 1769if ((ahc->flags & AHC_TARGETROLE) != 0) { 1770/* 1771 * Change to a new phase. If we are changing the state of the I/O signal, 1772 * from out to in, wait an additional data release delay before continuing. 1773 */ 1774change_phase: 1775 /* Wait for preceeding I/O session to complete. */ 1776 test SCSISIGI, ACKI jnz .; 1777 1778 /* Change the phase */ 1779 and DINDEX, IOI, SCSISIGI; 1780 mov SCSISIGO, SINDEX; 1781 and A, IOI, SINDEX; 1782 1783 /* 1784 * If the data direction has changed, from 1785 * out (initiator driving) to in (target driving), 1786 * we must wait at least a data release delay plus 1787 * the normal bus settle delay. [SCSI III SPI 10.11.0] 1788 */ 1789 cmp DINDEX, A je change_phase_wait; 1790 test SINDEX, IOI jz change_phase_wait; 1791 call change_phase_wait; 1792change_phase_wait: 1793 nop; 1794 nop; 1795 nop; 1796 nop ret; 1797 1798/* 1799 * Send a byte to an initiator in Automatic PIO mode. 1800 */ 1801target_outb: 1802 or SXFRCTL0, SPIOEN; 1803 test SSTAT0, SPIORDY jz .; 1804 mov SCSIDATL, SINDEX; 1805 test SSTAT0, SPIORDY jz .; 1806 and SXFRCTL0, ~SPIOEN ret; 1807} 1808 1809 1810/* 1811 * Assert that if we've been reselected, then we've seen an IDENTIFY 1812 * message. 1813 */ 1814assert: 1815 test SEQ_FLAGS,IDENTIFY_SEEN jnz return; /* seen IDENTIFY? */ 1816 1817 mvi NO_IDENT jmp set_seqint; /* no - tell the kernel */ 1818 1819/* 1820 * Locate a disconnected SCB by SCBID. Upon return, SCBPTR and SINDEX will 1821 * be set to the position of the SCB. If the SCB cannot be found locally, 1822 * it will be paged in from host memory. RETURN_2 stores the address of the 1823 * preceding SCB in the disconnected list which can be used to speed up 1824 * removal of the found SCB from the disconnected list. 1825 */ 1826if ((ahc->flags & AHC_PAGESCBS) != 0) { 1827BEGIN_CRITICAL 1828findSCB: 1829 mov A, SINDEX; /* Tag passed in SINDEX */ 1830 cmp DISCONNECTED_SCBH, SCB_LIST_NULL je findSCB_notFound; 1831 mov SCBPTR, DISCONNECTED_SCBH; /* Initialize SCBPTR */ 1832 mvi ARG_2, SCB_LIST_NULL; /* Head of list */ 1833 jmp findSCB_loop; 1834findSCB_next: 1835 cmp SCB_NEXT, SCB_LIST_NULL je findSCB_notFound; 1836 mov ARG_2, SCBPTR; 1837 mov SCBPTR,SCB_NEXT; 1838findSCB_loop: 1839 cmp SCB_TAG, A jne findSCB_next; 1840rem_scb_from_disc_list: 1841 cmp ARG_2, SCB_LIST_NULL je rHead; 1842 mov DINDEX, SCB_NEXT; 1843 mov SINDEX, SCBPTR; 1844 mov SCBPTR, ARG_2; 1845 mov SCB_NEXT, DINDEX; 1846 mov SCBPTR, SINDEX ret; 1847rHead: 1848 mov DISCONNECTED_SCBH,SCB_NEXT ret; 1849END_CRITICAL 1850findSCB_notFound: 1851 /* 1852 * We didn't find it. Page in the SCB. 1853 */ 1854 mov ARG_1, A; /* Save tag */ 1855 mov ALLZEROS call get_free_or_disc_scb; 1856 mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET; 1857 mov ARG_1 jmp dma_scb; 1858} 1859 1860/* 1861 * Prepare the hardware to post a byte to host memory given an 1862 * index of (A + (256 * SINDEX)) and a base address of SHARED_DATA_ADDR. 1863 */ 1864post_byte_setup: 1865 mov ARG_2, SINDEX; 1866 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1867 mvi DINDEX, CCHADDR; 1868 mvi SHARED_DATA_ADDR call set_1byte_addr; 1869 mvi CCHCNT, 1; 1870 mvi CCSCBCTL, CCSCBRESET ret; 1871 } else { 1872 mvi DINDEX, HADDR; 1873 mvi SHARED_DATA_ADDR call set_1byte_addr; 1874 mvi 1 call set_hcnt; 1875 mvi DFCNTRL, FIFORESET ret; 1876 } 1877 1878post_byte: 1879 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1880 bmov CCSCBRAM, SINDEX, 1; 1881 or CCSCBCTL, CCSCBEN|CCSCBRESET; 1882 test CCSCBCTL, CCSCBDONE jz .; 1883 clr CCSCBCTL ret; 1884 } else { 1885 mov DFDAT, SINDEX; 1886 or DFCNTRL, HDMAEN|FIFOFLUSH; 1887 jmp dma_finish; 1888 } 1889 1890phase_lock_perr: 1891 mvi PERR_DETECTED call set_seqint; 1892phase_lock: 1893 /* 1894 * If there is a parity error, wait for the kernel to 1895 * see the interrupt and prepare our message response 1896 * before continuing. 1897 */ 1898 test SSTAT1, REQINIT jz phase_lock; 1899 test SSTAT1, SCSIPERR jnz phase_lock_perr; 1900phase_lock_latch_phase: 1901 and SCSISIGO, PHASE_MASK, SCSISIGI; 1902 and LASTPHASE, PHASE_MASK, SCSISIGI ret; 1903 1904if ((ahc->features & AHC_CMD_CHAN) == 0) { 1905set_hcnt: 1906 mov HCNT[0], SINDEX; 1907clear_hcnt: 1908 clr HCNT[1]; 1909 clr HCNT[2] ret; 1910 1911set_stcnt_from_hcnt: 1912 mov STCNT[0], HCNT[0]; 1913 mov STCNT[1], HCNT[1]; 1914 mov STCNT[2], HCNT[2] ret; 1915 1916bcopy_8: 1917 mov DINDIR, SINDIR; 1918bcopy_7: 1919 mov DINDIR, SINDIR; 1920 mov DINDIR, SINDIR; 1921bcopy_5: 1922 mov DINDIR, SINDIR; 1923bcopy_4: 1924 mov DINDIR, SINDIR; 1925bcopy_3: 1926 mov DINDIR, SINDIR; 1927 mov DINDIR, SINDIR; 1928 mov DINDIR, SINDIR ret; 1929} 1930 1931if ((ahc->flags & AHC_TARGETROLE) != 0) { 1932/* 1933 * Setup addr assuming that A is an index into 1934 * an array of 32byte objects, SINDEX contains 1935 * the base address of that array, and DINDEX 1936 * contains the base address of the location 1937 * to store the indexed address. 1938 */ 1939set_32byte_addr: 1940 shr ARG_2, 3, A; 1941 shl A, 5; 1942 jmp set_1byte_addr; 1943} 1944 1945/* 1946 * Setup addr assuming that A is an index into 1947 * an array of 64byte objects, SINDEX contains 1948 * the base address of that array, and DINDEX 1949 * contains the base address of the location 1950 * to store the indexed address. 1951 */ 1952set_64byte_addr: 1953 shr ARG_2, 2, A; 1954 shl A, 6; 1955 1956/* 1957 * Setup addr assuming that A + (ARG_2 * 256) is an 1958 * index into an array of 1byte objects, SINDEX contains 1959 * the base address of that array, and DINDEX contains 1960 * the base address of the location to store the computed 1961 * address. 1962 */ 1963set_1byte_addr: 1964 add DINDIR, A, SINDIR; 1965 mov A, ARG_2; 1966 adc DINDIR, A, SINDIR; 1967 clr A; 1968 adc DINDIR, A, SINDIR; 1969 adc DINDIR, A, SINDIR ret; 1970 1971/* 1972 * Either post or fetch and SCB from host memory based on the 1973 * DIRECTION bit in DMAPARAMS. The host SCB index is in SINDEX. 1974 */ 1975dma_scb: 1976 mov A, SINDEX; 1977 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1978 mvi DINDEX, CCHADDR; 1979 mvi HSCB_ADDR call set_64byte_addr; 1980 mov CCSCBPTR, SCBPTR; 1981 test DMAPARAMS, DIRECTION jz dma_scb_tohost; 1982 if ((ahc->flags & AHC_SCB_BTT) != 0) { 1983 mvi CCHCNT, SCB_DOWNLOAD_SIZE_64; 1984 } else { 1985 mvi CCHCNT, SCB_DOWNLOAD_SIZE; 1986 } 1987 mvi CCSCBCTL, CCARREN|CCSCBEN|CCSCBDIR|CCSCBRESET; 1988 cmp CCSCBCTL, CCSCBDONE|ARRDONE|CCARREN|CCSCBEN|CCSCBDIR jne .; 1989 jmp dma_scb_finish; 1990dma_scb_tohost: 1991 mvi CCHCNT, SCB_UPLOAD_SIZE; 1992 if ((ahc->features & AHC_ULTRA2) == 0) { 1993 mvi CCSCBCTL, CCSCBRESET; 1994 bmov CCSCBRAM, SCB_BASE, SCB_UPLOAD_SIZE; 1995 or CCSCBCTL, CCSCBEN|CCSCBRESET; 1996 test CCSCBCTL, CCSCBDONE jz .; 1997 } else if ((ahc->bugs & AHC_SCBCHAN_UPLOAD_BUG) != 0) { 1998 mvi CCSCBCTL, CCARREN|CCSCBRESET; 1999 cmp CCSCBCTL, ARRDONE|CCARREN jne .; 2000 mvi CCHCNT, SCB_UPLOAD_SIZE; 2001 mvi CCSCBCTL, CCSCBEN|CCSCBRESET; 2002 cmp CCSCBCTL, CCSCBDONE|CCSCBEN jne .; 2003 } else { 2004 mvi CCSCBCTL, CCARREN|CCSCBEN|CCSCBRESET; 2005 cmp CCSCBCTL, CCSCBDONE|ARRDONE|CCARREN|CCSCBEN jne .; 2006 } 2007dma_scb_finish: 2008 clr CCSCBCTL; 2009 test CCSCBCTL, CCARREN|CCSCBEN jnz .; 2010 ret; 2011 } else { 2012 mvi DINDEX, HADDR; 2013 mvi HSCB_ADDR call set_64byte_addr; 2014 mvi SCB_DOWNLOAD_SIZE call set_hcnt; 2015 mov DFCNTRL, DMAPARAMS; 2016 test DMAPARAMS, DIRECTION jnz dma_scb_fromhost; 2017 /* Fill it with the SCB data */ 2018copy_scb_tofifo: 2019 mvi SINDEX, SCB_BASE; 2020 add A, SCB_DOWNLOAD_SIZE, SINDEX; 2021copy_scb_tofifo_loop: 2022 call copy_to_fifo_8; 2023 cmp SINDEX, A jne copy_scb_tofifo_loop; 2024 or DFCNTRL, HDMAEN|FIFOFLUSH; 2025 jmp dma_finish; 2026dma_scb_fromhost: 2027 mvi DINDEX, SCB_BASE; 2028 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0) { 2029 /* 2030 * The PCI module will only issue a PCI 2031 * retry if the data FIFO is empty. If the 2032 * host disconnects in the middle of a 2033 * transfer, we must empty the fifo of all 2034 * available data to force the chip to 2035 * continue the transfer. This does not 2036 * happen for SCSI transfers as the SCSI module 2037 * will drain the FIFO as data is made available. 2038 * When the hang occurs, we know that at least 2039 * 8 bytes are in the FIFO because the PCI 2040 * module has an 8 byte input latch that only 2041 * dumps to the FIFO when HCNT == 0 or the 2042 * latch is full. 2043 */ 2044 mvi A, -24; 2045 /* Wait for some data to arrive. */ 2046dma_scb_hang_fifo: 2047 test DFSTATUS, FIFOEMP jnz dma_scb_hang_fifo; 2048dma_scb_hang_wait: 2049 test DFSTATUS, MREQPEND jnz dma_scb_hang_wait; 2050 test DFSTATUS, HDONE jnz dma_scb_hang_dma_done; 2051 test DFSTATUS, HDONE jnz dma_scb_hang_dma_done; 2052 test DFSTATUS, HDONE jnz dma_scb_hang_dma_done; 2053 /* 2054 * The PCI no longer intends to perform a PCI 2055 * transaction and HDONE has not come true. 2056 * We are hung. Drain the fifo. 2057 */ 2058dma_scb_hang_empty_fifo: 2059 call dfdat_in_8; 2060 add A, 8; 2061 add SINDEX, A, HCNT; 2062 /* 2063 * The result will be <= 0 (carry set) if at 2064 * least 8 bytes of data have been placed 2065 * into the fifo. 2066 */ 2067 jc dma_scb_hang_empty_fifo; 2068 jmp dma_scb_hang_fifo; 2069dma_scb_hang_dma_done: 2070 and DFCNTRL, ~HDMAEN; 2071 test DFCNTRL, HDMAEN jnz .; 2072 call dfdat_in_8; 2073 add A, 8; 2074 cmp A, 8 jne . - 2; 2075 } else { 2076 call dma_finish; 2077 /* If we were putting the SCB, we are done */ 2078 call dfdat_in_8; 2079 call dfdat_in_8; 2080 call dfdat_in_8; 2081 } 2082dfdat_in_8: 2083 mov DINDIR,DFDAT; 2084dfdat_in_7: 2085 mov DINDIR,DFDAT; 2086 mov DINDIR,DFDAT; 2087 mov DINDIR,DFDAT; 2088 mov DINDIR,DFDAT; 2089 mov DINDIR,DFDAT; 2090dfdat_in_2: 2091 mov DINDIR,DFDAT; 2092 mov DINDIR,DFDAT ret; 2093 } 2094 2095copy_to_fifo_8: 2096 mov DFDAT,SINDIR; 2097 mov DFDAT,SINDIR; 2098copy_to_fifo_6: 2099 mov DFDAT,SINDIR; 2100copy_to_fifo_5: 2101 mov DFDAT,SINDIR; 2102copy_to_fifo_4: 2103 mov DFDAT,SINDIR; 2104 mov DFDAT,SINDIR; 2105 mov DFDAT,SINDIR; 2106 mov DFDAT,SINDIR ret; 2107 2108/* 2109 * Wait for DMA from host memory to data FIFO to complete, then disable 2110 * DMA and wait for it to acknowledge that it's off. 2111 */ 2112dma_finish: 2113 test DFSTATUS,HDONE jz dma_finish; 2114 /* Turn off DMA */ 2115 and DFCNTRL, ~HDMAEN; 2116 test DFCNTRL, HDMAEN jnz .; 2117 ret; 2118 2119add_scb_to_free_list: 2120 if ((ahc->flags & AHC_PAGESCBS) != 0) { 2121BEGIN_CRITICAL 2122 mov SCB_NEXT, FREE_SCBH; 2123 mvi SCB_TAG, SCB_LIST_NULL; 2124 mov FREE_SCBH, SCBPTR ret; 2125END_CRITICAL 2126 } else { 2127 mvi SCB_TAG, SCB_LIST_NULL ret; 2128 } 2129 2130if ((ahc->flags & AHC_PAGESCBS) != 0) { 2131get_free_or_disc_scb: 2132BEGIN_CRITICAL 2133 cmp FREE_SCBH, SCB_LIST_NULL jne dequeue_free_scb; 2134 cmp DISCONNECTED_SCBH, SCB_LIST_NULL jne dequeue_disc_scb; 2135return_error: 2136 mvi NO_FREE_SCB call set_seqint; 2137 mvi SINDEX, SCB_LIST_NULL ret; 2138dequeue_disc_scb: 2139 mov SCBPTR, DISCONNECTED_SCBH; 2140 mov DISCONNECTED_SCBH, SCB_NEXT; 2141END_CRITICAL 2142 mvi DMAPARAMS, FIFORESET; 2143 mov SCB_TAG jmp dma_scb; 2144BEGIN_CRITICAL 2145dequeue_free_scb: 2146 mov SCBPTR, FREE_SCBH; 2147 mov FREE_SCBH, SCB_NEXT ret; 2148END_CRITICAL 2149 2150add_scb_to_disc_list: 2151/* 2152 * Link this SCB into the DISCONNECTED list. This list holds the 2153 * candidates for paging out an SCB if one is needed for a new command. 2154 * Modifying the disconnected list is a critical(pause dissabled) section. 2155 */ 2156BEGIN_CRITICAL 2157 mov SCB_NEXT, DISCONNECTED_SCBH; 2158 mov DISCONNECTED_SCBH, SCBPTR ret; 2159END_CRITICAL 2160} 2161set_seqint: 2162 mov INTSTAT, SINDEX; 2163 nop; 2164return: 2165 ret; 2166