aic7xxx.seq revision 70204
1/* 2 * Adaptec 274x/284x/294x device driver firmware for Linux and FreeBSD. 3 * 4 * Copyright (c) 1994-2000 Justin Gibbs. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * Alternatively, this software may be distributed under the terms of the 17 * GNU Public License ("GPL"). 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $Id: //depot/src/aic7xxx/aic7xxx.seq#15 $ 32 * 33 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.seq 70204 2000-12-20 01:11:37Z gibbs $ 34 */ 35 36#include "aic7xxx.reg" 37#include "scsi_message.h" 38 39/* 40 * A few words on the waiting SCB list: 41 * After starting the selection hardware, we check for reconnecting targets 42 * as well as for our selection to complete just in case the reselection wins 43 * bus arbitration. The problem with this is that we must keep track of the 44 * SCB that we've already pulled from the QINFIFO and started the selection 45 * on just in case the reselection wins so that we can retry the selection at 46 * a later time. This problem cannot be resolved by holding a single entry 47 * in scratch ram since a reconnecting target can request sense and this will 48 * create yet another SCB waiting for selection. The solution used here is to 49 * use byte 27 of the SCB as a psuedo-next pointer and to thread a list 50 * of SCBs that are awaiting selection. Since 0-0xfe are valid SCB indexes, 51 * SCB_LIST_NULL is 0xff which is out of range. An entry is also added to 52 * this list everytime a request sense occurs or after completing a non-tagged 53 * command for which a second SCB has been queued. The sequencer will 54 * automatically consume the entries. 55 */ 56 57poll_for_work: 58 call clear_target_state; 59 and SXFRCTL0, ~SPIOEN; 60 if ((ahc->features & AHC_ULTRA2) != 0) { 61 clr SCSIBUSL; 62 } 63poll_for_work_loop: 64 test SSTAT0, SELDO|SELDI jnz selection; 65 test SCSISEQ, ENSELO jnz poll_for_work_loop; 66 if ((ahc->features & AHC_TWIN) != 0) { 67 /* 68 * Twin channel devices cannot handle things like SELTO 69 * interrupts on the "background" channel. So, if we 70 * are selecting, keep polling the current channel util 71 * either a selection or reselection occurs. 72 */ 73 xor SBLKCTL,SELBUSB; /* Toggle to the other bus */ 74 test SSTAT0, SELDO|SELDI jnz selection; 75 xor SBLKCTL,SELBUSB; /* Toggle back */ 76 } 77 cmp WAITING_SCBH,SCB_LIST_NULL jne start_waiting; 78test_queue: 79 /* Has the driver posted any work for us? */ 80BEGIN_CRITICAL 81 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 82 test QOFF_CTLSTA, SCB_AVAIL jz poll_for_work_loop; 83 } else { 84 mov A, QINPOS; 85 cmp KERNEL_QINPOS, A je poll_for_work_loop; 86 } 87 mov ARG_1, NEXT_QUEUED_SCB; 88END_CRITICAL 89 90 /* 91 * We have at least one queued SCB now and we don't have any 92 * SCBs in the list of SCBs awaiting selection. Allocate a 93 * card SCB for the host's SCB and get to work on it. 94 */ 95 if ((ahc->flags & AHC_PAGESCBS) != 0) { 96 mov ALLZEROS call get_free_or_disc_scb; 97 } else { 98 /* In the non-paging case, the SCBID == hardware SCB index */ 99 mov SCBPTR, ARG_1; 100 } 101dma_queued_scb: 102 /* 103 * DMA the SCB from host ram into the current SCB location. 104 */ 105 mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET; 106 mov ARG_1 call dma_scb; 107 /* 108 * Check one last time to see if this SCB was canceled 109 * before we completed the DMA operation. If it was, 110 * the QINFIFO next pointer will not match our saved 111 * value. 112 */ 113 mov A, ARG_1; 114BEGIN_CRITICAL 115 cmp NEXT_QUEUED_SCB, A jne abort_qinscb; 116 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 117 cmp SCB_TAG, A je . + 2; 118 mvi SCB_MISMATCH call set_seqint; 119 } 120 mov NEXT_QUEUED_SCB, SCB_NEXT; 121 mov SCB_NEXT,WAITING_SCBH; 122 mov WAITING_SCBH, SCBPTR; 123 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 124 mov NONE, SNSCB_QOFF; 125 } else { 126 inc QINPOS; 127 } 128END_CRITICAL 129start_waiting: 130 /* 131 * Start the first entry on the waiting SCB list. 132 */ 133 mov SCBPTR, WAITING_SCBH; 134 call start_selection; 135 jmp poll_for_work_loop; 136 137abort_qinscb: 138 mvi ABORT_QINSCB call set_seqint; 139 call add_scb_to_free_list; 140 jmp poll_for_work_loop; 141 142start_selection: 143 /* 144 * If bus reset interrupts have been disabled (from a previous 145 * reset), re-enable them now. Resets are only of interest 146 * when we have outstanding transactions, so we can safely 147 * defer re-enabling the interrupt until, as an initiator, 148 * we start sending out transactions again. 149 */ 150 test SIMODE1, ENSCSIRST jnz . + 3; 151 mvi CLRSINT1, CLRSCSIRSTI; 152 or SIMODE1, ENSCSIRST; 153 if ((ahc->features & AHC_TWIN) != 0) { 154 and SINDEX,~SELBUSB,SBLKCTL;/* Clear channel select bit */ 155 test SCB_SCSIID, TWIN_CHNLB jz . + 2; 156 or SINDEX, SELBUSB; 157 mov SBLKCTL,SINDEX; /* select channel */ 158 } 159initialize_scsiid: 160 if ((ahc->features & AHC_ULTRA2) != 0) { 161 mov SCSIID_ULTRA2, SCB_SCSIID; 162 } else if ((ahc->features & AHC_TWIN) != 0) { 163 and SCSIID, TWIN_TID|OID, SCB_SCSIID; 164 } else { 165 mov SCSIID, SCB_SCSIID; 166 } 167 if ((ahc->flags & AHC_TARGETROLE) != 0) { 168 mov SINDEX, SCSISEQ_TEMPLATE; 169 test SCB_CONTROL, TARGET_SCB jz . + 2; 170 or SINDEX, TEMODE; 171 mov SCSISEQ, SINDEX ret; 172 } else { 173 mov SCSISEQ, SCSISEQ_TEMPLATE ret; 174 } 175 176/* 177 * Initialize transfer settings and clear the SCSI channel. 178 * SINDEX should contain any additional bit's the client wants 179 * set in SXFRCTL0. We also assume that the current SCB is 180 * a valid SCB for the target we wish to talk to. 181 */ 182initialize_channel: 183 or SXFRCTL0, SPIOEN|CLRSTCNT|CLRCHN; 184set_transfer_settings: 185 if ((ahc->features & AHC_ULTRA) != 0) { 186 test SCB_CONTROL, ULTRAENB jz . + 2; 187 or SXFRCTL0, FAST20; 188 } 189 /* 190 * Initialize SCSIRATE with the appropriate value for this target. 191 */ 192 if ((ahc->features & AHC_ULTRA2) != 0) { 193 bmov SCSIRATE, SCB_SCSIRATE, 2 ret; 194 } else { 195 mov SCSIRATE, SCB_SCSIRATE ret; 196 } 197 198selection: 199 /* 200 * We aren't expecting a bus free, so interrupt 201 * the kernel driver if it happens. 202 */ 203 mvi CLRSINT1,CLRBUSFREE; 204 or SIMODE1, ENBUSFREE; 205 206 /* 207 * Guard against a bus free after (re)selection 208 * but prior to enabling the busfree interrupt. SELDI 209 * and SELDO will be cleared in that case. 210 */ 211 test SSTAT0,SELDO jnz select_out; 212 test SSTAT0, SELDI jnz . + 3; 213 and SIMODE1, ~ENBUSFREE; 214 jmp poll_for_work; 215 mvi CLRSINT0, CLRSELDI; 216select_in: 217 if ((ahc->flags & AHC_TARGETROLE) != 0) { 218 if ((ahc->flags & AHC_INITIATORROLE) != 0) { 219 test SSTAT0, TARGET jz initiator_reselect; 220 } 221 222 /* 223 * We've just been selected. Assert BSY and 224 * setup the phase for receiving messages 225 * from the target. 226 * 227 * If bus reset interrupts have been disabled (from a 228 * previous reset), re-enable them now. Resets are only 229 * of interest when we have outstanding transactions, so 230 * we can safely defer re-enabling the interrupt until, 231 * as a target, we start receiving transactions again. 232 */ 233 test SIMODE1, ENSCSIRST jnz . + 3; 234 mvi CLRSINT1, CLRSCSIRSTI; 235 or SIMODE1, ENSCSIRST; 236 mvi SCSISIGO, P_MESGOUT|BSYO; 237 238 /* 239 * Setup the DMA for sending the identify and 240 * command information. 241 */ 242 or SEQ_FLAGS, CMDPHASE_PENDING; 243 244 mov A, TQINPOS; 245 if ((ahc->features & AHC_CMD_CHAN) != 0) { 246 mvi DINDEX, CCHADDR; 247 mvi SHARED_DATA_ADDR call set_32byte_addr; 248 mvi CCSCBCTL, CCSCBRESET; 249 } else { 250 mvi DINDEX, HADDR; 251 mvi SHARED_DATA_ADDR call set_32byte_addr; 252 mvi DFCNTRL, FIFORESET; 253 } 254 255 /* Initiator that selected us */ 256 and SAVED_SCSIID, SELID_MASK, SELID; 257 /* The Target ID we were selected at */ 258 if ((ahc->features & AHC_MULTI_TID) != 0) { 259 and A, OID, TARGIDIN; 260 } else if ((ahc->features & AHC_ULTRA2) != 0) { 261 and A, OID, SCSIID_ULTRA2; 262 } else { 263 and A, OID, SCSIID; 264 } 265 or SAVED_SCSIID, A; 266 if ((ahc->features & AHC_TWIN) != 0) { 267 test SBLKCTL, SELBUSB jz . + 2; 268 or SAVED_SCSIID, TWIN_CHNLB; 269 } 270 if ((ahc->features & AHC_CMD_CHAN) != 0) { 271 mov CCSCBRAM, SAVED_SCSIID; 272 } else { 273 mov DFDAT, SAVED_SCSIID; 274 } 275 276 /* 277 * If ATN isn't asserted, the target isn't interested 278 * in talking to us. Go directly to bus free. 279 * XXX SCSI-1 may require us to assume lun 0 if 280 * ATN is false. 281 */ 282 test SCSISIGI, ATNI jz target_busfree; 283 284 /* 285 * Watch ATN closely now as we pull in messages from the 286 * initiator. We follow the guidlines from section 6.5 287 * of the SCSI-2 spec for what messages are allowed when. 288 */ 289 call target_inb; 290 291 /* 292 * Our first message must be one of IDENTIFY, ABORT, or 293 * BUS_DEVICE_RESET. 294 */ 295 test DINDEX, MSG_IDENTIFYFLAG jz host_target_message_loop; 296 /* Store for host */ 297 if ((ahc->features & AHC_CMD_CHAN) != 0) { 298 mov CCSCBRAM, DINDEX; 299 } else { 300 mov DFDAT, DINDEX; 301 } 302 303 /* Remember for disconnection decision */ 304 test DINDEX, MSG_IDENTIFY_DISCFLAG jnz . + 2; 305 /* XXX Honor per target settings too */ 306 or SEQ_FLAGS, NO_DISCONNECT; 307 308 test SCSISIGI, ATNI jz ident_messages_done; 309 call target_inb; 310 /* 311 * If this is a tagged request, the tagged message must 312 * immediately follow the identify. We test for a valid 313 * tag message by seeing if it is >= MSG_SIMPLE_Q_TAG and 314 * < MSG_IGN_WIDE_RESIDUE. 315 */ 316 add A, -MSG_SIMPLE_Q_TAG, DINDEX; 317 jnc ident_messages_done; 318 add A, -MSG_IGN_WIDE_RESIDUE, DINDEX; 319 jc ident_messages_done; 320 /* Store for host */ 321 if ((ahc->features & AHC_CMD_CHAN) != 0) { 322 mov CCSCBRAM, DINDEX; 323 } else { 324 mov DFDAT, DINDEX; 325 } 326 327 /* 328 * If the initiator doesn't feel like providing a tag number, 329 * we've got a failed selection and must transition to bus 330 * free. 331 */ 332 test SCSISIGI, ATNI jz target_busfree; 333 334 /* 335 * Store the tag for the host. 336 */ 337 call target_inb; 338 if ((ahc->features & AHC_CMD_CHAN) != 0) { 339 mov CCSCBRAM, DINDEX; 340 } else { 341 mov DFDAT, DINDEX; 342 } 343 mov INITIATOR_TAG, DINDEX; 344 or SEQ_FLAGS, TARGET_CMD_IS_TAGGED; 345 test SCSISIGI, ATNI jz . + 2; 346 /* Initiator still wants to give us messages */ 347 call target_inb; 348 jmp ident_messages_done; 349 350 /* 351 * Pushed message loop to allow the kernel to 352 * run it's own target mode message state engine. 353 */ 354host_target_message_loop: 355 mvi HOST_MSG_LOOP call set_seqint; 356 cmp RETURN_1, EXIT_MSG_LOOP je target_ITloop; 357 test SSTAT0, SPIORDY jz .; 358 jmp host_target_message_loop; 359 360ident_messages_done: 361 /* If ring buffer is full, return busy or queue full */ 362 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 363 and A, HOST_TQINPOS, HS_MAILBOX; 364 } else { 365 mov A, KERNEL_TQINPOS; 366 } 367 cmp TQINPOS, A jne tqinfifo_has_space; 368 mvi P_STATUS|BSYO call change_phase; 369 test SEQ_FLAGS, TARGET_CMD_IS_TAGGED jz . + 3; 370 mvi STATUS_QUEUE_FULL call target_outb; 371 jmp target_busfree_wait; 372 mvi STATUS_BUSY call target_outb; 373 jmp target_busfree_wait; 374tqinfifo_has_space: 375 /* Terminate the ident list */ 376 if ((ahc->features & AHC_CMD_CHAN) != 0) { 377 mvi CCSCBRAM, SCB_LIST_NULL; 378 } else { 379 mvi DFDAT, SCB_LIST_NULL; 380 } 381 or SEQ_FLAGS, TARG_CMD_PENDING|IDENTIFY_SEEN; 382 test SCSISIGI, ATNI jnz target_mesgout_pending; 383 jmp target_ITloop; 384 385/* 386 * We carefully toggle SPIOEN to allow us to return the 387 * message byte we receive so it can be checked prior to 388 * driving REQ on the bus for the next byte. 389 */ 390target_inb: 391 /* 392 * Drive REQ on the bus by enabling SCSI PIO. 393 */ 394 or SXFRCTL0, SPIOEN; 395 /* Wait for the byte */ 396 test SSTAT0, SPIORDY jz .; 397 /* Prevent our read from triggering another REQ */ 398 and SXFRCTL0, ~SPIOEN; 399 /* Save latched contents */ 400 mov DINDEX, SCSIDATL ret; 401 } 402 403if ((ahc->flags & AHC_INITIATORROLE) != 0) { 404/* 405 * Reselection has been initiated by a target. Make a note that we've been 406 * reselected, but haven't seen an IDENTIFY message from the target yet. 407 */ 408initiator_reselect: 409 /* XXX test for and handle ONE BIT condition */ 410 and SAVED_SCSIID, SELID_MASK, SELID; 411 if ((ahc->features & AHC_ULTRA2) != 0) { 412 and A, OID, SCSIID_ULTRA2; 413 } else { 414 and A, OID, SCSIID; 415 } 416 or SAVED_SCSIID, A; 417 if ((ahc->features & AHC_TWIN) != 0) { 418 test SBLKCTL, SELBUSB jz . + 2; 419 or SAVED_SCSIID, TWIN_CHNLB; 420 } 421 or SXFRCTL0, SPIOEN|CLRSTCNT|CLRCHN; 422 jmp ITloop; 423} 424 425/* 426 * After the selection, remove this SCB from the "waiting SCB" 427 * list. This is achieved by simply moving our "next" pointer into 428 * WAITING_SCBH. Our next pointer will be set to null the next time this 429 * SCB is used, so don't bother with it now. 430 */ 431select_out: 432 /* Turn off the selection hardware */ 433 and SCSISEQ, TEMODE|ENSELI|ENRSELI|ENAUTOATNP, SCSISEQ; 434 mvi CLRSINT0, CLRSELDO; 435 mov SCBPTR, WAITING_SCBH; 436 mov WAITING_SCBH,SCB_NEXT; 437 mov SAVED_SCSIID, SCB_SCSIID; 438 mov SAVED_LUN, SCB_LUN; 439 call initialize_channel; 440 if ((ahc->flags & AHC_TARGETROLE) != 0) { 441 test SSTAT0, TARGET jz initiator_select; 442 443 /* 444 * We've just re-selected an initiator. 445 * Assert BSY and setup the phase for 446 * sending our identify messages. 447 */ 448 mvi P_MESGIN|BSYO call change_phase; 449 450 /* 451 * Start out with a simple identify message. 452 */ 453 or SCB_LUN, MSG_IDENTIFYFLAG call target_outb; 454 455 /* 456 * If we are the result of a tagged command, send 457 * a simple Q tag and the tag id. 458 */ 459 test SCB_CONTROL, TAG_ENB jz . + 3; 460 mvi MSG_SIMPLE_Q_TAG call target_outb; 461 mov SCB_TARGET_INFO[SCB_INITIATOR_TAG] call target_outb; 462target_synccmd: 463 /* 464 * Now determine what phases the host wants us 465 * to go through. 466 */ 467 mov SEQ_FLAGS, SCB_TARGET_INFO[SCB_TARGET_PHASES]; 468 469target_ITloop: 470 /* 471 * Start honoring ATN signals now that 472 * we properly identified ourselves. 473 */ 474 test SCSISIGI, ATNI jnz target_mesgout; 475 test SEQ_FLAGS, CMDPHASE_PENDING jnz target_cmdphase; 476 test SEQ_FLAGS, DPHASE_PENDING jnz target_dphase; 477 test SEQ_FLAGS, SPHASE_PENDING jnz target_sphase; 478 479 /* 480 * No more work to do. Either disconnect or not depending 481 * on the state of NO_DISCONNECT. 482 */ 483 test SEQ_FLAGS, NO_DISCONNECT jz target_disconnect; 484 if ((ahc->flags & AHC_PAGESCBS) != 0) { 485 mov ALLZEROS call get_free_or_disc_scb; 486 } 487 mov RETURN_1, ALLZEROS; 488 call complete_target_cmd; 489 cmp RETURN_1, CONT_MSG_LOOP jne .; 490 mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET; 491 mov SCB_TAG call dma_scb; 492 jmp target_synccmd; 493 494target_mesgout: 495 mvi SCSISIGO, P_MESGOUT|BSYO; 496target_mesgout_continue: 497 call target_inb; 498target_mesgout_pending: 499 /* Local Processing goes here... */ 500 jmp host_target_message_loop; 501 502target_disconnect: 503 mvi P_MESGIN|BSYO call change_phase; 504 test SEQ_FLAGS, DPHASE jz . + 2; 505 mvi MSG_SAVEDATAPOINTER call target_outb; 506 mvi MSG_DISCONNECT call target_outb; 507 508target_busfree_wait: 509 /* Wait for preceeding I/O session to complete. */ 510 test SCSISIGI, ACKI jnz .; 511target_busfree: 512 and SIMODE1, ~ENBUSFREE; 513 if ((ahc->features & AHC_ULTRA2) != 0) { 514 clr SCSIBUSL; 515 } 516 clr SCSISIGO; 517 mvi LASTPHASE, P_BUSFREE; 518 call complete_target_cmd; 519 jmp poll_for_work; 520 521target_cmdphase: 522 mvi P_COMMAND|BSYO call change_phase; 523 call target_inb; 524 mov A, DINDEX; 525 /* Store for host */ 526 if ((ahc->features & AHC_CMD_CHAN) != 0) { 527 mov CCSCBRAM, A; 528 } else { 529 mov DFDAT, A; 530 } 531 532 /* 533 * Determine the number of bytes to read 534 * based on the command group code via table lookup. 535 * We reuse the first 8 bytes of the TARG_SCSIRATE 536 * BIOS array for this table. Count is one less than 537 * the total for the command since we've already fetched 538 * the first byte. 539 */ 540 shr A, CMD_GROUP_CODE_SHIFT; 541 add SINDEX, CMDSIZE_TABLE, A; 542 mov A, SINDIR; 543 544 test A, 0xFF jz command_phase_done; 545command_loop: 546 or SXFRCTL0, SPIOEN; 547 test SSTAT0, SPIORDY jz .; 548 cmp A, 1 jne . + 2; 549 and SXFRCTL0, ~SPIOEN; /* Last Byte */ 550 if ((ahc->features & AHC_CMD_CHAN) != 0) { 551 mov CCSCBRAM, SCSIDATL; 552 } else { 553 mov DFDAT, SCSIDATL; 554 } 555 dec A; 556 test A, 0xFF jnz command_loop; 557 558command_phase_done: 559 and SEQ_FLAGS, ~CMDPHASE_PENDING; 560 jmp target_ITloop; 561 562target_dphase: 563 /* 564 * Data phases on the bus are from the 565 * perspective of the initiator. The dma 566 * code looks at LASTPHASE to determine the 567 * data direction of the DMA. Toggle it for 568 * target transfers. 569 */ 570 xor LASTPHASE, IOI, SCB_TARGET_INFO[SCB_TARGET_DATA_DIR]; 571 or SCB_TARGET_INFO[SCB_TARGET_DATA_DIR], BSYO 572 call change_phase; 573 jmp p_data; 574 575target_sphase: 576 mvi P_STATUS|BSYO call change_phase; 577 mvi LASTPHASE, P_STATUS; 578 mov SCB_TARGET_INFO[SCB_TARGET_STATUS] call target_outb; 579 /* XXX Watch for ATN or parity errors??? */ 580 mvi SCSISIGO, P_MESGIN|BSYO; 581 /* MSG_CMDCMPLT is 0, but we can't do an immediate of 0 */ 582 mov ALLZEROS call target_outb; 583 jmp target_busfree_wait; 584 585complete_target_cmd: 586 test SEQ_FLAGS, TARG_CMD_PENDING jnz . + 2; 587 mov SCB_TAG jmp complete_post; 588 if ((ahc->features & AHC_CMD_CHAN) != 0) { 589 /* Set the valid byte */ 590 mvi CCSCBADDR, 24; 591 mov CCSCBRAM, ALLONES; 592 mvi CCHCNT, 28; 593 or CCSCBCTL, CCSCBEN|CCSCBRESET; 594 test CCSCBCTL, CCSCBDONE jz .; 595 clr CCSCBCTL; 596 } else { 597 /* Set the valid byte */ 598 or DFCNTRL, FIFORESET; 599 mvi DFWADDR, 3; /* Third 64bit word or byte 24 */ 600 mov DFDAT, ALLONES; 601 mvi 28 call set_hcnt; 602 or DFCNTRL, HDMAEN|FIFOFLUSH; 603 call dma_finish; 604 } 605 inc TQINPOS; 606 mvi INTSTAT,CMDCMPLT ret; 607 } 608 609if ((ahc->flags & AHC_INITIATORROLE) != 0) { 610initiator_select: 611 /* 612 * As soon as we get a successful selection, the target 613 * should go into the message out phase since we have ATN 614 * asserted. 615 */ 616 mvi MSG_OUT, MSG_IDENTIFYFLAG; 617 or SEQ_FLAGS, IDENTIFY_SEEN; 618 619 /* 620 * Main loop for information transfer phases. Wait for the 621 * target to assert REQ before checking MSG, C/D and I/O for 622 * the bus phase. 623 */ 624mesgin_phasemis: 625ITloop: 626 call phase_lock; 627 628 mov A, LASTPHASE; 629 630 test A, ~P_DATAIN jz p_data; 631 cmp A,P_COMMAND je p_command; 632 cmp A,P_MESGOUT je p_mesgout; 633 cmp A,P_STATUS je p_status; 634 cmp A,P_MESGIN je p_mesgin; 635 636 mvi BAD_PHASE call set_seqint; 637 jmp ITloop; /* Try reading the bus again. */ 638 639await_busfree: 640 and SIMODE1, ~ENBUSFREE; 641 mov NONE, SCSIDATL; /* Ack the last byte */ 642 if ((ahc->features & AHC_ULTRA2) != 0) { 643 clr SCSIBUSL; /* Prevent bit leakage durint SELTO */ 644 } 645 and SXFRCTL0, ~SPIOEN; 646 test SSTAT1,REQINIT|BUSFREE jz .; 647 test SSTAT1, BUSFREE jnz poll_for_work; 648 mvi MISSED_BUSFREE call set_seqint; 649} 650 651clear_target_state: 652 /* 653 * We assume that the kernel driver may reset us 654 * at any time, even in the middle of a DMA, so 655 * clear DFCNTRL too. 656 */ 657 clr DFCNTRL; 658 or SXFRCTL0, CLRSTCNT|CLRCHN; 659 660 /* 661 * We don't know the target we will connect to, 662 * so default to narrow transfers to avoid 663 * parity problems. 664 */ 665 if ((ahc->features & AHC_ULTRA2) != 0) { 666 bmov SCSIRATE, ALLZEROS, 2; 667 } else { 668 clr SCSIRATE; 669 if ((ahc->features & AHC_ULTRA) != 0) { 670 and SXFRCTL0, ~(FAST20); 671 } 672 } 673 mvi LASTPHASE, P_BUSFREE; 674 /* clear target specific flags */ 675 clr SEQ_FLAGS ret; 676 677sg_advance: 678 clr A; /* add sizeof(struct scatter) */ 679 add SCB_RESIDUAL_SGPTR[0],SG_SIZEOF; 680 adc SCB_RESIDUAL_SGPTR[1],A; 681 adc SCB_RESIDUAL_SGPTR[2],A; 682 adc SCB_RESIDUAL_SGPTR[3],A ret; 683 684idle_loop: 685 if ((ahc->features & AHC_CMD_CHAN) != 0) { 686 /* Did we just finish fetching segs? */ 687 cmp CCSGCTL, CCSGEN|CCSGDONE je idle_sgfetch_complete; 688 689 /* Are we actively fetching segments? */ 690 test CCSGCTL, CCSGEN jnz return; 691 692 /* 693 * Do we need any more segments? 694 */ 695 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jnz return; 696 697 /* 698 * Do we have any prefetch left??? 699 */ 700 cmp CCSGADDR, SG_PREFETCH_CNT jne idle_sg_avail; 701 702 /* 703 * Need to fetch segments, but we can only do that 704 * if the command channel is completely idle. Make 705 * sure we don't have an SCB prefetch going on. 706 */ 707 test CCSCBCTL, CCSCBEN jnz return; 708 709 /* 710 * We fetch a "cacheline aligned" and sized amount of data 711 * so we don't end up referencing a non-existant page. 712 * Cacheline aligned is in quotes because the kernel will 713 * set the prefetch amount to a reasonable level if the 714 * cacheline size is unknown. 715 */ 716 mvi CCHCNT, SG_PREFETCH_CNT; 717 and CCHADDR[0], SG_PREFETCH_ALIGN_MASK, SCB_RESIDUAL_SGPTR; 718 bmov CCHADDR[1], SCB_RESIDUAL_SGPTR[1], 3; 719 mvi CCSGCTL, CCSGEN|CCSGRESET ret; 720idle_sgfetch_complete: 721 clr CCSGCTL; 722 test CCSGCTL, CCSGEN jnz .; 723 and CCSGADDR, SG_PREFETCH_ADDR_MASK, SCB_RESIDUAL_SGPTR; 724idle_sg_avail: 725 if ((ahc->features & AHC_ULTRA2) != 0) { 726 /* Does the hardware have space for another SG entry? */ 727 test DFSTATUS, PRELOAD_AVAIL jz return; 728 bmov HADDR, CCSGRAM, 4; 729 bmov SINDEX, CCSGRAM, 1; 730 test SINDEX, 0x1 jz . + 2; 731 xor DATA_COUNT_ODD, 0x1; 732 bmov HCNT[0], SINDEX, 1; 733 bmov HCNT[1], CCSGRAM, 2; 734 bmov SCB_RESIDUAL_DATACNT[3], CCSGRAM, 1; 735 call sg_advance; 736 mov SINDEX, SCB_RESIDUAL_SGPTR[0]; 737 test DATA_COUNT_ODD, 0x1 jz . + 2; 738 or SINDEX, ODD_SEG; 739 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 2; 740 or SINDEX, LAST_SEG; 741 mov SG_CACHE_PRE, SINDEX; 742 /* Load the segment by writing DFCNTRL again */ 743 mov DFCNTRL, DMAPARAMS; 744 } 745 ret; 746 } 747 748if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0) { 749/* 750 * Calculate the trailing portion of this S/G segment that cannot 751 * be transferred using memory write and invalidate PCI transactions. 752 * XXX Can we optimize this for PCI writes only??? 753 */ 754calc_mwi_residual: 755 /* 756 * If the ending address is on a cacheline boundary, 757 * there is no need for an extra segment. 758 */ 759 mov A, HCNT[0]; 760 add A, A, HADDR[0]; 761 and A, CACHESIZE_MASK; 762 test A, 0xFF jz return; 763 764 /* 765 * If the transfer is less than a cachline, 766 * there is no need for an extra segment. 767 */ 768 test HCNT[1], 0xFF jnz calc_mwi_residual_final; 769 test HCNT[2], 0xFF jnz calc_mwi_residual_final; 770 add NONE, INVERTED_CACHESIZE_MASK, HCNT[0]; 771 jnc return; 772 773calc_mwi_residual_final: 774 mov MWI_RESIDUAL, A; 775 not A; 776 inc A; 777 add HCNT[0], A; 778 adc HCNT[1], -1; 779 adc HCNT[2], -1 ret; 780} 781 782/* 783 * If we re-enter the data phase after going through another phase, the 784 * STCNT may have been cleared, so restore it from the residual field. 785 */ 786data_phase_reinit: 787 if ((ahc->features & AHC_ULTRA2) != 0) { 788 /* 789 * The preload circuitry requires us to 790 * reload the address too, so pull it from 791 * the shaddow address. 792 */ 793 bmov HADDR, SHADDR, 4; 794 bmov HCNT, SCB_RESIDUAL_DATACNT, 3; 795 } else if ((ahc->features & AHC_CMD_CHAN) != 0) { 796 bmov STCNT, SCB_RESIDUAL_DATACNT, 3; 797 } else { 798 mvi DINDEX, STCNT; 799 mvi SCB_RESIDUAL_DATACNT call bcopy_3; 800 } 801 and DATA_COUNT_ODD, 0x1, SCB_RESIDUAL_DATACNT[0]; 802 jmp data_phase_loop; 803 804p_data: 805 if ((ahc->features & AHC_ULTRA2) != 0) { 806 mvi DMAPARAMS, PRELOADEN|SCSIEN|HDMAEN; 807 } else { 808 mvi DMAPARAMS, WIDEODD|SCSIEN|SDMAEN|HDMAEN|FIFORESET; 809 } 810 test LASTPHASE, IOI jnz . + 2; 811 or DMAPARAMS, DIRECTION; 812 call assert; /* 813 * Ensure entering a data 814 * phase is okay - seen identify, etc. 815 */ 816 if ((ahc->features & AHC_CMD_CHAN) != 0) { 817 /* We don't have any valid S/G elements */ 818 mvi CCSGADDR, SG_PREFETCH_CNT; 819 } 820 test SEQ_FLAGS, DPHASE jnz data_phase_reinit; 821 822 /* We have seen a data phase */ 823 or SEQ_FLAGS, DPHASE; 824 825 /* 826 * Initialize the DMA address and counter from the SCB. 827 * Also set SCB_RESIDUAL_SGPTR, including the LAST_SEG 828 * flag in the highest byte of the data count. We cannot 829 * modify the saved values in the SCB until we see a save 830 * data pointers message. 831 */ 832 if ((ahc->features & AHC_CMD_CHAN) != 0) { 833 bmov HADDR, SCB_DATAPTR, 7; 834 bmov SCB_RESIDUAL_DATACNT[3], SCB_DATACNT[3], 5; 835 } else { 836 mvi DINDEX, HADDR; 837 mvi SCB_DATAPTR call bcopy_7; 838 mvi DINDEX, SCB_RESIDUAL_DATACNT + 3; 839 mvi SCB_DATACNT + 3 call bcopy_5; 840 } 841 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0) { 842 call calc_mwi_residual; 843 } 844 and SCB_RESIDUAL_SGPTR[0], ~SG_FULL_RESID; 845 and DATA_COUNT_ODD, 0x1, HCNT[0]; 846 847 if ((ahc->features & AHC_ULTRA2) == 0) { 848 if ((ahc->features & AHC_CMD_CHAN) != 0) { 849 bmov STCNT, HCNT, 3; 850 } else { 851 call set_stcnt_from_hcnt; 852 } 853 } 854 855data_phase_loop: 856 /* Guard against overruns */ 857 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz data_phase_inbounds; 858 859 /* 860 * Turn on `Bit Bucket' mode, wait until the target takes 861 * us to another phase, and then notify the host. 862 */ 863 and DMAPARAMS, DIRECTION; 864 mov DFCNTRL, DMAPARAMS; 865 or SXFRCTL1,BITBUCKET; 866 test SSTAT1,PHASEMIS jz .; 867 and SXFRCTL1, ~BITBUCKET; 868 mvi DATA_OVERRUN call set_seqint; 869 jmp ITloop; 870 871data_phase_inbounds: 872 if ((ahc->features & AHC_ULTRA2) != 0) { 873 mov SINDEX, SCB_RESIDUAL_SGPTR[0]; 874 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 2; 875 or SINDEX, LAST_SEG; 876 test DATA_COUNT_ODD, 0x1 jz . + 2; 877 or SINDEX, ODD_SEG; 878 mov SG_CACHE_PRE, SINDEX; 879 mov DFCNTRL, DMAPARAMS; 880ultra2_dma_loop: 881 call idle_loop; 882 /* 883 * The transfer is complete if either the last segment 884 * completes or the target changes phase. 885 */ 886 test SG_CACHE_SHADOW, LAST_SEG_DONE jnz ultra2_dmafinish; 887 if ((ahc->flags & AHC_TARGETROLE) != 0) { 888 /* 889 * As a target, we control the phases, 890 * so ignore PHASEMIS. 891 */ 892 test SSTAT0, TARGET jnz ultra2_dma_loop; 893 } 894 if ((ahc->flags & AHC_INITIATORROLE) != 0) { 895 test SSTAT1,PHASEMIS jz ultra2_dma_loop; 896 } 897 898ultra2_dmafinish: 899 test DFCNTRL, DIRECTION jnz ultra2_dmafifoempty; 900 and DFCNTRL, ~SCSIEN; 901 test DFCNTRL, SCSIEN jnz .; 902 if ((ahc->bugs & AHC_AUTOFLUSH_BUG) != 0) { 903 test DFSTATUS, FIFOEMP jnz ultra2_dmafifoempty; 904 } 905ultra2_dmafifoflush: 906 if ((ahc->bugs & AHC_AUTOFLUSH_BUG) != 0) { 907 /* 908 * On Rev A of the aic7890, the autoflush 909 * features doesn't function correctly. 910 * Perform an explicit manual flush. During 911 * a manual flush, the FIFOEMP bit becomes 912 * true every time the PCI FIFO empties 913 * regardless of the state of the SCSI FIFO. 914 * It can take up to 4 clock cycles for the 915 * SCSI FIFO to get data into the PCI FIFO 916 * and for FIFOEMP to de-assert. Here we 917 * guard against this condition by making 918 * sure the FIFOEMP bit stays on for 5 full 919 * clock cycles. 920 */ 921 or DFCNTRL, FIFOFLUSH; 922 test DFSTATUS, FIFOEMP jz ultra2_dmafifoflush; 923 test DFSTATUS, FIFOEMP jz ultra2_dmafifoflush; 924 test DFSTATUS, FIFOEMP jz ultra2_dmafifoflush; 925 test DFSTATUS, FIFOEMP jz ultra2_dmafifoflush; 926 } 927 test DFSTATUS, FIFOEMP jz ultra2_dmafifoflush; 928ultra2_dmafifoempty: 929 /* Don't clobber an inprogress host data transfer */ 930 test DFSTATUS, MREQPEND jnz ultra2_dmafifoempty; 931ultra2_dmahalt: 932 and DFCNTRL, ~(SCSIEN|HDMAEN); 933 test DFCNTRL, HDMAEN jnz .; 934 935 /* 936 * If, by chance, we stopped before being able 937 * to fetch additional segments for this transfer, 938 * yet the last S/G was completely exhausted, 939 * call our idle loop until it is able to load 940 * another segment. This will allow us to immediately 941 * pickup on the next segment on the next data phase. 942 * 943 * If we happened to stop on the last segment, then 944 * our residual information is still correct from 945 * the idle loop and there is no need to perform 946 * any fixups. Just jump to data_phase_finish. 947 */ 948ultra2_ensure_sg: 949 test SG_CACHE_SHADOW, LAST_SEG jz ultra2_shvalid; 950 /* Record if we've consumed all S/G entries */ 951 test SG_CACHE_SHADOW, LAST_SEG_DONE jz data_phase_finish; 952 or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL; 953 jmp data_phase_finish; 954 955ultra2_shvalid: 956 test SSTAT2, SHVALID jnz sgptr_fixup; 957 call idle_loop; 958 jmp ultra2_ensure_sg; 959 960sgptr_fixup: 961 /* 962 * Fixup the residual next S/G pointer. The S/G preload 963 * feature of the chip allows us to load two elements 964 * in addition to the currently active element. We 965 * store the bottom byte of the next S/G pointer in 966 * the SG_CACEPTR register so we can restore the 967 * correct value when the DMA completes. If the next 968 * sg ptr value has advanced to the point where higher 969 * bytes in the address have been affected, fix them 970 * too. 971 */ 972 test SG_CACHE_SHADOW, 0x80 jz sgptr_fixup_done; 973 test SCB_RESIDUAL_SGPTR[0], 0x80 jnz sgptr_fixup_done; 974 add SCB_RESIDUAL_SGPTR[1], -1; 975 adc SCB_RESIDUAL_SGPTR[2], -1; 976 adc SCB_RESIDUAL_SGPTR[3], -1; 977sgptr_fixup_done: 978 and SCB_RESIDUAL_SGPTR[0], SG_ADDR_MASK, SG_CACHE_SHADOW; 979 clr DATA_COUNT_ODD; 980 test SG_CACHE_SHADOW, ODD_SEG jz . + 2; 981 or DATA_COUNT_ODD, 0x1; 982 clr SCB_RESIDUAL_DATACNT[3]; /* We are not the last seg */ 983 } else { 984 /* If we are the last SG block, tell the hardware. */ 985 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 986 && ahc->pci_cachesize != 0) { 987 test MWI_RESIDUAL, 0xFF jnz dma_mid_sg; 988 } 989 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz dma_mid_sg; 990 if ((ahc->flags & AHC_TARGETROLE) != 0) { 991 test SSTAT0, TARGET jz dma_last_sg; 992 if ((ahc->flags & AHC_TMODE_WIDEODD_BUG) != 0) { 993 test DMAPARAMS, DIRECTION jz dma_mid_sg; 994 } 995 } 996dma_last_sg: 997 and DMAPARAMS, ~WIDEODD; 998dma_mid_sg: 999 /* Start DMA data transfer. */ 1000 mov DFCNTRL, DMAPARAMS; 1001dma_loop: 1002 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1003 call idle_loop; 1004 } 1005 test SSTAT0,DMADONE jnz dma_dmadone; 1006 test SSTAT1,PHASEMIS jz dma_loop; /* ie. underrun */ 1007dma_phasemis: 1008 /* 1009 * We will be "done" DMAing when the transfer count goes to 1010 * zero, or the target changes the phase (in light of this, 1011 * it makes sense that the DMA circuitry doesn't ACK when 1012 * PHASEMIS is active). If we are doing a SCSI->Host transfer, 1013 * the data FIFO should be flushed auto-magically on STCNT=0 1014 * or a phase change, so just wait for FIFO empty status. 1015 */ 1016dma_checkfifo: 1017 test DFCNTRL,DIRECTION jnz dma_fifoempty; 1018dma_fifoflush: 1019 test DFSTATUS,FIFOEMP jz dma_fifoflush; 1020dma_fifoempty: 1021 /* Don't clobber an inprogress host data transfer */ 1022 test DFSTATUS, MREQPEND jnz dma_fifoempty; 1023 1024 /* 1025 * Now shut off the DMA and make sure that the DMA 1026 * hardware has actually stopped. Touching the DMA 1027 * counters, etc. while a DMA is active will result 1028 * in an ILLSADDR exception. 1029 */ 1030dma_dmadone: 1031 and DFCNTRL, ~(SCSIEN|SDMAEN|HDMAEN); 1032dma_halt: 1033 /* 1034 * Some revisions of the aic78XX have a problem where, if the 1035 * data fifo is full, but the PCI input latch is not empty, 1036 * HDMAEN cannot be cleared. The fix used here is to drain 1037 * the prefetched but unused data from the data fifo until 1038 * there is space for the input latch to drain. 1039 */ 1040 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0) { 1041 mov NONE, DFDAT; 1042 } 1043 test DFCNTRL, (SCSIEN|SDMAEN|HDMAEN) jnz dma_halt; 1044 1045 /* See if we have completed this last segment */ 1046 test STCNT[0], 0xff jnz data_phase_finish; 1047 test STCNT[1], 0xff jnz data_phase_finish; 1048 test STCNT[2], 0xff jnz data_phase_finish; 1049 1050 /* 1051 * Advance the scatter-gather pointers if needed 1052 */ 1053 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 1054 && ahc->pci_cachesize != 0) { 1055 test MWI_RESIDUAL, 0xFF jz no_mwi_resid; 1056 /* 1057 * Reload HADDR from SHADDR and setup the 1058 * count to be the size of our residual. 1059 */ 1060 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1061 bmov HADDR, SHADDR, 4; 1062 mov HCNT, MWI_RESIDUAL; 1063 bmov HCNT[1], ALLZEROS, 2; 1064 } else { 1065 mvi DINDEX, HADDR; 1066 mvi SHADDR call bcopy_4; 1067 mov MWI_RESIDUAL call set_hcnt; 1068 } 1069 clr MWI_RESIDUAL; 1070 jmp sg_load_done; 1071no_mwi_resid: 1072 } 1073 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz sg_load; 1074 or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL; 1075 jmp data_phase_finish; 1076sg_load: 1077 /* 1078 * Load the next SG element's data address and length 1079 * into the DMA engine. If we don't have hardware 1080 * to perform a prefetch, we'll have to fetch the 1081 * segment from host memory first. 1082 */ 1083 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1084 /* Wait for the idle loop to complete */ 1085 test CCSGCTL, CCSGEN jz . + 3; 1086 call idle_loop; 1087 test CCSGCTL, CCSGEN jnz . - 1; 1088 bmov HADDR, CCSGRAM, 7; 1089 test CCSGRAM, SG_LAST_SEG jz . + 2; 1090 or SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG; 1091 } else { 1092 mvi DINDEX, HADDR; 1093 mvi SCB_RESIDUAL_SGPTR call bcopy_4; 1094 1095 mvi SG_SIZEOF call set_hcnt; 1096 1097 or DFCNTRL, HDMAEN|DIRECTION|FIFORESET; 1098 1099 call dma_finish; 1100 1101 mvi DINDEX, HADDR; 1102 call dfdat_in_7; 1103 mov SCB_RESIDUAL_DATACNT[3], DFDAT; 1104 } 1105 1106 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 1107 && ahc->pci_cachesize != 0) { 1108 call calc_mwi_residual; 1109 } 1110 1111 /* Point to the new next sg in memory */ 1112 call sg_advance; 1113 1114sg_load_done: 1115 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1116 bmov STCNT, HCNT, 3; 1117 } else { 1118 call set_stcnt_from_hcnt; 1119 } 1120 /* Track odd'ness */ 1121 test HCNT[0], 0x1 jz . + 2; 1122 xor DATA_COUNT_ODD, 0x1; 1123 1124 if ((ahc->flags & AHC_TARGETROLE) != 0) { 1125 test SSTAT0, TARGET jnz data_phase_loop; 1126 } 1127 } 1128data_phase_finish: 1129 /* 1130 * If the target has left us in data phase, loop through 1131 * the dma code again. In the case of ULTRA2 adapters, 1132 * we should only loop if there is a data overrun. For 1133 * all other adapters, we'll loop after each S/G element 1134 * is loaded as well as if there is an overrun. 1135 */ 1136 if ((ahc->flags & AHC_TARGETROLE) != 0) { 1137 test SSTAT0, TARGET jnz data_phase_done; 1138 } 1139 if ((ahc->flags & AHC_INITIATORROLE) != 0) { 1140 test SSTAT1, REQINIT jz .; 1141 test SSTAT1,PHASEMIS jz data_phase_loop; 1142 1143 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1144 /* Kill off any pending prefetch */ 1145 clr CCSGCTL; 1146 test CCSGCTL, CCSGEN jnz .; 1147 } 1148 } 1149 1150data_phase_done: 1151 /* 1152 * After a DMA finishes, save the SG and STCNT residuals back into 1153 * the SCB. We use STCNT instead of HCNT, since it's a reflection 1154 * of how many bytes were transferred on the SCSI (as opposed to the 1155 * host) bus. 1156 */ 1157 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1158 /* Kill off any pending prefetch */ 1159 clr CCSGCTL; 1160 test CCSGCTL, CCSGEN jnz .; 1161 } 1162 1163 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 1164 && ahc->pci_cachesize != 0) { 1165 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1166 test MWI_RESIDUAL, 0xFF jz bmov_resid; 1167 } 1168 mov A, MWI_RESIDUAL; 1169 add SCB_RESIDUAL_DATACNT[0], A, STCNT[0]; 1170 clr A; 1171 adc SCB_RESIDUAL_DATACNT[1], A, STCNT[1]; 1172 adc SCB_RESIDUAL_DATACNT[2], A, STCNT[2]; 1173 clr MWI_RESIDUAL; 1174 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1175 jmp . + 2; 1176bmov_resid: 1177 bmov SCB_RESIDUAL_DATACNT, STCNT, 3; 1178 } 1179 } else if ((ahc->features & AHC_CMD_CHAN) != 0) { 1180 bmov SCB_RESIDUAL_DATACNT, STCNT, 3; 1181 } else { 1182 mov SCB_RESIDUAL_DATACNT[0], STCNT[0]; 1183 mov SCB_RESIDUAL_DATACNT[1], STCNT[1]; 1184 mov SCB_RESIDUAL_DATACNT[2], STCNT[2]; 1185 } 1186 1187 /* 1188 * Since we've been through a data phase, the SCB_RESID* fields 1189 * are now initialized. Clear the full residual flag. 1190 */ 1191 and SCB_SGPTR[0], ~SG_FULL_RESID; 1192 1193 if ((ahc->features & AHC_ULTRA2) != 0) { 1194 /* Clear the channel in case we return to data phase later */ 1195 or SXFRCTL0, CLRSTCNT|CLRCHN; 1196 or SXFRCTL0, CLRSTCNT|CLRCHN; 1197 } 1198 1199 if ((ahc->flags & AHC_TARGETROLE) != 0) { 1200 test SEQ_FLAGS, DPHASE_PENDING jz ITloop; 1201 and SEQ_FLAGS, ~DPHASE_PENDING; 1202 /* 1203 * For data-in phases, wait for any pending acks from the 1204 * initiator before changing phase. 1205 */ 1206 test DFCNTRL, DIRECTION jz target_ITloop; 1207 test SSTAT1, REQINIT jnz .; 1208 jmp target_ITloop; 1209 } else { 1210 jmp ITloop; 1211 } 1212 1213if ((ahc->flags & AHC_INITIATORROLE) != 0) { 1214/* 1215 * Command phase. Set up the DMA registers and let 'er rip. 1216 */ 1217p_command: 1218 call assert; 1219 1220 if ((ahc->features & AHC_ULTRA2) != 0) { 1221 bmov HCNT[0], SCB_CDB_LEN, 1; 1222 bmov HCNT[1], ALLZEROS, 2; 1223 mvi SG_CACHE_PRE, LAST_SEG; 1224 } else if ((ahc->features & AHC_CMD_CHAN) != 0) { 1225 bmov STCNT[0], SCB_CDB_LEN, 1; 1226 bmov STCNT[1], ALLZEROS, 2; 1227 } else { 1228 mov STCNT[0], SCB_CDB_LEN; 1229 clr STCNT[1]; 1230 clr STCNT[2]; 1231 } 1232 add NONE, -13, SCB_CDB_LEN; 1233 mvi SCB_CDB_STORE jnc p_command_embedded; 1234p_command_from_host: 1235 if ((ahc->features & AHC_ULTRA2) != 0) { 1236 bmov HADDR[0], SCB_CDB_PTR, 4; 1237 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN|DIRECTION); 1238 } else { 1239 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1240 bmov HADDR[0], SCB_CDB_PTR, 4; 1241 bmov HCNT, STCNT, 3; 1242 } else { 1243 mvi DINDEX, HADDR; 1244 mvi SCB_CDB_PTR call bcopy_4; 1245 mov SCB_CDB_LEN call set_hcnt; 1246 } 1247 mvi DFCNTRL, (SCSIEN|SDMAEN|HDMAEN|DIRECTION|FIFORESET); 1248 } 1249 jmp p_command_loop; 1250p_command_embedded: 1251 /* 1252 * The data fifo seems to require 4 byte alligned 1253 * transfers from the sequencer. Force this to 1254 * be the case by clearing HADDR[0] even though 1255 * we aren't going to touch host memeory. 1256 */ 1257 clr HADDR[0]; 1258 if ((ahc->features & AHC_ULTRA2) != 0) { 1259 mvi DFCNTRL, (PRELOADEN|SCSIEN|DIRECTION); 1260 bmov DFDAT, SCB_CDB_STORE, 12; 1261 } else if ((ahc->features & AHC_CMD_CHAN) != 0) { 1262 if ((ahc->features & AHC_SCB_BTT) != 0) { 1263 /* 1264 * On the 7895 the data FIFO will 1265 * get corrupted if you try to dump 1266 * data from external SCB memory into 1267 * the FIFO while it is enabled. So, 1268 * fill the fifo and then enable SCSI 1269 * transfers. 1270 */ 1271 mvi DFCNTRL, (DIRECTION|FIFORESET); 1272 } else { 1273 mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFORESET); 1274 } 1275 bmov DFDAT, SCB_CDB_STORE, 12; 1276 if ((ahc->features & AHC_SCB_BTT) != 0) { 1277 mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFOFLUSH); 1278 } else { 1279 or DFCNTRL, FIFOFLUSH; 1280 } 1281 } else { 1282 mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFORESET); 1283 call copy_to_fifo_6; 1284 call copy_to_fifo_6; 1285 or DFCNTRL, FIFOFLUSH; 1286 } 1287p_command_loop: 1288 test SSTAT0, SDONE jnz . + 2; 1289 test SSTAT1, PHASEMIS jz p_command_loop; 1290 /* 1291 * Wait for our ACK to go-away on it's own 1292 * instead of being killed by SCSIEN getting cleared. 1293 */ 1294 test SCSISIGI, ACKI jnz .; 1295 and DFCNTRL, ~(SCSIEN|SDMAEN|HDMAEN); 1296 test DFCNTRL, (SCSIEN|SDMAEN|HDMAEN) jnz .; 1297 if ((ahc->features & AHC_ULTRA2) != 0) { 1298 /* Drop any residual from the S/G Preload queue */ 1299 or SXFRCTL0, CLRSTCNT; 1300 } 1301 jmp ITloop; 1302 1303/* 1304 * Status phase. Wait for the data byte to appear, then read it 1305 * and store it into the SCB. 1306 */ 1307p_status: 1308 call assert; 1309 1310 mov SCB_SCSI_STATUS, SCSIDATL; 1311 jmp ITloop; 1312 1313/* 1314 * Message out phase. If MSG_OUT is MSG_IDENTIFYFLAG, build a full 1315 * indentify message sequence and send it to the target. The host may 1316 * override this behavior by setting the MK_MESSAGE bit in the SCB 1317 * control byte. This will cause us to interrupt the host and allow 1318 * it to handle the message phase completely on its own. If the bit 1319 * associated with this target is set, we will also interrupt the host, 1320 * thereby allowing it to send a message on the next selection regardless 1321 * of the transaction being sent. 1322 * 1323 * If MSG_OUT is == HOST_MSG, also interrupt the host and take a message. 1324 * This is done to allow the host to send messages outside of an identify 1325 * sequence while protecting the seqencer from testing the MK_MESSAGE bit 1326 * on an SCB that might not be for the current nexus. (For example, a 1327 * BDR message in responce to a bad reselection would leave us pointed to 1328 * an SCB that doesn't have anything to do with the current target). 1329 * 1330 * Otherwise, treat MSG_OUT as a 1 byte message to send (abort, abort tag, 1331 * bus device reset). 1332 * 1333 * When there are no messages to send, MSG_OUT should be set to MSG_NOOP, 1334 * in case the target decides to put us in this phase for some strange 1335 * reason. 1336 */ 1337p_mesgout_retry: 1338 or SCSISIGO,ATNO,LASTPHASE;/* turn on ATN for the retry */ 1339p_mesgout: 1340 mov SINDEX, MSG_OUT; 1341 cmp SINDEX, MSG_IDENTIFYFLAG jne p_mesgout_from_host; 1342 test SCB_CONTROL,MK_MESSAGE jnz host_message_loop; 1343 mov FUNCTION1, SCB_SCSIID; 1344 mov A, FUNCTION1; 1345 mov SINDEX, TARGET_MSG_REQUEST[0]; 1346 if ((ahc->features & AHC_TWIN) != 0) { 1347 /* Second Channel uses high byte bits */ 1348 test SCB_SCSIID, TWIN_CHNLB jz . + 2; 1349 mov SINDEX, TARGET_MSG_REQUEST[1]; 1350 } else if ((ahc->features & AHC_WIDE) != 0) { 1351 test SCB_SCSIID, 0x80 jz . + 2; /* target > 7 */ 1352 mov SINDEX, TARGET_MSG_REQUEST[1]; 1353 } 1354 test SINDEX, A jnz host_message_loop; 1355p_mesgout_identify: 1356 or SINDEX, MSG_IDENTIFYFLAG|DISCENB, SCB_LUN; 1357 test SCB_CONTROL, DISCENB jnz . + 2; 1358 and SINDEX, ~DISCENB; 1359/* 1360 * Send a tag message if TAG_ENB is set in the SCB control block. 1361 * Use SCB_TAG (the position in the kernel's SCB array) as the tag value. 1362 */ 1363p_mesgout_tag: 1364 test SCB_CONTROL,TAG_ENB jz p_mesgout_onebyte; 1365 mov SCSIDATL, SINDEX; /* Send the identify message */ 1366 call phase_lock; 1367 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done; 1368 and SCSIDATL,TAG_ENB|SCB_TAG_TYPE,SCB_CONTROL; 1369 call phase_lock; 1370 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done; 1371 mov SCB_TAG jmp p_mesgout_onebyte; 1372/* 1373 * Interrupt the driver, and allow it to handle this message 1374 * phase and any required retries. 1375 */ 1376p_mesgout_from_host: 1377 cmp SINDEX, HOST_MSG jne p_mesgout_onebyte; 1378 jmp host_message_loop; 1379 1380p_mesgout_onebyte: 1381 mvi CLRSINT1, CLRATNO; 1382 mov SCSIDATL, SINDEX; 1383 1384/* 1385 * If the next bus phase after ATN drops is message out, it means 1386 * that the target is requesting that the last message(s) be resent. 1387 */ 1388 call phase_lock; 1389 cmp LASTPHASE, P_MESGOUT je p_mesgout_retry; 1390 1391p_mesgout_done: 1392 mvi CLRSINT1,CLRATNO; /* Be sure to turn ATNO off */ 1393 mov LAST_MSG, MSG_OUT; 1394 mvi MSG_OUT, MSG_NOOP; /* No message left */ 1395 jmp ITloop; 1396 1397/* 1398 * Message in phase. Bytes are read using Automatic PIO mode. 1399 */ 1400p_mesgin: 1401 mvi ACCUM call inb_first; /* read the 1st message byte */ 1402 1403 test A,MSG_IDENTIFYFLAG jnz mesgin_identify; 1404 cmp A,MSG_DISCONNECT je mesgin_disconnect; 1405 cmp A,MSG_SAVEDATAPOINTER je mesgin_sdptrs; 1406 cmp ALLZEROS,A je mesgin_complete; 1407 cmp A,MSG_RESTOREPOINTERS je mesgin_rdptrs; 1408 cmp A,MSG_IGN_WIDE_RESIDUE je mesgin_ign_wide_residue; 1409 cmp A,MSG_NOOP je mesgin_done; 1410 1411/* 1412 * Pushed message loop to allow the kernel to 1413 * run it's own message state engine. To avoid an 1414 * extra nop instruction after signaling the kernel, 1415 * we perform the phase_lock before checking to see 1416 * if we should exit the loop and skip the phase_lock 1417 * in the ITloop. Performing back to back phase_locks 1418 * shouldn't hurt, but why do it twice... 1419 */ 1420host_message_loop: 1421 mvi HOST_MSG_LOOP call set_seqint; 1422 call phase_lock; 1423 cmp RETURN_1, EXIT_MSG_LOOP je ITloop + 1; 1424 jmp host_message_loop; 1425 1426mesgin_ign_wide_residue: 1427if ((ahc->features & AHC_WIDE) != 0) { 1428 test SCSIRATE, WIDEXFER jz mesgin_reject; 1429 /* Pull the residue byte */ 1430 mvi ARG_1 call inb_next; 1431 cmp ARG_1, 0x01 jne mesgin_reject; 1432 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz . + 2; 1433 test DATA_COUNT_ODD, 0x1 jz mesgin_done; 1434 mvi IGN_WIDE_RES call set_seqint; 1435 jmp mesgin_done; 1436} 1437 1438mesgin_reject: 1439 mvi MSG_MESSAGE_REJECT call mk_mesg; 1440mesgin_done: 1441 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/ 1442 jmp ITloop; 1443 1444mesgin_complete: 1445/* 1446 * We received a "command complete" message. Put the SCB_TAG into the QOUTFIFO, 1447 * and trigger a completion interrupt. Before doing so, check to see if there 1448 * is a residual or the status byte is something other than STATUS_GOOD (0). 1449 * In either of these conditions, we upload the SCB back to the host so it can 1450 * process this information. In the case of a non zero status byte, we 1451 * additionally interrupt the kernel driver synchronously, allowing it to 1452 * decide if sense should be retrieved. If the kernel driver wishes to request 1453 * sense, it will fill the kernel SCB with a request sense command, requeue 1454 * it to the QINFIFO and tell us not to post to the QOUTFIFO by setting 1455 * RETURN_1 to SEND_SENSE. 1456 */ 1457 1458/* 1459 * If ATN is raised, we still want to give the target a message. 1460 * Perhaps there was a parity error on this last message byte. 1461 * Either way, the target should take us to message out phase 1462 * and then attempt to complete the command again. 1463 * XXX - Need a critical section to do this corrctly. Wait until 1464 * we queue completions. 1465 test SCSISIGI, ATNI jnz mesgin_done; 1466 */ 1467 1468/* 1469 * See if we attempted to deliver a message but the target ingnored us. 1470 */ 1471 test SCB_CONTROL, MK_MESSAGE jz . + 2; 1472 mvi MKMSG_FAILED call set_seqint; 1473 1474/* 1475 * Check for residuals 1476 */ 1477 test SCB_SGPTR, SG_LIST_NULL jnz check_status;/* No xfer */ 1478 test SCB_SGPTR, SG_FULL_RESID jnz upload_scb;/* Never xfered */ 1479 test SCB_RESIDUAL_SGPTR, SG_LIST_NULL jz upload_scb; 1480check_status: 1481 test SCB_SCSI_STATUS,0xff jz complete; /* Good Status? */ 1482upload_scb: 1483 or SCB_SGPTR, SG_RESID_VALID; 1484 mvi DMAPARAMS, FIFORESET; 1485 mov SCB_TAG call dma_scb; 1486 test SCB_SCSI_STATUS, 0xff jz complete; /* Just a residual? */ 1487 mvi BAD_STATUS call set_seqint; /* let driver know */ 1488 cmp RETURN_1, SEND_SENSE jne complete; 1489 call add_scb_to_free_list; 1490 jmp await_busfree; 1491complete: 1492 mov SCB_TAG call complete_post; 1493 jmp await_busfree; 1494} 1495 1496complete_post: 1497 /* Post the SCBID in SINDEX and issue an interrupt */ 1498 call add_scb_to_free_list; 1499 mov ARG_1, SINDEX; 1500 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 1501 mov A, SDSCB_QOFF; 1502 } else { 1503 mov A, QOUTPOS; 1504 } 1505 mvi QOUTFIFO_OFFSET call post_byte_setup; 1506 mov ARG_1 call post_byte; 1507 if ((ahc->features & AHC_QUEUE_REGS) == 0) { 1508 inc QOUTPOS; 1509 } 1510 mvi INTSTAT,CMDCMPLT ret; 1511 1512if ((ahc->flags & AHC_INITIATORROLE) != 0) { 1513/* 1514 * Is it a disconnect message? Set a flag in the SCB to remind us 1515 * and await the bus going free. If this is an untagged transaction 1516 * store the SCB id for it in our untagged target table for lookup on 1517 * a reselction. 1518 */ 1519mesgin_disconnect: 1520 /* 1521 * If ATN is raised, we still want to give the target a message. 1522 * Perhaps there was a parity error on this last message byte 1523 * or we want to abort this command. Either way, the target 1524 * should take us to message out phase and then attempt to 1525 * disconnect again. 1526 * XXX - Wait for more testing. 1527 test SCSISIGI, ATNI jnz mesgin_done; 1528 */ 1529 1530 or SCB_CONTROL,DISCONNECTED; 1531 if ((ahc->flags & AHC_PAGESCBS) != 0) { 1532 call add_scb_to_disc_list; 1533 } 1534 test SCB_CONTROL, TAG_ENB jnz await_busfree; 1535 mov ARG_1, SCB_TAG; 1536 mov SAVED_LUN, SCB_LUN; 1537 mov SCB_SCSIID call set_busy_target; 1538 jmp await_busfree; 1539 1540/* 1541 * Save data pointers message: 1542 * Copying RAM values back to SCB, for Save Data Pointers message, but 1543 * only if we've actually been into a data phase to change them. This 1544 * protects against bogus data in scratch ram and the residual counts 1545 * since they are only initialized when we go into data_in or data_out. 1546 */ 1547mesgin_sdptrs: 1548 test SEQ_FLAGS, DPHASE jz mesgin_done; 1549 1550 /* 1551 * The SCB_SGPTR becomes the next one we'll download, 1552 * and the SCB_DATAPTR becomes the current SHADDR. 1553 * Use the residual number since STCNT is corrupted by 1554 * any message transfer. 1555 */ 1556 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1557 bmov SCB_DATAPTR, SHADDR, 4; 1558 bmov SCB_DATACNT, SCB_RESIDUAL_DATACNT, 8; 1559 } else { 1560 mvi DINDEX, SCB_DATAPTR; 1561 mvi SHADDR call bcopy_4; 1562 mvi SCB_RESIDUAL_DATACNT call bcopy_8; 1563 } 1564 jmp mesgin_done; 1565 1566/* 1567 * Restore pointers message? Data pointers are recopied from the 1568 * SCB anytime we enter a data phase for the first time, so all 1569 * we need to do is clear the DPHASE flag and let the data phase 1570 * code do the rest. 1571 */ 1572mesgin_rdptrs: 1573 and SEQ_FLAGS, ~DPHASE; /* 1574 * We'll reload them 1575 * the next time through 1576 * the dataphase. 1577 */ 1578 jmp mesgin_done; 1579 1580/* 1581 * Index into our Busy Target table. SINDEX and DINDEX are modified 1582 * upon return. SCBPTR may be modified by this action. 1583 */ 1584set_busy_target: 1585 shr DINDEX, 4, SINDEX; 1586 if ((ahc->features & AHC_SCB_BTT) != 0) { 1587 mov SCBPTR, SAVED_LUN; 1588 add DINDEX, SCB_64_BTT; 1589 } else { 1590 add DINDEX, BUSY_TARGETS; 1591 } 1592 mov DINDIR, ARG_1 ret; 1593 1594/* 1595 * Identify message? For a reconnecting target, this tells us the lun 1596 * that the reconnection is for - find the correct SCB and switch to it, 1597 * clearing the "disconnected" bit so we don't "find" it by accident later. 1598 */ 1599mesgin_identify: 1600 and SAVED_LUN, MSG_IDENTIFY_LUNMASK, A; 1601 /* 1602 * Determine whether a target is using tagged or non-tagged 1603 * transactions by first looking at the transaction stored in 1604 * the busy target array. If there is no untagged transaction 1605 * for this target or the transaction is for a different lun, then 1606 * this must be an untagged transaction. 1607 */ 1608fetch_busy_target: 1609 shr A, 4, SAVED_SCSIID; 1610 if ((ahc->features & AHC_SCB_BTT) != 0) { 1611 add SINDEX, SCB_64_BTT, A; 1612 mov SCBPTR, SAVED_LUN; 1613 } else { 1614 add SINDEX, BUSY_TARGETS, A; 1615 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 1616 add A, -BUSY_TARGETS, SINDEX; 1617 jc . + 2; 1618 mvi INTSTAT, OUT_OF_RANGE; 1619 nop; 1620 add A, -(BUSY_TARGETS + 16), SINDEX; 1621 jnc . + 2; 1622 mvi INTSTAT, OUT_OF_RANGE; 1623 nop; 1624 } 1625 } 1626 mov ARG_1, SINDIR; 1627 cmp ARG_1, SCB_LIST_NULL je snoop_tag; 1628 if ((ahc->flags & AHC_PAGESCBS) != 0) { 1629 mov ARG_1 call findSCB; 1630 } else { 1631 mov SCBPTR, RETURN_1; 1632 } 1633 if ((ahc->features & AHC_SCB_BTT) != 0) { 1634 jmp setup_SCB_id_lun_okay; 1635 } else { 1636 mov A, SCB_LUN; 1637 cmp SAVED_LUN, A je setup_SCB_id_lun_okay; 1638 } 1639 if ((ahc->flags & AHC_PAGESCBS) != 0) { 1640 call add_scb_to_disc_list; 1641 } 1642 1643/* 1644 * Here we "snoop" the bus looking for a SIMPLE QUEUE TAG message. 1645 * If we get one, we use the tag returned to find the proper 1646 * SCB. With SCB paging, we must search for non-tagged 1647 * transactions since the SCB may exist in any slot. If we're not 1648 * using SCB paging, we can use the tag as the direct index to the 1649 * SCB. 1650 */ 1651snoop_tag: 1652 mov NONE,SCSIDATL; /* ACK Identify MSG */ 1653 call phase_lock; 1654 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 1655 or SEQ_FLAGS, 0x1; 1656 } 1657 cmp LASTPHASE, P_MESGIN jne not_found; 1658 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 1659 or SEQ_FLAGS, 0x2; 1660 } 1661 cmp SCSIBUSL,MSG_SIMPLE_Q_TAG jne not_found; 1662get_tag: 1663 if ((ahc->flags & AHC_PAGESCBS) != 0) { 1664 mvi ARG_1 call inb_next; /* tag value */ 1665 mov ARG_1 call findSCB; 1666 } else { 1667 mvi ARG_1 call inb_next; /* tag value */ 1668 mov SCBPTR, ARG_1; 1669 } 1670 1671/* 1672 * Ensure that the SCB the tag points to is for 1673 * an SCB transaction to the reconnecting target. 1674 */ 1675setup_SCB: 1676 mov A, SAVED_SCSIID; 1677 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 1678 or SEQ_FLAGS, 0x4; 1679 } 1680 cmp SCB_SCSIID, A jne not_found_cleanup_scb; 1681 mov A, SAVED_LUN; 1682 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 1683 or SEQ_FLAGS, 0x8; 1684 } 1685 cmp SCB_LUN, A jne not_found_cleanup_scb; 1686setup_SCB_id_lun_okay: 1687 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 1688 or SEQ_FLAGS, 0x10; 1689 } 1690 test SCB_CONTROL,DISCONNECTED jz not_found_cleanup_scb; 1691 and SCB_CONTROL,~DISCONNECTED; 1692 test SCB_CONTROL, TAG_ENB jnz setup_SCB_tagged; 1693 mov A, SCBPTR; 1694 mvi ARG_1, SCB_LIST_NULL; 1695 mov SAVED_SCSIID call set_busy_target; 1696 mov SCBPTR, A; 1697setup_SCB_tagged: 1698 mvi SEQ_FLAGS,IDENTIFY_SEEN; /* make note of IDENTIFY */ 1699 call set_transfer_settings; 1700 /* See if the host wants to send a message upon reconnection */ 1701 test SCB_CONTROL, MK_MESSAGE jz mesgin_done; 1702 mvi HOST_MSG call mk_mesg; 1703 jmp mesgin_done; 1704 1705not_found_cleanup_scb: 1706 if ((ahc->flags & AHC_PAGESCBS) != 0) { 1707 call add_scb_to_free_list; 1708 } 1709not_found: 1710 mvi NO_MATCH call set_seqint; 1711 jmp mesgin_done; 1712 1713mk_mesg: 1714 or SCSISIGO,ATNO,LASTPHASE;/* turn on ATNO */ 1715 mov MSG_OUT,SINDEX ret; 1716 1717/* 1718 * Functions to read data in Automatic PIO mode. 1719 * 1720 * According to Adaptec's documentation, an ACK is not sent on input from 1721 * the target until SCSIDATL is read from. So we wait until SCSIDATL is 1722 * latched (the usual way), then read the data byte directly off the bus 1723 * using SCSIBUSL. When we have pulled the ATN line, or we just want to 1724 * acknowledge the byte, then we do a dummy read from SCISDATL. The SCSI 1725 * spec guarantees that the target will hold the data byte on the bus until 1726 * we send our ACK. 1727 * 1728 * The assumption here is that these are called in a particular sequence, 1729 * and that REQ is already set when inb_first is called. inb_{first,next} 1730 * use the same calling convention as inb. 1731 */ 1732inb_next_wait_perr: 1733 mvi PERR_DETECTED call set_seqint; 1734 jmp inb_next_wait; 1735inb_next: 1736 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/ 1737inb_next_wait: 1738 /* 1739 * If there is a parity error, wait for the kernel to 1740 * see the interrupt and prepare our message response 1741 * before continuing. 1742 */ 1743 test SSTAT1, REQINIT jz inb_next_wait; 1744 test SSTAT1, SCSIPERR jnz inb_next_wait_perr; 1745inb_next_check_phase: 1746 and LASTPHASE, PHASE_MASK, SCSISIGI; 1747 cmp LASTPHASE, P_MESGIN jne mesgin_phasemis; 1748inb_first: 1749 mov DINDEX,SINDEX; 1750 mov DINDIR,SCSIBUSL ret; /*read byte directly from bus*/ 1751inb_last: 1752 mov NONE,SCSIDATL ret; /*dummy read from latch to ACK*/ 1753} 1754 1755if ((ahc->flags & AHC_TARGETROLE) != 0) { 1756/* 1757 * Change to a new phase. If we are changing the state of the I/O signal, 1758 * from out to in, wait an additional data release delay before continuing. 1759 */ 1760change_phase: 1761 /* Wait for preceeding I/O session to complete. */ 1762 test SCSISIGI, ACKI jnz .; 1763 1764 /* Change the phase */ 1765 and DINDEX, IOI, SCSISIGI; 1766 mov SCSISIGO, SINDEX; 1767 and A, IOI, SINDEX; 1768 1769 /* 1770 * If the data direction has changed, from 1771 * out (initiator driving) to in (target driving), 1772 * we must wait at least a data release delay plus 1773 * the normal bus settle delay. [SCSI III SPI 10.11.0] 1774 */ 1775 cmp DINDEX, A je change_phase_wait; 1776 test SINDEX, IOI jz change_phase_wait; 1777 call change_phase_wait; 1778change_phase_wait: 1779 nop; 1780 nop; 1781 nop; 1782 nop ret; 1783 1784/* 1785 * Send a byte to an initiator in Automatic PIO mode. 1786 */ 1787target_outb: 1788 or SXFRCTL0, SPIOEN; 1789 test SSTAT0, SPIORDY jz .; 1790 mov SCSIDATL, SINDEX; 1791 test SSTAT0, SPIORDY jz .; 1792 and SXFRCTL0, ~SPIOEN ret; 1793} 1794 1795 1796/* 1797 * Assert that if we've been reselected, then we've seen an IDENTIFY 1798 * message. 1799 */ 1800assert: 1801 test SEQ_FLAGS,IDENTIFY_SEEN jnz return; /* seen IDENTIFY? */ 1802 1803 mvi NO_IDENT jmp set_seqint; /* no - tell the kernel */ 1804 1805/* 1806 * Locate a disconnected SCB by SCBID. Upon return, SCBPTR and SINDEX will 1807 * be set to the position of the SCB. If the SCB cannot be found locally, 1808 * it will be paged in from host memory. RETURN_2 stores the address of the 1809 * preceding SCB in the disconnected list which can be used to speed up 1810 * removal of the found SCB from the disconnected list. 1811 */ 1812if ((ahc->flags & AHC_PAGESCBS) != 0) { 1813BEGIN_CRITICAL 1814findSCB: 1815 mov A, SINDEX; /* Tag passed in SINDEX */ 1816 cmp DISCONNECTED_SCBH, SCB_LIST_NULL je findSCB_notFound; 1817 mov SCBPTR, DISCONNECTED_SCBH; /* Initialize SCBPTR */ 1818 mvi ARG_2, SCB_LIST_NULL; /* Head of list */ 1819 jmp findSCB_loop; 1820findSCB_next: 1821 cmp SCB_NEXT, SCB_LIST_NULL je findSCB_notFound; 1822 mov ARG_2, SCBPTR; 1823 mov SCBPTR,SCB_NEXT; 1824findSCB_loop: 1825 cmp SCB_TAG, A jne findSCB_next; 1826rem_scb_from_disc_list: 1827 cmp ARG_2, SCB_LIST_NULL je rHead; 1828 mov DINDEX, SCB_NEXT; 1829 mov SINDEX, SCBPTR; 1830 mov SCBPTR, ARG_2; 1831 mov SCB_NEXT, DINDEX; 1832 mov SCBPTR, SINDEX ret; 1833rHead: 1834 mov DISCONNECTED_SCBH,SCB_NEXT ret; 1835END_CRITICAL 1836findSCB_notFound: 1837 /* 1838 * We didn't find it. Page in the SCB. 1839 */ 1840 mov ARG_1, A; /* Save tag */ 1841 mov ALLZEROS call get_free_or_disc_scb; 1842 mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET; 1843 mov ARG_1 jmp dma_scb; 1844} 1845 1846/* 1847 * Prepare the hardware to post a byte to host memory given an 1848 * index of (A + (256 * SINDEX)) and a base address of SHARED_DATA_ADDR. 1849 */ 1850post_byte_setup: 1851 mov ARG_2, SINDEX; 1852 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1853 mvi DINDEX, CCHADDR; 1854 mvi SHARED_DATA_ADDR call set_1byte_addr; 1855 mvi CCHCNT, 1; 1856 mvi CCSCBCTL, CCSCBRESET ret; 1857 } else { 1858 mvi DINDEX, HADDR; 1859 mvi SHARED_DATA_ADDR call set_1byte_addr; 1860 mvi 1 call set_hcnt; 1861 mvi DFCNTRL, FIFORESET ret; 1862 } 1863 1864post_byte: 1865 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1866 bmov CCSCBRAM, SINDEX, 1; 1867 or CCSCBCTL, CCSCBEN|CCSCBRESET; 1868 test CCSCBCTL, CCSCBDONE jz .; 1869 clr CCSCBCTL ret; 1870 } else { 1871 mov DFDAT, SINDEX; 1872 or DFCNTRL, HDMAEN|FIFOFLUSH; 1873 jmp dma_finish; 1874 } 1875 1876phase_lock_perr: 1877 mvi PERR_DETECTED call set_seqint; 1878phase_lock: 1879 /* 1880 * If there is a parity error, wait for the kernel to 1881 * see the interrupt and prepare our message response 1882 * before continuing. 1883 */ 1884 test SSTAT1, REQINIT jz phase_lock; 1885 test SSTAT1, SCSIPERR jnz phase_lock_perr; 1886phase_lock_latch_phase: 1887 and SCSISIGO, PHASE_MASK, SCSISIGI; 1888 and LASTPHASE, PHASE_MASK, SCSISIGI ret; 1889 1890if ((ahc->features & AHC_CMD_CHAN) == 0) { 1891set_hcnt: 1892 mov HCNT[0], SINDEX; 1893clear_hcnt: 1894 clr HCNT[1]; 1895 clr HCNT[2] ret; 1896 1897set_stcnt_from_hcnt: 1898 mov STCNT[0], HCNT[0]; 1899 mov STCNT[1], HCNT[1]; 1900 mov STCNT[2], HCNT[2] ret; 1901 1902bcopy_8: 1903 mov DINDIR, SINDIR; 1904bcopy_7: 1905 mov DINDIR, SINDIR; 1906 mov DINDIR, SINDIR; 1907bcopy_5: 1908 mov DINDIR, SINDIR; 1909bcopy_4: 1910 mov DINDIR, SINDIR; 1911bcopy_3: 1912 mov DINDIR, SINDIR; 1913 mov DINDIR, SINDIR; 1914 mov DINDIR, SINDIR ret; 1915} 1916 1917if ((ahc->flags & AHC_TARGETROLE) != 0) { 1918/* 1919 * Setup addr assuming that A is an index into 1920 * an array of 32byte objects, SINDEX contains 1921 * the base address of that array, and DINDEX 1922 * contains the base address of the location 1923 * to store the indexed address. 1924 */ 1925set_32byte_addr: 1926 shr ARG_2, 3, A; 1927 shl A, 5; 1928 jmp set_1byte_addr; 1929} 1930 1931/* 1932 * Setup addr assuming that A is an index into 1933 * an array of 64byte objects, SINDEX contains 1934 * the base address of that array, and DINDEX 1935 * contains the base address of the location 1936 * to store the indexed address. 1937 */ 1938set_64byte_addr: 1939 shr ARG_2, 2, A; 1940 shl A, 6; 1941 1942/* 1943 * Setup addr assuming that A + (ARG_2 * 256) is an 1944 * index into an array of 1byte objects, SINDEX contains 1945 * the base address of that array, and DINDEX contains 1946 * the base address of the location to store the computed 1947 * address. 1948 */ 1949set_1byte_addr: 1950 add DINDIR, A, SINDIR; 1951 mov A, ARG_2; 1952 adc DINDIR, A, SINDIR; 1953 clr A; 1954 adc DINDIR, A, SINDIR; 1955 adc DINDIR, A, SINDIR ret; 1956 1957/* 1958 * Either post or fetch and SCB from host memory based on the 1959 * DIRECTION bit in DMAPARAMS. The host SCB index is in SINDEX. 1960 */ 1961dma_scb: 1962 mov A, SINDEX; 1963 if ((ahc->features & AHC_CMD_CHAN) != 0) { 1964 mvi DINDEX, CCHADDR; 1965 mvi HSCB_ADDR call set_64byte_addr; 1966 mov CCSCBPTR, SCBPTR; 1967 test DMAPARAMS, DIRECTION jz dma_scb_tohost; 1968 if ((ahc->features & AHC_SCB_BTT) != 0) { 1969 mvi CCHCNT, SCB_DOWNLOAD_SIZE_64; 1970 } else { 1971 mvi CCHCNT, SCB_DOWNLOAD_SIZE; 1972 } 1973 mvi CCSCBCTL, CCARREN|CCSCBEN|CCSCBDIR|CCSCBRESET; 1974 cmp CCSCBCTL, CCSCBDONE|ARRDONE|CCARREN|CCSCBEN|CCSCBDIR jne .; 1975 jmp dma_scb_finish; 1976dma_scb_tohost: 1977 mvi CCHCNT, SCB_UPLOAD_SIZE; 1978 if ((ahc->features & AHC_ULTRA2) == 0) { 1979 mvi CCSCBCTL, CCSCBRESET; 1980 bmov CCSCBRAM, SCB_BASE, SCB_UPLOAD_SIZE; 1981 or CCSCBCTL, CCSCBEN|CCSCBRESET; 1982 test CCSCBCTL, CCSCBDONE jz .; 1983 } else if ((ahc->bugs & AHC_SCBCHAN_UPLOAD_BUG) != 0) { 1984 mvi CCSCBCTL, CCARREN|CCSCBRESET; 1985 cmp CCSCBCTL, ARRDONE|CCARREN jne .; 1986 mvi CCHCNT, SCB_UPLOAD_SIZE; 1987 mvi CCSCBCTL, CCSCBEN|CCSCBRESET; 1988 cmp CCSCBCTL, CCSCBDONE|CCSCBEN jne .; 1989 } else { 1990 mvi CCSCBCTL, CCARREN|CCSCBEN|CCSCBRESET; 1991 cmp CCSCBCTL, CCSCBDONE|ARRDONE|CCARREN|CCSCBEN jne .; 1992 } 1993dma_scb_finish: 1994 clr CCSCBCTL; 1995 test CCSCBCTL, CCARREN|CCSCBEN jnz .; 1996 ret; 1997 } else { 1998 mvi DINDEX, HADDR; 1999 mvi HSCB_ADDR call set_64byte_addr; 2000 mvi SCB_DOWNLOAD_SIZE call set_hcnt; 2001 mov DFCNTRL, DMAPARAMS; 2002 test DMAPARAMS, DIRECTION jnz dma_scb_fromhost; 2003 /* Fill it with the SCB data */ 2004copy_scb_tofifo: 2005 mvi SINDEX, SCB_BASE; 2006 add A, SCB_DOWNLOAD_SIZE, SINDEX; 2007copy_scb_tofifo_loop: 2008 call copy_to_fifo_8; 2009 cmp SINDEX, A jne copy_scb_tofifo_loop; 2010 or DFCNTRL, HDMAEN|FIFOFLUSH; 2011 jmp dma_finish; 2012dma_scb_fromhost: 2013 mvi DINDEX, SCB_BASE; 2014 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0) { 2015 /* 2016 * The PCI module will only issue a PCI 2017 * retry if the data FIFO is empty. If the 2018 * host disconnects in the middle of a 2019 * transfer, we must empty the fifo of all 2020 * available data to force the chip to 2021 * continue the transfer. This does not 2022 * happen for SCSI transfers as the SCSI module 2023 * will drain the FIFO as data is made available. 2024 * When the hang occurs, we know that at least 2025 * 8 bytes are in the FIFO because the PCI 2026 * module has an 8 byte input latch that only 2027 * dumps to the FIFO when HCNT == 0 or the 2028 * latch is full. 2029 */ 2030 mvi A, -24; 2031 /* Wait for some data to arrive. */ 2032dma_scb_hang_fifo: 2033 test DFSTATUS, FIFOEMP jnz dma_scb_hang_fifo; 2034dma_scb_hang_wait: 2035 test DFSTATUS, MREQPEND jnz dma_scb_hang_wait; 2036 test DFSTATUS, HDONE jnz dma_scb_hang_dma_done; 2037 test DFSTATUS, HDONE jnz dma_scb_hang_dma_done; 2038 test DFSTATUS, HDONE jnz dma_scb_hang_dma_done; 2039 /* 2040 * The PCI no longer intends to perform a PCI 2041 * transaction and HDONE has not come true. 2042 * We are hung. Drain the fifo. 2043 */ 2044dma_scb_hang_empty_fifo: 2045 call dfdat_in_8; 2046 add A, 8; 2047 add SINDEX, A, HCNT; 2048 /* 2049 * The result will be <= 0 (carry set) if at 2050 * least 8 bytes of data have been placed 2051 * into the fifo. 2052 */ 2053 jc dma_scb_hang_empty_fifo; 2054 jmp dma_scb_hang_fifo; 2055dma_scb_hang_dma_done: 2056 and DFCNTRL, ~HDMAEN; 2057 test DFCNTRL, HDMAEN jnz .; 2058 call dfdat_in_8; 2059 add A, 8; 2060 cmp A, 8 jne . - 2; 2061 } else { 2062 call dma_finish; 2063 /* If we were putting the SCB, we are done */ 2064 call dfdat_in_8; 2065 call dfdat_in_8; 2066 call dfdat_in_8; 2067 } 2068dfdat_in_8: 2069 mov DINDIR,DFDAT; 2070dfdat_in_7: 2071 mov DINDIR,DFDAT; 2072 mov DINDIR,DFDAT; 2073 mov DINDIR,DFDAT; 2074 mov DINDIR,DFDAT; 2075 mov DINDIR,DFDAT; 2076dfdat_in_2: 2077 mov DINDIR,DFDAT; 2078 mov DINDIR,DFDAT ret; 2079 } 2080 2081copy_to_fifo_8: 2082 mov DFDAT,SINDIR; 2083 mov DFDAT,SINDIR; 2084copy_to_fifo_6: 2085 mov DFDAT,SINDIR; 2086copy_to_fifo_5: 2087 mov DFDAT,SINDIR; 2088copy_to_fifo_4: 2089 mov DFDAT,SINDIR; 2090 mov DFDAT,SINDIR; 2091 mov DFDAT,SINDIR; 2092 mov DFDAT,SINDIR ret; 2093 2094/* 2095 * Wait for DMA from host memory to data FIFO to complete, then disable 2096 * DMA and wait for it to acknowledge that it's off. 2097 */ 2098dma_finish: 2099 test DFSTATUS,HDONE jz dma_finish; 2100 /* Turn off DMA */ 2101 and DFCNTRL, ~HDMAEN; 2102 test DFCNTRL, HDMAEN jnz .; 2103 ret; 2104 2105add_scb_to_free_list: 2106 if ((ahc->flags & AHC_PAGESCBS) != 0) { 2107BEGIN_CRITICAL 2108 mov SCB_NEXT, FREE_SCBH; 2109 mvi SCB_TAG, SCB_LIST_NULL; 2110 mov FREE_SCBH, SCBPTR ret; 2111END_CRITICAL 2112 } else { 2113 mvi SCB_TAG, SCB_LIST_NULL ret; 2114 } 2115 2116if ((ahc->flags & AHC_PAGESCBS) != 0) { 2117get_free_or_disc_scb: 2118BEGIN_CRITICAL 2119 cmp FREE_SCBH, SCB_LIST_NULL jne dequeue_free_scb; 2120 cmp DISCONNECTED_SCBH, SCB_LIST_NULL jne dequeue_disc_scb; 2121return_error: 2122 mvi NO_FREE_SCB call set_seqint; 2123 mvi SINDEX, SCB_LIST_NULL ret; 2124dequeue_disc_scb: 2125 mov SCBPTR, DISCONNECTED_SCBH; 2126 mov DISCONNECTED_SCBH, SCB_NEXT; 2127END_CRITICAL 2128 mvi DMAPARAMS, FIFORESET; 2129 mov SCB_TAG jmp dma_scb; 2130BEGIN_CRITICAL 2131dequeue_free_scb: 2132 mov SCBPTR, FREE_SCBH; 2133 mov FREE_SCBH, SCB_NEXT ret; 2134END_CRITICAL 2135 2136add_scb_to_disc_list: 2137/* 2138 * Link this SCB into the DISCONNECTED list. This list holds the 2139 * candidates for paging out an SCB if one is needed for a new command. 2140 * Modifying the disconnected list is a critical(pause dissabled) section. 2141 */ 2142BEGIN_CRITICAL 2143 mov SCB_NEXT, DISCONNECTED_SCBH; 2144 mov DISCONNECTED_SCBH, SCBPTR ret; 2145END_CRITICAL 2146} 2147set_seqint: 2148 mov INTSTAT, SINDEX; 2149 nop; 2150return: 2151 ret; 2152