aic7xxx.seq revision 123579
126997Sgibbs/* 226997Sgibbs * Adaptec 274x/284x/294x device driver firmware for Linux and FreeBSD. 313177Sgibbs * 495378Sgibbs * Copyright (c) 1994-2001 Justin T. Gibbs. 595378Sgibbs * Copyright (c) 2000-2001 Adaptec Inc. 626997Sgibbs * All rights reserved. 713177Sgibbs * 826997Sgibbs * Redistribution and use in source and binary forms, with or without 926997Sgibbs * modification, are permitted provided that the following conditions 1026997Sgibbs * are met: 1126997Sgibbs * 1. Redistributions of source code must retain the above copyright 1226997Sgibbs * notice, this list of conditions, and the following disclaimer, 1354211Sgibbs * without modification. 1495378Sgibbs * 2. Redistributions in binary form must reproduce at minimum a disclaimer 1595378Sgibbs * substantially similar to the "NO WARRANTY" disclaimer below 1695378Sgibbs * ("Disclaimer") and any redistribution must be conditioned upon 1795378Sgibbs * including a substantially similar Disclaimer requirement for further 1895378Sgibbs * binary redistribution. 1995378Sgibbs * 3. Neither the names of the above-listed copyright holders nor the names 2095378Sgibbs * of any contributors may be used to endorse or promote products derived 2195378Sgibbs * from this software without specific prior written permission. 2213177Sgibbs * 2354211Sgibbs * Alternatively, this software may be distributed under the terms of the 2495378Sgibbs * GNU General Public License ("GPL") version 2 as published by the Free 2595378Sgibbs * Software Foundation. 2613177Sgibbs * 2795378Sgibbs * NO WARRANTY 2895378Sgibbs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2995378Sgibbs * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3095378Sgibbs * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 3195378Sgibbs * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3295378Sgibbs * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 3326997Sgibbs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 3426997Sgibbs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 3595378Sgibbs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 3695378Sgibbs * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 3795378Sgibbs * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3895378Sgibbs * POSSIBILITY OF SUCH DAMAGES. 3913177Sgibbs * 4050477Speter * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.seq 123579 2003-12-17 00:02:10Z gibbs $ 4126997Sgibbs */ 424568Sgibbs 43123579SgibbsVERSION = "$Id: //depot/aic7xxx/aic7xxx/aic7xxx.seq#58 $" 4495378SgibbsPATCH_ARG_LIST = "struct ahc_softc *ahc" 45102673SgibbsPREFIX = "ahc_" 4679874Sgibbs 4766268Sgibbs#include "aic7xxx.reg" 4866268Sgibbs#include "scsi_message.h" 495647Sgibbs 5013177Sgibbs/* 5119164Sgibbs * A few words on the waiting SCB list: 5219164Sgibbs * After starting the selection hardware, we check for reconnecting targets 5313690Sgibbs * as well as for our selection to complete just in case the reselection wins 5413690Sgibbs * bus arbitration. The problem with this is that we must keep track of the 5513690Sgibbs * SCB that we've already pulled from the QINFIFO and started the selection 5613690Sgibbs * on just in case the reselection wins so that we can retry the selection at 5713690Sgibbs * a later time. This problem cannot be resolved by holding a single entry 5813690Sgibbs * in scratch ram since a reconnecting target can request sense and this will 5913690Sgibbs * create yet another SCB waiting for selection. The solution used here is to 6013690Sgibbs * use byte 27 of the SCB as a psuedo-next pointer and to thread a list 6119164Sgibbs * of SCBs that are awaiting selection. Since 0-0xfe are valid SCB indexes, 6219164Sgibbs * SCB_LIST_NULL is 0xff which is out of range. An entry is also added to 6319164Sgibbs * this list everytime a request sense occurs or after completing a non-tagged 6419164Sgibbs * command for which a second SCB has been queued. The sequencer will 6519164Sgibbs * automatically consume the entries. 6613177Sgibbs */ 674568Sgibbs 6871390Sgibbsbus_free_sel: 6971390Sgibbs /* 7071390Sgibbs * Turn off the selection hardware. We need to reset the 7171390Sgibbs * selection request in order to perform a new selection. 7271390Sgibbs */ 73109590Sgibbs and SCSISEQ, TEMODE|ENSELI|ENRSELI|ENAUTOATNP; 7471390Sgibbs and SIMODE1, ~ENBUSFREE; 7544507Sgibbspoll_for_work: 7623925Sgibbs call clear_target_state; 7739220Sgibbs and SXFRCTL0, ~SPIOEN; 7868623Sgibbs if ((ahc->features & AHC_ULTRA2) != 0) { 7968623Sgibbs clr SCSIBUSL; 8068623Sgibbs } 8172811Sgibbs test SCSISEQ, ENSELO jnz poll_for_selection; 8272811Sgibbs if ((ahc->features & AHC_TWIN) != 0) { 8372811Sgibbs xor SBLKCTL,SELBUSB; /* Toggle to the other bus */ 8472811Sgibbs test SCSISEQ, ENSELO jnz poll_for_selection; 8572811Sgibbs } 8672811Sgibbs cmp WAITING_SCBH,SCB_LIST_NULL jne start_waiting; 8739220Sgibbspoll_for_work_loop: 8839220Sgibbs if ((ahc->features & AHC_TWIN) != 0) { 8939220Sgibbs xor SBLKCTL,SELBUSB; /* Toggle to the other bus */ 9039220Sgibbs } 9172811Sgibbs test SSTAT0, SELDO|SELDI jnz selection; 9219164Sgibbstest_queue: 9319164Sgibbs /* Has the driver posted any work for us? */ 9495378SgibbsBEGIN_CRITICAL; 9539220Sgibbs if ((ahc->features & AHC_QUEUE_REGS) != 0) { 9639220Sgibbs test QOFF_CTLSTA, SCB_AVAIL jz poll_for_work_loop; 9739220Sgibbs } else { 9868087Sgibbs mov A, QINPOS; 9939220Sgibbs cmp KERNEL_QINPOS, A je poll_for_work_loop; 10039220Sgibbs } 10166647Sgibbs mov ARG_1, NEXT_QUEUED_SCB; 1024568Sgibbs 10363457Sgibbs /* 10463457Sgibbs * We have at least one queued SCB now and we don't have any 10566647Sgibbs * SCBs in the list of SCBs awaiting selection. Allocate a 10666647Sgibbs * card SCB for the host's SCB and get to work on it. 10763457Sgibbs */ 10839220Sgibbs if ((ahc->flags & AHC_PAGESCBS) != 0) { 10939220Sgibbs mov ALLZEROS call get_free_or_disc_scb; 11066647Sgibbs } else { 11139220Sgibbs /* In the non-paging case, the SCBID == hardware SCB index */ 11266647Sgibbs mov SCBPTR, ARG_1; 11339220Sgibbs } 11474094Sgibbs or SEQ_FLAGS2, SCB_DMA; 11595378SgibbsEND_CRITICAL; 11619164Sgibbsdma_queued_scb: 11763457Sgibbs /* 11863457Sgibbs * DMA the SCB from host ram into the current SCB location. 11963457Sgibbs */ 12023925Sgibbs mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET; 12166647Sgibbs mov ARG_1 call dma_scb; 12219164Sgibbs /* 12366647Sgibbs * Check one last time to see if this SCB was canceled 12466647Sgibbs * before we completed the DMA operation. If it was, 12566647Sgibbs * the QINFIFO next pointer will not match our saved 12666647Sgibbs * value. 12719164Sgibbs */ 12866647Sgibbs mov A, ARG_1; 12995378SgibbsBEGIN_CRITICAL; 13066647Sgibbs cmp NEXT_QUEUED_SCB, A jne abort_qinscb; 13168087Sgibbs if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 13268087Sgibbs cmp SCB_TAG, A je . + 2; 13368402Sgibbs mvi SCB_MISMATCH call set_seqint; 13468087Sgibbs } 13566647Sgibbs mov NEXT_QUEUED_SCB, SCB_NEXT; 13623925Sgibbs mov SCB_NEXT,WAITING_SCBH; 13723925Sgibbs mov WAITING_SCBH, SCBPTR; 13868402Sgibbs if ((ahc->features & AHC_QUEUE_REGS) != 0) { 13968402Sgibbs mov NONE, SNSCB_QOFF; 14068402Sgibbs } else { 14168402Sgibbs inc QINPOS; 14268402Sgibbs } 14374094Sgibbs and SEQ_FLAGS2, ~SCB_DMA; 14495378SgibbsEND_CRITICAL; 14523925Sgibbsstart_waiting: 14623925Sgibbs /* 14763457Sgibbs * Start the first entry on the waiting SCB list. 14823925Sgibbs */ 14923925Sgibbs mov SCBPTR, WAITING_SCBH; 15023925Sgibbs call start_selection; 1518104Sgibbs 15272811Sgibbspoll_for_selection: 15368579Sgibbs /* 15472811Sgibbs * Twin channel devices cannot handle things like SELTO 15572811Sgibbs * interrupts on the "background" channel. So, while 15672811Sgibbs * selecting, keep polling the current channel until 15772811Sgibbs * either a selection or reselection occurs. 15868579Sgibbs */ 15972811Sgibbs test SSTAT0, SELDO|SELDI jz poll_for_selection; 16039220Sgibbs 16139220Sgibbsselection: 16263457Sgibbs /* 16363457Sgibbs * We aren't expecting a bus free, so interrupt 16463457Sgibbs * the kernel driver if it happens. 16563457Sgibbs */ 16663457Sgibbs mvi CLRSINT1,CLRBUSFREE; 16776634Sgibbs if ((ahc->features & AHC_DT) == 0) { 16876634Sgibbs or SIMODE1, ENBUSFREE; 16976634Sgibbs } 17063457Sgibbs 17168579Sgibbs /* 17268579Sgibbs * Guard against a bus free after (re)selection 17368579Sgibbs * but prior to enabling the busfree interrupt. SELDI 17468579Sgibbs * and SELDO will be cleared in that case. 17568579Sgibbs */ 17671390Sgibbs test SSTAT0, SELDI|SELDO jz bus_free_sel; 17739220Sgibbs test SSTAT0,SELDO jnz select_out; 17839220Sgibbsselect_in: 17968087Sgibbs if ((ahc->flags & AHC_TARGETROLE) != 0) { 18068087Sgibbs if ((ahc->flags & AHC_INITIATORROLE) != 0) { 18141646Sgibbs test SSTAT0, TARGET jz initiator_reselect; 18241646Sgibbs } 18371390Sgibbs mvi CLRSINT0, CLRSELDI; 18442652Sgibbs 18539220Sgibbs /* 18639220Sgibbs * We've just been selected. Assert BSY and 18739220Sgibbs * setup the phase for receiving messages 18839220Sgibbs * from the target. 18939220Sgibbs */ 19039220Sgibbs mvi SCSISIGO, P_MESGOUT|BSYO; 19139220Sgibbs 19239220Sgibbs /* 19339220Sgibbs * Setup the DMA for sending the identify and 19441299Sgibbs * command information. 19539220Sgibbs */ 196109590Sgibbs mvi SEQ_FLAGS, CMDPHASE_PENDING; 19741299Sgibbs 19841299Sgibbs mov A, TQINPOS; 19939220Sgibbs if ((ahc->features & AHC_CMD_CHAN) != 0) { 20039220Sgibbs mvi DINDEX, CCHADDR; 20163457Sgibbs mvi SHARED_DATA_ADDR call set_32byte_addr; 20239220Sgibbs mvi CCSCBCTL, CCSCBRESET; 20339220Sgibbs } else { 20439220Sgibbs mvi DINDEX, HADDR; 20563457Sgibbs mvi SHARED_DATA_ADDR call set_32byte_addr; 20639220Sgibbs mvi DFCNTRL, FIFORESET; 20739220Sgibbs } 20839220Sgibbs 20939220Sgibbs /* Initiator that selected us */ 21063457Sgibbs and SAVED_SCSIID, SELID_MASK, SELID; 21163457Sgibbs /* The Target ID we were selected at */ 21263457Sgibbs if ((ahc->features & AHC_MULTI_TID) != 0) { 21363457Sgibbs and A, OID, TARGIDIN; 21463457Sgibbs } else if ((ahc->features & AHC_ULTRA2) != 0) { 21563457Sgibbs and A, OID, SCSIID_ULTRA2; 21639220Sgibbs } else { 21763457Sgibbs and A, OID, SCSIID; 21839220Sgibbs } 21963457Sgibbs or SAVED_SCSIID, A; 22063457Sgibbs if ((ahc->features & AHC_TWIN) != 0) { 22163457Sgibbs test SBLKCTL, SELBUSB jz . + 2; 22263457Sgibbs or SAVED_SCSIID, TWIN_CHNLB; 22363457Sgibbs } 22444507Sgibbs if ((ahc->features & AHC_CMD_CHAN) != 0) { 22563457Sgibbs mov CCSCBRAM, SAVED_SCSIID; 22639220Sgibbs } else { 22763457Sgibbs mov DFDAT, SAVED_SCSIID; 22839220Sgibbs } 22939220Sgibbs 23039220Sgibbs /* 23139220Sgibbs * If ATN isn't asserted, the target isn't interested 23239220Sgibbs * in talking to us. Go directly to bus free. 23363457Sgibbs * XXX SCSI-1 may require us to assume lun 0 if 23463457Sgibbs * ATN is false. 23539220Sgibbs */ 23639220Sgibbs test SCSISIGI, ATNI jz target_busfree; 23739220Sgibbs 23839220Sgibbs /* 23939220Sgibbs * Watch ATN closely now as we pull in messages from the 24039220Sgibbs * initiator. We follow the guidlines from section 6.5 24139220Sgibbs * of the SCSI-2 spec for what messages are allowed when. 24239220Sgibbs */ 24341646Sgibbs call target_inb; 24439220Sgibbs 24539220Sgibbs /* 24639220Sgibbs * Our first message must be one of IDENTIFY, ABORT, or 24739220Sgibbs * BUS_DEVICE_RESET. 24839220Sgibbs */ 24942652Sgibbs test DINDEX, MSG_IDENTIFYFLAG jz host_target_message_loop; 25039220Sgibbs /* Store for host */ 25139220Sgibbs if ((ahc->features & AHC_CMD_CHAN) != 0) { 25239220Sgibbs mov CCSCBRAM, DINDEX; 25339220Sgibbs } else { 25439220Sgibbs mov DFDAT, DINDEX; 25539220Sgibbs } 25695378Sgibbs and SAVED_LUN, MSG_IDENTIFY_LUNMASK, DINDEX; 25739220Sgibbs 25839220Sgibbs /* Remember for disconnection decision */ 25939220Sgibbs test DINDEX, MSG_IDENTIFY_DISCFLAG jnz . + 2; 26039220Sgibbs /* XXX Honor per target settings too */ 26139220Sgibbs or SEQ_FLAGS, NO_DISCONNECT; 26239220Sgibbs 26339220Sgibbs test SCSISIGI, ATNI jz ident_messages_done; 26441646Sgibbs call target_inb; 26539220Sgibbs /* 26639220Sgibbs * If this is a tagged request, the tagged message must 26739220Sgibbs * immediately follow the identify. We test for a valid 26839220Sgibbs * tag message by seeing if it is >= MSG_SIMPLE_Q_TAG and 26939220Sgibbs * < MSG_IGN_WIDE_RESIDUE. 27039220Sgibbs */ 27139220Sgibbs add A, -MSG_SIMPLE_Q_TAG, DINDEX; 27295378Sgibbs jnc ident_messages_done_msg_pending; 27339220Sgibbs add A, -MSG_IGN_WIDE_RESIDUE, DINDEX; 27495378Sgibbs jc ident_messages_done_msg_pending; 27595378Sgibbs 27639220Sgibbs /* Store for host */ 27739220Sgibbs if ((ahc->features & AHC_CMD_CHAN) != 0) { 27839220Sgibbs mov CCSCBRAM, DINDEX; 27939220Sgibbs } else { 28039220Sgibbs mov DFDAT, DINDEX; 28139220Sgibbs } 28239220Sgibbs 28339220Sgibbs /* 28439220Sgibbs * If the initiator doesn't feel like providing a tag number, 28539220Sgibbs * we've got a failed selection and must transition to bus 28639220Sgibbs * free. 28739220Sgibbs */ 28839220Sgibbs test SCSISIGI, ATNI jz target_busfree; 28942652Sgibbs 29039220Sgibbs /* 29139220Sgibbs * Store the tag for the host. 29239220Sgibbs */ 29341646Sgibbs call target_inb; 29439220Sgibbs if ((ahc->features & AHC_CMD_CHAN) != 0) { 29539220Sgibbs mov CCSCBRAM, DINDEX; 29639220Sgibbs } else { 29739220Sgibbs mov DFDAT, DINDEX; 29839220Sgibbs } 29942652Sgibbs mov INITIATOR_TAG, DINDEX; 30063457Sgibbs or SEQ_FLAGS, TARGET_CMD_IS_TAGGED; 30195378Sgibbs 30295378Sgibbsident_messages_done: 30395378Sgibbs /* Terminate the ident list */ 30495378Sgibbs if ((ahc->features & AHC_CMD_CHAN) != 0) { 30595378Sgibbs mvi CCSCBRAM, SCB_LIST_NULL; 30695378Sgibbs } else { 30795378Sgibbs mvi DFDAT, SCB_LIST_NULL; 30895378Sgibbs } 309109590Sgibbs or SEQ_FLAGS, TARG_CMD_PENDING; 31095378Sgibbs test SEQ_FLAGS2, TARGET_MSG_PENDING 31195378Sgibbs jnz target_mesgout_pending; 31295378Sgibbs test SCSISIGI, ATNI jnz target_mesgout_continue; 31395378Sgibbs jmp target_ITloop; 31495378Sgibbs 31595378Sgibbs 31695378Sgibbsident_messages_done_msg_pending: 31795378Sgibbs or SEQ_FLAGS2, TARGET_MSG_PENDING; 31839220Sgibbs jmp ident_messages_done; 31939220Sgibbs 32041646Sgibbs /* 32141646Sgibbs * Pushed message loop to allow the kernel to 32242652Sgibbs * run it's own target mode message state engine. 32341646Sgibbs */ 32441646Sgibbshost_target_message_loop: 32568402Sgibbs mvi HOST_MSG_LOOP call set_seqint; 32641646Sgibbs cmp RETURN_1, EXIT_MSG_LOOP je target_ITloop; 32741646Sgibbs test SSTAT0, SPIORDY jz .; 32841646Sgibbs jmp host_target_message_loop; 32939220Sgibbs } 33039220Sgibbs 33168087Sgibbsif ((ahc->flags & AHC_INITIATORROLE) != 0) { 33239220Sgibbs/* 33323925Sgibbs * Reselection has been initiated by a target. Make a note that we've been 33423925Sgibbs * reselected, but haven't seen an IDENTIFY message from the target yet. 33513177Sgibbs */ 33639220Sgibbsinitiator_reselect: 33723925Sgibbs /* XXX test for and handle ONE BIT condition */ 33871390Sgibbs or SXFRCTL0, SPIOEN|CLRSTCNT|CLRCHN; 33963457Sgibbs and SAVED_SCSIID, SELID_MASK, SELID; 34063457Sgibbs if ((ahc->features & AHC_ULTRA2) != 0) { 34163457Sgibbs and A, OID, SCSIID_ULTRA2; 34263457Sgibbs } else { 34363457Sgibbs and A, OID, SCSIID; 34463457Sgibbs } 34563457Sgibbs or SAVED_SCSIID, A; 34639545Sgibbs if ((ahc->features & AHC_TWIN) != 0) { 34739545Sgibbs test SBLKCTL, SELBUSB jz . + 2; 34863457Sgibbs or SAVED_SCSIID, TWIN_CHNLB; 34939545Sgibbs } 35071390Sgibbs mvi CLRSINT0, CLRSELDI; 35139220Sgibbs jmp ITloop; 35241646Sgibbs} 3534568Sgibbs 35472811Sgibbsabort_qinscb: 35572811Sgibbs call add_scb_to_free_list; 35672811Sgibbs jmp poll_for_work_loop; 35772811Sgibbs 35872811Sgibbsstart_selection: 35972811Sgibbs /* 36072811Sgibbs * If bus reset interrupts have been disabled (from a previous 36172811Sgibbs * reset), re-enable them now. Resets are only of interest 36272811Sgibbs * when we have outstanding transactions, so we can safely 36372811Sgibbs * defer re-enabling the interrupt until, as an initiator, 36472811Sgibbs * we start sending out transactions again. 36572811Sgibbs */ 36672811Sgibbs test SIMODE1, ENSCSIRST jnz . + 3; 36772811Sgibbs mvi CLRSINT1, CLRSCSIRSTI; 36872811Sgibbs or SIMODE1, ENSCSIRST; 36972811Sgibbs if ((ahc->features & AHC_TWIN) != 0) { 37072811Sgibbs and SINDEX,~SELBUSB,SBLKCTL;/* Clear channel select bit */ 37172811Sgibbs test SCB_SCSIID, TWIN_CHNLB jz . + 2; 37272811Sgibbs or SINDEX, SELBUSB; 37372811Sgibbs mov SBLKCTL,SINDEX; /* select channel */ 37472811Sgibbs } 37572811Sgibbsinitialize_scsiid: 37672811Sgibbs if ((ahc->features & AHC_ULTRA2) != 0) { 37772811Sgibbs mov SCSIID_ULTRA2, SCB_SCSIID; 37872811Sgibbs } else if ((ahc->features & AHC_TWIN) != 0) { 37972811Sgibbs and SCSIID, TWIN_TID|OID, SCB_SCSIID; 38072811Sgibbs } else { 38172811Sgibbs mov SCSIID, SCB_SCSIID; 38272811Sgibbs } 38372811Sgibbs if ((ahc->flags & AHC_TARGETROLE) != 0) { 38472811Sgibbs mov SINDEX, SCSISEQ_TEMPLATE; 38572811Sgibbs test SCB_CONTROL, TARGET_SCB jz . + 2; 38672811Sgibbs or SINDEX, TEMODE; 38772811Sgibbs mov SCSISEQ, SINDEX ret; 38872811Sgibbs } else { 38972811Sgibbs mov SCSISEQ, SCSISEQ_TEMPLATE ret; 39072811Sgibbs } 39172811Sgibbs 39213177Sgibbs/* 393102673Sgibbs * Initialize transfer settings with SCB provided settings. 39472811Sgibbs */ 39572811Sgibbsset_transfer_settings: 39672811Sgibbs if ((ahc->features & AHC_ULTRA) != 0) { 39772811Sgibbs test SCB_CONTROL, ULTRAENB jz . + 2; 39872811Sgibbs or SXFRCTL0, FAST20; 39972811Sgibbs } 40072811Sgibbs /* 40172811Sgibbs * Initialize SCSIRATE with the appropriate value for this target. 40272811Sgibbs */ 40372811Sgibbs if ((ahc->features & AHC_ULTRA2) != 0) { 40472811Sgibbs bmov SCSIRATE, SCB_SCSIRATE, 2 ret; 40572811Sgibbs } else { 40672811Sgibbs mov SCSIRATE, SCB_SCSIRATE ret; 40772811Sgibbs } 40872811Sgibbs 40972811Sgibbsif ((ahc->flags & AHC_TARGETROLE) != 0) { 41072811Sgibbs/* 41172811Sgibbs * We carefully toggle SPIOEN to allow us to return the 41272811Sgibbs * message byte we receive so it can be checked prior to 41372811Sgibbs * driving REQ on the bus for the next byte. 41472811Sgibbs */ 41572811Sgibbstarget_inb: 41672811Sgibbs /* 41772811Sgibbs * Drive REQ on the bus by enabling SCSI PIO. 41872811Sgibbs */ 41972811Sgibbs or SXFRCTL0, SPIOEN; 42072811Sgibbs /* Wait for the byte */ 42172811Sgibbs test SSTAT0, SPIORDY jz .; 42272811Sgibbs /* Prevent our read from triggering another REQ */ 42372811Sgibbs and SXFRCTL0, ~SPIOEN; 42472811Sgibbs /* Save latched contents */ 42572811Sgibbs mov DINDEX, SCSIDATL ret; 42672811Sgibbs} 42772811Sgibbs 42872811Sgibbs/* 42923925Sgibbs * After the selection, remove this SCB from the "waiting SCB" 43023925Sgibbs * list. This is achieved by simply moving our "next" pointer into 43123925Sgibbs * WAITING_SCBH. Our next pointer will be set to null the next time this 43223925Sgibbs * SCB is used, so don't bother with it now. 43323925Sgibbs */ 43439220Sgibbsselect_out: 43525005Sgibbs /* Turn off the selection hardware */ 43658258Sgibbs and SCSISEQ, TEMODE|ENSELI|ENRSELI|ENAUTOATNP, SCSISEQ; 43725005Sgibbs mov SCBPTR, WAITING_SCBH; 43824914Sgibbs mov WAITING_SCBH,SCB_NEXT; 43963457Sgibbs mov SAVED_SCSIID, SCB_SCSIID; 440115333Sgibbs and SAVED_LUN, LID, SCB_LUN; 441102673Sgibbs call set_transfer_settings; 44268087Sgibbs if ((ahc->flags & AHC_TARGETROLE) != 0) { 44339220Sgibbs test SSTAT0, TARGET jz initiator_select; 4448567Sdg 445102673Sgibbs or SXFRCTL0, CLRSTCNT|CLRCHN; 446102673Sgibbs 44739220Sgibbs /* 448102673Sgibbs * Put tag in connonical location since not 449102673Sgibbs * all connections have an SCB. 450102673Sgibbs */ 451102673Sgibbs mov INITIATOR_TAG, SCB_TARGET_ITAG; 452102673Sgibbs 453102673Sgibbs /* 45439220Sgibbs * We've just re-selected an initiator. 45539220Sgibbs * Assert BSY and setup the phase for 45639220Sgibbs * sending our identify messages. 45739220Sgibbs */ 45841646Sgibbs mvi P_MESGIN|BSYO call change_phase; 459102673Sgibbs mvi CLRSINT0, CLRSELDO; 4604568Sgibbs 46139220Sgibbs /* 46239220Sgibbs * Start out with a simple identify message. 46339220Sgibbs */ 464115333Sgibbs or SAVED_LUN, MSG_IDENTIFYFLAG call target_outb; 4656608Sgibbs 46639220Sgibbs /* 46739220Sgibbs * If we are the result of a tagged command, send 46839220Sgibbs * a simple Q tag and the tag id. 46939220Sgibbs */ 47039220Sgibbs test SCB_CONTROL, TAG_ENB jz . + 3; 47139220Sgibbs mvi MSG_SIMPLE_Q_TAG call target_outb; 47295378Sgibbs mov SCB_TARGET_ITAG call target_outb; 47339220Sgibbstarget_synccmd: 47439220Sgibbs /* 47539220Sgibbs * Now determine what phases the host wants us 47639220Sgibbs * to go through. 47739220Sgibbs */ 47895378Sgibbs mov SEQ_FLAGS, SCB_TARGET_PHASES; 47942652Sgibbs 48074972Sgibbs test SCB_CONTROL, MK_MESSAGE jz target_ITloop; 48174972Sgibbs mvi P_MESGIN|BSYO call change_phase; 48274972Sgibbs jmp host_target_message_loop; 48339220Sgibbstarget_ITloop: 48439220Sgibbs /* 48541646Sgibbs * Start honoring ATN signals now that 48644507Sgibbs * we properly identified ourselves. 48739220Sgibbs */ 48841646Sgibbs test SCSISIGI, ATNI jnz target_mesgout; 48939220Sgibbs test SEQ_FLAGS, CMDPHASE_PENDING jnz target_cmdphase; 49039220Sgibbs test SEQ_FLAGS, DPHASE_PENDING jnz target_dphase; 49139220Sgibbs test SEQ_FLAGS, SPHASE_PENDING jnz target_sphase; 49239220Sgibbs 49339220Sgibbs /* 49439220Sgibbs * No more work to do. Either disconnect or not depending 49539220Sgibbs * on the state of NO_DISCONNECT. 49639220Sgibbs */ 49739220Sgibbs test SEQ_FLAGS, NO_DISCONNECT jz target_disconnect; 498102673Sgibbs mvi TARG_IMMEDIATE_SCB, SCB_LIST_NULL; 49974972Sgibbs call complete_target_cmd; 50039220Sgibbs if ((ahc->flags & AHC_PAGESCBS) != 0) { 50139220Sgibbs mov ALLZEROS call get_free_or_disc_scb; 50239220Sgibbs } 503102673Sgibbs cmp TARG_IMMEDIATE_SCB, SCB_LIST_NULL je .; 50439220Sgibbs mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET; 505102673Sgibbs mov TARG_IMMEDIATE_SCB call dma_scb; 50695378Sgibbs call set_transfer_settings; 507102673Sgibbs or SXFRCTL0, CLRSTCNT|CLRCHN; 50839220Sgibbs jmp target_synccmd; 50939220Sgibbs 51041646Sgibbstarget_mesgout: 51141646Sgibbs mvi SCSISIGO, P_MESGOUT|BSYO; 51263457Sgibbstarget_mesgout_continue: 51341646Sgibbs call target_inb; 51463457Sgibbstarget_mesgout_pending: 515109590Sgibbs and SEQ_FLAGS2, ~TARGET_MSG_PENDING; 51641646Sgibbs /* Local Processing goes here... */ 51741646Sgibbs jmp host_target_message_loop; 51841646Sgibbs 51939220Sgibbstarget_disconnect: 52041646Sgibbs mvi P_MESGIN|BSYO call change_phase; 52141816Sgibbs test SEQ_FLAGS, DPHASE jz . + 2; 52241816Sgibbs mvi MSG_SAVEDATAPOINTER call target_outb; 52339220Sgibbs mvi MSG_DISCONNECT call target_outb; 52439220Sgibbs 52543880Sgibbstarget_busfree_wait: 52672640Sasmodai /* Wait for preceding I/O session to complete. */ 52743880Sgibbs test SCSISIGI, ACKI jnz .; 52839220Sgibbstarget_busfree: 52963457Sgibbs and SIMODE1, ~ENBUSFREE; 53068623Sgibbs if ((ahc->features & AHC_ULTRA2) != 0) { 53168623Sgibbs clr SCSIBUSL; 53268623Sgibbs } 53339220Sgibbs clr SCSISIGO; 53457099Sgibbs mvi LASTPHASE, P_BUSFREE; 53539220Sgibbs call complete_target_cmd; 53639220Sgibbs jmp poll_for_work; 53739220Sgibbs 53839220Sgibbstarget_cmdphase: 53995378Sgibbs /* 54095378Sgibbs * The target has dropped ATN (doesn't want to abort or BDR) 54195378Sgibbs * and we believe this selection to be valid. If the ring 54295378Sgibbs * buffer for new commands is full, return busy or queue full. 54395378Sgibbs */ 54495378Sgibbs if ((ahc->features & AHC_HS_MAILBOX) != 0) { 54595378Sgibbs and A, HOST_TQINPOS, HS_MAILBOX; 54695378Sgibbs } else { 54795378Sgibbs mov A, KERNEL_TQINPOS; 54895378Sgibbs } 54995378Sgibbs cmp TQINPOS, A jne tqinfifo_has_space; 55095378Sgibbs mvi P_STATUS|BSYO call change_phase; 55195378Sgibbs test SEQ_FLAGS, TARGET_CMD_IS_TAGGED jz . + 3; 55295378Sgibbs mvi STATUS_QUEUE_FULL call target_outb; 55395378Sgibbs jmp target_busfree_wait; 55495378Sgibbs mvi STATUS_BUSY call target_outb; 55595378Sgibbs jmp target_busfree_wait; 55695378Sgibbstqinfifo_has_space: 55741646Sgibbs mvi P_COMMAND|BSYO call change_phase; 55841646Sgibbs call target_inb; 55939220Sgibbs mov A, DINDEX; 56039220Sgibbs /* Store for host */ 56139220Sgibbs if ((ahc->features & AHC_CMD_CHAN) != 0) { 56239220Sgibbs mov CCSCBRAM, A; 56339220Sgibbs } else { 56439220Sgibbs mov DFDAT, A; 56539220Sgibbs } 56639220Sgibbs 56739220Sgibbs /* 56839220Sgibbs * Determine the number of bytes to read 56941299Sgibbs * based on the command group code via table lookup. 57041299Sgibbs * We reuse the first 8 bytes of the TARG_SCSIRATE 57141299Sgibbs * BIOS array for this table. Count is one less than 57241299Sgibbs * the total for the command since we've already fetched 57341299Sgibbs * the first byte. 57439220Sgibbs */ 57539220Sgibbs shr A, CMD_GROUP_CODE_SHIFT; 57668087Sgibbs add SINDEX, CMDSIZE_TABLE, A; 57739220Sgibbs mov A, SINDIR; 57839220Sgibbs 57939220Sgibbs test A, 0xFF jz command_phase_done; 58071390Sgibbs or SXFRCTL0, SPIOEN; 58139220Sgibbscommand_loop: 58239220Sgibbs test SSTAT0, SPIORDY jz .; 58339220Sgibbs cmp A, 1 jne . + 2; 58439220Sgibbs and SXFRCTL0, ~SPIOEN; /* Last Byte */ 58539220Sgibbs if ((ahc->features & AHC_CMD_CHAN) != 0) { 58639220Sgibbs mov CCSCBRAM, SCSIDATL; 58739220Sgibbs } else { 58839220Sgibbs mov DFDAT, SCSIDATL; 58939220Sgibbs } 59039220Sgibbs dec A; 59139220Sgibbs test A, 0xFF jnz command_loop; 59239220Sgibbs 59339220Sgibbscommand_phase_done: 59439220Sgibbs and SEQ_FLAGS, ~CMDPHASE_PENDING; 59539220Sgibbs jmp target_ITloop; 59639220Sgibbs 59739220Sgibbstarget_dphase: 59839220Sgibbs /* 59963457Sgibbs * Data phases on the bus are from the 60063457Sgibbs * perspective of the initiator. The dma 60163457Sgibbs * code looks at LASTPHASE to determine the 60263457Sgibbs * data direction of the DMA. Toggle it for 60363457Sgibbs * target transfers. 60439220Sgibbs */ 60595378Sgibbs xor LASTPHASE, IOI, SCB_TARGET_DATA_DIR; 60695378Sgibbs or SCB_TARGET_DATA_DIR, BSYO call change_phase; 60739220Sgibbs jmp p_data; 60839220Sgibbs 60939220Sgibbstarget_sphase: 61041646Sgibbs mvi P_STATUS|BSYO call change_phase; 61141646Sgibbs mvi LASTPHASE, P_STATUS; 61295378Sgibbs mov SCB_SCSI_STATUS call target_outb; 61341646Sgibbs /* XXX Watch for ATN or parity errors??? */ 61439220Sgibbs mvi SCSISIGO, P_MESGIN|BSYO; 61539220Sgibbs /* MSG_CMDCMPLT is 0, but we can't do an immediate of 0 */ 61639220Sgibbs mov ALLZEROS call target_outb; 61743880Sgibbs jmp target_busfree_wait; 61839220Sgibbs 61939220Sgibbscomplete_target_cmd: 62039220Sgibbs test SEQ_FLAGS, TARG_CMD_PENDING jnz . + 2; 62139220Sgibbs mov SCB_TAG jmp complete_post; 62239220Sgibbs if ((ahc->features & AHC_CMD_CHAN) != 0) { 62341299Sgibbs /* Set the valid byte */ 62441299Sgibbs mvi CCSCBADDR, 24; 62541299Sgibbs mov CCSCBRAM, ALLONES; 62641299Sgibbs mvi CCHCNT, 28; 62739220Sgibbs or CCSCBCTL, CCSCBEN|CCSCBRESET; 62839220Sgibbs test CCSCBCTL, CCSCBDONE jz .; 62939220Sgibbs clr CCSCBCTL; 63039220Sgibbs } else { 63141299Sgibbs /* Set the valid byte */ 63241299Sgibbs or DFCNTRL, FIFORESET; 63341299Sgibbs mvi DFWADDR, 3; /* Third 64bit word or byte 24 */ 63441299Sgibbs mov DFDAT, ALLONES; 63563457Sgibbs mvi 28 call set_hcnt; 63639220Sgibbs or DFCNTRL, HDMAEN|FIFOFLUSH; 63739220Sgibbs call dma_finish; 63839220Sgibbs } 63941299Sgibbs inc TQINPOS; 64041299Sgibbs mvi INTSTAT,CMDCMPLT ret; 64139220Sgibbs } 64241646Sgibbs 64368087Sgibbsif ((ahc->flags & AHC_INITIATORROLE) != 0) { 64439220Sgibbsinitiator_select: 645102673Sgibbs or SXFRCTL0, SPIOEN|CLRSTCNT|CLRCHN; 64641646Sgibbs /* 64741646Sgibbs * As soon as we get a successful selection, the target 64841646Sgibbs * should go into the message out phase since we have ATN 64941646Sgibbs * asserted. 65041646Sgibbs */ 65139220Sgibbs mvi MSG_OUT, MSG_IDENTIFYFLAG; 652107420Sscottl mvi SEQ_FLAGS, NO_CDB_SENT; 653102673Sgibbs mvi CLRSINT0, CLRSELDO; 65413177Sgibbs 65541646Sgibbs /* 65641646Sgibbs * Main loop for information transfer phases. Wait for the 65741646Sgibbs * target to assert REQ before checking MSG, C/D and I/O for 65841646Sgibbs * the bus phase. 65941646Sgibbs */ 66063457Sgibbsmesgin_phasemis: 6614568SgibbsITloop: 66239220Sgibbs call phase_lock; 6634568Sgibbs 66439220Sgibbs mov A, LASTPHASE; 6654568Sgibbs 66639220Sgibbs test A, ~P_DATAIN jz p_data; 66723925Sgibbs cmp A,P_COMMAND je p_command; 66823925Sgibbs cmp A,P_MESGOUT je p_mesgout; 66923925Sgibbs cmp A,P_STATUS je p_status; 67023925Sgibbs cmp A,P_MESGIN je p_mesgin; 6714568Sgibbs 67268402Sgibbs mvi BAD_PHASE call set_seqint; 67323925Sgibbs jmp ITloop; /* Try reading the bus again. */ 6744568Sgibbs 67523925Sgibbsawait_busfree: 67623925Sgibbs and SIMODE1, ~ENBUSFREE; 67723925Sgibbs mov NONE, SCSIDATL; /* Ack the last byte */ 67868623Sgibbs if ((ahc->features & AHC_ULTRA2) != 0) { 67968623Sgibbs clr SCSIBUSL; /* Prevent bit leakage durint SELTO */ 68068623Sgibbs } 68139220Sgibbs and SXFRCTL0, ~SPIOEN; 682123579Sgibbs mvi SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT; 68323925Sgibbs test SSTAT1,REQINIT|BUSFREE jz .; 68423925Sgibbs test SSTAT1, BUSFREE jnz poll_for_work; 68568579Sgibbs mvi MISSED_BUSFREE call set_seqint; 68641646Sgibbs} 68723925Sgibbs 68823925Sgibbsclear_target_state: 68941646Sgibbs /* 69041646Sgibbs * We assume that the kernel driver may reset us 69141646Sgibbs * at any time, even in the middle of a DMA, so 69241646Sgibbs * clear DFCNTRL too. 69341646Sgibbs */ 69441646Sgibbs clr DFCNTRL; 69568087Sgibbs or SXFRCTL0, CLRSTCNT|CLRCHN; 69641646Sgibbs 69741646Sgibbs /* 69841646Sgibbs * We don't know the target we will connect to, 69941646Sgibbs * so default to narrow transfers to avoid 70041646Sgibbs * parity problems. 70141646Sgibbs */ 70241646Sgibbs if ((ahc->features & AHC_ULTRA2) != 0) { 70341646Sgibbs bmov SCSIRATE, ALLZEROS, 2; 70441646Sgibbs } else { 70541646Sgibbs clr SCSIRATE; 70663457Sgibbs if ((ahc->features & AHC_ULTRA) != 0) { 70763457Sgibbs and SXFRCTL0, ~(FAST20); 70863457Sgibbs } 70941646Sgibbs } 71023925Sgibbs mvi LASTPHASE, P_BUSFREE; 71123925Sgibbs /* clear target specific flags */ 712107420Sscottl mvi SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT ret; 71323925Sgibbs 71463457Sgibbssg_advance: 71563457Sgibbs clr A; /* add sizeof(struct scatter) */ 71663457Sgibbs add SCB_RESIDUAL_SGPTR[0],SG_SIZEOF; 71763457Sgibbs adc SCB_RESIDUAL_SGPTR[1],A; 71863457Sgibbs adc SCB_RESIDUAL_SGPTR[2],A; 71963457Sgibbs adc SCB_RESIDUAL_SGPTR[3],A ret; 72063457Sgibbs 72174094Sgibbsif ((ahc->features & AHC_CMD_CHAN) != 0) { 72274094Sgibbsdisable_ccsgen: 72374094Sgibbs test CCSGCTL, CCSGEN jz return; 72474094Sgibbs test CCSGCTL, CCSGDONE jz .; 72574094Sgibbsdisable_ccsgen_fetch_done: 72674094Sgibbs clr CCSGCTL; 72774094Sgibbs test CCSGCTL, CCSGEN jnz .; 72874094Sgibbs ret; 72963457Sgibbsidle_loop: 73076634Sgibbs /* 73176634Sgibbs * Do we need any more segments for this transfer? 73276634Sgibbs */ 73376634Sgibbs test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jnz return; 73476634Sgibbs 73574094Sgibbs /* Did we just finish fetching segs? */ 73674094Sgibbs cmp CCSGCTL, CCSGEN|CCSGDONE je idle_sgfetch_complete; 73763457Sgibbs 73874094Sgibbs /* Are we actively fetching segments? */ 73974094Sgibbs test CCSGCTL, CCSGEN jnz return; 74063457Sgibbs 74174094Sgibbs /* 74274094Sgibbs * Do we have any prefetch left??? 74374094Sgibbs */ 74474094Sgibbs cmp CCSGADDR, SG_PREFETCH_CNT jne idle_sg_avail; 74563457Sgibbs 74674094Sgibbs /* 74774094Sgibbs * Need to fetch segments, but we can only do that 74874094Sgibbs * if the command channel is completely idle. Make 74974094Sgibbs * sure we don't have an SCB prefetch going on. 75074094Sgibbs */ 75174094Sgibbs test CCSCBCTL, CCSCBEN jnz return; 75263457Sgibbs 75374094Sgibbs /* 75474094Sgibbs * We fetch a "cacheline aligned" and sized amount of data 75574094Sgibbs * so we don't end up referencing a non-existant page. 75674094Sgibbs * Cacheline aligned is in quotes because the kernel will 75774094Sgibbs * set the prefetch amount to a reasonable level if the 75874094Sgibbs * cacheline size is unknown. 75974094Sgibbs */ 76074094Sgibbs mvi CCHCNT, SG_PREFETCH_CNT; 76174094Sgibbs and CCHADDR[0], SG_PREFETCH_ALIGN_MASK, SCB_RESIDUAL_SGPTR; 76274094Sgibbs bmov CCHADDR[1], SCB_RESIDUAL_SGPTR[1], 3; 76374094Sgibbs mvi CCSGCTL, CCSGEN|CCSGRESET ret; 76463457Sgibbsidle_sgfetch_complete: 76574094Sgibbs call disable_ccsgen_fetch_done; 76674094Sgibbs and CCSGADDR, SG_PREFETCH_ADDR_MASK, SCB_RESIDUAL_SGPTR; 76763457Sgibbsidle_sg_avail: 76874094Sgibbs if ((ahc->features & AHC_ULTRA2) != 0) { 76974094Sgibbs /* Does the hardware have space for another SG entry? */ 77074094Sgibbs test DFSTATUS, PRELOAD_AVAIL jz return; 77179874Sgibbs bmov HADDR, CCSGRAM, 7; 77274094Sgibbs bmov SCB_RESIDUAL_DATACNT[3], CCSGRAM, 1; 77379874Sgibbs if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 77479874Sgibbs mov SCB_RESIDUAL_DATACNT[3] call set_hhaddr; 77579874Sgibbs } 77674094Sgibbs call sg_advance; 77774094Sgibbs mov SINDEX, SCB_RESIDUAL_SGPTR[0]; 77874094Sgibbs test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 2; 77974094Sgibbs or SINDEX, LAST_SEG; 78074094Sgibbs mov SG_CACHE_PRE, SINDEX; 78174507Sgibbs /* Load the segment */ 78274507Sgibbs or DFCNTRL, PRELOADEN; 78363457Sgibbs } 78474094Sgibbs ret; 78574094Sgibbs} 78663457Sgibbs 78765942Sgibbsif ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0) { 78813177Sgibbs/* 78965942Sgibbs * Calculate the trailing portion of this S/G segment that cannot 79065942Sgibbs * be transferred using memory write and invalidate PCI transactions. 79165942Sgibbs * XXX Can we optimize this for PCI writes only??? 79265942Sgibbs */ 79365942Sgibbscalc_mwi_residual: 79465942Sgibbs /* 79565942Sgibbs * If the ending address is on a cacheline boundary, 79665942Sgibbs * there is no need for an extra segment. 79765942Sgibbs */ 79865942Sgibbs mov A, HCNT[0]; 79965942Sgibbs add A, A, HADDR[0]; 80065942Sgibbs and A, CACHESIZE_MASK; 80165942Sgibbs test A, 0xFF jz return; 80265942Sgibbs 80365942Sgibbs /* 80465942Sgibbs * If the transfer is less than a cachline, 80565942Sgibbs * there is no need for an extra segment. 80665942Sgibbs */ 80765942Sgibbs test HCNT[1], 0xFF jnz calc_mwi_residual_final; 80865942Sgibbs test HCNT[2], 0xFF jnz calc_mwi_residual_final; 80965942Sgibbs add NONE, INVERTED_CACHESIZE_MASK, HCNT[0]; 81065942Sgibbs jnc return; 81165942Sgibbs 81265942Sgibbscalc_mwi_residual_final: 81365942Sgibbs mov MWI_RESIDUAL, A; 81465942Sgibbs not A; 81565942Sgibbs inc A; 81665942Sgibbs add HCNT[0], A; 81765942Sgibbs adc HCNT[1], -1; 81865942Sgibbs adc HCNT[2], -1 ret; 81965942Sgibbs} 82065942Sgibbs 82139220Sgibbsp_data: 822107420Sscottl test SEQ_FLAGS,NOT_IDENTIFIED|NO_CDB_SENT jz p_data_allowed; 823107420Sscottl mvi PROTO_VIOLATION call set_seqint; 824107420Sscottlp_data_allowed: 82539220Sgibbs if ((ahc->features & AHC_ULTRA2) != 0) { 82639220Sgibbs mvi DMAPARAMS, PRELOADEN|SCSIEN|HDMAEN; 82739220Sgibbs } else { 82839220Sgibbs mvi DMAPARAMS, WIDEODD|SCSIEN|SDMAEN|HDMAEN|FIFORESET; 82939220Sgibbs } 83039220Sgibbs test LASTPHASE, IOI jnz . + 2; 83139220Sgibbs or DMAPARAMS, DIRECTION; 83239220Sgibbs if ((ahc->features & AHC_CMD_CHAN) != 0) { 83363457Sgibbs /* We don't have any valid S/G elements */ 83466647Sgibbs mvi CCSGADDR, SG_PREFETCH_CNT; 83539220Sgibbs } 83679874Sgibbs test SEQ_FLAGS, DPHASE jz data_phase_initialize; 8374568Sgibbs 83879874Sgibbs /* 83979874Sgibbs * If we re-enter the data phase after going through another 84079874Sgibbs * phase, our transfer location has almost certainly been 84179874Sgibbs * corrupted by the interveining, non-data, transfers. Ask 84279874Sgibbs * the host driver to fix us up based on the transfer residual. 84379874Sgibbs */ 84479874Sgibbs mvi PDATA_REINIT call set_seqint; 84579874Sgibbs jmp data_phase_loop; 84679874Sgibbs 84779874Sgibbsdata_phase_initialize: 84879874Sgibbs /* We have seen a data phase for the first time */ 84939220Sgibbs or SEQ_FLAGS, DPHASE; 85039220Sgibbs 85119164Sgibbs /* 85219164Sgibbs * Initialize the DMA address and counter from the SCB. 85363457Sgibbs * Also set SCB_RESIDUAL_SGPTR, including the LAST_SEG 85463457Sgibbs * flag in the highest byte of the data count. We cannot 85563457Sgibbs * modify the saved values in the SCB until we see a save 85663457Sgibbs * data pointers message. 85719164Sgibbs */ 85879874Sgibbs if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 85979874Sgibbs /* The lowest address byte must be loaded last. */ 86079874Sgibbs mov SCB_DATACNT[3] call set_hhaddr; 86179874Sgibbs } 86239220Sgibbs if ((ahc->features & AHC_CMD_CHAN) != 0) { 86339220Sgibbs bmov HADDR, SCB_DATAPTR, 7; 86463457Sgibbs bmov SCB_RESIDUAL_DATACNT[3], SCB_DATACNT[3], 5; 86539220Sgibbs } else { 86639220Sgibbs mvi DINDEX, HADDR; 86739220Sgibbs mvi SCB_DATAPTR call bcopy_7; 86863457Sgibbs mvi DINDEX, SCB_RESIDUAL_DATACNT + 3; 86963457Sgibbs mvi SCB_DATACNT + 3 call bcopy_5; 87039220Sgibbs } 87165942Sgibbs if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0) { 87265942Sgibbs call calc_mwi_residual; 87365942Sgibbs } 87463457Sgibbs and SCB_RESIDUAL_SGPTR[0], ~SG_FULL_RESID; 87519164Sgibbs 87639220Sgibbs if ((ahc->features & AHC_ULTRA2) == 0) { 87739220Sgibbs if ((ahc->features & AHC_CMD_CHAN) != 0) { 87839220Sgibbs bmov STCNT, HCNT, 3; 87939220Sgibbs } else { 88039220Sgibbs call set_stcnt_from_hcnt; 88139220Sgibbs } 88239220Sgibbs } 88319164Sgibbs 88463457Sgibbsdata_phase_loop: 88563457Sgibbs /* Guard against overruns */ 88663457Sgibbs test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz data_phase_inbounds; 88719164Sgibbs 88863457Sgibbs /* 88968087Sgibbs * Turn on `Bit Bucket' mode, wait until the target takes 89068087Sgibbs * us to another phase, and then notify the host. 89163457Sgibbs */ 89268087Sgibbs and DMAPARAMS, DIRECTION; 89368087Sgibbs mov DFCNTRL, DMAPARAMS; 89423925Sgibbs or SXFRCTL1,BITBUCKET; 89576634Sgibbs if ((ahc->features & AHC_DT) == 0) { 89676634Sgibbs test SSTAT1,PHASEMIS jz .; 89776634Sgibbs } else { 89876634Sgibbs test SCSIPHASE, DATA_PHASE_MASK jnz .; 89976634Sgibbs } 90068087Sgibbs and SXFRCTL1, ~BITBUCKET; 90168402Sgibbs mvi DATA_OVERRUN call set_seqint; 90268087Sgibbs jmp ITloop; 90368087Sgibbs 90416260Sgibbsdata_phase_inbounds: 90539220Sgibbs if ((ahc->features & AHC_ULTRA2) != 0) { 90663457Sgibbs mov SINDEX, SCB_RESIDUAL_SGPTR[0]; 90763457Sgibbs test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 2; 90863457Sgibbs or SINDEX, LAST_SEG; 90963457Sgibbs mov SG_CACHE_PRE, SINDEX; 91063457Sgibbs mov DFCNTRL, DMAPARAMS; 91163457Sgibbsultra2_dma_loop: 91263457Sgibbs call idle_loop; 91363457Sgibbs /* 91463457Sgibbs * The transfer is complete if either the last segment 91563457Sgibbs * completes or the target changes phase. 91663457Sgibbs */ 91763457Sgibbs test SG_CACHE_SHADOW, LAST_SEG_DONE jnz ultra2_dmafinish; 91876634Sgibbs if ((ahc->features & AHC_DT) == 0) { 91976634Sgibbs if ((ahc->flags & AHC_TARGETROLE) != 0) { 92076634Sgibbs /* 92176634Sgibbs * As a target, we control the phases, 92276634Sgibbs * so ignore PHASEMIS. 92376634Sgibbs */ 92476634Sgibbs test SSTAT0, TARGET jnz ultra2_dma_loop; 92576634Sgibbs } 92676634Sgibbs if ((ahc->flags & AHC_INITIATORROLE) != 0) { 92776634Sgibbs test SSTAT1,PHASEMIS jz ultra2_dma_loop; 92876634Sgibbs } 92976634Sgibbs } else { 93076634Sgibbs test DFCNTRL, SCSIEN jnz ultra2_dma_loop; 93170204Sgibbs } 93263457Sgibbs 93363457Sgibbsultra2_dmafinish: 93476634Sgibbs /* 93576634Sgibbs * The transfer has terminated either due to a phase 93676634Sgibbs * change, and/or the completion of the last segment. 93776634Sgibbs * We have two goals here. Do as much other work 93876634Sgibbs * as possible while the data fifo drains on a read 93976634Sgibbs * and respond as quickly as possible to the standard 94076634Sgibbs * messages (save data pointers/disconnect and command 94176634Sgibbs * complete) that usually follow a data phase. 94276634Sgibbs */ 94363457Sgibbs if ((ahc->bugs & AHC_AUTOFLUSH_BUG) != 0) { 94463457Sgibbs /* 94576634Sgibbs * On chips with broken auto-flush, start 94676634Sgibbs * the flushing process now. We'll poke 94776634Sgibbs * the chip from time to time to keep the 94876634Sgibbs * flush process going as we complete the 94976634Sgibbs * data phase. 95063457Sgibbs */ 95163457Sgibbs or DFCNTRL, FIFOFLUSH; 95263457Sgibbs } 95363457Sgibbs /* 95476634Sgibbs * We assume that, even though data may still be 95576634Sgibbs * transferring to the host, that the SCSI side of 95676634Sgibbs * the DMA engine is now in a static state. This 95776634Sgibbs * allows us to update our notion of where we are 95876634Sgibbs * in this transfer. 95976634Sgibbs * 96063944Sgibbs * If, by chance, we stopped before being able 96163944Sgibbs * to fetch additional segments for this transfer, 96263944Sgibbs * yet the last S/G was completely exhausted, 96363944Sgibbs * call our idle loop until it is able to load 96463944Sgibbs * another segment. This will allow us to immediately 96563944Sgibbs * pickup on the next segment on the next data phase. 96663944Sgibbs * 96763944Sgibbs * If we happened to stop on the last segment, then 96863944Sgibbs * our residual information is still correct from 96963944Sgibbs * the idle loop and there is no need to perform 97076634Sgibbs * any fixups. 97163944Sgibbs */ 97263944Sgibbsultra2_ensure_sg: 97363944Sgibbs test SG_CACHE_SHADOW, LAST_SEG jz ultra2_shvalid; 97463944Sgibbs /* Record if we've consumed all S/G entries */ 97595378Sgibbs test SSTAT2, SHVALID jnz residuals_correct; 97663944Sgibbs or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL; 97776634Sgibbs jmp residuals_correct; 97863944Sgibbs 97963944Sgibbsultra2_shvalid: 98095378Sgibbs test SSTAT2, SHVALID jnz sgptr_fixup; 98163944Sgibbs call idle_loop; 98263944Sgibbs jmp ultra2_ensure_sg; 98363944Sgibbs 98463944Sgibbssgptr_fixup: 98563944Sgibbs /* 98663457Sgibbs * Fixup the residual next S/G pointer. The S/G preload 98763457Sgibbs * feature of the chip allows us to load two elements 98863457Sgibbs * in addition to the currently active element. We 98963457Sgibbs * store the bottom byte of the next S/G pointer in 99063457Sgibbs * the SG_CACEPTR register so we can restore the 99163457Sgibbs * correct value when the DMA completes. If the next 99263457Sgibbs * sg ptr value has advanced to the point where higher 99363457Sgibbs * bytes in the address have been affected, fix them 99463457Sgibbs * too. 99563457Sgibbs */ 99663457Sgibbs test SG_CACHE_SHADOW, 0x80 jz sgptr_fixup_done; 99763457Sgibbs test SCB_RESIDUAL_SGPTR[0], 0x80 jnz sgptr_fixup_done; 99863457Sgibbs add SCB_RESIDUAL_SGPTR[1], -1; 99963457Sgibbs adc SCB_RESIDUAL_SGPTR[2], -1; 100063457Sgibbs adc SCB_RESIDUAL_SGPTR[3], -1; 100163457Sgibbssgptr_fixup_done: 100263457Sgibbs and SCB_RESIDUAL_SGPTR[0], SG_ADDR_MASK, SG_CACHE_SHADOW; 1003115333Sgibbs /* We are not the last seg */ 1004115333Sgibbs and SCB_RESIDUAL_DATACNT[3], ~SG_LAST_SEG; 100576634Sgibbsresiduals_correct: 100676634Sgibbs /* 100776634Sgibbs * Go ahead and shut down the DMA engine now. 100876634Sgibbs * In the future, we'll want to handle end of 100976634Sgibbs * transfer messages prior to doing this, but this 101076634Sgibbs * requires similar restructuring for pre-ULTRA2 101176634Sgibbs * controllers. 101276634Sgibbs */ 101376634Sgibbs test DMAPARAMS, DIRECTION jnz ultra2_fifoempty; 101476634Sgibbsultra2_fifoflush: 101576634Sgibbs if ((ahc->features & AHC_DT) == 0) { 101676634Sgibbs if ((ahc->bugs & AHC_AUTOFLUSH_BUG) != 0) { 101776634Sgibbs /* 101876634Sgibbs * On Rev A of the aic7890, the autoflush 101976634Sgibbs * feature doesn't function correctly. 102076634Sgibbs * Perform an explicit manual flush. During 102176634Sgibbs * a manual flush, the FIFOEMP bit becomes 102276634Sgibbs * true every time the PCI FIFO empties 102376634Sgibbs * regardless of the state of the SCSI FIFO. 102476634Sgibbs * It can take up to 4 clock cycles for the 102576634Sgibbs * SCSI FIFO to get data into the PCI FIFO 102676634Sgibbs * and for FIFOEMP to de-assert. Here we 102776634Sgibbs * guard against this condition by making 102876634Sgibbs * sure the FIFOEMP bit stays on for 5 full 102976634Sgibbs * clock cycles. 103076634Sgibbs */ 103176634Sgibbs or DFCNTRL, FIFOFLUSH; 103276634Sgibbs test DFSTATUS, FIFOEMP jz ultra2_fifoflush; 103376634Sgibbs test DFSTATUS, FIFOEMP jz ultra2_fifoflush; 103476634Sgibbs test DFSTATUS, FIFOEMP jz ultra2_fifoflush; 103576634Sgibbs test DFSTATUS, FIFOEMP jz ultra2_fifoflush; 103676634Sgibbs } 103776634Sgibbs test DFSTATUS, FIFOEMP jz ultra2_fifoflush; 103876634Sgibbs } else { 103976634Sgibbs /* 104076634Sgibbs * We enable the auto-ack feature on DT capable 104176634Sgibbs * controllers. This means that the controller may 104276634Sgibbs * have already transferred some overrun bytes into 104376634Sgibbs * the data FIFO and acked them on the bus. The only 104476634Sgibbs * way to detect this situation is to wait for 104576634Sgibbs * LAST_SEG_DONE to come true on a completed transfer 104676634Sgibbs * and then test to see if the data FIFO is non-empty. 104776634Sgibbs */ 1048115334Sgibbs test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL 1049115334Sgibbs jz ultra2_wait_fifoemp; 105076634Sgibbs test SG_CACHE_SHADOW, LAST_SEG_DONE jz .; 1051115334Sgibbs /* 1052115334Sgibbs * FIFOEMP can lag LAST_SEG_DONE. Wait a few 1053115334Sgibbs * clocks before calling this an overrun. 1054115334Sgibbs */ 105576634Sgibbs test DFSTATUS, FIFOEMP jnz ultra2_fifoempty; 1056115334Sgibbs test DFSTATUS, FIFOEMP jnz ultra2_fifoempty; 1057115334Sgibbs test DFSTATUS, FIFOEMP jnz ultra2_fifoempty; 105876634Sgibbs /* Overrun */ 105976634Sgibbs jmp data_phase_loop; 1060115334Sgibbsultra2_wait_fifoemp: 106176634Sgibbs test DFSTATUS, FIFOEMP jz .; 106276634Sgibbs } 106376634Sgibbsultra2_fifoempty: 106476634Sgibbs /* Don't clobber an inprogress host data transfer */ 106576634Sgibbs test DFSTATUS, MREQPEND jnz ultra2_fifoempty; 106676634Sgibbsultra2_dmahalt: 106776634Sgibbs and DFCNTRL, ~(SCSIEN|HDMAEN); 106876634Sgibbs test DFCNTRL, SCSIEN|HDMAEN jnz .; 106979874Sgibbs if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 107079874Sgibbs /* 107179874Sgibbs * Keep HHADDR cleared for future, 32bit addressed 107279874Sgibbs * only, DMA operations. 107379874Sgibbs * 107479874Sgibbs * Due to bayonette style S/G handling, our residual 107579874Sgibbs * data must be "fixed up" once the transfer is halted. 107679874Sgibbs * Here we fixup the HSHADDR stored in the high byte 107779874Sgibbs * of the residual data cnt. By postponing the fixup, 107879874Sgibbs * we can batch the clearing of HADDR with the fixup. 107979874Sgibbs * If we halted on the last segment, the residual is 108079874Sgibbs * already correct. If we are not on the last 108179874Sgibbs * segment, copy the high address directly from HSHADDR. 108279874Sgibbs * We don't need to worry about maintaining the 108379874Sgibbs * SG_LAST_SEG flag as it will always be false in the 108479874Sgibbs * case where an update is required. 108579874Sgibbs */ 108679874Sgibbs or DSCOMMAND1, HADDLDSEL0; 108779874Sgibbs test SG_CACHE_SHADOW, LAST_SEG jnz . + 2; 108879874Sgibbs mov SCB_RESIDUAL_DATACNT[3], SHADDR; 108979874Sgibbs clr HADDR; 109079874Sgibbs and DSCOMMAND1, ~HADDLDSEL0; 109179874Sgibbs } 109239220Sgibbs } else { 109363457Sgibbs /* If we are the last SG block, tell the hardware. */ 109465942Sgibbs if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 109565942Sgibbs && ahc->pci_cachesize != 0) { 109665942Sgibbs test MWI_RESIDUAL, 0xFF jnz dma_mid_sg; 109765942Sgibbs } 109863457Sgibbs test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz dma_mid_sg; 109968087Sgibbs if ((ahc->flags & AHC_TARGETROLE) != 0) { 110063944Sgibbs test SSTAT0, TARGET jz dma_last_sg; 1101123579Sgibbs if ((ahc->bugs & AHC_TMODE_WIDEODD_BUG) != 0) { 110263944Sgibbs test DMAPARAMS, DIRECTION jz dma_mid_sg; 110363944Sgibbs } 110457099Sgibbs } 110563944Sgibbsdma_last_sg: 110639220Sgibbs and DMAPARAMS, ~WIDEODD; 110763457Sgibbsdma_mid_sg: 110863457Sgibbs /* Start DMA data transfer. */ 110939220Sgibbs mov DFCNTRL, DMAPARAMS; 111063457Sgibbsdma_loop: 111163457Sgibbs if ((ahc->features & AHC_CMD_CHAN) != 0) { 111263457Sgibbs call idle_loop; 111363457Sgibbs } 111463457Sgibbs test SSTAT0,DMADONE jnz dma_dmadone; 111563457Sgibbs test SSTAT1,PHASEMIS jz dma_loop; /* ie. underrun */ 111663457Sgibbsdma_phasemis: 111739220Sgibbs /* 111863457Sgibbs * We will be "done" DMAing when the transfer count goes to 111963457Sgibbs * zero, or the target changes the phase (in light of this, 112063457Sgibbs * it makes sense that the DMA circuitry doesn't ACK when 112163457Sgibbs * PHASEMIS is active). If we are doing a SCSI->Host transfer, 112263457Sgibbs * the data FIFO should be flushed auto-magically on STCNT=0 112363457Sgibbs * or a phase change, so just wait for FIFO empty status. 112439220Sgibbs */ 112563457Sgibbsdma_checkfifo: 112663457Sgibbs test DFCNTRL,DIRECTION jnz dma_fifoempty; 112763457Sgibbsdma_fifoflush: 112863457Sgibbs test DFSTATUS,FIFOEMP jz dma_fifoflush; 112963457Sgibbsdma_fifoempty: 113063457Sgibbs /* Don't clobber an inprogress host data transfer */ 113163457Sgibbs test DFSTATUS, MREQPEND jnz dma_fifoempty; 11324568Sgibbs 113339220Sgibbs /* 113463457Sgibbs * Now shut off the DMA and make sure that the DMA 113563457Sgibbs * hardware has actually stopped. Touching the DMA 113663457Sgibbs * counters, etc. while a DMA is active will result 113763457Sgibbs * in an ILLSADDR exception. 113839220Sgibbs */ 113963457Sgibbsdma_dmadone: 114063457Sgibbs and DFCNTRL, ~(SCSIEN|SDMAEN|HDMAEN); 114163457Sgibbsdma_halt: 114263457Sgibbs /* 114365942Sgibbs * Some revisions of the aic78XX have a problem where, if the 114463457Sgibbs * data fifo is full, but the PCI input latch is not empty, 114563457Sgibbs * HDMAEN cannot be cleared. The fix used here is to drain 114663457Sgibbs * the prefetched but unused data from the data fifo until 114763457Sgibbs * there is space for the input latch to drain. 114863457Sgibbs */ 114965942Sgibbs if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0) { 115065942Sgibbs mov NONE, DFDAT; 115165942Sgibbs } 115263457Sgibbs test DFCNTRL, (SCSIEN|SDMAEN|HDMAEN) jnz dma_halt; 115322568Sgibbs 115463457Sgibbs /* See if we have completed this last segment */ 115563457Sgibbs test STCNT[0], 0xff jnz data_phase_finish; 115663457Sgibbs test STCNT[1], 0xff jnz data_phase_finish; 115763457Sgibbs test STCNT[2], 0xff jnz data_phase_finish; 11589928Sgibbs 115939220Sgibbs /* 116063457Sgibbs * Advance the scatter-gather pointers if needed 116139220Sgibbs */ 116265942Sgibbs if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 116365942Sgibbs && ahc->pci_cachesize != 0) { 116465942Sgibbs test MWI_RESIDUAL, 0xFF jz no_mwi_resid; 116565942Sgibbs /* 116665942Sgibbs * Reload HADDR from SHADDR and setup the 116765942Sgibbs * count to be the size of our residual. 116865942Sgibbs */ 116965942Sgibbs if ((ahc->features & AHC_CMD_CHAN) != 0) { 117065942Sgibbs bmov HADDR, SHADDR, 4; 117165942Sgibbs mov HCNT, MWI_RESIDUAL; 117265942Sgibbs bmov HCNT[1], ALLZEROS, 2; 117365942Sgibbs } else { 117465942Sgibbs mvi DINDEX, HADDR; 117565942Sgibbs mvi SHADDR call bcopy_4; 117665942Sgibbs mov MWI_RESIDUAL call set_hcnt; 117765942Sgibbs } 117865942Sgibbs clr MWI_RESIDUAL; 117965942Sgibbs jmp sg_load_done; 118065942Sgibbsno_mwi_resid: 118165942Sgibbs } 118263457Sgibbs test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz sg_load; 118363457Sgibbs or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL; 118463457Sgibbs jmp data_phase_finish; 118563457Sgibbssg_load: 118663457Sgibbs /* 118763457Sgibbs * Load the next SG element's data address and length 118863457Sgibbs * into the DMA engine. If we don't have hardware 118963457Sgibbs * to perform a prefetch, we'll have to fetch the 119063457Sgibbs * segment from host memory first. 119163457Sgibbs */ 119239220Sgibbs if ((ahc->features & AHC_CMD_CHAN) != 0) { 119363457Sgibbs /* Wait for the idle loop to complete */ 119463457Sgibbs test CCSGCTL, CCSGEN jz . + 3; 119563457Sgibbs call idle_loop; 119663457Sgibbs test CCSGCTL, CCSGEN jnz . - 1; 119763457Sgibbs bmov HADDR, CCSGRAM, 7; 119879874Sgibbs /* 119979874Sgibbs * Workaround for flaky external SCB RAM 120079874Sgibbs * on certain aic7895 setups. It seems 120179874Sgibbs * unable to handle direct transfers from 120279874Sgibbs * S/G ram to certain SCB locations. 120379874Sgibbs */ 120479874Sgibbs mov SINDEX, CCSGRAM; 120579874Sgibbs mov SCB_RESIDUAL_DATACNT[3], SINDEX; 120639220Sgibbs } else { 120779874Sgibbs if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 120879874Sgibbs mov ALLZEROS call set_hhaddr; 120979874Sgibbs } 121063457Sgibbs mvi DINDEX, HADDR; 121163457Sgibbs mvi SCB_RESIDUAL_SGPTR call bcopy_4; 121263457Sgibbs 121363457Sgibbs mvi SG_SIZEOF call set_hcnt; 121463457Sgibbs 121563457Sgibbs or DFCNTRL, HDMAEN|DIRECTION|FIFORESET; 121663457Sgibbs 121763457Sgibbs call dma_finish; 121863457Sgibbs 121965942Sgibbs mvi DINDEX, HADDR; 122065942Sgibbs call dfdat_in_7; 122163457Sgibbs mov SCB_RESIDUAL_DATACNT[3], DFDAT; 122265942Sgibbs } 122365942Sgibbs 122479874Sgibbs if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 122579874Sgibbs mov SCB_RESIDUAL_DATACNT[3] call set_hhaddr; 122679874Sgibbs 122779874Sgibbs /* 122879874Sgibbs * The lowest address byte must be loaded 122979874Sgibbs * last as it triggers the computation of 123079874Sgibbs * some items in the PCI block. The ULTRA2 123179874Sgibbs * chips do this on PRELOAD. 123279874Sgibbs */ 123379874Sgibbs mov HADDR, HADDR; 123479874Sgibbs } 123565942Sgibbs if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 123665942Sgibbs && ahc->pci_cachesize != 0) { 123765942Sgibbs call calc_mwi_residual; 123865942Sgibbs } 123965942Sgibbs 124065942Sgibbs /* Point to the new next sg in memory */ 124165942Sgibbs call sg_advance; 124265942Sgibbs 124365942Sgibbssg_load_done: 124465942Sgibbs if ((ahc->features & AHC_CMD_CHAN) != 0) { 124565942Sgibbs bmov STCNT, HCNT, 3; 124665942Sgibbs } else { 124739220Sgibbs call set_stcnt_from_hcnt; 124839220Sgibbs } 124939220Sgibbs 125068087Sgibbs if ((ahc->flags & AHC_TARGETROLE) != 0) { 125163457Sgibbs test SSTAT0, TARGET jnz data_phase_loop; 125263457Sgibbs } 125363457Sgibbs } 125463457Sgibbsdata_phase_finish: 125563457Sgibbs /* 125663457Sgibbs * If the target has left us in data phase, loop through 125763457Sgibbs * the dma code again. In the case of ULTRA2 adapters, 125863457Sgibbs * we should only loop if there is a data overrun. For 125963457Sgibbs * all other adapters, we'll loop after each S/G element 126063457Sgibbs * is loaded as well as if there is an overrun. 126163457Sgibbs */ 126268087Sgibbs if ((ahc->flags & AHC_TARGETROLE) != 0) { 126363457Sgibbs test SSTAT0, TARGET jnz data_phase_done; 126441646Sgibbs } 126568087Sgibbs if ((ahc->flags & AHC_INITIATORROLE) != 0) { 126663457Sgibbs test SSTAT1, REQINIT jz .; 126776634Sgibbs if ((ahc->features & AHC_DT) == 0) { 126876634Sgibbs test SSTAT1,PHASEMIS jz data_phase_loop; 126976634Sgibbs } else { 127076634Sgibbs test SCSIPHASE, DATA_PHASE_MASK jnz data_phase_loop; 127176634Sgibbs } 127239220Sgibbs } 12734568Sgibbs 127463457Sgibbsdata_phase_done: 127563457Sgibbs /* 127663457Sgibbs * After a DMA finishes, save the SG and STCNT residuals back into 127763457Sgibbs * the SCB. We use STCNT instead of HCNT, since it's a reflection 127863457Sgibbs * of how many bytes were transferred on the SCSI (as opposed to the 127963457Sgibbs * host) bus. 128063457Sgibbs */ 128139220Sgibbs if ((ahc->features & AHC_CMD_CHAN) != 0) { 128263457Sgibbs /* Kill off any pending prefetch */ 128374094Sgibbs call disable_ccsgen; 128465942Sgibbs } 128563457Sgibbs 128679874Sgibbs if ((ahc->features & AHC_ULTRA2) == 0) { 128779874Sgibbs /* 128879874Sgibbs * Clear the high address byte so that all other DMA 128979874Sgibbs * operations, which use 32bit addressing, can assume 129079874Sgibbs * HHADDR is 0. 129179874Sgibbs */ 129279874Sgibbs if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 129379874Sgibbs mov ALLZEROS call set_hhaddr; 129479874Sgibbs } 129579874Sgibbs } 129679874Sgibbs 129779874Sgibbs /* 129879874Sgibbs * Update our residual information before the information is 129979874Sgibbs * lost by some other type of SCSI I/O (e.g. PIO). If we have 130079874Sgibbs * transferred all data, no update is needed. 130179874Sgibbs * 130279874Sgibbs */ 130379874Sgibbs test SCB_RESIDUAL_SGPTR, SG_LIST_NULL jnz residual_update_done; 130465942Sgibbs if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 130565942Sgibbs && ahc->pci_cachesize != 0) { 130665942Sgibbs if ((ahc->features & AHC_CMD_CHAN) != 0) { 130765942Sgibbs test MWI_RESIDUAL, 0xFF jz bmov_resid; 130865942Sgibbs } 130965942Sgibbs mov A, MWI_RESIDUAL; 131065942Sgibbs add SCB_RESIDUAL_DATACNT[0], A, STCNT[0]; 131165942Sgibbs clr A; 131265942Sgibbs adc SCB_RESIDUAL_DATACNT[1], A, STCNT[1]; 131365942Sgibbs adc SCB_RESIDUAL_DATACNT[2], A, STCNT[2]; 131465942Sgibbs clr MWI_RESIDUAL; 131565942Sgibbs if ((ahc->features & AHC_CMD_CHAN) != 0) { 131665942Sgibbs jmp . + 2; 131765942Sgibbsbmov_resid: 131865942Sgibbs bmov SCB_RESIDUAL_DATACNT, STCNT, 3; 131965942Sgibbs } 132065942Sgibbs } else if ((ahc->features & AHC_CMD_CHAN) != 0) { 132163457Sgibbs bmov SCB_RESIDUAL_DATACNT, STCNT, 3; 132239220Sgibbs } else { 132365942Sgibbs mov SCB_RESIDUAL_DATACNT[0], STCNT[0]; 132465942Sgibbs mov SCB_RESIDUAL_DATACNT[1], STCNT[1]; 132565942Sgibbs mov SCB_RESIDUAL_DATACNT[2], STCNT[2]; 132639220Sgibbs } 132779874Sgibbsresidual_update_done: 132863457Sgibbs /* 132963457Sgibbs * Since we've been through a data phase, the SCB_RESID* fields 133063457Sgibbs * are now initialized. Clear the full residual flag. 133163457Sgibbs */ 133263457Sgibbs and SCB_SGPTR[0], ~SG_FULL_RESID; 133363457Sgibbs 133439220Sgibbs if ((ahc->features & AHC_ULTRA2) != 0) { 133563457Sgibbs /* Clear the channel in case we return to data phase later */ 133639220Sgibbs or SXFRCTL0, CLRSTCNT|CLRCHN; 133768402Sgibbs or SXFRCTL0, CLRSTCNT|CLRCHN; 133839220Sgibbs } 133922568Sgibbs 134068087Sgibbs if ((ahc->flags & AHC_TARGETROLE) != 0) { 134141646Sgibbs test SEQ_FLAGS, DPHASE_PENDING jz ITloop; 134239220Sgibbs and SEQ_FLAGS, ~DPHASE_PENDING; 134342652Sgibbs /* 134442652Sgibbs * For data-in phases, wait for any pending acks from the 134595378Sgibbs * initiator before changing phase. We only need to 134695378Sgibbs * send Ignore Wide Residue messages for data-in phases. 134742652Sgibbs */ 134842652Sgibbs test DFCNTRL, DIRECTION jz target_ITloop; 134942652Sgibbs test SSTAT1, REQINIT jnz .; 1350115333Sgibbs test SCB_LUN, SCB_XFERLEN_ODD jz target_ITloop; 135195378Sgibbs test SCSIRATE, WIDEXFER jz target_ITloop; 135295378Sgibbs /* 135395378Sgibbs * Issue an Ignore Wide Residue Message. 135495378Sgibbs */ 135595378Sgibbs mvi P_MESGIN|BSYO call change_phase; 135695378Sgibbs mvi MSG_IGN_WIDE_RESIDUE call target_outb; 135795378Sgibbs mvi 1 call target_outb; 135839220Sgibbs jmp target_ITloop; 135963457Sgibbs } else { 136063457Sgibbs jmp ITloop; 136139220Sgibbs } 13624568Sgibbs 136368087Sgibbsif ((ahc->flags & AHC_INITIATORROLE) != 0) { 136416260Sgibbs/* 136515328Sgibbs * Command phase. Set up the DMA registers and let 'er rip. 136613177Sgibbs */ 13674568Sgibbsp_command: 1368107420Sscottl test SEQ_FLAGS, NOT_IDENTIFIED jz p_command_okay; 1369107420Sscottl mvi PROTO_VIOLATION call set_seqint; 137079874Sgibbsp_command_okay: 13714568Sgibbs 137263457Sgibbs if ((ahc->features & AHC_ULTRA2) != 0) { 137363457Sgibbs bmov HCNT[0], SCB_CDB_LEN, 1; 137439220Sgibbs bmov HCNT[1], ALLZEROS, 2; 137563944Sgibbs mvi SG_CACHE_PRE, LAST_SEG; 137663457Sgibbs } else if ((ahc->features & AHC_CMD_CHAN) != 0) { 137763457Sgibbs bmov STCNT[0], SCB_CDB_LEN, 1; 137863457Sgibbs bmov STCNT[1], ALLZEROS, 2; 137939220Sgibbs } else { 138063457Sgibbs mov STCNT[0], SCB_CDB_LEN; 138163457Sgibbs clr STCNT[1]; 138263457Sgibbs clr STCNT[2]; 138339220Sgibbs } 138463457Sgibbs add NONE, -13, SCB_CDB_LEN; 138565942Sgibbs mvi SCB_CDB_STORE jnc p_command_embedded; 138663457Sgibbsp_command_from_host: 138763457Sgibbs if ((ahc->features & AHC_ULTRA2) != 0) { 138863457Sgibbs bmov HADDR[0], SCB_CDB_PTR, 4; 138963457Sgibbs mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN|DIRECTION); 139063457Sgibbs } else { 139163457Sgibbs if ((ahc->features & AHC_CMD_CHAN) != 0) { 139263457Sgibbs bmov HADDR[0], SCB_CDB_PTR, 4; 139365942Sgibbs bmov HCNT, STCNT, 3; 139463457Sgibbs } else { 139563457Sgibbs mvi DINDEX, HADDR; 139668087Sgibbs mvi SCB_CDB_PTR call bcopy_4; 139768087Sgibbs mov SCB_CDB_LEN call set_hcnt; 139839220Sgibbs } 139939220Sgibbs mvi DFCNTRL, (SCSIEN|SDMAEN|HDMAEN|DIRECTION|FIFORESET); 140063457Sgibbs } 1401107420Sscottl jmp p_command_xfer; 140263457Sgibbsp_command_embedded: 140363457Sgibbs /* 140476634Sgibbs * The data fifo seems to require 4 byte aligned 140563457Sgibbs * transfers from the sequencer. Force this to 140663457Sgibbs * be the case by clearing HADDR[0] even though 140795378Sgibbs * we aren't going to touch host memory. 140863457Sgibbs */ 140963457Sgibbs clr HADDR[0]; 141063457Sgibbs if ((ahc->features & AHC_ULTRA2) != 0) { 141163457Sgibbs mvi DFCNTRL, (PRELOADEN|SCSIEN|DIRECTION); 141263457Sgibbs bmov DFDAT, SCB_CDB_STORE, 12; 141365942Sgibbs } else if ((ahc->features & AHC_CMD_CHAN) != 0) { 141471390Sgibbs if ((ahc->flags & AHC_SCB_BTT) != 0) { 141565942Sgibbs /* 141665942Sgibbs * On the 7895 the data FIFO will 141765942Sgibbs * get corrupted if you try to dump 141865942Sgibbs * data from external SCB memory into 141965942Sgibbs * the FIFO while it is enabled. So, 142065942Sgibbs * fill the fifo and then enable SCSI 142165942Sgibbs * transfers. 142265942Sgibbs */ 142365942Sgibbs mvi DFCNTRL, (DIRECTION|FIFORESET); 142465942Sgibbs } else { 142565942Sgibbs mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFORESET); 142665942Sgibbs } 142765942Sgibbs bmov DFDAT, SCB_CDB_STORE, 12; 142871390Sgibbs if ((ahc->flags & AHC_SCB_BTT) != 0) { 142965942Sgibbs mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFOFLUSH); 143065942Sgibbs } else { 143163821Sgibbs or DFCNTRL, FIFOFLUSH; 143263821Sgibbs } 143363457Sgibbs } else { 143465942Sgibbs mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFORESET); 143563821Sgibbs call copy_to_fifo_6; 143663821Sgibbs call copy_to_fifo_6; 143763821Sgibbs or DFCNTRL, FIFOFLUSH; 143863457Sgibbs } 1439107420Sscottlp_command_xfer: 1440107420Sscottl and SEQ_FLAGS, ~NO_CDB_SENT; 144176634Sgibbs if ((ahc->features & AHC_DT) == 0) { 144276634Sgibbs test SSTAT0, SDONE jnz . + 2; 1443107420Sscottl test SSTAT1, PHASEMIS jz . - 1; 144476634Sgibbs /* 144576634Sgibbs * Wait for our ACK to go-away on it's own 144676634Sgibbs * instead of being killed by SCSIEN getting cleared. 144776634Sgibbs */ 144876634Sgibbs test SCSISIGI, ACKI jnz .; 144976634Sgibbs } else { 1450107420Sscottl test DFCNTRL, SCSIEN jnz .; 145176634Sgibbs } 1452107420Sscottl test SSTAT0, SDONE jnz p_command_successful; 1453107420Sscottl /* 1454107420Sscottl * Don't allow a data phase if the command 1455107420Sscottl * was not fully transferred. 1456107420Sscottl */ 1457107420Sscottl or SEQ_FLAGS, NO_CDB_SENT; 1458107420Sscottlp_command_successful: 145955581Sgibbs and DFCNTRL, ~(SCSIEN|SDMAEN|HDMAEN); 146039220Sgibbs test DFCNTRL, (SCSIEN|SDMAEN|HDMAEN) jnz .; 146123925Sgibbs jmp ITloop; 14624568Sgibbs 146313177Sgibbs/* 146413177Sgibbs * Status phase. Wait for the data byte to appear, then read it 146513177Sgibbs * and store it into the SCB. 146613177Sgibbs */ 14674568Sgibbsp_status: 1468107420Sscottl test SEQ_FLAGS, NOT_IDENTIFIED jnz mesgin_proto_violation; 146979874Sgibbsp_status_okay: 147063457Sgibbs mov SCB_SCSI_STATUS, SCSIDATL; 1471107420Sscottl or SCB_CONTROL, STATUS_RCVD; 147223925Sgibbs jmp ITloop; 14734568Sgibbs 147413177Sgibbs/* 147541646Sgibbs * Message out phase. If MSG_OUT is MSG_IDENTIFYFLAG, build a full 147641646Sgibbs * indentify message sequence and send it to the target. The host may 147741646Sgibbs * override this behavior by setting the MK_MESSAGE bit in the SCB 147841646Sgibbs * control byte. This will cause us to interrupt the host and allow 147941646Sgibbs * it to handle the message phase completely on its own. If the bit 148041646Sgibbs * associated with this target is set, we will also interrupt the host, 148141646Sgibbs * thereby allowing it to send a message on the next selection regardless 148241646Sgibbs * of the transaction being sent. 148339220Sgibbs * 148439220Sgibbs * If MSG_OUT is == HOST_MSG, also interrupt the host and take a message. 148541646Sgibbs * This is done to allow the host to send messages outside of an identify 148639220Sgibbs * sequence while protecting the seqencer from testing the MK_MESSAGE bit 148739220Sgibbs * on an SCB that might not be for the current nexus. (For example, a 148839220Sgibbs * BDR message in responce to a bad reselection would leave us pointed to 148939220Sgibbs * an SCB that doesn't have anything to do with the current target). 149041646Sgibbs * 149139220Sgibbs * Otherwise, treat MSG_OUT as a 1 byte message to send (abort, abort tag, 149239220Sgibbs * bus device reset). 149339220Sgibbs * 149439220Sgibbs * When there are no messages to send, MSG_OUT should be set to MSG_NOOP, 149539220Sgibbs * in case the target decides to put us in this phase for some strange 149639220Sgibbs * reason. 149713177Sgibbs */ 149841646Sgibbsp_mesgout_retry: 149976634Sgibbs /* Turn on ATN for the retry */ 150076634Sgibbs if ((ahc->features & AHC_DT) == 0) { 150176634Sgibbs or SCSISIGO, ATNO, LASTPHASE; 150276634Sgibbs } else { 150376634Sgibbs mvi SCSISIGO, ATNO; 150476634Sgibbs } 15054568Sgibbsp_mesgout: 150639220Sgibbs mov SINDEX, MSG_OUT; 150739220Sgibbs cmp SINDEX, MSG_IDENTIFYFLAG jne p_mesgout_from_host; 150841646Sgibbs test SCB_CONTROL,MK_MESSAGE jnz host_message_loop; 150939220Sgibbsp_mesgout_identify: 1510115333Sgibbs or SINDEX, MSG_IDENTIFYFLAG|DISCENB, SAVED_LUN; 151163457Sgibbs test SCB_CONTROL, DISCENB jnz . + 2; 151263457Sgibbs and SINDEX, ~DISCENB; 151313177Sgibbs/* 151439220Sgibbs * Send a tag message if TAG_ENB is set in the SCB control block. 151539220Sgibbs * Use SCB_TAG (the position in the kernel's SCB array) as the tag value. 151613177Sgibbs */ 151739220Sgibbsp_mesgout_tag: 151839220Sgibbs test SCB_CONTROL,TAG_ENB jz p_mesgout_onebyte; 151939220Sgibbs mov SCSIDATL, SINDEX; /* Send the identify message */ 152039220Sgibbs call phase_lock; 152139220Sgibbs cmp LASTPHASE, P_MESGOUT jne p_mesgout_done; 152239220Sgibbs and SCSIDATL,TAG_ENB|SCB_TAG_TYPE,SCB_CONTROL; 152339220Sgibbs call phase_lock; 152439220Sgibbs cmp LASTPHASE, P_MESGOUT jne p_mesgout_done; 152539220Sgibbs mov SCB_TAG jmp p_mesgout_onebyte; 152613177Sgibbs/* 152741646Sgibbs * Interrupt the driver, and allow it to handle this message 152841646Sgibbs * phase and any required retries. 152913177Sgibbs */ 153039220Sgibbsp_mesgout_from_host: 153139220Sgibbs cmp SINDEX, HOST_MSG jne p_mesgout_onebyte; 153241646Sgibbs jmp host_message_loop; 153339220Sgibbs 153439220Sgibbsp_mesgout_onebyte: 153539220Sgibbs mvi CLRSINT1, CLRATNO; 153639220Sgibbs mov SCSIDATL, SINDEX; 153739220Sgibbs 153813177Sgibbs/* 153941646Sgibbs * If the next bus phase after ATN drops is message out, it means 154013177Sgibbs * that the target is requesting that the last message(s) be resent. 154113177Sgibbs */ 154239220Sgibbs call phase_lock; 154341646Sgibbs cmp LASTPHASE, P_MESGOUT je p_mesgout_retry; 15444568Sgibbs 154519906Sgibbsp_mesgout_done: 154623925Sgibbs mvi CLRSINT1,CLRATNO; /* Be sure to turn ATNO off */ 154739220Sgibbs mov LAST_MSG, MSG_OUT; 154839220Sgibbs mvi MSG_OUT, MSG_NOOP; /* No message left */ 154923925Sgibbs jmp ITloop; 15504568Sgibbs 155113177Sgibbs/* 155213177Sgibbs * Message in phase. Bytes are read using Automatic PIO mode. 155313177Sgibbs */ 15544568Sgibbsp_mesgin: 155523925Sgibbs mvi ACCUM call inb_first; /* read the 1st message byte */ 15564568Sgibbs 155723925Sgibbs test A,MSG_IDENTIFYFLAG jnz mesgin_identify; 155823925Sgibbs cmp A,MSG_DISCONNECT je mesgin_disconnect; 155923925Sgibbs cmp A,MSG_SAVEDATAPOINTER je mesgin_sdptrs; 156023925Sgibbs cmp ALLZEROS,A je mesgin_complete; 156123925Sgibbs cmp A,MSG_RESTOREPOINTERS je mesgin_rdptrs; 156263457Sgibbs cmp A,MSG_IGN_WIDE_RESIDUE je mesgin_ign_wide_residue; 156323925Sgibbs cmp A,MSG_NOOP je mesgin_done; 15644568Sgibbs 156513177Sgibbs/* 156641887Sgibbs * Pushed message loop to allow the kernel to 156757099Sgibbs * run it's own message state engine. To avoid an 156841887Sgibbs * extra nop instruction after signaling the kernel, 156941887Sgibbs * we perform the phase_lock before checking to see 157041887Sgibbs * if we should exit the loop and skip the phase_lock 157141887Sgibbs * in the ITloop. Performing back to back phase_locks 157241887Sgibbs * shouldn't hurt, but why do it twice... 157313177Sgibbs */ 157441887Sgibbshost_message_loop: 157568402Sgibbs mvi HOST_MSG_LOOP call set_seqint; 157641887Sgibbs call phase_lock; 157741887Sgibbs cmp RETURN_1, EXIT_MSG_LOOP je ITloop + 1; 157841887Sgibbs jmp host_message_loop; 15799954Sgibbs 158063457Sgibbsmesgin_ign_wide_residue: 158163457Sgibbsif ((ahc->features & AHC_WIDE) != 0) { 158263457Sgibbs test SCSIRATE, WIDEXFER jz mesgin_reject; 158363457Sgibbs /* Pull the residue byte */ 158463457Sgibbs mvi ARG_1 call inb_next; 158563457Sgibbs cmp ARG_1, 0x01 jne mesgin_reject; 158663457Sgibbs test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz . + 2; 1587115333Sgibbs test SCB_LUN, SCB_XFERLEN_ODD jnz mesgin_done; 158868402Sgibbs mvi IGN_WIDE_RES call set_seqint; 158963457Sgibbs jmp mesgin_done; 159063457Sgibbs} 159163457Sgibbs 1592107420Sscottlmesgin_proto_violation: 1593107420Sscottl mvi PROTO_VIOLATION call set_seqint; 1594107420Sscottl jmp mesgin_done; 159563457Sgibbsmesgin_reject: 159663457Sgibbs mvi MSG_MESSAGE_REJECT call mk_mesg; 15979954Sgibbsmesgin_done: 159823925Sgibbs mov NONE,SCSIDATL; /*dummy read from latch to ACK*/ 159923925Sgibbs jmp ITloop; 16009954Sgibbs 160113177Sgibbs/* 160263457Sgibbs * We received a "command complete" message. Put the SCB_TAG into the QOUTFIFO, 160319164Sgibbs * and trigger a completion interrupt. Before doing so, check to see if there 160439220Sgibbs * is a residual or the status byte is something other than STATUS_GOOD (0). 160539220Sgibbs * In either of these conditions, we upload the SCB back to the host so it can 160619164Sgibbs * process this information. In the case of a non zero status byte, we 160719164Sgibbs * additionally interrupt the kernel driver synchronously, allowing it to 160819164Sgibbs * decide if sense should be retrieved. If the kernel driver wishes to request 160968087Sgibbs * sense, it will fill the kernel SCB with a request sense command, requeue 161068087Sgibbs * it to the QINFIFO and tell us not to post to the QOUTFIFO by setting 161168087Sgibbs * RETURN_1 to SEND_SENSE. 161213177Sgibbs */ 1613107420Sscottlmesgin_complete: 161419164Sgibbs 1615107420Sscottl /* 1616107420Sscottl * If ATN is raised, we still want to give the target a message. 1617107420Sscottl * Perhaps there was a parity error on this last message byte. 1618107420Sscottl * Either way, the target should take us to message out phase 1619107420Sscottl * and then attempt to complete the command again. We should use a 1620107420Sscottl * critical section here to guard against a timeout triggering 1621107420Sscottl * for this command and setting ATN while we are still processing 1622107420Sscottl * the completion. 162368579Sgibbs test SCSISIGI, ATNI jnz mesgin_done; 1624107420Sscottl */ 162568579Sgibbs 1626107420Sscottl /* 1627107420Sscottl * If we are identified and have successfully sent the CDB, 1628107420Sscottl * any status will do. Optimize this fast path. 1629107420Sscottl */ 1630107420Sscottl test SCB_CONTROL, STATUS_RCVD jz mesgin_proto_violation; 1631107420Sscottl test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT jz complete_accepted; 1632107420Sscottl 1633107420Sscottl /* 1634107420Sscottl * If the target never sent an identify message but instead went 1635107420Sscottl * to mesgin to give an invalid message, let the host abort us. 1636107420Sscottl */ 1637107420Sscottl test SEQ_FLAGS, NOT_IDENTIFIED jnz mesgin_proto_violation; 1638107420Sscottl 1639107420Sscottl /* 1640107420Sscottl * If we recevied good status but never successfully sent the 1641107420Sscottl * cdb, abort the command. 1642107420Sscottl */ 1643107420Sscottl test SCB_SCSI_STATUS,0xff jnz complete_accepted; 1644107420Sscottl test SEQ_FLAGS, NO_CDB_SENT jnz mesgin_proto_violation; 1645107420Sscottl 1646107420Sscottlcomplete_accepted: 1647107420Sscottl /* 1648107420Sscottl * See if we attempted to deliver a message but the target ingnored us. 1649107420Sscottl */ 165068402Sgibbs test SCB_CONTROL, MK_MESSAGE jz . + 2; 165168402Sgibbs mvi MKMSG_FAILED call set_seqint; 165268402Sgibbs 1653107420Sscottl /* 1654107420Sscottl * Check for residuals 1655107420Sscottl */ 165663457Sgibbs test SCB_SGPTR, SG_LIST_NULL jnz check_status;/* No xfer */ 165763457Sgibbs test SCB_SGPTR, SG_FULL_RESID jnz upload_scb;/* Never xfered */ 165863457Sgibbs test SCB_RESIDUAL_SGPTR, SG_LIST_NULL jz upload_scb; 165963457Sgibbscheck_status: 166063457Sgibbs test SCB_SCSI_STATUS,0xff jz complete; /* Good Status? */ 166119164Sgibbsupload_scb: 166263457Sgibbs or SCB_SGPTR, SG_RESID_VALID; 166323925Sgibbs mvi DMAPARAMS, FIFORESET; 166423925Sgibbs mov SCB_TAG call dma_scb; 166563457Sgibbs test SCB_SCSI_STATUS, 0xff jz complete; /* Just a residual? */ 166668402Sgibbs mvi BAD_STATUS call set_seqint; /* let driver know */ 166739220Sgibbs cmp RETURN_1, SEND_SENSE jne complete; 166868087Sgibbs call add_scb_to_free_list; 166923925Sgibbs jmp await_busfree; 167039220Sgibbscomplete: 167139220Sgibbs mov SCB_TAG call complete_post; 167223925Sgibbs jmp await_busfree; 167341646Sgibbs} 16744568Sgibbs 167539220Sgibbscomplete_post: 167639220Sgibbs /* Post the SCBID in SINDEX and issue an interrupt */ 167744507Sgibbs call add_scb_to_free_list; 167839220Sgibbs mov ARG_1, SINDEX; 167939220Sgibbs if ((ahc->features & AHC_QUEUE_REGS) != 0) { 168039220Sgibbs mov A, SDSCB_QOFF; 168139220Sgibbs } else { 168239220Sgibbs mov A, QOUTPOS; 168339220Sgibbs } 168439220Sgibbs mvi QOUTFIFO_OFFSET call post_byte_setup; 168539220Sgibbs mov ARG_1 call post_byte; 168639220Sgibbs if ((ahc->features & AHC_QUEUE_REGS) == 0) { 168739220Sgibbs inc QOUTPOS; 168839220Sgibbs } 168939220Sgibbs mvi INTSTAT,CMDCMPLT ret; 169039220Sgibbs 169168087Sgibbsif ((ahc->flags & AHC_INITIATORROLE) != 0) { 169213177Sgibbs/* 169313177Sgibbs * Is it a disconnect message? Set a flag in the SCB to remind us 169463457Sgibbs * and await the bus going free. If this is an untagged transaction 169563457Sgibbs * store the SCB id for it in our untagged target table for lookup on 169663457Sgibbs * a reselction. 169713177Sgibbs */ 16989954Sgibbsmesgin_disconnect: 169968579Sgibbs /* 170068579Sgibbs * If ATN is raised, we still want to give the target a message. 170168579Sgibbs * Perhaps there was a parity error on this last message byte 170268579Sgibbs * or we want to abort this command. Either way, the target 170368579Sgibbs * should take us to message out phase and then attempt to 170468579Sgibbs * disconnect again. 170568579Sgibbs * XXX - Wait for more testing. 170668579Sgibbs test SCSISIGI, ATNI jnz mesgin_done; 170768579Sgibbs */ 1708107420Sscottl test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT 1709107420Sscottl jnz mesgin_proto_violation; 171023925Sgibbs or SCB_CONTROL,DISCONNECTED; 171163457Sgibbs if ((ahc->flags & AHC_PAGESCBS) != 0) { 171263457Sgibbs call add_scb_to_disc_list; 171363457Sgibbs } 171463457Sgibbs test SCB_CONTROL, TAG_ENB jnz await_busfree; 171563457Sgibbs mov ARG_1, SCB_TAG; 1716115333Sgibbs and SAVED_LUN, LID, SCB_LUN; 171768087Sgibbs mov SCB_SCSIID call set_busy_target; 171823925Sgibbs jmp await_busfree; 171919164Sgibbs 172015328Sgibbs/* 172119164Sgibbs * Save data pointers message: 172219164Sgibbs * Copying RAM values back to SCB, for Save Data Pointers message, but 172319164Sgibbs * only if we've actually been into a data phase to change them. This 172419164Sgibbs * protects against bogus data in scratch ram and the residual counts 172519164Sgibbs * since they are only initialized when we go into data_in or data_out. 172676634Sgibbs * Ack the message as soon as possible. For chips without S/G pipelining, 172776634Sgibbs * we can only ack the message after SHADDR has been saved. On these 172876634Sgibbs * chips, SHADDR increments with every bus transaction, even PIO. 172915328Sgibbs */ 173019164Sgibbsmesgin_sdptrs: 173176634Sgibbs if ((ahc->features & AHC_ULTRA2) != 0) { 173276634Sgibbs mov NONE,SCSIDATL; /*dummy read from latch to ACK*/ 173376634Sgibbs test SEQ_FLAGS, DPHASE jz ITloop; 173476634Sgibbs } else { 173576634Sgibbs test SEQ_FLAGS, DPHASE jz mesgin_done; 173676634Sgibbs } 173779874Sgibbs 173839220Sgibbs /* 173979874Sgibbs * If we are asked to save our position at the end of the 174079874Sgibbs * transfer, just mark us at the end rather than perform a 174179874Sgibbs * full save. 174279874Sgibbs */ 174379874Sgibbs test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz mesgin_sdptrs_full; 174479874Sgibbs or SCB_SGPTR, SG_LIST_NULL; 174581170Sgibbs if ((ahc->features & AHC_ULTRA2) != 0) { 174681170Sgibbs jmp ITloop; 174781170Sgibbs } else { 174881170Sgibbs jmp mesgin_done; 174981170Sgibbs } 175079874Sgibbs 175179874Sgibbsmesgin_sdptrs_full: 175279874Sgibbs 175379874Sgibbs /* 175463457Sgibbs * The SCB_SGPTR becomes the next one we'll download, 175563457Sgibbs * and the SCB_DATAPTR becomes the current SHADDR. 175639220Sgibbs * Use the residual number since STCNT is corrupted by 175739220Sgibbs * any message transfer. 175839220Sgibbs */ 175939220Sgibbs if ((ahc->features & AHC_CMD_CHAN) != 0) { 176039220Sgibbs bmov SCB_DATAPTR, SHADDR, 4; 176176634Sgibbs if ((ahc->features & AHC_ULTRA2) == 0) { 176276634Sgibbs mov NONE,SCSIDATL; /*dummy read from latch to ACK*/ 176376634Sgibbs } 176463457Sgibbs bmov SCB_DATACNT, SCB_RESIDUAL_DATACNT, 8; 176539220Sgibbs } else { 176639220Sgibbs mvi DINDEX, SCB_DATAPTR; 176763457Sgibbs mvi SHADDR call bcopy_4; 176876634Sgibbs mov NONE,SCSIDATL; /*dummy read from latch to ACK*/ 176963457Sgibbs mvi SCB_RESIDUAL_DATACNT call bcopy_8; 177039220Sgibbs } 177176634Sgibbs jmp ITloop; 17724568Sgibbs 177313177Sgibbs/* 177413177Sgibbs * Restore pointers message? Data pointers are recopied from the 177513177Sgibbs * SCB anytime we enter a data phase for the first time, so all 177613177Sgibbs * we need to do is clear the DPHASE flag and let the data phase 1777107420Sscottl * code do the rest. We also reset/reallocate the FIFO to make 1778107420Sscottl * sure we have a clean start for the next data or command phase. 177913177Sgibbs */ 17809954Sgibbsmesgin_rdptrs: 178123925Sgibbs and SEQ_FLAGS, ~DPHASE; /* 178223925Sgibbs * We'll reload them 178313177Sgibbs * the next time through 178423925Sgibbs * the dataphase. 178513177Sgibbs */ 1786107420Sscottl or SXFRCTL0, CLRSTCNT|CLRCHN; 178723925Sgibbs jmp mesgin_done; 17884568Sgibbs 178913177Sgibbs/* 179063457Sgibbs * Index into our Busy Target table. SINDEX and DINDEX are modified 179163457Sgibbs * upon return. SCBPTR may be modified by this action. 179263457Sgibbs */ 179368087Sgibbsset_busy_target: 179468087Sgibbs shr DINDEX, 4, SINDEX; 179571390Sgibbs if ((ahc->flags & AHC_SCB_BTT) != 0) { 179663457Sgibbs mov SCBPTR, SAVED_LUN; 179768087Sgibbs add DINDEX, SCB_64_BTT; 179863457Sgibbs } else { 179968087Sgibbs add DINDEX, BUSY_TARGETS; 180063457Sgibbs } 180168087Sgibbs mov DINDIR, ARG_1 ret; 180263457Sgibbs 180363457Sgibbs/* 180413177Sgibbs * Identify message? For a reconnecting target, this tells us the lun 180513177Sgibbs * that the reconnection is for - find the correct SCB and switch to it, 180613177Sgibbs * clearing the "disconnected" bit so we don't "find" it by accident later. 180713177Sgibbs */ 18089954Sgibbsmesgin_identify: 180963457Sgibbs /* 181063457Sgibbs * Determine whether a target is using tagged or non-tagged 181163457Sgibbs * transactions by first looking at the transaction stored in 181263457Sgibbs * the busy target array. If there is no untagged transaction 181363457Sgibbs * for this target or the transaction is for a different lun, then 1814102673Sgibbs * this must be a tagged transaction. 181563457Sgibbs */ 181672325Sgibbs shr SINDEX, 4, SAVED_SCSIID; 181771390Sgibbs and SAVED_LUN, MSG_IDENTIFY_LUNMASK, A; 181871390Sgibbs if ((ahc->flags & AHC_SCB_BTT) != 0) { 181971390Sgibbs add SINDEX, SCB_64_BTT; 182068087Sgibbs mov SCBPTR, SAVED_LUN; 182171390Sgibbs if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 182271390Sgibbs add NONE, -SCB_64_BTT, SINDEX; 182371390Sgibbs jc . + 2; 182471390Sgibbs mvi INTSTAT, OUT_OF_RANGE; 182571390Sgibbs nop; 182671390Sgibbs add NONE, -(SCB_64_BTT + 16), SINDEX; 182771390Sgibbs jnc . + 2; 182871390Sgibbs mvi INTSTAT, OUT_OF_RANGE; 182971390Sgibbs nop; 183071390Sgibbs } 183168087Sgibbs } else { 183271390Sgibbs add SINDEX, BUSY_TARGETS; 183368087Sgibbs if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 183471390Sgibbs add NONE, -BUSY_TARGETS, SINDEX; 183568087Sgibbs jc . + 2; 183668087Sgibbs mvi INTSTAT, OUT_OF_RANGE; 183768402Sgibbs nop; 183871390Sgibbs add NONE, -(BUSY_TARGETS + 16), SINDEX; 183968087Sgibbs jnc . + 2; 184068087Sgibbs mvi INTSTAT, OUT_OF_RANGE; 184168402Sgibbs nop; 184268087Sgibbs } 184368087Sgibbs } 184468087Sgibbs mov ARG_1, SINDIR; 184568087Sgibbs cmp ARG_1, SCB_LIST_NULL je snoop_tag; 184663457Sgibbs if ((ahc->flags & AHC_PAGESCBS) != 0) { 184768579Sgibbs mov ARG_1 call findSCB; 184839220Sgibbs } else { 184974094Sgibbs mov SCBPTR, ARG_1; 185039220Sgibbs } 185171390Sgibbs if ((ahc->flags & AHC_SCB_BTT) != 0) { 185263457Sgibbs jmp setup_SCB_id_lun_okay; 185363457Sgibbs } else { 185474094Sgibbs /* 185574094Sgibbs * We only allow one untagged command per-target 185674094Sgibbs * at a time. So, if the lun doesn't match, look 185774094Sgibbs * for a tag message. 185874094Sgibbs */ 1859115333Sgibbs and A, LID, SCB_LUN; 186074094Sgibbs cmp SAVED_LUN, A je setup_SCB_id_lun_okay; 186174094Sgibbs if ((ahc->flags & AHC_PAGESCBS) != 0) { 186274094Sgibbs /* 186374094Sgibbs * findSCB removes the SCB from the 186474094Sgibbs * disconnected list, so we must replace 186574094Sgibbs * it there should this SCB be for another 186674094Sgibbs * lun. 186774094Sgibbs */ 186874094Sgibbs call cleanup_scb; 186974094Sgibbs } 187063457Sgibbs } 187139220Sgibbs 187213177Sgibbs/* 187313177Sgibbs * Here we "snoop" the bus looking for a SIMPLE QUEUE TAG message. 187423168Sgibbs * If we get one, we use the tag returned to find the proper 187563457Sgibbs * SCB. With SCB paging, we must search for non-tagged 187663457Sgibbs * transactions since the SCB may exist in any slot. If we're not 187763457Sgibbs * using SCB paging, we can use the tag as the direct index to the 187863457Sgibbs * SCB. 187913177Sgibbs */ 188024608Sgibbssnoop_tag: 188171390Sgibbs if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 188271390Sgibbs or SEQ_FLAGS, 0x80; 188371390Sgibbs } 188423925Sgibbs mov NONE,SCSIDATL; /* ACK Identify MSG */ 188539220Sgibbs call phase_lock; 188668087Sgibbs if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 188768087Sgibbs or SEQ_FLAGS, 0x1; 188868087Sgibbs } 188923925Sgibbs cmp LASTPHASE, P_MESGIN jne not_found; 189068087Sgibbs if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 189168087Sgibbs or SEQ_FLAGS, 0x2; 189268087Sgibbs } 189323925Sgibbs cmp SCSIBUSL,MSG_SIMPLE_Q_TAG jne not_found; 18946608Sgibbsget_tag: 189563457Sgibbs if ((ahc->flags & AHC_PAGESCBS) != 0) { 189663457Sgibbs mvi ARG_1 call inb_next; /* tag value */ 189763457Sgibbs mov ARG_1 call findSCB; 189863457Sgibbs } else { 189968087Sgibbs mvi ARG_1 call inb_next; /* tag value */ 190068087Sgibbs mov SCBPTR, ARG_1; 190163457Sgibbs } 190213177Sgibbs 190363457Sgibbs/* 190463457Sgibbs * Ensure that the SCB the tag points to is for 190563457Sgibbs * an SCB transaction to the reconnecting target. 190663457Sgibbs */ 190739220Sgibbssetup_SCB: 190868087Sgibbs if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 190968087Sgibbs or SEQ_FLAGS, 0x4; 191068087Sgibbs } 191171390Sgibbs mov A, SCB_SCSIID; 191271390Sgibbs cmp SAVED_SCSIID, A jne not_found_cleanup_scb; 191368087Sgibbs if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 191468087Sgibbs or SEQ_FLAGS, 0x8; 191568087Sgibbs } 191671390Sgibbssetup_SCB_id_okay: 1917115333Sgibbs and A, LID, SCB_LUN; 191871390Sgibbs cmp SAVED_LUN, A jne not_found_cleanup_scb; 191963457Sgibbssetup_SCB_id_lun_okay: 192068087Sgibbs if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) { 192168087Sgibbs or SEQ_FLAGS, 0x10; 192263457Sgibbs } 192368087Sgibbs test SCB_CONTROL,DISCONNECTED jz not_found_cleanup_scb; 192423925Sgibbs and SCB_CONTROL,~DISCONNECTED; 192563457Sgibbs test SCB_CONTROL, TAG_ENB jnz setup_SCB_tagged; 192674094Sgibbs if ((ahc->flags & AHC_SCB_BTT) != 0) { 192774094Sgibbs mov A, SCBPTR; 192874094Sgibbs } 192968087Sgibbs mvi ARG_1, SCB_LIST_NULL; 193068087Sgibbs mov SAVED_SCSIID call set_busy_target; 193174094Sgibbs if ((ahc->flags & AHC_SCB_BTT) != 0) { 193274094Sgibbs mov SCBPTR, A; 193374094Sgibbs } 193463457Sgibbssetup_SCB_tagged: 1935107420Sscottl clr SEQ_FLAGS; /* make note of IDENTIFY */ 193639220Sgibbs call set_transfer_settings; 193739220Sgibbs /* See if the host wants to send a message upon reconnection */ 193839220Sgibbs test SCB_CONTROL, MK_MESSAGE jz mesgin_done; 193939220Sgibbs mvi HOST_MSG call mk_mesg; 194023925Sgibbs jmp mesgin_done; 194115328Sgibbs 194268087Sgibbsnot_found_cleanup_scb: 194368087Sgibbs if ((ahc->flags & AHC_PAGESCBS) != 0) { 194474094Sgibbs call cleanup_scb; 194568087Sgibbs } 194619218Sgibbsnot_found: 194768402Sgibbs mvi NO_MATCH call set_seqint; 194823925Sgibbs jmp mesgin_done; 19496608Sgibbs 19504568Sgibbsmk_mesg: 195176634Sgibbs if ((ahc->features & AHC_DT) == 0) { 195276634Sgibbs or SCSISIGO, ATNO, LASTPHASE; 195376634Sgibbs } else { 195476634Sgibbs mvi SCSISIGO, ATNO; 195576634Sgibbs } 195639220Sgibbs mov MSG_OUT,SINDEX ret; 19574568Sgibbs 195813177Sgibbs/* 195913177Sgibbs * Functions to read data in Automatic PIO mode. 196013177Sgibbs * 196113177Sgibbs * According to Adaptec's documentation, an ACK is not sent on input from 196213177Sgibbs * the target until SCSIDATL is read from. So we wait until SCSIDATL is 196313177Sgibbs * latched (the usual way), then read the data byte directly off the bus 196413177Sgibbs * using SCSIBUSL. When we have pulled the ATN line, or we just want to 196513177Sgibbs * acknowledge the byte, then we do a dummy read from SCISDATL. The SCSI 196613177Sgibbs * spec guarantees that the target will hold the data byte on the bus until 196713177Sgibbs * we send our ACK. 196813177Sgibbs * 196913177Sgibbs * The assumption here is that these are called in a particular sequence, 197013177Sgibbs * and that REQ is already set when inb_first is called. inb_{first,next} 197113177Sgibbs * use the same calling convention as inb. 197213177Sgibbs */ 197357099Sgibbsinb_next_wait_perr: 197468402Sgibbs mvi PERR_DETECTED call set_seqint; 197557099Sgibbs jmp inb_next_wait; 197613177Sgibbsinb_next: 197723925Sgibbs mov NONE,SCSIDATL; /*dummy read from latch to ACK*/ 197813360Sgibbsinb_next_wait: 197921947Sgibbs /* 198021947Sgibbs * If there is a parity error, wait for the kernel to 198121947Sgibbs * see the interrupt and prepare our message response 198221947Sgibbs * before continuing. 198321947Sgibbs */ 198423925Sgibbs test SSTAT1, REQINIT jz inb_next_wait; 198557099Sgibbs test SSTAT1, SCSIPERR jnz inb_next_wait_perr; 198657099Sgibbsinb_next_check_phase: 198723925Sgibbs and LASTPHASE, PHASE_MASK, SCSISIGI; 198823925Sgibbs cmp LASTPHASE, P_MESGIN jne mesgin_phasemis; 198919623Sgibbsinb_first: 199023925Sgibbs mov DINDEX,SINDEX; 199123925Sgibbs mov DINDIR,SCSIBUSL ret; /*read byte directly from bus*/ 199213177Sgibbsinb_last: 199323925Sgibbs mov NONE,SCSIDATL ret; /*dummy read from latch to ACK*/ 199441646Sgibbs} 19954568Sgibbs 199668087Sgibbsif ((ahc->flags & AHC_TARGETROLE) != 0) { 199741646Sgibbs/* 199841646Sgibbs * Change to a new phase. If we are changing the state of the I/O signal, 199941646Sgibbs * from out to in, wait an additional data release delay before continuing. 200041646Sgibbs */ 200141646Sgibbschange_phase: 200276634Sgibbs /* Wait for preceeding I/O session to complete. */ 200343880Sgibbs test SCSISIGI, ACKI jnz .; 200443880Sgibbs 200543880Sgibbs /* Change the phase */ 200641646Sgibbs and DINDEX, IOI, SCSISIGI; 200741646Sgibbs mov SCSISIGO, SINDEX; 200841646Sgibbs and A, IOI, SINDEX; 200943880Sgibbs 201043880Sgibbs /* 201143880Sgibbs * If the data direction has changed, from 201243880Sgibbs * out (initiator driving) to in (target driving), 201363457Sgibbs * we must wait at least a data release delay plus 201443880Sgibbs * the normal bus settle delay. [SCSI III SPI 10.11.0] 201543880Sgibbs */ 201641646Sgibbs cmp DINDEX, A je change_phase_wait; 201741646Sgibbs test SINDEX, IOI jz change_phase_wait; 201841646Sgibbs call change_phase_wait; 201941646Sgibbschange_phase_wait: 202041646Sgibbs nop; 202141646Sgibbs nop; 202241646Sgibbs nop; 202341646Sgibbs nop ret; 202441646Sgibbs 202541646Sgibbs/* 202641646Sgibbs * Send a byte to an initiator in Automatic PIO mode. 202741646Sgibbs */ 202839220Sgibbstarget_outb: 202939220Sgibbs or SXFRCTL0, SPIOEN; 203039220Sgibbs test SSTAT0, SPIORDY jz .; 203139220Sgibbs mov SCSIDATL, SINDEX; 203239220Sgibbs test SSTAT0, SPIORDY jz .; 203341646Sgibbs and SXFRCTL0, ~SPIOEN ret; 203439220Sgibbs} 203539220Sgibbs 203613177Sgibbs/* 203763457Sgibbs * Locate a disconnected SCB by SCBID. Upon return, SCBPTR and SINDEX will 203863457Sgibbs * be set to the position of the SCB. If the SCB cannot be found locally, 203963457Sgibbs * it will be paged in from host memory. RETURN_2 stores the address of the 204063457Sgibbs * preceding SCB in the disconnected list which can be used to speed up 204163457Sgibbs * removal of the found SCB from the disconnected list. 204213177Sgibbs */ 204365942Sgibbsif ((ahc->flags & AHC_PAGESCBS) != 0) { 204495378SgibbsBEGIN_CRITICAL; 20454568SgibbsfindSCB: 204668087Sgibbs mov A, SINDEX; /* Tag passed in SINDEX */ 204768087Sgibbs cmp DISCONNECTED_SCBH, SCB_LIST_NULL je findSCB_notFound; 204863457Sgibbs mov SCBPTR, DISCONNECTED_SCBH; /* Initialize SCBPTR */ 204968087Sgibbs mvi ARG_2, SCB_LIST_NULL; /* Head of list */ 205063457Sgibbs jmp findSCB_loop; 205139220SgibbsfindSCB_next: 205263457Sgibbs cmp SCB_NEXT, SCB_LIST_NULL je findSCB_notFound; 205368087Sgibbs mov ARG_2, SCBPTR; 205439220Sgibbs mov SCBPTR,SCB_NEXT; 205523168SgibbsfindSCB_loop: 205663457Sgibbs cmp SCB_TAG, A jne findSCB_next; 205719164Sgibbsrem_scb_from_disc_list: 205839220Sgibbs cmp ARG_2, SCB_LIST_NULL je rHead; 205939220Sgibbs mov DINDEX, SCB_NEXT; 206068087Sgibbs mov SINDEX, SCBPTR; 206139220Sgibbs mov SCBPTR, ARG_2; 206239220Sgibbs mov SCB_NEXT, DINDEX; 206323925Sgibbs mov SCBPTR, SINDEX ret; 206415328SgibbsrHead: 206523925Sgibbs mov DISCONNECTED_SCBH,SCB_NEXT ret; 206695378SgibbsEND_CRITICAL; 206768087SgibbsfindSCB_notFound: 206868087Sgibbs /* 206968087Sgibbs * We didn't find it. Page in the SCB. 207068087Sgibbs */ 207168087Sgibbs mov ARG_1, A; /* Save tag */ 207268087Sgibbs mov ALLZEROS call get_free_or_disc_scb; 207368087Sgibbs mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET; 207468087Sgibbs mov ARG_1 jmp dma_scb; 207568087Sgibbs} 20764568Sgibbs 207739220Sgibbs/* 207839220Sgibbs * Prepare the hardware to post a byte to host memory given an 207963457Sgibbs * index of (A + (256 * SINDEX)) and a base address of SHARED_DATA_ADDR. 208039220Sgibbs */ 208139220Sgibbspost_byte_setup: 208239220Sgibbs mov ARG_2, SINDEX; 208339220Sgibbs if ((ahc->features & AHC_CMD_CHAN) != 0) { 208439220Sgibbs mvi DINDEX, CCHADDR; 208563457Sgibbs mvi SHARED_DATA_ADDR call set_1byte_addr; 208639220Sgibbs mvi CCHCNT, 1; 208739220Sgibbs mvi CCSCBCTL, CCSCBRESET ret; 208839220Sgibbs } else { 208939220Sgibbs mvi DINDEX, HADDR; 209063457Sgibbs mvi SHARED_DATA_ADDR call set_1byte_addr; 209163457Sgibbs mvi 1 call set_hcnt; 209239220Sgibbs mvi DFCNTRL, FIFORESET ret; 209339220Sgibbs } 209439220Sgibbs 209539220Sgibbspost_byte: 209639220Sgibbs if ((ahc->features & AHC_CMD_CHAN) != 0) { 209739220Sgibbs bmov CCSCBRAM, SINDEX, 1; 209839220Sgibbs or CCSCBCTL, CCSCBEN|CCSCBRESET; 209939220Sgibbs test CCSCBCTL, CCSCBDONE jz .; 210039220Sgibbs clr CCSCBCTL ret; 210139220Sgibbs } else { 210239220Sgibbs mov DFDAT, SINDEX; 210339220Sgibbs or DFCNTRL, HDMAEN|FIFOFLUSH; 210439220Sgibbs jmp dma_finish; 210539220Sgibbs } 210639220Sgibbs 210757099Sgibbsphase_lock_perr: 210868402Sgibbs mvi PERR_DETECTED call set_seqint; 210939220Sgibbsphase_lock: 211057099Sgibbs /* 211157099Sgibbs * If there is a parity error, wait for the kernel to 211257099Sgibbs * see the interrupt and prepare our message response 211357099Sgibbs * before continuing. 211457099Sgibbs */ 211539220Sgibbs test SSTAT1, REQINIT jz phase_lock; 211657099Sgibbs test SSTAT1, SCSIPERR jnz phase_lock_perr; 211757099Sgibbsphase_lock_latch_phase: 211876634Sgibbs if ((ahc->features & AHC_DT) == 0) { 211976634Sgibbs and SCSISIGO, PHASE_MASK, SCSISIGI; 212076634Sgibbs } 212141646Sgibbs and LASTPHASE, PHASE_MASK, SCSISIGI ret; 212239220Sgibbs 212339220Sgibbsif ((ahc->features & AHC_CMD_CHAN) == 0) { 212463457Sgibbsset_hcnt: 212563457Sgibbs mov HCNT[0], SINDEX; 212663457Sgibbsclear_hcnt: 212763457Sgibbs clr HCNT[1]; 212863457Sgibbs clr HCNT[2] ret; 212963457Sgibbs 213019164Sgibbsset_stcnt_from_hcnt: 213123925Sgibbs mov STCNT[0], HCNT[0]; 213223925Sgibbs mov STCNT[1], HCNT[1]; 213323925Sgibbs mov STCNT[2], HCNT[2] ret; 21344568Sgibbs 213563457Sgibbsbcopy_8: 213663457Sgibbs mov DINDIR, SINDIR; 213719164Sgibbsbcopy_7: 213823925Sgibbs mov DINDIR, SINDIR; 213923925Sgibbs mov DINDIR, SINDIR; 214019164Sgibbsbcopy_5: 214123925Sgibbs mov DINDIR, SINDIR; 214219164Sgibbsbcopy_4: 214323925Sgibbs mov DINDIR, SINDIR; 214419164Sgibbsbcopy_3: 214523925Sgibbs mov DINDIR, SINDIR; 214623925Sgibbs mov DINDIR, SINDIR; 214723925Sgibbs mov DINDIR, SINDIR ret; 214839220Sgibbs} 21494568Sgibbs 215068087Sgibbsif ((ahc->flags & AHC_TARGETROLE) != 0) { 215139220Sgibbs/* 215239220Sgibbs * Setup addr assuming that A is an index into 215339220Sgibbs * an array of 32byte objects, SINDEX contains 215439220Sgibbs * the base address of that array, and DINDEX 215539220Sgibbs * contains the base address of the location 215639220Sgibbs * to store the indexed address. 215739220Sgibbs */ 215839220Sgibbsset_32byte_addr: 215939220Sgibbs shr ARG_2, 3, A; 216039220Sgibbs shl A, 5; 216139220Sgibbs jmp set_1byte_addr; 216239220Sgibbs} 216339220Sgibbs 216439220Sgibbs/* 216539220Sgibbs * Setup addr assuming that A is an index into 216639220Sgibbs * an array of 64byte objects, SINDEX contains 216739220Sgibbs * the base address of that array, and DINDEX 216839220Sgibbs * contains the base address of the location 216939220Sgibbs * to store the indexed address. 217039220Sgibbs */ 217139220Sgibbsset_64byte_addr: 217239220Sgibbs shr ARG_2, 2, A; 217339220Sgibbs shl A, 6; 217439220Sgibbs 217539220Sgibbs/* 217663457Sgibbs * Setup addr assuming that A + (ARG_2 * 256) is an 217739220Sgibbs * index into an array of 1byte objects, SINDEX contains 217839220Sgibbs * the base address of that array, and DINDEX contains 217939220Sgibbs * the base address of the location to store the computed 218039220Sgibbs * address. 218139220Sgibbs */ 218239220Sgibbsset_1byte_addr: 218339220Sgibbs add DINDIR, A, SINDIR; 218439220Sgibbs mov A, ARG_2; 218539220Sgibbs adc DINDIR, A, SINDIR; 218639220Sgibbs clr A; 218739220Sgibbs adc DINDIR, A, SINDIR; 218839220Sgibbs adc DINDIR, A, SINDIR ret; 218939220Sgibbs 219039220Sgibbs/* 219195378Sgibbs * Either post or fetch an SCB from host memory based on the 219239220Sgibbs * DIRECTION bit in DMAPARAMS. The host SCB index is in SINDEX. 219339220Sgibbs */ 219419164Sgibbsdma_scb: 219539220Sgibbs mov A, SINDEX; 219639220Sgibbs if ((ahc->features & AHC_CMD_CHAN) != 0) { 219739220Sgibbs mvi DINDEX, CCHADDR; 219839220Sgibbs mvi HSCB_ADDR call set_64byte_addr; 219939220Sgibbs mov CCSCBPTR, SCBPTR; 220039220Sgibbs test DMAPARAMS, DIRECTION jz dma_scb_tohost; 220171390Sgibbs if ((ahc->flags & AHC_SCB_BTT) != 0) { 220265942Sgibbs mvi CCHCNT, SCB_DOWNLOAD_SIZE_64; 220365942Sgibbs } else { 220465942Sgibbs mvi CCHCNT, SCB_DOWNLOAD_SIZE; 220565942Sgibbs } 220639220Sgibbs mvi CCSCBCTL, CCARREN|CCSCBEN|CCSCBDIR|CCSCBRESET; 220739220Sgibbs cmp CCSCBCTL, CCSCBDONE|ARRDONE|CCARREN|CCSCBEN|CCSCBDIR jne .; 220839220Sgibbs jmp dma_scb_finish; 220939220Sgibbsdma_scb_tohost: 221065942Sgibbs mvi CCHCNT, SCB_UPLOAD_SIZE; 221165942Sgibbs if ((ahc->features & AHC_ULTRA2) == 0) { 221239220Sgibbs mvi CCSCBCTL, CCSCBRESET; 221365942Sgibbs bmov CCSCBRAM, SCB_BASE, SCB_UPLOAD_SIZE; 221439220Sgibbs or CCSCBCTL, CCSCBEN|CCSCBRESET; 221568579Sgibbs test CCSCBCTL, CCSCBDONE jz .; 221665942Sgibbs } else if ((ahc->bugs & AHC_SCBCHAN_UPLOAD_BUG) != 0) { 221765942Sgibbs mvi CCSCBCTL, CCARREN|CCSCBRESET; 221865942Sgibbs cmp CCSCBCTL, ARRDONE|CCARREN jne .; 221965942Sgibbs mvi CCHCNT, SCB_UPLOAD_SIZE; 222065942Sgibbs mvi CCSCBCTL, CCSCBEN|CCSCBRESET; 222165942Sgibbs cmp CCSCBCTL, CCSCBDONE|CCSCBEN jne .; 222239220Sgibbs } else { 222339220Sgibbs mvi CCSCBCTL, CCARREN|CCSCBEN|CCSCBRESET; 222439220Sgibbs cmp CCSCBCTL, CCSCBDONE|ARRDONE|CCARREN|CCSCBEN jne .; 222539220Sgibbs } 222639220Sgibbsdma_scb_finish: 222739220Sgibbs clr CCSCBCTL; 222839220Sgibbs test CCSCBCTL, CCARREN|CCSCBEN jnz .; 222939220Sgibbs ret; 223039220Sgibbs } else { 223139220Sgibbs mvi DINDEX, HADDR; 223239220Sgibbs mvi HSCB_ADDR call set_64byte_addr; 223365942Sgibbs mvi SCB_DOWNLOAD_SIZE call set_hcnt; 223439220Sgibbs mov DFCNTRL, DMAPARAMS; 223539220Sgibbs test DMAPARAMS, DIRECTION jnz dma_scb_fromhost; 223639220Sgibbs /* Fill it with the SCB data */ 223724175Sgibbscopy_scb_tofifo: 223865942Sgibbs mvi SINDEX, SCB_BASE; 223965942Sgibbs add A, SCB_DOWNLOAD_SIZE, SINDEX; 224024175Sgibbscopy_scb_tofifo_loop: 224165942Sgibbs call copy_to_fifo_8; 224239220Sgibbs cmp SINDEX, A jne copy_scb_tofifo_loop; 224339220Sgibbs or DFCNTRL, HDMAEN|FIFOFLUSH; 224465942Sgibbs jmp dma_finish; 224519164Sgibbsdma_scb_fromhost: 224665942Sgibbs mvi DINDEX, SCB_BASE; 224765942Sgibbs if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0) { 224865942Sgibbs /* 224965942Sgibbs * The PCI module will only issue a PCI 225065942Sgibbs * retry if the data FIFO is empty. If the 225165942Sgibbs * host disconnects in the middle of a 225265942Sgibbs * transfer, we must empty the fifo of all 225365942Sgibbs * available data to force the chip to 225465942Sgibbs * continue the transfer. This does not 225565942Sgibbs * happen for SCSI transfers as the SCSI module 2256102673Sgibbs * will drain the FIFO as data are made available. 225772325Sgibbs * When the hang occurs, we know that a multiple 2258102673Sgibbs * of 8 bytes is in the FIFO because the PCI 225965942Sgibbs * module has an 8 byte input latch that only 226065942Sgibbs * dumps to the FIFO when HCNT == 0 or the 226165942Sgibbs * latch is full. 226265942Sgibbs */ 226372325Sgibbs clr A; 226474507Sgibbs /* Wait for at least 8 bytes of data to arrive. */ 226565942Sgibbsdma_scb_hang_fifo: 226674434Sgibbs test DFSTATUS, FIFOQWDEMP jnz dma_scb_hang_fifo; 226765942Sgibbsdma_scb_hang_wait: 226865942Sgibbs test DFSTATUS, MREQPEND jnz dma_scb_hang_wait; 226965942Sgibbs test DFSTATUS, HDONE jnz dma_scb_hang_dma_done; 227065942Sgibbs test DFSTATUS, HDONE jnz dma_scb_hang_dma_done; 227165942Sgibbs test DFSTATUS, HDONE jnz dma_scb_hang_dma_done; 227265942Sgibbs /* 227372325Sgibbs * The PCI module no longer intends to perform 227474507Sgibbs * a PCI transaction. Drain the fifo. 227565942Sgibbs */ 227681170Sgibbsdma_scb_hang_dma_drain_fifo: 227781170Sgibbs not A, HCNT; 227881170Sgibbs add A, SCB_DOWNLOAD_SIZE+SCB_BASE+1; 227981170Sgibbs and A, ~0x7; 228081170Sgibbs mov DINDIR,DFDAT; 228181170Sgibbs cmp DINDEX, A jne . - 1; 228281170Sgibbs cmp DINDEX, SCB_DOWNLOAD_SIZE+SCB_BASE 228381170Sgibbs je dma_finish_nowait; 228481170Sgibbs /* Restore A as the lines left to transfer. */ 228581170Sgibbs add A, -SCB_BASE, DINDEX; 228681170Sgibbs shr A, 3; 228765942Sgibbs jmp dma_scb_hang_fifo; 228865942Sgibbsdma_scb_hang_dma_done: 228965942Sgibbs and DFCNTRL, ~HDMAEN; 229065942Sgibbs test DFCNTRL, HDMAEN jnz .; 229172325Sgibbs add SEQADDR0, A; 229265942Sgibbs } else { 229365942Sgibbs call dma_finish; 229465942Sgibbs } 229572325Sgibbs call dfdat_in_8; 229672325Sgibbs call dfdat_in_8; 229772325Sgibbs call dfdat_in_8; 229865942Sgibbsdfdat_in_8: 229965942Sgibbs mov DINDIR,DFDAT; 230019164Sgibbsdfdat_in_7: 230139220Sgibbs mov DINDIR,DFDAT; 230239220Sgibbs mov DINDIR,DFDAT; 230339220Sgibbs mov DINDIR,DFDAT; 230439220Sgibbs mov DINDIR,DFDAT; 230539220Sgibbs mov DINDIR,DFDAT; 230665942Sgibbsdfdat_in_2: 230739220Sgibbs mov DINDIR,DFDAT; 230839220Sgibbs mov DINDIR,DFDAT ret; 230939220Sgibbs } 231019164Sgibbs 231165942Sgibbscopy_to_fifo_8: 231265942Sgibbs mov DFDAT,SINDIR; 231365942Sgibbs mov DFDAT,SINDIR; 231463457Sgibbscopy_to_fifo_6: 231563457Sgibbs mov DFDAT,SINDIR; 231663457Sgibbscopy_to_fifo_5: 231763457Sgibbs mov DFDAT,SINDIR; 231863457Sgibbscopy_to_fifo_4: 231963457Sgibbs mov DFDAT,SINDIR; 232063457Sgibbs mov DFDAT,SINDIR; 232163457Sgibbs mov DFDAT,SINDIR; 232263457Sgibbs mov DFDAT,SINDIR ret; 232339220Sgibbs 232413177Sgibbs/* 232519164Sgibbs * Wait for DMA from host memory to data FIFO to complete, then disable 232619164Sgibbs * DMA and wait for it to acknowledge that it's off. 232713177Sgibbs */ 232819164Sgibbsdma_finish: 232923925Sgibbs test DFSTATUS,HDONE jz dma_finish; 233074434Sgibbsdma_finish_nowait: 233122234Sgibbs /* Turn off DMA */ 233223925Sgibbs and DFCNTRL, ~HDMAEN; 233323925Sgibbs test DFCNTRL, HDMAEN jnz .; 233423925Sgibbs ret; 23359928Sgibbs 233674094Sgibbs/* 233774094Sgibbs * Restore an SCB that failed to match an incoming reselection 233874094Sgibbs * to the correct/safe state. If the SCB is for a disconnected 233974094Sgibbs * transaction, it must be returned to the disconnected list. 234074094Sgibbs * If it is not in the disconnected state, it must be free. 234174094Sgibbs */ 234274094Sgibbscleanup_scb: 234374094Sgibbs if ((ahc->flags & AHC_PAGESCBS) != 0) { 234474094Sgibbs test SCB_CONTROL,DISCONNECTED jnz add_scb_to_disc_list; 234574094Sgibbs } 234623925Sgibbsadd_scb_to_free_list: 234739220Sgibbs if ((ahc->flags & AHC_PAGESCBS) != 0) { 234895378SgibbsBEGIN_CRITICAL; 234939220Sgibbs mov SCB_NEXT, FREE_SCBH; 235057099Sgibbs mvi SCB_TAG, SCB_LIST_NULL; 235157099Sgibbs mov FREE_SCBH, SCBPTR ret; 235295378SgibbsEND_CRITICAL; 235357099Sgibbs } else { 235457099Sgibbs mvi SCB_TAG, SCB_LIST_NULL ret; 235539220Sgibbs } 23564568Sgibbs 235779874Sgibbsif ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 235879874Sgibbsset_hhaddr: 235979874Sgibbs or DSCOMMAND1, HADDLDSEL0; 236079874Sgibbs and HADDR, SG_HIGH_ADDR_BITS, SINDEX; 236179874Sgibbs and DSCOMMAND1, ~HADDLDSEL0 ret; 236279874Sgibbs} 236379874Sgibbs 236439220Sgibbsif ((ahc->flags & AHC_PAGESCBS) != 0) { 236519164Sgibbsget_free_or_disc_scb: 236695378SgibbsBEGIN_CRITICAL; 236723925Sgibbs cmp FREE_SCBH, SCB_LIST_NULL jne dequeue_free_scb; 236823925Sgibbs cmp DISCONNECTED_SCBH, SCB_LIST_NULL jne dequeue_disc_scb; 236919623Sgibbsreturn_error: 237068402Sgibbs mvi NO_FREE_SCB call set_seqint; 237123925Sgibbs mvi SINDEX, SCB_LIST_NULL ret; 237219623Sgibbsdequeue_disc_scb: 237323925Sgibbs mov SCBPTR, DISCONNECTED_SCBH; 237468579Sgibbs mov DISCONNECTED_SCBH, SCB_NEXT; 237595378SgibbsEND_CRITICAL; 237623925Sgibbs mvi DMAPARAMS, FIFORESET; 237768579Sgibbs mov SCB_TAG jmp dma_scb; 237895378SgibbsBEGIN_CRITICAL; 237919164Sgibbsdequeue_free_scb: 238023925Sgibbs mov SCBPTR, FREE_SCBH; 238123925Sgibbs mov FREE_SCBH, SCB_NEXT ret; 238295378SgibbsEND_CRITICAL; 23834568Sgibbs 238419164Sgibbsadd_scb_to_disc_list: 238513177Sgibbs/* 238619164Sgibbs * Link this SCB into the DISCONNECTED list. This list holds the 238719164Sgibbs * candidates for paging out an SCB if one is needed for a new command. 238819164Sgibbs * Modifying the disconnected list is a critical(pause dissabled) section. 238913177Sgibbs */ 239095378SgibbsBEGIN_CRITICAL; 239123925Sgibbs mov SCB_NEXT, DISCONNECTED_SCBH; 239239220Sgibbs mov DISCONNECTED_SCBH, SCBPTR ret; 239395378SgibbsEND_CRITICAL; 239465942Sgibbs} 239568402Sgibbsset_seqint: 239668402Sgibbs mov INTSTAT, SINDEX; 239768402Sgibbs nop; 239863457Sgibbsreturn: 239963457Sgibbs ret; 2400