aic79xx.reg revision 115407
197883Sgibbs/* 297883Sgibbs * Aic79xx register and scratch ram definitions. 397883Sgibbs * 497883Sgibbs * Copyright (c) 1994-2001 Justin T. Gibbs. 5102681Sgibbs * Copyright (c) 2000-2002 Adaptec Inc. 697883Sgibbs * All rights reserved. 797883Sgibbs * 897883Sgibbs * Redistribution and use in source and binary forms, with or without 997883Sgibbs * modification, are permitted provided that the following conditions 1097883Sgibbs * are met: 1197883Sgibbs * 1. Redistributions of source code must retain the above copyright 1297883Sgibbs * notice, this list of conditions, and the following disclaimer, 1397883Sgibbs * without modification. 1497883Sgibbs * 2. Redistributions in binary form must reproduce at minimum a disclaimer 1597883Sgibbs * substantially similar to the "NO WARRANTY" disclaimer below 1697883Sgibbs * ("Disclaimer") and any redistribution must be conditioned upon 1797883Sgibbs * including a substantially similar Disclaimer requirement for further 1897883Sgibbs * binary redistribution. 1997883Sgibbs * 3. Neither the names of the above-listed copyright holders nor the names 2097883Sgibbs * of any contributors may be used to endorse or promote products derived 2197883Sgibbs * from this software without specific prior written permission. 2297883Sgibbs * 2397883Sgibbs * Alternatively, this software may be distributed under the terms of the 2497883Sgibbs * GNU General Public License ("GPL") version 2 as published by the Free 2597883Sgibbs * Software Foundation. 2697883Sgibbs * 2797883Sgibbs * NO WARRANTY 2897883Sgibbs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2997883Sgibbs * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3097883Sgibbs * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 3197883Sgibbs * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3297883Sgibbs * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 3397883Sgibbs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 3497883Sgibbs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 3597883Sgibbs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 3697883Sgibbs * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 3797883Sgibbs * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3897883Sgibbs * POSSIBILITY OF SUCH DAMAGES. 3997883Sgibbs * 4097883Sgibbs * $FreeBSD: head/sys/dev/aic7xxx/aic79xx.reg 115407 2003-05-30 02:14:22Z scottl $ 4197883Sgibbs */ 42115407SscottlVERSION = "$Id: aic79xx.reg,v 1.13 2003/05/26 21:26:51 gibbs Exp $" 4397883Sgibbs 4497883Sgibbs/* 4597883Sgibbs * This file is processed by the aic7xxx_asm utility for use in assembling 4697883Sgibbs * firmware for the aic79xx family of SCSI host adapters as well as to generate 4797883Sgibbs * a C header file for use in the kernel portion of the Aic79xx driver. 4897883Sgibbs */ 4997883Sgibbs 5097883Sgibbs/* Register window Modes */ 5197883Sgibbs#define M_DFF0 0 5297883Sgibbs#define M_DFF1 1 5397883Sgibbs#define M_CCHAN 2 5497883Sgibbs#define M_SCSI 3 5597883Sgibbs#define M_CFG 4 5697883Sgibbs#define M_DST_SHIFT 4 5797883Sgibbs 5897883Sgibbs#define MK_MODE(src, dst) ((src) | ((dst) << M_DST_SHIFT)) 59104023Sgibbs#define SET_MODE(src, dst) \ 60104023Sgibbs SET_SRC_MODE src; \ 61104023Sgibbs SET_DST_MODE dst; \ 62104023Sgibbs if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ 63104023Sgibbs mvi MK_MODE(src, dst) call set_mode_work_around; \ 64104023Sgibbs } else { \ 65104023Sgibbs mvi MODE_PTR, MK_MODE(src, dst); \ 66104023Sgibbs } 6797883Sgibbs 68104023Sgibbs#define TOGGLE_DFF_MODE \ 69104023Sgibbs if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ 70104023Sgibbs call toggle_dff_mode_work_around; \ 71104023Sgibbs } else { \ 72104023Sgibbs xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1); \ 73104023Sgibbs } 74104023Sgibbs 75107441Sscottl#define RESTORE_MODE(mode) \ 76107441Sscottl if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ 77107441Sscottl mov mode call set_mode_work_around; \ 78107441Sscottl } else { \ 79107441Sscottl mov MODE_PTR, mode; \ 80107441Sscottl } 81104023Sgibbs 82107441Sscottl#define SET_SEQINTCODE(code) \ 83107441Sscottl if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { \ 84107441Sscottl mvi code call set_seqint_work_around; \ 85107441Sscottl } else { \ 86107441Sscottl mvi SEQINTCODE, code; \ 87107441Sscottl } 88107441Sscottl 8997883Sgibbs/* 9097883Sgibbs * Mode Pointer 9197883Sgibbs * Controls which of the 5, 512byte, address spaces should be used 9297883Sgibbs * as the source and destination of any register accesses in our 9397883Sgibbs * register window. 9497883Sgibbs */ 9597883Sgibbsregister MODE_PTR { 9697883Sgibbs address 0x000 9797883Sgibbs access_mode RW 98102681Sgibbs field DST_MODE 0x70 99102681Sgibbs field SRC_MODE 0x07 10097883Sgibbs mode_pointer 10197883Sgibbs} 10297883Sgibbs 10397883Sgibbsconst SRC_MODE_SHIFT 0 10497883Sgibbsconst DST_MODE_SHIFT 4 10597883Sgibbs 10697883Sgibbs/* 10797883Sgibbs * Host Interrupt Status 10897883Sgibbs */ 10997883Sgibbsregister INTSTAT { 11097883Sgibbs address 0x001 11197883Sgibbs access_mode RW 112102681Sgibbs field HWERRINT 0x80 113102681Sgibbs field BRKADRINT 0x40 114102681Sgibbs field SWTMINT 0x20 115102681Sgibbs field PCIINT 0x10 116102681Sgibbs field SCSIINT 0x08 117102681Sgibbs field SEQINT 0x04 118102681Sgibbs field CMDCMPLT 0x02 119102681Sgibbs field SPLTINT 0x01 12097883Sgibbs mask INT_PEND 0xFF 12197883Sgibbs} 12297883Sgibbs 12397883Sgibbs/* 12497883Sgibbs * Sequencer Interrupt Code 12597883Sgibbs */ 12697883Sgibbsregister SEQINTCODE { 12797883Sgibbs address 0x002 12897883Sgibbs access_mode RW 129102681Sgibbs field { 130107441Sscottl NO_SEQINT, /* No seqint pending. */ 131107441Sscottl BAD_PHASE, /* unknown scsi bus phase */ 132102681Sgibbs SEND_REJECT, /* sending a message reject */ 133102681Sgibbs PROTO_VIOLATION, /* Protocol Violation */ 134102681Sgibbs NO_MATCH, /* no cmd match for reconnect */ 135102681Sgibbs IGN_WIDE_RES, /* Complex IGN Wide Res Msg */ 136102681Sgibbs PDATA_REINIT, /* 13797883Sgibbs * Returned to data phase 13897883Sgibbs * that requires data 13997883Sgibbs * transfer pointers to be 14097883Sgibbs * recalculated from the 14197883Sgibbs * transfer residual. 14297883Sgibbs */ 143102681Sgibbs HOST_MSG_LOOP, /* 14497883Sgibbs * The bus is ready for the 14597883Sgibbs * host to perform another 14697883Sgibbs * message transaction. This 14797883Sgibbs * mechanism is used for things 14897883Sgibbs * like sync/wide negotiation 14997883Sgibbs * that require a kernel based 15097883Sgibbs * message state engine. 15197883Sgibbs */ 152102681Sgibbs BAD_STATUS, /* Bad status from target */ 153102681Sgibbs DATA_OVERRUN, /* 15497883Sgibbs * Target attempted to write 15597883Sgibbs * beyond the bounds of its 15697883Sgibbs * command. 15797883Sgibbs */ 158102681Sgibbs MKMSG_FAILED, /* 15997883Sgibbs * Target completed command 16097883Sgibbs * without honoring our ATN 16197883Sgibbs * request to issue a message. 16297883Sgibbs */ 163102681Sgibbs MISSED_BUSFREE, /* 16497883Sgibbs * The sequencer never saw 16597883Sgibbs * the bus go free after 16697883Sgibbs * either a command complete 16797883Sgibbs * or disconnect message. 16897883Sgibbs */ 169102681Sgibbs DUMP_CARD_STATE, 170102681Sgibbs ILLEGAL_PHASE, 171102681Sgibbs INVALID_SEQINT, 172102681Sgibbs CFG4ISTAT_INTR, 173102681Sgibbs STATUS_OVERRUN, 174102681Sgibbs CFG4OVERRUN, 175107441Sscottl ENTERING_NONPACK, 176109588Sgibbs TASKMGMT_FUNC_COMPLETE, /* 177109588Sgibbs * Task management function 178109588Sgibbs * request completed with 179109588Sgibbs * an expected busfree. 180109588Sgibbs */ 181109588Sgibbs TASKMGMT_CMD_CMPLT_OKAY, /* 182109588Sgibbs * A command with a non-zero 183109588Sgibbs * task management function 184109588Sgibbs * has completed via the normal 185109588Sgibbs * command completion method 186109588Sgibbs * for commands with a zero 187109588Sgibbs * task management function. 188109588Sgibbs * This happens when an attempt 189109588Sgibbs * to abort a command loses 190109588Sgibbs * the race for the command to 191109588Sgibbs * complete normally. 192109588Sgibbs */ 193107441Sscottl TRACEPOINT0, 194107441Sscottl TRACEPOINT1, 195107441Sscottl TRACEPOINT2, 196107441Sscottl TRACEPOINT3, 197114623Sgibbs SAW_HWERR, 198114623Sgibbs BAD_SCB_STATUS 199102681Sgibbs } 20097883Sgibbs} 20197883Sgibbs 20297883Sgibbs/* 20397883Sgibbs * Clear Host Interrupt 20497883Sgibbs */ 20597883Sgibbsregister CLRINT { 20697883Sgibbs address 0x003 20797883Sgibbs access_mode WO 208102681Sgibbs field CLRHWERRINT 0x80 /* Rev B or greater */ 209102681Sgibbs field CLRBRKADRINT 0x40 210102681Sgibbs field CLRSWTMINT 0x20 211107623Sscottl field CLRPCIINT 0x10 212102681Sgibbs field CLRSCSIINT 0x08 213102681Sgibbs field CLRSEQINT 0x04 214102681Sgibbs field CLRCMDINT 0x02 215102681Sgibbs field CLRSPLTINT 0x01 21697883Sgibbs} 21797883Sgibbs 21897883Sgibbs/* 21997883Sgibbs * Error Register 22097883Sgibbs */ 22197883Sgibbsregister ERROR { 22297883Sgibbs address 0x004 22397883Sgibbs access_mode RO 224102681Sgibbs field CIOPARERR 0x80 225102681Sgibbs field CIOACCESFAIL 0x40 /* Rev B or greater */ 226102681Sgibbs field MPARERR 0x20 227102681Sgibbs field DPARERR 0x10 228102681Sgibbs field SQPARERR 0x08 229102681Sgibbs field ILLOPCODE 0x04 230102681Sgibbs field DSCTMOUT 0x02 23197883Sgibbs} 23297883Sgibbs 23397883Sgibbs/* 23497883Sgibbs * Clear Error 23597883Sgibbs */ 23697883Sgibbsregister CLRERR { 23797883Sgibbs address 0x004 23897883Sgibbs access_mode WO 239102681Sgibbs field CLRCIOPARERR 0x80 240102681Sgibbs field CLRCIOACCESFAIL 0x40 /* Rev B or greater */ 241102681Sgibbs field CLRMPARERR 0x20 242102681Sgibbs field CLRDPARERR 0x10 243102681Sgibbs field CLRSQPARERR 0x08 244102681Sgibbs field CLRILLOPCODE 0x04 245102681Sgibbs field CLRDSCTMOUT 0x02 24697883Sgibbs} 24797883Sgibbs 24897883Sgibbs/* 24997883Sgibbs * Host Control Register 25097883Sgibbs * Overall host control of the device. 25197883Sgibbs */ 25297883Sgibbsregister HCNTRL { 25397883Sgibbs address 0x005 25497883Sgibbs access_mode RW 255102681Sgibbs field SEQ_RESET 0x80 /* Rev B or greater */ 256102681Sgibbs field POWRDN 0x40 257102681Sgibbs field SWINT 0x10 258102681Sgibbs field SWTIMER_START_B 0x08 /* Rev B or greater */ 259102681Sgibbs field PAUSE 0x04 260102681Sgibbs field INTEN 0x02 261102681Sgibbs field CHIPRST 0x01 262102681Sgibbs field CHIPRSTACK 0x01 26397883Sgibbs} 26497883Sgibbs 26597883Sgibbs/* 26697883Sgibbs * Host New SCB Queue Offset 26797883Sgibbs */ 26897883Sgibbsregister HNSCB_QOFF { 26997883Sgibbs address 0x006 27097883Sgibbs access_mode RW 27197883Sgibbs size 2 27297883Sgibbs} 27397883Sgibbs 27497883Sgibbs/* 27597883Sgibbs * Host Empty SCB Queue Offset 27697883Sgibbs */ 27797883Sgibbsregister HESCB_QOFF { 27897883Sgibbs address 0x008 27997883Sgibbs access_mode RW 28097883Sgibbs} 28197883Sgibbs 28297883Sgibbs/* 28397883Sgibbs * Host Mailbox 28497883Sgibbs */ 28597883Sgibbsregister HS_MAILBOX { 286109588Sgibbs address 0x00B 28797883Sgibbs access_mode RW 28897883Sgibbs mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */ 289115329Sgibbs mask ENINT_COALESCE 0x40 /* Perform interrupt coalescing */ 29097883Sgibbs} 29197883Sgibbs 29297883Sgibbs/* 29397883Sgibbs * Sequencer Interupt Status 29497883Sgibbs */ 29597883Sgibbsregister SEQINTSTAT { 296109588Sgibbs address 0x00C 29797883Sgibbs access_mode RO 298102681Sgibbs field SEQ_SWTMRTO 0x10 299102681Sgibbs field SEQ_SEQINT 0x08 300102681Sgibbs field SEQ_SCSIINT 0x04 301102681Sgibbs field SEQ_PCIINT 0x02 302102681Sgibbs field SEQ_SPLTINT 0x01 30397883Sgibbs} 30497883Sgibbs 30597883Sgibbs/* 30697883Sgibbs * Clear SEQ Interrupt 30797883Sgibbs */ 30897883Sgibbsregister CLRSEQINTSTAT { 309109588Sgibbs address 0x00C 31097883Sgibbs access_mode WO 311102681Sgibbs field CLRSEQ_SWTMRTO 0x10 312102681Sgibbs field CLRSEQ_SEQINT 0x08 313102681Sgibbs field CLRSEQ_SCSIINT 0x04 314102681Sgibbs field CLRSEQ_PCIINT 0x02 315102681Sgibbs field CLRSEQ_SPLTINT 0x01 31697883Sgibbs} 31797883Sgibbs 31897883Sgibbs/* 31997883Sgibbs * Software Timer 32097883Sgibbs */ 32197883Sgibbsregister SWTIMER { 322109588Sgibbs address 0x00E 32397883Sgibbs access_mode RW 32497883Sgibbs size 2 32597883Sgibbs} 32697883Sgibbs 32797883Sgibbs/* 32897883Sgibbs * SEQ New SCB Queue Offset 32997883Sgibbs */ 33097883Sgibbsregister SNSCB_QOFF { 33197883Sgibbs address 0x010 33297883Sgibbs access_mode RW 33397883Sgibbs size 2 33497883Sgibbs modes M_CCHAN 33597883Sgibbs} 33697883Sgibbs 33797883Sgibbs/* 33897883Sgibbs * SEQ Empty SCB Queue Offset 33997883Sgibbs */ 34097883Sgibbsregister SESCB_QOFF { 34197883Sgibbs address 0x012 34297883Sgibbs access_mode RW 34397883Sgibbs modes M_CCHAN 34497883Sgibbs} 34597883Sgibbs 34697883Sgibbs/* 34797883Sgibbs * SEQ Done SCB Queue Offset 34897883Sgibbs */ 34997883Sgibbsregister SDSCB_QOFF { 35097883Sgibbs address 0x014 35197883Sgibbs access_mode RW 35297883Sgibbs modes M_CCHAN 35397883Sgibbs size 2 35497883Sgibbs} 35597883Sgibbs 35697883Sgibbs/* 35797883Sgibbs * Queue Offset Control & Status 35897883Sgibbs */ 35997883Sgibbsregister QOFF_CTLSTA { 36097883Sgibbs address 0x016 36197883Sgibbs access_mode RW 36297883Sgibbs modes M_CCHAN 363102681Sgibbs field EMPTY_SCB_AVAIL 0x80 364102681Sgibbs field NEW_SCB_AVAIL 0x40 365102681Sgibbs field SDSCB_ROLLOVR 0x20 366102681Sgibbs field HS_MAILBOX_ACT 0x10 367102681Sgibbs field SCB_QSIZE 0x0F { 368102681Sgibbs SCB_QSIZE_4, 369102681Sgibbs SCB_QSIZE_8, 370102681Sgibbs SCB_QSIZE_16, 371102681Sgibbs SCB_QSIZE_32, 372102681Sgibbs SCB_QSIZE_64, 373102681Sgibbs SCB_QSIZE_128, 374102681Sgibbs SCB_QSIZE_256, 375102681Sgibbs SCB_QSIZE_512, 376102681Sgibbs SCB_QSIZE_1024, 377102681Sgibbs SCB_QSIZE_2048, 378102681Sgibbs SCB_QSIZE_4096, 379102681Sgibbs SCB_QSIZE_8192, 380102681Sgibbs SCB_QSIZE_16384 381102681Sgibbs } 38297883Sgibbs} 38397883Sgibbs 38497883Sgibbs/* 38597883Sgibbs * Interrupt Control 38697883Sgibbs */ 38797883Sgibbsregister INTCTL { 38897883Sgibbs address 0x018 38997883Sgibbs access_mode RW 390102681Sgibbs field SWTMINTMASK 0x80 391102681Sgibbs field SWTMINTEN 0x40 392102681Sgibbs field SWTIMER_START 0x20 393102681Sgibbs field AUTOCLRCMDINT 0x10 394102681Sgibbs field PCIINTEN 0x08 395102681Sgibbs field SCSIINTEN 0x04 396102681Sgibbs field SEQINTEN 0x02 397102681Sgibbs field SPLTINTEN 0x01 39897883Sgibbs} 39997883Sgibbs 40097883Sgibbs/* 40197883Sgibbs * Data FIFO Control 40297883Sgibbs */ 40397883Sgibbsregister DFCNTRL { 40497883Sgibbs address 0x019 40597883Sgibbs access_mode RW 40697883Sgibbs modes M_DFF0, M_DFF1 407102681Sgibbs field PRELOADEN 0x80 408107441Sscottl field SCSIENWRDIS 0x40 /* Rev B only. */ 409102681Sgibbs field SCSIEN 0x20 410102681Sgibbs field SCSIENACK 0x20 411102681Sgibbs field HDMAEN 0x08 412102681Sgibbs field HDMAENACK 0x08 413102681Sgibbs field DIRECTION 0x04 414102681Sgibbs field DIRECTIONACK 0x04 415102681Sgibbs field FIFOFLUSH 0x02 416102681Sgibbs field FIFOFLUSHACK 0x02 417102681Sgibbs field DIRECTIONEN 0x01 41897883Sgibbs} 41997883Sgibbs 42097883Sgibbs/* 42197883Sgibbs * Device Space Command 0 42297883Sgibbs */ 42397883Sgibbsregister DSCOMMAND0 { 42497883Sgibbs address 0x019 42597883Sgibbs access_mode RW 42697883Sgibbs modes M_CFG 427102681Sgibbs field CACHETHEN 0x80 /* Cache Threshold enable */ 428102681Sgibbs field DPARCKEN 0x40 /* Data Parity Check Enable */ 429102681Sgibbs field MPARCKEN 0x20 /* Memory Parity Check Enable */ 430102681Sgibbs field EXTREQLCK 0x10 /* External Request Lock */ 431102681Sgibbs field DISABLE_TWATE 0x02 /* Rev B or greater */ 432102681Sgibbs field CIOPARCKEN 0x01 /* Internal bus parity error enable */ 43397883Sgibbs} 43497883Sgibbs 43597883Sgibbs/* 43697883Sgibbs * Data FIFO Status 43797883Sgibbs */ 43897883Sgibbsregister DFSTATUS { 43997883Sgibbs address 0x01A 44097883Sgibbs access_mode RO 44197883Sgibbs modes M_DFF0, M_DFF1 442102681Sgibbs field PRELOAD_AVAIL 0x80 443102681Sgibbs field PKT_PRELOAD_AVAIL 0x40 444102681Sgibbs field MREQPEND 0x10 445102681Sgibbs field HDONE 0x08 446102681Sgibbs field DFTHRESH 0x04 447102681Sgibbs field FIFOFULL 0x02 448102681Sgibbs field FIFOEMP 0x01 44997883Sgibbs} 45097883Sgibbs 45197883Sgibbs/* 45297883Sgibbs * S/G Cache Pointer 45397883Sgibbs */ 45497883Sgibbsregister SG_CACHE_PRE { 45597883Sgibbs address 0x01B 45697883Sgibbs access_mode WO 45797883Sgibbs modes M_DFF0, M_DFF1 458102681Sgibbs field SG_ADDR_MASK 0xf8 459102681Sgibbs field ODD_SEG 0x04 460102681Sgibbs field LAST_SEG 0x02 46197883Sgibbs} 46297883Sgibbs 46397883Sgibbsregister SG_CACHE_SHADOW { 46497883Sgibbs address 0x01B 46597883Sgibbs access_mode RO 46697883Sgibbs modes M_DFF0, M_DFF1 467102681Sgibbs field SG_ADDR_MASK 0xf8 468102681Sgibbs field ODD_SEG 0x04 469102681Sgibbs field LAST_SEG 0x02 470102681Sgibbs field LAST_SEG_DONE 0x01 47197883Sgibbs} 47297883Sgibbs 47397883Sgibbs/* 47497883Sgibbs * Arbiter Control 47597883Sgibbs */ 47697883Sgibbsregister ARBCTL { 47797883Sgibbs address 0x01B 47897883Sgibbs access_mode RW 47997883Sgibbs modes M_CFG 480102681Sgibbs field RESET_HARB 0x80 481102681Sgibbs field RETRY_SWEN 0x08 482102681Sgibbs field USE_TIME 0x07 48397883Sgibbs} 48497883Sgibbs 48597883Sgibbs/* 48697883Sgibbs * Data Channel Host Address 48797883Sgibbs */ 48897883Sgibbsregister HADDR { 48997883Sgibbs address 0x070 49097883Sgibbs access_mode RW 49197883Sgibbs size 8 49297883Sgibbs modes M_DFF0, M_DFF1 49397883Sgibbs} 49497883Sgibbs 49597883Sgibbs/* 49697883Sgibbs * Host Overlay DMA Address 49797883Sgibbs */ 49897883Sgibbsregister HODMAADR { 49997883Sgibbs address 0x070 50097883Sgibbs access_mode RW 50197883Sgibbs size 8 50297883Sgibbs modes M_SCSI 50397883Sgibbs} 50497883Sgibbs 50597883Sgibbs/* 506107441Sscottl * PCI PLL Delay. 507107441Sscottl */ 508107441Sscottlregister PLLDELAY { 509107441Sscottl address 0x070 510107441Sscottl access_mode RW 511107441Sscottl size 1 512107441Sscottl modes M_CFG 513107441Sscottl field SPLIT_DROP_REQ 0x80 514107441Sscottl} 515107441Sscottl 516107441Sscottl/* 51797883Sgibbs * Data Channel Host Count 51897883Sgibbs */ 51997883Sgibbsregister HCNT { 52097883Sgibbs address 0x078 52197883Sgibbs access_mode RW 52297883Sgibbs size 3 52397883Sgibbs modes M_DFF0, M_DFF1 52497883Sgibbs} 52597883Sgibbs 52697883Sgibbs/* 52797883Sgibbs * Host Overlay DMA Count 52897883Sgibbs */ 52997883Sgibbsregister HODMACNT { 53097883Sgibbs address 0x078 53197883Sgibbs access_mode RW 53297883Sgibbs size 2 53397883Sgibbs modes M_SCSI 53497883Sgibbs} 53597883Sgibbs 53697883Sgibbs/* 53797883Sgibbs * Host Overlay DMA Enable 53897883Sgibbs */ 53997883Sgibbsregister HODMAEN { 54097883Sgibbs address 0x07A 54197883Sgibbs access_mode RW 54297883Sgibbs modes M_SCSI 54397883Sgibbs} 54497883Sgibbs 54597883Sgibbs/* 54697883Sgibbs * Scatter/Gather Host Address 54797883Sgibbs */ 54897883Sgibbsregister SGHADDR { 54997883Sgibbs address 0x07C 55097883Sgibbs access_mode RW 55197883Sgibbs size 8 55297883Sgibbs modes M_DFF0, M_DFF1 55397883Sgibbs} 55497883Sgibbs 55597883Sgibbs/* 55697883Sgibbs * SCB Host Address 55797883Sgibbs */ 55897883Sgibbsregister SCBHADDR { 55997883Sgibbs address 0x07C 56097883Sgibbs access_mode RW 56197883Sgibbs size 8 56297883Sgibbs modes M_CCHAN 56397883Sgibbs} 56497883Sgibbs 56597883Sgibbs/* 56697883Sgibbs * Scatter/Gather Host Count 56797883Sgibbs */ 56897883Sgibbsregister SGHCNT { 56997883Sgibbs address 0x084 57097883Sgibbs access_mode RW 57197883Sgibbs modes M_DFF0, M_DFF1 57297883Sgibbs} 57397883Sgibbs 57497883Sgibbs/* 57597883Sgibbs * SCB Host Count 57697883Sgibbs */ 57797883Sgibbsregister SCBHCNT { 57897883Sgibbs address 0x084 57997883Sgibbs access_mode RW 58097883Sgibbs modes M_CCHAN 58197883Sgibbs} 58297883Sgibbs 58397883Sgibbs/* 58497883Sgibbs * Data FIFO Threshold 58597883Sgibbs */ 58697883Sgibbsregister DFF_THRSH { 58797883Sgibbs address 0x088 58897883Sgibbs access_mode RW 58997883Sgibbs modes M_CFG 590102681Sgibbs field WR_DFTHRSH 0x70 { 591102681Sgibbs WR_DFTHRSH_MIN, 592102681Sgibbs WR_DFTHRSH_25, 593102681Sgibbs WR_DFTHRSH_50, 594102681Sgibbs WR_DFTHRSH_63, 595102681Sgibbs WR_DFTHRSH_75, 596102681Sgibbs WR_DFTHRSH_85, 597102681Sgibbs WR_DFTHRSH_90, 598102681Sgibbs WR_DFTHRSH_MAX 599102681Sgibbs } 600102681Sgibbs field RD_DFTHRSH 0x07 { 601102681Sgibbs RD_DFTHRSH_MIN, 602102681Sgibbs RD_DFTHRSH_25, 603102681Sgibbs RD_DFTHRSH_50, 604102681Sgibbs RD_DFTHRSH_63, 605102681Sgibbs RD_DFTHRSH_75, 606102681Sgibbs RD_DFTHRSH_85, 607102681Sgibbs RD_DFTHRSH_90, 608102681Sgibbs RD_DFTHRSH_MAX 609102681Sgibbs } 61097883Sgibbs} 61197883Sgibbs 61297883Sgibbs/* 61397883Sgibbs * ROM Address 61497883Sgibbs */ 61597883Sgibbsregister ROMADDR { 61697883Sgibbs address 0x08A 61797883Sgibbs access_mode RW 61897883Sgibbs size 3 61997883Sgibbs} 62097883Sgibbs 62197883Sgibbs/* 62297883Sgibbs * ROM Control 62397883Sgibbs */ 62497883Sgibbsregister ROMCNTRL { 62597883Sgibbs address 0x08D 62697883Sgibbs access_mode RW 627102681Sgibbs field ROMOP 0xE0 628102681Sgibbs field ROMSPD 0x18 629102681Sgibbs field REPEAT 0x02 630102681Sgibbs field RDY 0x01 63197883Sgibbs} 63297883Sgibbs 63397883Sgibbs/* 63497883Sgibbs * ROM Data 63597883Sgibbs */ 63697883Sgibbsregister ROMDATA { 63797883Sgibbs address 0x08E 63897883Sgibbs access_mode RW 63997883Sgibbs} 64097883Sgibbs 64197883Sgibbs/* 64297883Sgibbs * Data Channel Receive Message 0 64397883Sgibbs */ 64497883Sgibbsregister DCHRXMSG0 { 64597883Sgibbs address 0x090 64697883Sgibbs access_mode RO 64797883Sgibbs modes M_DFF0, M_DFF1 648102681Sgibbs field CDNUM 0xF8 649102681Sgibbs field CFNUM 0x07 65097883Sgibbs} 65197883Sgibbs 65297883Sgibbs/* 65397883Sgibbs * CMC Recieve Message 0 65497883Sgibbs */ 65597883Sgibbsregister CMCRXMSG0 { 65697883Sgibbs address 0x090 65797883Sgibbs access_mode RO 65897883Sgibbs modes M_CCHAN 659102681Sgibbs field CDNUM 0xF8 660102681Sgibbs field CFNUM 0x07 66197883Sgibbs} 66297883Sgibbs 66397883Sgibbs/* 66497883Sgibbs * Overlay Recieve Message 0 66597883Sgibbs */ 66697883Sgibbsregister OVLYRXMSG0 { 66797883Sgibbs address 0x090 66897883Sgibbs access_mode RO 66997883Sgibbs modes M_SCSI 670102681Sgibbs field CDNUM 0xF8 671102681Sgibbs field CFNUM 0x07 67297883Sgibbs} 67397883Sgibbs 67497883Sgibbs/* 67597883Sgibbs * Relaxed Order Enable 67697883Sgibbs */ 67797883Sgibbsregister ROENABLE { 67897883Sgibbs address 0x090 67997883Sgibbs access_mode RW 68097883Sgibbs modes M_CFG 681102681Sgibbs field MSIROEN 0x20 682102681Sgibbs field OVLYROEN 0x10 683102681Sgibbs field CMCROEN 0x08 684102681Sgibbs field SGROEN 0x04 685102681Sgibbs field DCH1ROEN 0x02 686102681Sgibbs field DCH0ROEN 0x01 68797883Sgibbs} 68897883Sgibbs 68997883Sgibbs/* 69097883Sgibbs * Data Channel Receive Message 1 69197883Sgibbs */ 69297883Sgibbsregister DCHRXMSG1 { 69397883Sgibbs address 0x091 69497883Sgibbs access_mode RO 69597883Sgibbs modes M_DFF0, M_DFF1 696102681Sgibbs field CBNUM 0xFF 69797883Sgibbs} 69897883Sgibbs 69997883Sgibbs/* 70097883Sgibbs * CMC Recieve Message 1 70197883Sgibbs */ 70297883Sgibbsregister CMCRXMSG1 { 70397883Sgibbs address 0x091 70497883Sgibbs access_mode RO 70597883Sgibbs modes M_CCHAN 706102681Sgibbs field CBNUM 0xFF 70797883Sgibbs} 70897883Sgibbs 70997883Sgibbs/* 71097883Sgibbs * Overlay Recieve Message 1 71197883Sgibbs */ 71297883Sgibbsregister OVLYRXMSG1 { 71397883Sgibbs address 0x091 71497883Sgibbs access_mode RO 71597883Sgibbs modes M_SCSI 716102681Sgibbs field CBNUM 0xFF 71797883Sgibbs} 71897883Sgibbs 71997883Sgibbs/* 72097883Sgibbs * No Snoop Enable 72197883Sgibbs */ 72297883Sgibbsregister NSENABLE { 72397883Sgibbs address 0x091 72497883Sgibbs access_mode RW 72597883Sgibbs modes M_CFG 726102681Sgibbs field MSINSEN 0x20 727102681Sgibbs field OVLYNSEN 0x10 728102681Sgibbs field CMCNSEN 0x08 729102681Sgibbs field SGNSEN 0x04 730102681Sgibbs field DCH1NSEN 0x02 731102681Sgibbs field DCH0NSEN 0x01 73297883Sgibbs} 73397883Sgibbs 73497883Sgibbs/* 73597883Sgibbs * Data Channel Receive Message 2 73697883Sgibbs */ 73797883Sgibbsregister DCHRXMSG2 { 73897883Sgibbs address 0x092 73997883Sgibbs access_mode RO 74097883Sgibbs modes M_DFF0, M_DFF1 741102681Sgibbs field MINDEX 0xFF 74297883Sgibbs} 74397883Sgibbs 74497883Sgibbs/* 74597883Sgibbs * CMC Recieve Message 2 74697883Sgibbs */ 74797883Sgibbsregister CMCRXMSG2 { 74897883Sgibbs address 0x092 74997883Sgibbs access_mode RO 75097883Sgibbs modes M_CCHAN 751102681Sgibbs field MINDEX 0xFF 75297883Sgibbs} 75397883Sgibbs 75497883Sgibbs/* 75597883Sgibbs * Overlay Recieve Message 2 75697883Sgibbs */ 75797883Sgibbsregister OVLYRXMSG2 { 75897883Sgibbs address 0x092 75997883Sgibbs access_mode RO 76097883Sgibbs modes M_SCSI 761102681Sgibbs field MINDEX 0xFF 76297883Sgibbs} 76397883Sgibbs 76497883Sgibbs/* 76597883Sgibbs * Outstanding Split Transactions 76697883Sgibbs */ 76797883Sgibbsregister OST { 76897883Sgibbs address 0x092 76997883Sgibbs access_mode RW 77097883Sgibbs modes M_CFG 77197883Sgibbs} 77297883Sgibbs 77397883Sgibbs/* 77497883Sgibbs * Data Channel Receive Message 3 77597883Sgibbs */ 77697883Sgibbsregister DCHRXMSG3 { 77797883Sgibbs address 0x093 77897883Sgibbs access_mode RO 77997883Sgibbs modes M_DFF0, M_DFF1 780102681Sgibbs field MCLASS 0x0F 78197883Sgibbs} 78297883Sgibbs 78397883Sgibbs/* 78497883Sgibbs * CMC Recieve Message 3 78597883Sgibbs */ 78697883Sgibbsregister CMCRXMSG3 { 78797883Sgibbs address 0x093 78897883Sgibbs access_mode RO 78997883Sgibbs modes M_CCHAN 790102681Sgibbs field MCLASS 0x0F 79197883Sgibbs} 79297883Sgibbs 79397883Sgibbs/* 79497883Sgibbs * Overlay Recieve Message 3 79597883Sgibbs */ 79697883Sgibbsregister OVLYRXMSG3 { 79797883Sgibbs address 0x093 79897883Sgibbs access_mode RO 79997883Sgibbs modes M_SCSI 800102681Sgibbs field MCLASS 0x0F 80197883Sgibbs} 80297883Sgibbs 80397883Sgibbs/* 80497883Sgibbs * PCI-X Control 80597883Sgibbs */ 80697883Sgibbsregister PCIXCTL { 80797883Sgibbs address 0x093 80897883Sgibbs access_mode RW 80997883Sgibbs modes M_CFG 810102681Sgibbs field SERRPULSE 0x80 811102681Sgibbs field UNEXPSCIEN 0x20 812102681Sgibbs field SPLTSMADIS 0x10 813102681Sgibbs field SPLTSTADIS 0x08 814102681Sgibbs field SRSPDPEEN 0x04 815102681Sgibbs field TSCSERREN 0x02 816102681Sgibbs field CMPABCDIS 0x01 81797883Sgibbs} 81897883Sgibbs 81997883Sgibbs/* 82097883Sgibbs * CMC Sequencer Byte Count 82197883Sgibbs */ 82297883Sgibbsregister CMCSEQBCNT { 82397883Sgibbs address 0x094 82497883Sgibbs access_mode RO 82597883Sgibbs modes M_CCHAN 82697883Sgibbs} 82797883Sgibbs 82897883Sgibbs/* 82997883Sgibbs * Overlay Sequencer Byte Count 83097883Sgibbs */ 83197883Sgibbsregister OVLYSEQBCNT { 83297883Sgibbs address 0x094 83397883Sgibbs access_mode RO 83497883Sgibbs modes M_SCSI 83597883Sgibbs} 83697883Sgibbs 83797883Sgibbs/* 83897883Sgibbs * Data Channel Sequencer Byte Count 83997883Sgibbs */ 84097883Sgibbsregister DCHSEQBCNT { 84197883Sgibbs address 0x094 84297883Sgibbs access_mode RO 84397883Sgibbs size 2 84497883Sgibbs modes M_DFF0, M_DFF1 84597883Sgibbs} 84697883Sgibbs 84797883Sgibbs/* 84897883Sgibbs * Data Channel Split Status 0 84997883Sgibbs */ 85097883Sgibbsregister DCHSPLTSTAT0 { 85197883Sgibbs address 0x096 85297883Sgibbs access_mode RW 85397883Sgibbs modes M_DFF0, M_DFF1 854102681Sgibbs field STAETERM 0x80 855102681Sgibbs field SCBCERR 0x40 856102681Sgibbs field SCADERR 0x20 857102681Sgibbs field SCDATBUCKET 0x10 858102681Sgibbs field CNTNOTCMPLT 0x08 859102681Sgibbs field RXOVRUN 0x04 860102681Sgibbs field RXSCEMSG 0x02 861102681Sgibbs field RXSPLTRSP 0x01 86297883Sgibbs} 86397883Sgibbs 86497883Sgibbs/* 86597883Sgibbs * CMC Split Status 0 86697883Sgibbs */ 86797883Sgibbsregister CMCSPLTSTAT0 { 86897883Sgibbs address 0x096 86997883Sgibbs access_mode RW 87097883Sgibbs modes M_CCHAN 871102681Sgibbs field STAETERM 0x80 872102681Sgibbs field SCBCERR 0x40 873102681Sgibbs field SCADERR 0x20 874102681Sgibbs field SCDATBUCKET 0x10 875102681Sgibbs field CNTNOTCMPLT 0x08 876102681Sgibbs field RXOVRUN 0x04 877102681Sgibbs field RXSCEMSG 0x02 878102681Sgibbs field RXSPLTRSP 0x01 87997883Sgibbs} 88097883Sgibbs 88197883Sgibbs/* 88297883Sgibbs * Overlay Split Status 0 88397883Sgibbs */ 88497883Sgibbsregister OVLYSPLTSTAT0 { 88597883Sgibbs address 0x096 88697883Sgibbs access_mode RW 88797883Sgibbs modes M_SCSI 888102681Sgibbs field STAETERM 0x80 889102681Sgibbs field SCBCERR 0x40 890102681Sgibbs field SCADERR 0x20 891102681Sgibbs field SCDATBUCKET 0x10 892102681Sgibbs field CNTNOTCMPLT 0x08 893102681Sgibbs field RXOVRUN 0x04 894102681Sgibbs field RXSCEMSG 0x02 895102681Sgibbs field RXSPLTRSP 0x01 89697883Sgibbs} 89797883Sgibbs 89897883Sgibbs/* 89997883Sgibbs * Data Channel Split Status 1 90097883Sgibbs */ 90197883Sgibbsregister DCHSPLTSTAT1 { 90297883Sgibbs address 0x097 90397883Sgibbs access_mode RW 90497883Sgibbs modes M_DFF0, M_DFF1 905102681Sgibbs field RXDATABUCKET 0x01 90697883Sgibbs} 90797883Sgibbs 90897883Sgibbs/* 90997883Sgibbs * CMC Split Status 1 91097883Sgibbs */ 91197883Sgibbsregister CMCSPLTSTAT1 { 91297883Sgibbs address 0x097 91397883Sgibbs access_mode RW 91497883Sgibbs modes M_CCHAN 915102681Sgibbs field RXDATABUCKET 0x01 91697883Sgibbs} 91797883Sgibbs 91897883Sgibbs/* 91997883Sgibbs * Overlay Split Status 1 92097883Sgibbs */ 92197883Sgibbsregister OVLYSPLTSTAT1 { 92297883Sgibbs address 0x097 92397883Sgibbs access_mode RW 92497883Sgibbs modes M_SCSI 925102681Sgibbs field RXDATABUCKET 0x01 92697883Sgibbs} 92797883Sgibbs 92897883Sgibbs/* 92997883Sgibbs * S/G Receive Message 0 93097883Sgibbs */ 93197883Sgibbsregister SGRXMSG0 { 93297883Sgibbs address 0x098 93397883Sgibbs access_mode RO 93497883Sgibbs modes M_DFF0, M_DFF1 935102681Sgibbs field CDNUM 0xF8 936102681Sgibbs field CFNUM 0x07 93797883Sgibbs} 93897883Sgibbs 93997883Sgibbs/* 94097883Sgibbs * S/G Receive Message 1 94197883Sgibbs */ 94297883Sgibbsregister SGRXMSG1 { 94397883Sgibbs address 0x099 94497883Sgibbs access_mode RO 94597883Sgibbs modes M_DFF0, M_DFF1 946102681Sgibbs field CBNUM 0xFF 94797883Sgibbs} 94897883Sgibbs 94997883Sgibbs/* 95097883Sgibbs * S/G Receive Message 2 95197883Sgibbs */ 95297883Sgibbsregister SGRXMSG2 { 95397883Sgibbs address 0x09A 95497883Sgibbs access_mode RO 95597883Sgibbs modes M_DFF0, M_DFF1 956102681Sgibbs field MINDEX 0xFF 95797883Sgibbs} 95897883Sgibbs 95997883Sgibbs/* 96097883Sgibbs * S/G Receive Message 3 96197883Sgibbs */ 96297883Sgibbsregister SGRXMSG3 { 96397883Sgibbs address 0x09B 96497883Sgibbs access_mode RO 96597883Sgibbs modes M_DFF0, M_DFF1 966102681Sgibbs field MCLASS 0x0F 96797883Sgibbs} 96897883Sgibbs 96997883Sgibbs/* 97097883Sgibbs * Slave Split Out Address 0 97197883Sgibbs */ 97297883Sgibbsregister SLVSPLTOUTADR0 { 97397883Sgibbs address 0x098 97497883Sgibbs access_mode RO 97597883Sgibbs modes M_SCSI 976102681Sgibbs field LOWER_ADDR 0x7F 97797883Sgibbs} 97897883Sgibbs 97997883Sgibbs/* 98097883Sgibbs * Slave Split Out Address 1 98197883Sgibbs */ 98297883Sgibbsregister SLVSPLTOUTADR1 { 98397883Sgibbs address 0x099 98497883Sgibbs access_mode RO 98597883Sgibbs modes M_SCSI 986102681Sgibbs field REQ_DNUM 0xF8 987102681Sgibbs field REQ_FNUM 0x07 98897883Sgibbs} 98997883Sgibbs 99097883Sgibbs/* 99197883Sgibbs * Slave Split Out Address 2 99297883Sgibbs */ 99397883Sgibbsregister SLVSPLTOUTADR2 { 99497883Sgibbs address 0x09A 99597883Sgibbs access_mode RO 99697883Sgibbs modes M_SCSI 997102681Sgibbs field REQ_BNUM 0xFF 99897883Sgibbs} 99997883Sgibbs 100097883Sgibbs/* 100197883Sgibbs * Slave Split Out Address 3 100297883Sgibbs */ 100397883Sgibbsregister SLVSPLTOUTADR3 { 100497883Sgibbs address 0x09B 100597883Sgibbs access_mode RO 100697883Sgibbs modes M_SCSI 1007102681Sgibbs field RLXORD 020 1008102681Sgibbs field TAG_NUM 0x1F 100997883Sgibbs} 101097883Sgibbs 101197883Sgibbs/* 101297883Sgibbs * SG Sequencer Byte Count 101397883Sgibbs */ 101497883Sgibbsregister SGSEQBCNT { 101597883Sgibbs address 0x09C 101697883Sgibbs access_mode RO 101797883Sgibbs modes M_DFF0, M_DFF1 101897883Sgibbs} 101997883Sgibbs 102097883Sgibbs/* 102197883Sgibbs * Slave Split Out Attribute 0 102297883Sgibbs */ 102397883Sgibbsregister SLVSPLTOUTATTR0 { 102497883Sgibbs address 0x09C 102597883Sgibbs access_mode RO 102697883Sgibbs modes M_SCSI 1027102681Sgibbs field LOWER_BCNT 0xFF 102897883Sgibbs} 102997883Sgibbs 103097883Sgibbs/* 103197883Sgibbs * Slave Split Out Attribute 1 103297883Sgibbs */ 103397883Sgibbsregister SLVSPLTOUTATTR1 { 103497883Sgibbs address 0x09D 103597883Sgibbs access_mode RO 103697883Sgibbs modes M_SCSI 1037102681Sgibbs field CMPLT_DNUM 0xF8 1038102681Sgibbs field CMPLT_FNUM 0x07 103997883Sgibbs} 104097883Sgibbs 104197883Sgibbs/* 104297883Sgibbs * Slave Split Out Attribute 2 104397883Sgibbs */ 104497883Sgibbsregister SLVSPLTOUTATTR2 { 104597883Sgibbs address 0x09E 104697883Sgibbs access_mode RO 104797883Sgibbs size 2 104897883Sgibbs modes M_SCSI 1049102681Sgibbs field CMPLT_BNUM 0xFF 105097883Sgibbs} 105197883Sgibbs/* 105297883Sgibbs * S/G Split Status 0 105397883Sgibbs */ 105497883Sgibbsregister SGSPLTSTAT0 { 105597883Sgibbs address 0x09E 105697883Sgibbs access_mode RW 105797883Sgibbs modes M_DFF0, M_DFF1 1058102681Sgibbs field STAETERM 0x80 1059102681Sgibbs field SCBCERR 0x40 1060102681Sgibbs field SCADERR 0x20 1061102681Sgibbs field SCDATBUCKET 0x10 1062102681Sgibbs field CNTNOTCMPLT 0x08 1063102681Sgibbs field RXOVRUN 0x04 1064102681Sgibbs field RXSCEMSG 0x02 1065102681Sgibbs field RXSPLTRSP 0x01 106697883Sgibbs} 106797883Sgibbs 106897883Sgibbs/* 106997883Sgibbs * S/G Split Status 1 107097883Sgibbs */ 107197883Sgibbsregister SGSPLTSTAT1 { 107297883Sgibbs address 0x09F 107397883Sgibbs access_mode RW 107497883Sgibbs modes M_DFF0, M_DFF1 1075102681Sgibbs field RXDATABUCKET 0x01 107697883Sgibbs} 107797883Sgibbs 107897883Sgibbs/* 107997883Sgibbs * Special Function 108097883Sgibbs */ 108197883Sgibbsregister SFUNCT { 108297883Sgibbs address 0x09f 108397883Sgibbs access_mode RW 108497883Sgibbs modes M_CFG 1085102681Sgibbs field TEST_GROUP 0xF0 1086102681Sgibbs field TEST_NUM 0x0F 108797883Sgibbs} 108897883Sgibbs 108997883Sgibbs/* 109097883Sgibbs * Data FIFO 0 PCI Status 109197883Sgibbs */ 109297883Sgibbsregister DF0PCISTAT { 109397883Sgibbs address 0x0A0 109497883Sgibbs access_mode RW 109597883Sgibbs modes M_CFG 1096102681Sgibbs field DPE 0x80 1097102681Sgibbs field SSE 0x40 1098102681Sgibbs field RMA 0x20 1099102681Sgibbs field RTA 0x10 1100102681Sgibbs field SCAAPERR 0x08 1101102681Sgibbs field RDPERR 0x04 1102102681Sgibbs field TWATERR 0x02 1103102681Sgibbs field DPR 0x01 110497883Sgibbs} 110597883Sgibbs 110697883Sgibbs/* 110797883Sgibbs * Data FIFO 1 PCI Status 110897883Sgibbs */ 110997883Sgibbsregister DF1PCISTAT { 111097883Sgibbs address 0x0A1 111197883Sgibbs access_mode RW 111297883Sgibbs modes M_CFG 1113102681Sgibbs field DPE 0x80 1114102681Sgibbs field SSE 0x40 1115102681Sgibbs field RMA 0x20 1116102681Sgibbs field RTA 0x10 1117102681Sgibbs field SCAAPERR 0x08 1118102681Sgibbs field RDPERR 0x04 1119102681Sgibbs field TWATERR 0x02 1120102681Sgibbs field DPR 0x01 112197883Sgibbs} 112297883Sgibbs 112397883Sgibbs/* 112497883Sgibbs * S/G PCI Status 112597883Sgibbs */ 112697883Sgibbsregister SGPCISTAT { 112797883Sgibbs address 0x0A2 112897883Sgibbs access_mode RW 112997883Sgibbs modes M_CFG 1130102681Sgibbs field DPE 0x80 1131102681Sgibbs field SSE 0x40 1132102681Sgibbs field RMA 0x20 1133102681Sgibbs field RTA 0x10 1134102681Sgibbs field SCAAPERR 0x08 1135102681Sgibbs field RDPERR 0x04 1136102681Sgibbs field DPR 0x01 113797883Sgibbs} 113897883Sgibbs 113997883Sgibbs/* 114097883Sgibbs * CMC PCI Status 114197883Sgibbs */ 114297883Sgibbsregister CMCPCISTAT { 114397883Sgibbs address 0x0A3 114497883Sgibbs access_mode RW 114597883Sgibbs modes M_CFG 1146102681Sgibbs field DPE 0x80 1147102681Sgibbs field SSE 0x40 1148102681Sgibbs field RMA 0x20 1149102681Sgibbs field RTA 0x10 1150102681Sgibbs field SCAAPERR 0x08 1151102681Sgibbs field RDPERR 0x04 1152102681Sgibbs field TWATERR 0x02 1153102681Sgibbs field DPR 0x01 115497883Sgibbs} 115597883Sgibbs 115697883Sgibbs/* 115797883Sgibbs * Overlay PCI Status 115897883Sgibbs */ 115997883Sgibbsregister OVLYPCISTAT { 116097883Sgibbs address 0x0A4 116197883Sgibbs access_mode RW 116297883Sgibbs modes M_CFG 1163102681Sgibbs field DPE 0x80 1164102681Sgibbs field SSE 0x40 1165102681Sgibbs field RMA 0x20 1166102681Sgibbs field RTA 0x10 1167102681Sgibbs field SCAAPERR 0x08 1168102681Sgibbs field RDPERR 0x04 1169102681Sgibbs field DPR 0x01 117097883Sgibbs} 117197883Sgibbs 117297883Sgibbs/* 117397883Sgibbs * PCI Status for MSI Master DMA Transfer 117497883Sgibbs */ 117597883Sgibbsregister MSIPCISTAT { 117697883Sgibbs address 0x0A6 117797883Sgibbs access_mode RW 117897883Sgibbs modes M_CFG 1179102681Sgibbs field SSE 0x40 1180102681Sgibbs field RMA 0x20 1181102681Sgibbs field RTA 0x10 1182102681Sgibbs field CLRPENDMSI 0x08 1183102681Sgibbs field TWATERR 0x02 1184102681Sgibbs field DPR 0x01 118597883Sgibbs} 118697883Sgibbs 118797883Sgibbs/* 118897883Sgibbs * PCI Status for Target 118997883Sgibbs */ 119097883Sgibbsregister TARGPCISTAT { 1191107623Sscottl address 0x0A7 119297883Sgibbs access_mode RW 119397883Sgibbs modes M_CFG 1194102681Sgibbs field DPE 0x80 1195102681Sgibbs field SSE 0x40 1196102681Sgibbs field STA 0x08 1197102681Sgibbs field TWATERR 0x02 119897883Sgibbs} 119997883Sgibbs 120097883Sgibbs/* 120197883Sgibbs * LQ Packet In 120297883Sgibbs * The last LQ Packet recieved 120397883Sgibbs */ 120497883Sgibbsregister LQIN { 120597883Sgibbs address 0x020 120697883Sgibbs access_mode RW 120797883Sgibbs size 20 120897883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 120997883Sgibbs} 121097883Sgibbs 121197883Sgibbs/* 121297883Sgibbs * SCB Type Pointer 121397883Sgibbs * SCB offset for Target Mode SCB type information 121497883Sgibbs */ 121597883Sgibbsregister TYPEPTR { 121697883Sgibbs address 0x020 121797883Sgibbs access_mode RW 121897883Sgibbs modes M_CFG 121997883Sgibbs} 122097883Sgibbs 122197883Sgibbs/* 122297883Sgibbs * Queue Tag Pointer 122397883Sgibbs * SCB offset to the Two Byte tag identifier used for target mode. 122497883Sgibbs */ 122597883Sgibbsregister TAGPTR { 122697883Sgibbs address 0x021 122797883Sgibbs access_mode RW 122897883Sgibbs modes M_CFG 122997883Sgibbs} 123097883Sgibbs 123197883Sgibbs/* 123297883Sgibbs * Logical Unit Number Pointer 123397883Sgibbs * SCB offset to the LSB (little endian) of the lun field. 123497883Sgibbs */ 123597883Sgibbsregister LUNPTR { 123697883Sgibbs address 0x022 123797883Sgibbs access_mode RW 123897883Sgibbs modes M_CFG 123997883Sgibbs} 124097883Sgibbs 124197883Sgibbs/* 124297883Sgibbs * Data Length Pointer 124397883Sgibbs * SCB offset for the 4 byte data length field in target mode. 124497883Sgibbs */ 124597883Sgibbsregister DATALENPTR { 124697883Sgibbs address 0x023 124797883Sgibbs access_mode RW 124897883Sgibbs modes M_CFG 124997883Sgibbs} 125097883Sgibbs 125197883Sgibbs/* 125297883Sgibbs * Status Length Pointer 125397883Sgibbs * SCB offset to the two byte status field in target SCBs. 125497883Sgibbs */ 125597883Sgibbsregister STATLENPTR { 125697883Sgibbs address 0x024 125797883Sgibbs access_mode RW 125897883Sgibbs modes M_CFG 125997883Sgibbs} 126097883Sgibbs 126197883Sgibbs/* 126297883Sgibbs * Command Length Pointer 126397883Sgibbs * Scb offset for the CDB length field in initiator SCBs. 126497883Sgibbs */ 126597883Sgibbsregister CMDLENPTR { 126697883Sgibbs address 0x025 126797883Sgibbs access_mode RW 126897883Sgibbs modes M_CFG 126997883Sgibbs} 127097883Sgibbs 127197883Sgibbs/* 127297883Sgibbs * Task Attribute Pointer 127397883Sgibbs * Scb offset for the byte field specifying the attribute byte 127497883Sgibbs * to be used in command packets. 127597883Sgibbs */ 127697883Sgibbsregister ATTRPTR { 127797883Sgibbs address 0x026 127897883Sgibbs access_mode RW 127997883Sgibbs modes M_CFG 128097883Sgibbs} 128197883Sgibbs 128297883Sgibbs/* 128397883Sgibbs * Task Management Flags Pointer 128497883Sgibbs * Scb offset for the byte field specifying the attribute flags 128597883Sgibbs * byte to be used in command packets. 128697883Sgibbs */ 128797883Sgibbsregister FLAGPTR { 128897883Sgibbs address 0x027 128997883Sgibbs access_mode RW 129097883Sgibbs modes M_CFG 129197883Sgibbs} 129297883Sgibbs 129397883Sgibbs/* 129497883Sgibbs * Command Pointer 129597883Sgibbs * Scb offset for the first byte in the CDB for initiator SCBs. 129697883Sgibbs */ 129797883Sgibbsregister CMDPTR { 129897883Sgibbs address 0x028 129997883Sgibbs access_mode RW 130097883Sgibbs modes M_CFG 130197883Sgibbs} 130297883Sgibbs 130397883Sgibbs/* 130497883Sgibbs * Queue Next Pointer 130597883Sgibbs * Scb offset for the 2 byte "next scb link". 130697883Sgibbs */ 130797883Sgibbsregister QNEXTPTR { 130897883Sgibbs address 0x029 130997883Sgibbs access_mode RW 131097883Sgibbs modes M_CFG 131197883Sgibbs} 131297883Sgibbs 131397883Sgibbs/* 131497883Sgibbs * SCSI ID Pointer 131597883Sgibbs * Scb offset to the value to place in the SCSIID register 131697883Sgibbs * during target mode connections. 131797883Sgibbs */ 131897883Sgibbsregister IDPTR { 131997883Sgibbs address 0x02A 132097883Sgibbs access_mode RW 132197883Sgibbs modes M_CFG 132297883Sgibbs} 132397883Sgibbs 132497883Sgibbs/* 132597883Sgibbs * Command Aborted Byte Pointer 132697883Sgibbs * Offset to the SCB flags field that includes the 132797883Sgibbs * "SCB aborted" status bit. 132897883Sgibbs */ 132997883Sgibbsregister ABRTBYTEPTR { 133097883Sgibbs address 0x02B 133197883Sgibbs access_mode RW 133297883Sgibbs modes M_CFG 133397883Sgibbs} 133497883Sgibbs 133597883Sgibbs/* 133697883Sgibbs * Command Aborted Bit Pointer 133797883Sgibbs * Bit offset in the SCB flags field for "SCB aborted" status. 133897883Sgibbs */ 133997883Sgibbsregister ABRTBITPTR { 134097883Sgibbs address 0x02C 134197883Sgibbs access_mode RW 134297883Sgibbs modes M_CFG 134397883Sgibbs} 134497883Sgibbs 134597883Sgibbs/* 1346102681Sgibbs * Rev B or greater. 1347102681Sgibbs */ 1348102681Sgibbsregister MAXCMDBYTES { 1349102681Sgibbs address 0x02D 1350102681Sgibbs access_mode RW 1351102681Sgibbs modes M_CFG 1352102681Sgibbs} 1353102681Sgibbs 1354102681Sgibbs/* 1355102681Sgibbs * Rev B or greater. 1356102681Sgibbs */ 1357102681Sgibbsregister MAXCMD2RCV { 1358102681Sgibbs address 0x02E 1359102681Sgibbs access_mode RW 1360102681Sgibbs modes M_CFG 1361102681Sgibbs} 1362102681Sgibbs 1363102681Sgibbs/* 1364102681Sgibbs * Rev B or greater. 1365102681Sgibbs */ 1366102681Sgibbsregister SHORTTHRESH { 1367102681Sgibbs address 0x02F 1368102681Sgibbs access_mode RW 1369102681Sgibbs modes M_CFG 1370102681Sgibbs} 1371102681Sgibbs 1372102681Sgibbs/* 137397883Sgibbs * Logical Unit Number Length 137497883Sgibbs * The length, in bytes, of the SCB lun field. 137597883Sgibbs */ 137697883Sgibbsregister LUNLEN { 137797883Sgibbs address 0x030 137897883Sgibbs access_mode RW 137997883Sgibbs modes M_CFG 1380115407Sscottl mask ILUNLEN 0x0F 1381115407Sscottl mask TLUNLEN 0xF0 138297883Sgibbs} 1383115407Sscottlconst LUNLEN_SINGLE_LEVEL_LUN 0xF 138497883Sgibbs 138597883Sgibbs/* 138697883Sgibbs * CDB Limit 138797883Sgibbs * The size, in bytes, of the embedded CDB field in initator SCBs. 138897883Sgibbs */ 138997883Sgibbsregister CDBLIMIT { 139097883Sgibbs address 0x031 139197883Sgibbs access_mode RW 139297883Sgibbs modes M_CFG 139397883Sgibbs} 139497883Sgibbs 139597883Sgibbs/* 139697883Sgibbs * Maximum Commands 139797883Sgibbs * The maximum number of commands to issue during a 139897883Sgibbs * single packetized connection. 139997883Sgibbs */ 140097883Sgibbsregister MAXCMD { 140197883Sgibbs address 0x032 140297883Sgibbs access_mode RW 140397883Sgibbs modes M_CFG 140497883Sgibbs} 140597883Sgibbs 140697883Sgibbs/* 140797883Sgibbs * Maximum Command Counter 140897883Sgibbs * The number of commands already sent during this connection 140997883Sgibbs */ 141097883Sgibbsregister MAXCMDCNT { 141197883Sgibbs address 0x033 141297883Sgibbs access_mode RW 141397883Sgibbs modes M_CFG 141497883Sgibbs} 141597883Sgibbs 141697883Sgibbs/* 141797883Sgibbs * LQ Packet Reserved Bytes 141897883Sgibbs * The bytes to be sent in the currently reserved fileds 141997883Sgibbs * of all LQ packets. 142097883Sgibbs */ 142197883Sgibbsregister LQRSVD01 { 142297883Sgibbs address 0x034 142397883Sgibbs access_mode RW 142497883Sgibbs modes M_SCSI 142597883Sgibbs} 142697883Sgibbsregister LQRSVD16 { 142797883Sgibbs address 0x035 142897883Sgibbs access_mode RW 142997883Sgibbs modes M_SCSI 143097883Sgibbs} 143197883Sgibbsregister LQRSVD17 { 143297883Sgibbs address 0x036 143397883Sgibbs access_mode RW 143497883Sgibbs modes M_SCSI 143597883Sgibbs} 143697883Sgibbs 143797883Sgibbs/* 143897883Sgibbs * Command Reserved 0 143997883Sgibbs * The byte to be sent for the reserved byte 0 of 144097883Sgibbs * outgoing command packets. 144197883Sgibbs */ 144297883Sgibbsregister CMDRSVD0 { 144397883Sgibbs address 0x037 144497883Sgibbs access_mode RW 144597883Sgibbs modes M_CFG 144697883Sgibbs} 144797883Sgibbs 144897883Sgibbs/* 144997883Sgibbs * LQ Manager Control 0 145097883Sgibbs */ 145197883Sgibbsregister LQCTL0 { 145297883Sgibbs address 0x038 145397883Sgibbs access_mode RW 145497883Sgibbs modes M_CFG 1455102681Sgibbs field LQITARGCLT 0xC0 1456102681Sgibbs field LQIINITGCLT 0x30 1457102681Sgibbs field LQ0TARGCLT 0x0C 1458102681Sgibbs field LQ0INITGCLT 0x03 145997883Sgibbs} 146097883Sgibbs 146197883Sgibbs/* 146297883Sgibbs * LQ Manager Control 1 146397883Sgibbs */ 146497883Sgibbsregister LQCTL1 { 146597883Sgibbs address 0x038 146697883Sgibbs access_mode RW 146797883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1468102681Sgibbs field PCI2PCI 0x04 1469102681Sgibbs field SINGLECMD 0x02 1470102681Sgibbs field ABORTPENDING 0x01 147197883Sgibbs} 147297883Sgibbs 147397883Sgibbs/* 147497883Sgibbs * LQ Manager Control 2 147597883Sgibbs */ 147697883Sgibbsregister LQCTL2 { 147797883Sgibbs address 0x039 147897883Sgibbs access_mode RW 147997883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1480102681Sgibbs field LQIRETRY 0x80 1481102681Sgibbs field LQICONTINUE 0x40 1482102681Sgibbs field LQITOIDLE 0x20 1483102681Sgibbs field LQIPAUSE 0x10 1484102681Sgibbs field LQORETRY 0x08 1485102681Sgibbs field LQOCONTINUE 0x04 1486102681Sgibbs field LQOTOIDLE 0x02 1487102681Sgibbs field LQOPAUSE 0x01 148897883Sgibbs} 148997883Sgibbs 149097883Sgibbs/* 149197883Sgibbs * SCSI RAM BIST0 149297883Sgibbs */ 149397883Sgibbsregister SCSBIST0 { 149497883Sgibbs address 0x039 149597883Sgibbs access_mode RW 149697883Sgibbs modes M_CFG 1497102681Sgibbs field GSBISTERR 0x40 1498102681Sgibbs field GSBISTDONE 0x20 1499102681Sgibbs field GSBISTRUN 0x10 1500102681Sgibbs field OSBISTERR 0x04 1501102681Sgibbs field OSBISTDONE 0x02 1502102681Sgibbs field OSBISTRUN 0x01 150397883Sgibbs} 150497883Sgibbs 150597883Sgibbs/* 150697883Sgibbs * SCSI Sequence Control0 150797883Sgibbs */ 150897883Sgibbsregister SCSISEQ0 { 150997883Sgibbs address 0x03A 151097883Sgibbs access_mode RW 151197883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1512102681Sgibbs field TEMODEO 0x80 1513102681Sgibbs field ENSELO 0x40 1514102681Sgibbs field ENARBO 0x20 1515102681Sgibbs field FORCEBUSFREE 0x10 1516102681Sgibbs field SCSIRSTO 0x01 151797883Sgibbs} 151897883Sgibbs 151997883Sgibbs/* 152097883Sgibbs * SCSI RAM BIST 1 152197883Sgibbs */ 152297883Sgibbsregister SCSBIST1 { 152397883Sgibbs address 0x03A 152497883Sgibbs access_mode RW 152597883Sgibbs modes M_CFG 1526102681Sgibbs field NTBISTERR 0x04 1527102681Sgibbs field NTBISTDONE 0x02 1528102681Sgibbs field NTBISTRUN 0x01 152997883Sgibbs} 153097883Sgibbs 153197883Sgibbs/* 153297883Sgibbs * SCSI Sequence Control 1 153397883Sgibbs */ 153497883Sgibbsregister SCSISEQ1 { 153597883Sgibbs address 0x03B 153697883Sgibbs access_mode RW 153797883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1538102681Sgibbs field MANUALCTL 0x40 1539102681Sgibbs field ENSELI 0x20 1540102681Sgibbs field ENRSELI 0x10 1541102681Sgibbs field MANUALP 0x0C 1542102681Sgibbs field ENAUTOATNP 0x02 1543102681Sgibbs field ALTSTIM 0x01 154497883Sgibbs} 154597883Sgibbs 154697883Sgibbs/* 154797883Sgibbs * SCSI Transfer Control 0 154897883Sgibbs */ 154997883Sgibbsregister SXFRCTL0 { 155097883Sgibbs address 0x03C 155197883Sgibbs access_mode RW 155297883Sgibbs modes M_SCSI 1553102681Sgibbs field DFON 0x80 1554102681Sgibbs field DFPEXP 0x40 1555102681Sgibbs field BIOSCANCELEN 0x10 1556102681Sgibbs field SPIOEN 0x08 155797883Sgibbs} 155897883Sgibbs 155997883Sgibbs/* 156097883Sgibbs * SCSI Transfer Control 1 156197883Sgibbs */ 156297883Sgibbsregister SXFRCTL1 { 156397883Sgibbs address 0x03D 156497883Sgibbs access_mode RW 156597883Sgibbs modes M_SCSI 1566102681Sgibbs field BITBUCKET 0x80 1567102681Sgibbs field ENSACHK 0x40 1568102681Sgibbs field ENSPCHK 0x20 1569102681Sgibbs field STIMESEL 0x18 1570102681Sgibbs field ENSTIMER 0x04 1571102681Sgibbs field ACTNEGEN 0x02 1572102681Sgibbs field STPWEN 0x01 157397883Sgibbs} 157497883Sgibbs 157597883Sgibbs/* 157697883Sgibbs * SCSI Transfer Control 2 157797883Sgibbs */ 157897883Sgibbsregister SXFRCTL2 { 157997883Sgibbs address 0x03E 158097883Sgibbs access_mode RW 158197883Sgibbs modes M_SCSI 1582102681Sgibbs field AUTORSTDIS 0x10 1583102681Sgibbs field CMDDMAEN 0x08 1584102681Sgibbs field ASU 0x07 158597883Sgibbs} 158697883Sgibbs 158797883Sgibbs/* 158897883Sgibbs * SCSI Bus Initiator IDs 158997883Sgibbs * Bitmask of observed initiators on the bus. 159097883Sgibbs */ 159197883Sgibbsregister BUSINITID { 159297883Sgibbs address 0x03C 159397883Sgibbs access_mode RW 159497883Sgibbs modes M_CFG 159597883Sgibbs size 2 159697883Sgibbs} 159797883Sgibbs 159897883Sgibbs/* 159997883Sgibbs * Data Length Counters 160097883Sgibbs * Packet byte counter. 160197883Sgibbs */ 160297883Sgibbsregister DLCOUNT { 160397883Sgibbs address 0x03C 160497883Sgibbs access_mode RW 160597883Sgibbs modes M_DFF0, M_DFF1 160697883Sgibbs size 3 160797883Sgibbs} 160897883Sgibbs 160997883Sgibbs/* 161097883Sgibbs * Data FIFO Status 161197883Sgibbs */ 161297883Sgibbsregister DFFSTAT { 161397883Sgibbs address 0x03F 161497883Sgibbs access_mode RW 161597883Sgibbs modes M_SCSI 1616102681Sgibbs field FIFO1FREE 0x20 1617102681Sgibbs field FIFO0FREE 0x10 1618107441Sscottl /* 1619107441Sscottl * On the B, this enum only works 1620107441Sscottl * in the read direction. For writes, 1621107441Sscottl * you must use the B version of the 1622107441Sscottl * CURRFIFO_0 definition which is defined 1623107441Sscottl * as a constant outside of this register 1624107441Sscottl * definition to avoid confusing the 1625107441Sscottl * register pretty printing code. 1626107441Sscottl */ 1627107441Sscottl enum CURRFIFO 0x03 { 1628107441Sscottl CURRFIFO_0, 1629107441Sscottl CURRFIFO_1, 1630107441Sscottl CURRFIFO_NONE 0x3 1631107441Sscottl } 163297883Sgibbs} 163397883Sgibbs 1634107441Sscottlconst B_CURRFIFO_0 0x2 1635107441Sscottl 163697883Sgibbs/* 163797883Sgibbs * SCSI Bus Target IDs 163897883Sgibbs * Bitmask of observed targets on the bus. 163997883Sgibbs */ 164097883Sgibbsregister BUSTARGID { 164197883Sgibbs address 0x03E 164297883Sgibbs access_mode RW 164397883Sgibbs modes M_CFG 164497883Sgibbs size 2 164597883Sgibbs} 164697883Sgibbs 164797883Sgibbs/* 164897883Sgibbs * SCSI Control Signal Out 164997883Sgibbs */ 165097883Sgibbsregister SCSISIGO { 165197883Sgibbs address 0x040 165297883Sgibbs access_mode RW 165397883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1654102681Sgibbs field CDO 0x80 1655102681Sgibbs field IOO 0x40 1656102681Sgibbs field MSGO 0x20 1657102681Sgibbs field ATNO 0x10 1658102681Sgibbs field SELO 0x08 1659102681Sgibbs field BSYO 0x04 1660102681Sgibbs field REQO 0x02 1661102681Sgibbs field ACKO 0x01 166297883Sgibbs/* 166397883Sgibbs * Possible phases to write into SCSISIG0 166497883Sgibbs */ 1665102681Sgibbs enum PHASE_MASK CDO|IOO|MSGO { 1666102681Sgibbs P_DATAOUT 0x0, 1667102681Sgibbs P_DATAIN IOO, 1668102681Sgibbs P_DATAOUT_DT P_DATAOUT|MSGO, 1669102681Sgibbs P_DATAIN_DT P_DATAIN|MSGO, 1670102681Sgibbs P_COMMAND CDO, 1671102681Sgibbs P_MESGOUT CDO|MSGO, 1672102681Sgibbs P_STATUS CDO|IOO, 1673102681Sgibbs P_MESGIN CDO|IOO|MSGO 1674102681Sgibbs } 167597883Sgibbs} 167697883Sgibbs 167797883Sgibbsregister SCSISIGI { 167897883Sgibbs address 0x041 167997883Sgibbs access_mode RO 168097883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1681102681Sgibbs field CDI 0x80 1682102681Sgibbs field IOI 0x40 1683102681Sgibbs field MSGI 0x20 1684102681Sgibbs field ATNI 0x10 1685102681Sgibbs field SELI 0x08 1686102681Sgibbs field BSYI 0x04 1687102681Sgibbs field REQI 0x02 1688102681Sgibbs field ACKI 0x01 168997883Sgibbs/* 169097883Sgibbs * Possible phases in SCSISIGI 169197883Sgibbs */ 1692102681Sgibbs enum PHASE_MASK CDO|IOO|MSGO { 1693102681Sgibbs P_DATAOUT 0x0, 1694102681Sgibbs P_DATAIN IOO, 1695102681Sgibbs P_DATAOUT_DT P_DATAOUT|MSGO, 1696102681Sgibbs P_DATAIN_DT P_DATAIN|MSGO, 1697102681Sgibbs P_COMMAND CDO, 1698102681Sgibbs P_MESGOUT CDO|MSGO, 1699102681Sgibbs P_STATUS CDO|IOO, 1700102681Sgibbs P_MESGIN CDO|IOO|MSGO 1701102681Sgibbs } 170297883Sgibbs} 170397883Sgibbs 170497883Sgibbs/* 170597883Sgibbs * Multiple Target IDs 170697883Sgibbs * Bitmask of ids to respond as a target. 170797883Sgibbs */ 170897883Sgibbsregister MULTARGID { 170997883Sgibbs address 0x040 171097883Sgibbs access_mode RW 171197883Sgibbs modes M_CFG 171297883Sgibbs size 2 171397883Sgibbs} 171497883Sgibbs 171597883Sgibbs/* 171697883Sgibbs * SCSI Phase 171797883Sgibbs */ 171897883Sgibbsregister SCSIPHASE { 171997883Sgibbs address 0x042 172097883Sgibbs access_mode RO 172197883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1722102681Sgibbs field STATUS_PHASE 0x20 1723102681Sgibbs field COMMAND_PHASE 0x10 1724102681Sgibbs field MSG_IN_PHASE 0x08 1725102681Sgibbs field MSG_OUT_PHASE 0x04 1726102681Sgibbs field DATA_PHASE_MASK 0x03 { 1727102681Sgibbs DATA_OUT_PHASE 0x01, 1728102681Sgibbs DATA_IN_PHASE 0x02 1729102681Sgibbs } 173097883Sgibbs} 173197883Sgibbs 173297883Sgibbs/* 173397883Sgibbs * SCSI Data 0 Image 173497883Sgibbs */ 173597883Sgibbsregister SCSIDAT0_IMG { 173697883Sgibbs address 0x043 173797883Sgibbs access_mode RW 173897883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 173997883Sgibbs} 174097883Sgibbs 174197883Sgibbs/* 174297883Sgibbs * SCSI Latched Data 174397883Sgibbs */ 174497883Sgibbsregister SCSIDAT { 174597883Sgibbs address 0x044 174697883Sgibbs access_mode RW 174797883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 174897883Sgibbs size 2 174997883Sgibbs} 175097883Sgibbs 175197883Sgibbs/* 175297883Sgibbs * SCSI Data Bus 175397883Sgibbs */ 175497883Sgibbsregister SCSIBUS { 175597883Sgibbs address 0x046 175697883Sgibbs access_mode RW 175797883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 175897883Sgibbs size 2 175997883Sgibbs} 176097883Sgibbs 176197883Sgibbs/* 176297883Sgibbs * Target ID In 176397883Sgibbs */ 176497883Sgibbsregister TARGIDIN { 176597883Sgibbs address 0x048 176697883Sgibbs access_mode RO 176797883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1768102681Sgibbs field CLKOUT 0x80 1769102681Sgibbs field TARGID 0x0F 177097883Sgibbs} 177197883Sgibbs 177297883Sgibbs/* 177397883Sgibbs * Selection/Reselection ID 177497883Sgibbs * Upper four bits are the device id. The ONEBIT is set when the re/selecting 177597883Sgibbs * device did not set its own ID. 177697883Sgibbs */ 177797883Sgibbsregister SELID { 177897883Sgibbs address 0x049 177997883Sgibbs access_mode RW 178097883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1781102681Sgibbs field SELID_MASK 0xf0 1782102681Sgibbs field ONEBIT 0x08 178397883Sgibbs} 178497883Sgibbs 178597883Sgibbs/* 178697883Sgibbs * SCSI Block Control 178797883Sgibbs * Controls Bus type and channel selection. SELWIDE allows for the 178897883Sgibbs * coexistence of 8bit and 16bit devices on a wide bus. 178997883Sgibbs */ 179097883Sgibbsregister SBLKCTL { 179197883Sgibbs address 0x04A 179297883Sgibbs access_mode RW 179397883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1794102681Sgibbs field DIAGLEDEN 0x80 1795102681Sgibbs field DIAGLEDON 0x40 1796102681Sgibbs field ENAB40 0x08 /* LVD transceiver active */ 1797102681Sgibbs field ENAB20 0x04 /* SE/HVD transceiver active */ 1798102681Sgibbs field SELWIDE 0x02 179997883Sgibbs} 180097883Sgibbs 180197883Sgibbs/* 180297883Sgibbs * Option Mode 180397883Sgibbs */ 180497883Sgibbsregister OPTIONMODE { 180597883Sgibbs address 0x04A 180697883Sgibbs access_mode RW 180797883Sgibbs modes M_CFG 1808102681Sgibbs field BIOSCANCTL 0x80 1809102681Sgibbs field AUTOACKEN 0x40 1810102681Sgibbs field BIASCANCTL 0x20 1811102681Sgibbs field BUSFREEREV 0x10 1812102681Sgibbs field ENDGFORMCHK 0x04 1813102681Sgibbs field AUTO_MSGOUT_DE 0x02 181497883Sgibbs mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE 181597883Sgibbs} 181697883Sgibbs 181797883Sgibbs/* 181897883Sgibbs * SCSI Status 0 181997883Sgibbs */ 182097883Sgibbsregister SSTAT0 { 182197883Sgibbs address 0x04B 182297883Sgibbs access_mode RO 182397883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1824102681Sgibbs field TARGET 0x80 /* Board acting as target */ 1825102681Sgibbs field SELDO 0x40 /* Selection Done */ 1826102681Sgibbs field SELDI 0x20 /* Board has been selected */ 1827102681Sgibbs field SELINGO 0x10 /* Selection In Progress */ 1828102681Sgibbs field IOERR 0x08 /* LVD Tranceiver mode changed */ 1829102681Sgibbs field OVERRUN 0x04 /* SCSI Offset overrun detected */ 1830102681Sgibbs field SPIORDY 0x02 /* SCSI PIO Ready */ 1831102681Sgibbs field ARBDO 0x01 /* Arbitration Done Out */ 183297883Sgibbs} 183397883Sgibbs 183497883Sgibbs/* 183597883Sgibbs * Clear SCSI Interrupt 0 183697883Sgibbs * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 183797883Sgibbs */ 183897883Sgibbsregister CLRSINT0 { 183997883Sgibbs address 0x04B 184097883Sgibbs access_mode WO 184197883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1842102681Sgibbs field CLRSELDO 0x40 1843102681Sgibbs field CLRSELDI 0x20 1844102681Sgibbs field CLRSELINGO 0x10 1845102681Sgibbs field CLRIOERR 0x08 1846102681Sgibbs field CLROVERRUN 0x04 1847102681Sgibbs field CLRSPIORDY 0x02 1848102681Sgibbs field CLRARBDO 0x01 184997883Sgibbs} 185097883Sgibbs 185197883Sgibbs/* 185297883Sgibbs * SCSI Interrupt Mode 0 185397883Sgibbs * Setting any bit will enable the corresponding function 185497883Sgibbs * in SIMODE0 to interrupt via the IRQ pin. 185597883Sgibbs */ 185697883Sgibbsregister SIMODE0 { 185797883Sgibbs address 0x04B 185897883Sgibbs access_mode RW 185997883Sgibbs modes M_CFG 1860102681Sgibbs field ENSELDO 0x40 1861102681Sgibbs field ENSELDI 0x20 1862102681Sgibbs field ENSELINGO 0x10 1863102681Sgibbs field ENIOERR 0x08 1864102681Sgibbs field ENOVERRUN 0x04 1865102681Sgibbs field ENSPIORDY 0x02 1866102681Sgibbs field ENARBDO 0x01 186797883Sgibbs} 186897883Sgibbs 186997883Sgibbs/* 187097883Sgibbs * SCSI Status 1 187197883Sgibbs */ 187297883Sgibbsregister SSTAT1 { 187397883Sgibbs address 0x04C 187497883Sgibbs access_mode RO 187597883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1876102681Sgibbs field SELTO 0x80 1877102681Sgibbs field ATNTARG 0x40 1878102681Sgibbs field SCSIRSTI 0x20 1879102681Sgibbs field PHASEMIS 0x10 1880102681Sgibbs field BUSFREE 0x08 1881102681Sgibbs field SCSIPERR 0x04 1882102681Sgibbs field STRB2FAST 0x02 1883102681Sgibbs field REQINIT 0x01 188497883Sgibbs} 188597883Sgibbs 188697883Sgibbs/* 188797883Sgibbs * Clear SCSI Interrupt 1 188897883Sgibbs * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 188997883Sgibbs */ 189097883Sgibbsregister CLRSINT1 { 1891104023Sgibbs address 0x04C 189297883Sgibbs access_mode WO 189397883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1894102681Sgibbs field CLRSELTIMEO 0x80 1895102681Sgibbs field CLRATNO 0x40 1896102681Sgibbs field CLRSCSIRSTI 0x20 1897102681Sgibbs field CLRBUSFREE 0x08 1898102681Sgibbs field CLRSCSIPERR 0x04 1899102681Sgibbs field CLRSTRB2FAST 0x02 1900102681Sgibbs field CLRREQINIT 0x01 190197883Sgibbs} 190297883Sgibbs 190397883Sgibbs/* 190497883Sgibbs * SCSI Status 2 190597883Sgibbs */ 190697883Sgibbsregister SSTAT2 { 190797883Sgibbs address 0x04d 190897883Sgibbs access_mode RO 190997883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1910102681Sgibbs field BUSFREETIME 0xc0 { 1911102681Sgibbs BUSFREE_LQO 0x40, 1912102681Sgibbs BUSFREE_DFF0 0x80, 1913102681Sgibbs BUSFREE_DFF1 0xC0 1914102681Sgibbs } 1915102681Sgibbs field NONPACKREQ 0x20 1916102681Sgibbs field EXP_ACTIVE 0x10 /* SCSI Expander Active */ 1917102681Sgibbs field BSYX 0x08 /* Busy Expander */ 1918102681Sgibbs field WIDE_RES 0x04 /* Modes 0 and 1 only */ 1919102681Sgibbs field SDONE 0x02 /* Modes 0 and 1 only */ 1920102681Sgibbs field DMADONE 0x01 /* Modes 0 and 1 only */ 192197883Sgibbs} 192297883Sgibbs 192397883Sgibbs/* 192497883Sgibbs * Clear SCSI Interrupt 2 192597883Sgibbs */ 192697883Sgibbsregister CLRSINT2 { 192797883Sgibbs address 0x04D 192897883Sgibbs access_mode WO 192997883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1930102681Sgibbs field CLRNONPACKREQ 0x20 1931102681Sgibbs field CLRWIDE_RES 0x04 /* Modes 0 and 1 only */ 1932102681Sgibbs field CLRSDONE 0x02 /* Modes 0 and 1 only */ 1933102681Sgibbs field CLRDMADONE 0x01 /* Modes 0 and 1 only */ 193497883Sgibbs} 193597883Sgibbs 193697883Sgibbs/* 193797883Sgibbs * SCSI Interrupt Mode 2 193897883Sgibbs */ 193997883Sgibbsregister SIMODE2 { 194097883Sgibbs address 0x04D 194197883Sgibbs access_mode RW 194297883Sgibbs modes M_CFG 1943102681Sgibbs field ENWIDE_RES 0x04 1944102681Sgibbs field ENSDONE 0x02 1945102681Sgibbs field ENDMADONE 0x01 194697883Sgibbs} 194797883Sgibbs 194897883Sgibbs/* 194997883Sgibbs * Physical Error Diagnosis 195097883Sgibbs */ 195197883Sgibbsregister PERRDIAG { 195297883Sgibbs address 0x04E 195397883Sgibbs access_mode RO 195497883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1955102681Sgibbs field HIZERO 0x80 1956102681Sgibbs field HIPERR 0x40 1957102681Sgibbs field PREVPHASE 0x20 1958102681Sgibbs field PARITYERR 0x10 1959102681Sgibbs field AIPERR 0x08 1960102681Sgibbs field CRCERR 0x04 1961102681Sgibbs field DGFORMERR 0x02 1962102681Sgibbs field DTERR 0x01 196397883Sgibbs} 196497883Sgibbs 196597883Sgibbs/* 196697883Sgibbs * LQI Manager Current State 196797883Sgibbs */ 196897883Sgibbsregister LQISTATE { 196997883Sgibbs address 0x04E 197097883Sgibbs access_mode RO 197197883Sgibbs modes M_CFG 197297883Sgibbs} 197397883Sgibbs 197497883Sgibbs/* 197597883Sgibbs * SCSI Offset Count 197697883Sgibbs */ 197797883Sgibbsregister SOFFCNT { 197897883Sgibbs address 0x04F 197997883Sgibbs access_mode RO 198097883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 198197883Sgibbs} 198297883Sgibbs 198397883Sgibbs/* 198497883Sgibbs * LQO Manager Current State 198597883Sgibbs */ 198697883Sgibbsregister LQOSTATE { 198797883Sgibbs address 0x04F 198897883Sgibbs access_mode RO 198997883Sgibbs modes M_CFG 199097883Sgibbs} 199197883Sgibbs 199297883Sgibbs/* 199397883Sgibbs * LQI Manager Status 199497883Sgibbs */ 199597883Sgibbsregister LQISTAT0 { 199697883Sgibbs address 0x050 199797883Sgibbs access_mode RO 199897883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1999102681Sgibbs field LQIATNQAS 0x20 2000102681Sgibbs field LQICRCT1 0x10 2001102681Sgibbs field LQICRCT2 0x08 2002102681Sgibbs field LQIBADLQT 0x04 2003102681Sgibbs field LQIATNLQ 0x02 2004102681Sgibbs field LQIATNCMD 0x01 200597883Sgibbs} 200697883Sgibbs 200797883Sgibbs/* 200897883Sgibbs * Clear LQI Interrupts 0 200997883Sgibbs */ 2010102681Sgibbsregister CLRLQIINT0 { 201197883Sgibbs address 0x050 201297883Sgibbs access_mode WO 201397883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2014102681Sgibbs field CLRLQIATNQAS 0x20 2015102681Sgibbs field CLRLQICRCT1 0x10 2016102681Sgibbs field CLRLQICRCT2 0x08 2017102681Sgibbs field CLRLQIBADLQT 0x04 2018102681Sgibbs field CLRLQIATNLQ 0x02 2019102681Sgibbs field CLRLQIATNCMD 0x01 202097883Sgibbs} 202197883Sgibbs 202297883Sgibbs/* 202397883Sgibbs * LQI Manager Interrupt Mode 0 202497883Sgibbs */ 202597883Sgibbsregister LQIMODE0 { 202697883Sgibbs address 0x050 202797883Sgibbs access_mode RW 202897883Sgibbs modes M_CFG 2029102681Sgibbs field ENLQIATNQASK 0x20 2030102681Sgibbs field ENLQICRCT1 0x10 2031102681Sgibbs field ENLQICRCT2 0x08 2032102681Sgibbs field ENLQIBADLQT 0x04 2033102681Sgibbs field ENLQIATNLQ 0x02 2034102681Sgibbs field ENLQIATNCMD 0x01 203597883Sgibbs} 203697883Sgibbs 203797883Sgibbs/* 203897883Sgibbs * LQI Manager Status 1 203997883Sgibbs */ 204097883Sgibbsregister LQISTAT1 { 204197883Sgibbs address 0x051 204297883Sgibbs access_mode RO 204397883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2044102681Sgibbs field LQIPHASE_LQ 0x80 2045102681Sgibbs field LQIPHASE_NLQ 0x40 2046102681Sgibbs field LQIABORT 0x20 2047102681Sgibbs field LQICRCI_LQ 0x10 2048102681Sgibbs field LQICRCI_NLQ 0x08 2049102681Sgibbs field LQIBADLQI 0x04 2050102681Sgibbs field LQIOVERI_LQ 0x02 2051102681Sgibbs field LQIOVERI_NLQ 0x01 205297883Sgibbs} 205397883Sgibbs 205497883Sgibbs/* 205597883Sgibbs * Clear LQI Manager Interrupts1 205697883Sgibbs */ 205797883Sgibbsregister CLRLQIINT1 { 205897883Sgibbs address 0x051 205997883Sgibbs access_mode WO 206097883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2061102681Sgibbs field CLRLQIPHASE_LQ 0x80 2062102681Sgibbs field CLRLQIPHASE_NLQ 0x40 2063102681Sgibbs field CLRLIQABORT 0x20 2064102681Sgibbs field CLRLQICRCI_LQ 0x10 2065102681Sgibbs field CLRLQICRCI_NLQ 0x08 2066102681Sgibbs field CLRLQIBADLQI 0x04 2067102681Sgibbs field CLRLQIOVERI_LQ 0x02 2068102681Sgibbs field CLRLQIOVERI_NLQ 0x01 206997883Sgibbs} 207097883Sgibbs 207197883Sgibbs/* 207297883Sgibbs * LQI Manager Interrupt Mode 1 207397883Sgibbs */ 207497883Sgibbsregister LQIMODE1 { 207597883Sgibbs address 0x051 207697883Sgibbs access_mode RW 207797883Sgibbs modes M_CFG 2078111653Sgibbs field ENLQIPHASE_LQ 0x80 /* LQIPHASE1 */ 2079111653Sgibbs field ENLQIPHASE_NLQ 0x40 /* LQIPHASE2 */ 2080102681Sgibbs field ENLIQABORT 0x20 2081111653Sgibbs field ENLQICRCI_LQ 0x10 /* LQICRCI1 */ 2082111653Sgibbs field ENLQICRCI_NLQ 0x08 /* LQICRCI2 */ 2083102681Sgibbs field ENLQIBADLQI 0x04 2084111653Sgibbs field ENLQIOVERI_LQ 0x02 /* LQIOVERI1 */ 2085111653Sgibbs field ENLQIOVERI_NLQ 0x01 /* LQIOVERI2 */ 208697883Sgibbs} 208797883Sgibbs 208897883Sgibbs/* 208997883Sgibbs * LQI Manager Status 2 209097883Sgibbs */ 209197883Sgibbsregister LQISTAT2 { 209297883Sgibbs address 0x052 209397883Sgibbs access_mode RO 209497883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2095102681Sgibbs field PACKETIZED 0x80 2096102681Sgibbs field LQIPHASE_OUTPKT 0x40 2097102681Sgibbs field LQIWORKONLQ 0x20 2098102681Sgibbs field LQIWAITFIFO 0x10 2099102681Sgibbs field LQISTOPPKT 0x08 2100102681Sgibbs field LQISTOPLQ 0x04 2101102681Sgibbs field LQISTOPCMD 0x02 2102102681Sgibbs field LQIGSAVAIL 0x01 210397883Sgibbs} 210497883Sgibbs 210597883Sgibbs/* 210697883Sgibbs * SCSI Status 3 210797883Sgibbs */ 210897883Sgibbsregister SSTAT3 { 210997883Sgibbs address 0x053 211097883Sgibbs access_mode RO 211197883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2112102681Sgibbs field NTRAMPERR 0x02 2113102681Sgibbs field OSRAMPERR 0x01 211497883Sgibbs} 211597883Sgibbs 211697883Sgibbs/* 211797883Sgibbs * Clear SCSI Status 3 211897883Sgibbs */ 211997883Sgibbsregister CLRSINT3 { 212097883Sgibbs address 0x053 212197883Sgibbs access_mode WO 212297883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2123102681Sgibbs field CLRNTRAMPERR 0x02 2124102681Sgibbs field CLROSRAMPERR 0x01 212597883Sgibbs} 212697883Sgibbs 212797883Sgibbs/* 212897883Sgibbs * SCSI Interrupt Mode 3 212997883Sgibbs */ 213097883Sgibbsregister SIMODE3 { 213197883Sgibbs address 0x053 213297883Sgibbs access_mode RW 213397883Sgibbs modes M_CFG 2134102681Sgibbs field ENNTRAMPERR 0x02 2135102681Sgibbs field ENOSRAMPERR 0x01 213697883Sgibbs} 213797883Sgibbs 213897883Sgibbs/* 213997883Sgibbs * LQO Manager Status 0 214097883Sgibbs */ 214197883Sgibbsregister LQOSTAT0 { 214297883Sgibbs address 0x054 214397883Sgibbs access_mode RO 214497883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2145102681Sgibbs field LQOTARGSCBPERR 0x10 2146102681Sgibbs field LQOSTOPT2 0x08 2147102681Sgibbs field LQOATNLQ 0x04 2148102681Sgibbs field LQOATNPKT 0x02 2149102681Sgibbs field LQOTCRC 0x01 215097883Sgibbs} 215197883Sgibbs 215297883Sgibbs/* 215397883Sgibbs * Clear LQO Manager interrupt 0 215497883Sgibbs */ 215597883Sgibbsregister CLRLQOINT0 { 215697883Sgibbs address 0x054 215797883Sgibbs access_mode WO 215897883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2159102681Sgibbs field CLRLQOTARGSCBPERR 0x10 2160102681Sgibbs field CLRLQOSTOPT2 0x08 2161102681Sgibbs field CLRLQOATNLQ 0x04 2162102681Sgibbs field CLRLQOATNPKT 0x02 2163102681Sgibbs field CLRLQOTCRC 0x01 216497883Sgibbs} 216597883Sgibbs 216697883Sgibbs/* 216797883Sgibbs * LQO Manager Interrupt Mode 0 216897883Sgibbs */ 216997883Sgibbsregister LQOMODE0 { 217097883Sgibbs address 0x054 217197883Sgibbs access_mode RW 217297883Sgibbs modes M_CFG 2173102681Sgibbs field ENLQOTARGSCBPERR 0x10 2174102681Sgibbs field ENLQOSTOPT2 0x08 2175102681Sgibbs field ENLQOATNLQ 0x04 2176102681Sgibbs field ENLQOATNPKT 0x02 2177102681Sgibbs field ENLQOTCRC 0x01 217897883Sgibbs} 217997883Sgibbs 218097883Sgibbs/* 218197883Sgibbs * LQO Manager Status 1 218297883Sgibbs */ 218397883Sgibbsregister LQOSTAT1 { 218497883Sgibbs address 0x055 218597883Sgibbs access_mode RO 218697883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2187102681Sgibbs field LQOINITSCBPERR 0x10 2188102681Sgibbs field LQOSTOPI2 0x08 2189102681Sgibbs field LQOBADQAS 0x04 2190102681Sgibbs field LQOBUSFREE 0x02 2191102681Sgibbs field LQOPHACHGINPKT 0x01 219297883Sgibbs} 219397883Sgibbs 219497883Sgibbs/* 219597883Sgibbs * Clear LOQ Interrupt 1 219697883Sgibbs */ 219797883Sgibbsregister CLRLQOINT1 { 219897883Sgibbs address 0x055 219997883Sgibbs access_mode WO 220097883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2201102681Sgibbs field CLRLQOINITSCBPERR 0x10 2202102681Sgibbs field CLRLQOSTOPI2 0x08 2203102681Sgibbs field CLRLQOBADQAS 0x04 2204102681Sgibbs field CLRLQOBUSFREE 0x02 2205102681Sgibbs field CLRLQOPHACHGINPKT 0x01 220697883Sgibbs} 220797883Sgibbs 220897883Sgibbs/* 220997883Sgibbs * LQO Manager Interrupt Mode 1 221097883Sgibbs */ 221197883Sgibbsregister LQOMODE1 { 221297883Sgibbs address 0x055 221397883Sgibbs access_mode RW 221497883Sgibbs modes M_CFG 2215102681Sgibbs field ENLQOINITSCBPERR 0x10 2216102681Sgibbs field ENLQOSTOPI2 0x08 2217102681Sgibbs field ENLQOBADQAS 0x04 2218102681Sgibbs field ENLQOBUSFREE 0x02 2219102681Sgibbs field ENLQOPHACHGINPKT 0x01 222097883Sgibbs} 222197883Sgibbs 222297883Sgibbs/* 222397883Sgibbs * LQO Manager Status 2 222497883Sgibbs */ 222597883Sgibbsregister LQOSTAT2 { 222697883Sgibbs address 0x056 222797883Sgibbs access_mode RO 222897883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2229102681Sgibbs field LQOPKT 0xE0 2230102681Sgibbs field LQOWAITFIFO 0x10 2231102681Sgibbs field LQOPHACHGOUTPKT 0x02 /* outside of packet boundaries. */ 2232102681Sgibbs field LQOSTOP0 0x01 /* Stopped after sending all packets */ 223397883Sgibbs} 223497883Sgibbs 223597883Sgibbs/* 223697883Sgibbs * Output Synchronizer Space Count 223797883Sgibbs */ 223897883Sgibbsregister OS_SPACE_CNT { 223997883Sgibbs address 0x056 224097883Sgibbs access_mode RO 224197883Sgibbs modes M_CFG 224297883Sgibbs} 224397883Sgibbs 224497883Sgibbs/* 224597883Sgibbs * SCSI Interrupt Mode 1 224697883Sgibbs * Setting any bit will enable the corresponding function 224797883Sgibbs * in SIMODE1 to interrupt via the IRQ pin. 224897883Sgibbs */ 224997883Sgibbsregister SIMODE1 { 225097883Sgibbs address 0x057 225197883Sgibbs access_mode RW 225297883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2253102681Sgibbs field ENSELTIMO 0x80 2254102681Sgibbs field ENATNTARG 0x40 2255102681Sgibbs field ENSCSIRST 0x20 2256102681Sgibbs field ENPHASEMIS 0x10 2257102681Sgibbs field ENBUSFREE 0x08 2258102681Sgibbs field ENSCSIPERR 0x04 2259102681Sgibbs field ENSTRB2FAST 0x02 2260102681Sgibbs field ENREQINIT 0x01 226197883Sgibbs} 226297883Sgibbs 226397883Sgibbs/* 226497883Sgibbs * Good Status FIFO 226597883Sgibbs */ 226697883Sgibbsregister GSFIFO { 226797883Sgibbs address 0x058 226897883Sgibbs access_mode RO 226997883Sgibbs size 2 227097883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 227197883Sgibbs} 227297883Sgibbs 227397883Sgibbs/* 227497883Sgibbs * Data FIFO SCSI Transfer Control 227597883Sgibbs */ 227697883Sgibbsregister DFFSXFRCTL { 227797883Sgibbs address 0x05A 227897883Sgibbs access_mode RW 227997883Sgibbs modes M_DFF0, M_DFF1 2280107441Sscottl field DFFBITBUCKET 0x08 2281102681Sgibbs field CLRSHCNT 0x04 2282102681Sgibbs field CLRCHN 0x02 2283102681Sgibbs field RSTCHN 0x01 228497883Sgibbs} 228597883Sgibbs 228697883Sgibbs/* 228797883Sgibbs * Next SCSI Control Block 228897883Sgibbs */ 228997883Sgibbsregister NEXTSCB { 229097883Sgibbs address 0x05A 229197883Sgibbs access_mode RW 229297883Sgibbs size 2 229397883Sgibbs modes M_SCSI 229497883Sgibbs} 2295107441Sscottl 2296107441Sscottl/* Rev B only. */ 2297107441Sscottlregister LQOSCSCTL { 2298107441Sscottl address 0x05A 2299107441Sscottl access_mode RW 2300107441Sscottl size 1 2301107441Sscottl modes M_CFG 2302107441Sscottl field LQOH2A_VERSION 0x80 2303107441Sscottl field LQONOCHKOVER 0x01 2304107441Sscottl} 2305107441Sscottl 230697883Sgibbs/* 230797883Sgibbs * SEQ Interrupts 230897883Sgibbs */ 230997883Sgibbsregister SEQINTSRC { 231097883Sgibbs address 0x05B 231197883Sgibbs access_mode RO 231297883Sgibbs modes M_DFF0, M_DFF1 2313102681Sgibbs field CTXTDONE 0x40 2314102681Sgibbs field SAVEPTRS 0x20 2315102681Sgibbs field CFG4DATA 0x10 2316102681Sgibbs field CFG4ISTAT 0x08 2317102681Sgibbs field CFG4TSTAT 0x04 2318102681Sgibbs field CFG4ICMD 0x02 2319102681Sgibbs field CFG4TCMD 0x01 232097883Sgibbs} 232197883Sgibbs 232297883Sgibbs/* 232397883Sgibbs * Clear Arp Interrupts 232497883Sgibbs */ 232597883Sgibbsregister CLRSEQINTSRC { 232697883Sgibbs address 0x05B 232797883Sgibbs access_mode WO 232897883Sgibbs modes M_DFF0, M_DFF1 2329102681Sgibbs field CLRCTXTDONE 0x40 2330102681Sgibbs field CLRSAVEPTRS 0x20 2331102681Sgibbs field CLRCFG4DATA 0x10 2332102681Sgibbs field CLRCFG4ISTAT 0x08 2333102681Sgibbs field CLRCFG4TSTAT 0x04 2334102681Sgibbs field CLRCFG4ICMD 0x02 2335102681Sgibbs field CLRCFG4TCMD 0x01 233697883Sgibbs} 233797883Sgibbs 233897883Sgibbs/* 233997883Sgibbs * SEQ Interrupt Enabled (Shared) 234097883Sgibbs */ 234197883Sgibbsregister SEQIMODE { 234297883Sgibbs address 0x05C 234397883Sgibbs access_mode RW 234497883Sgibbs modes M_DFF0, M_DFF1 2345102681Sgibbs field ENCTXTDONE 0x40 2346102681Sgibbs field ENSAVEPTRS 0x20 2347102681Sgibbs field ENCFG4DATA 0x10 2348102681Sgibbs field ENCFG4ISTAT 0x08 2349102681Sgibbs field ENCFG4TSTAT 0x04 2350102681Sgibbs field ENCFG4ICMD 0x02 2351102681Sgibbs field ENCFG4TCMD 0x01 235297883Sgibbs} 235397883Sgibbs 235497883Sgibbs/* 235597883Sgibbs * Current SCSI Control Block 235697883Sgibbs */ 235797883Sgibbsregister CURRSCB { 235897883Sgibbs address 0x05C 235997883Sgibbs access_mode RW 236097883Sgibbs size 2 236197883Sgibbs modes M_SCSI 236297883Sgibbs} 236397883Sgibbs 236497883Sgibbs/* 236597883Sgibbs * Data FIFO Status 236697883Sgibbs */ 236797883Sgibbsregister MDFFSTAT { 236897883Sgibbs address 0x05D 236997883Sgibbs access_mode RO 237097883Sgibbs modes M_DFF0, M_DFF1 2371102681Sgibbs field SHCNTNEGATIVE 0x40 /* Rev B or higher */ 2372102681Sgibbs field SHCNTMINUS1 0x20 /* Rev B or higher */ 2373102681Sgibbs field LASTSDONE 0x10 2374102681Sgibbs field SHVALID 0x08 2375102681Sgibbs field DLZERO 0x04 /* FIFO data ends on packet boundary. */ 2376102681Sgibbs field DATAINFIFO 0x02 2377102681Sgibbs field FIFOFREE 0x01 237897883Sgibbs} 237997883Sgibbs 238097883Sgibbs/* 238197883Sgibbs * CRC Control 238297883Sgibbs */ 238397883Sgibbsregister CRCCONTROL { 238497883Sgibbs address 0x05d 238597883Sgibbs access_mode RW 238697883Sgibbs modes M_CFG 2387102681Sgibbs field CRCVALCHKEN 0x40 238897883Sgibbs} 238997883Sgibbs 239097883Sgibbs/* 239197883Sgibbs * SCSI Test Control 239297883Sgibbs */ 239397883Sgibbsregister SCSITEST { 239497883Sgibbs address 0x05E 239597883Sgibbs access_mode RW 239697883Sgibbs modes M_CFG 2397102681Sgibbs field CNTRTEST 0x08 2398102681Sgibbs field SEL_TXPLL_DEBUG 0x04 239997883Sgibbs} 240097883Sgibbs 240197883Sgibbs/* 240297883Sgibbs * Data FIFO Queue Tag 240397883Sgibbs */ 240497883Sgibbsregister DFFTAG { 240597883Sgibbs address 0x05E 240697883Sgibbs access_mode RW 240797883Sgibbs size 2 240897883Sgibbs modes M_DFF0, M_DFF1 240997883Sgibbs} 241097883Sgibbs 241197883Sgibbs/* 241297883Sgibbs * Last SCSI Control Block 241397883Sgibbs */ 241497883Sgibbsregister LASTSCB { 241597883Sgibbs address 0x05E 241697883Sgibbs access_mode RW 241797883Sgibbs size 2 241897883Sgibbs modes M_SCSI 241997883Sgibbs} 242097883Sgibbs 242197883Sgibbs/* 242297883Sgibbs * SCSI I/O Cell Power-down Control 242397883Sgibbs */ 242497883Sgibbsregister IOPDNCTL { 242597883Sgibbs address 0x05F 242697883Sgibbs access_mode RW 242797883Sgibbs modes M_CFG 2428102681Sgibbs field DISABLE_OE 0x80 2429102681Sgibbs field PDN_IDIST 0x04 2430102681Sgibbs field PDN_DIFFSENSE 0x01 243197883Sgibbs} 243297883Sgibbs 243397883Sgibbs/* 243497883Sgibbs * Shaddow Host Address. 243597883Sgibbs */ 243697883Sgibbsregister SHADDR { 243797883Sgibbs address 0x060 243897883Sgibbs access_mode RO 243997883Sgibbs size 8 244097883Sgibbs modes M_DFF0, M_DFF1 244197883Sgibbs} 244297883Sgibbs 244397883Sgibbs/* 244497883Sgibbs * Data Group CRC Interval. 244597883Sgibbs */ 244697883Sgibbsregister DGRPCRCI { 244797883Sgibbs address 0x060 244897883Sgibbs access_mode RW 244997883Sgibbs size 2 245097883Sgibbs modes M_CFG 245197883Sgibbs} 245297883Sgibbs 245397883Sgibbs/* 245497883Sgibbs * Data Transfer Negotiation Address 245597883Sgibbs */ 245697883Sgibbsregister NEGOADDR { 245797883Sgibbs address 0x060 245897883Sgibbs access_mode RW 245997883Sgibbs modes M_SCSI 246097883Sgibbs} 246197883Sgibbs 246297883Sgibbs/* 246397883Sgibbs * Data Transfer Negotiation Data - Period Byte 246497883Sgibbs */ 246597883Sgibbsregister NEGPERIOD { 246697883Sgibbs address 0x061 246797883Sgibbs access_mode RW 246897883Sgibbs modes M_SCSI 246997883Sgibbs} 247097883Sgibbs 247197883Sgibbs/* 247297883Sgibbs * Packetized CRC Interval 247397883Sgibbs */ 247497883Sgibbsregister PACKCRCI { 247597883Sgibbs address 0x062 247697883Sgibbs access_mode RW 247797883Sgibbs size 2 247897883Sgibbs modes M_CFG 247997883Sgibbs} 248097883Sgibbs 248197883Sgibbs/* 248297883Sgibbs * Data Transfer Negotiation Data - Offset Byte 248397883Sgibbs */ 248497883Sgibbsregister NEGOFFSET { 248597883Sgibbs address 0x062 248697883Sgibbs access_mode RW 248797883Sgibbs modes M_SCSI 248897883Sgibbs} 248997883Sgibbs 249097883Sgibbs/* 249197883Sgibbs * Data Transfer Negotiation Data - PPR Options 249297883Sgibbs */ 249397883Sgibbsregister NEGPPROPTS { 249497883Sgibbs address 0x063 249597883Sgibbs access_mode RW 249697883Sgibbs modes M_SCSI 2497102681Sgibbs field PPROPT_PACE 0x08 2498102681Sgibbs field PPROPT_QAS 0x04 2499102681Sgibbs field PPROPT_DT 0x02 2500102681Sgibbs field PPROPT_IUT 0x01 250197883Sgibbs} 250297883Sgibbs 250397883Sgibbs/* 250497883Sgibbs * Data Transfer Negotiation Data - Connection Options 250597883Sgibbs */ 250697883Sgibbsregister NEGCONOPTS { 250797883Sgibbs address 0x064 250897883Sgibbs access_mode RW 250997883Sgibbs modes M_SCSI 2510107441Sscottl field ENSNAPSHOT 0x40 2511107441Sscottl field RTI_WRTDIS 0x20 2512107441Sscottl field RTI_OVRDTRN 0x10 2513107441Sscottl field ENSLOWCRC 0x08 2514102681Sgibbs field ENAUTOATNI 0x04 2515102681Sgibbs field ENAUTOATNO 0x02 2516102681Sgibbs field WIDEXFER 0x01 251797883Sgibbs} 251897883Sgibbs 251997883Sgibbs/* 252097883Sgibbs * Negotiation Table Annex Column Index. 252197883Sgibbs */ 252297883Sgibbsregister ANNEXCOL { 252397883Sgibbs address 0x065 252497883Sgibbs access_mode RW 252597883Sgibbs modes M_SCSI 252697883Sgibbs} 252797883Sgibbs 2528102681Sgibbsregister SCSCHKN { 2529102681Sgibbs address 0x066 2530102681Sgibbs access_mode RW 2531102681Sgibbs modes M_CFG 2532102681Sgibbs field STSELSKIDDIS 0x40 2533107441Sscottl field CURRFIFODEF 0x20 2534102681Sgibbs field WIDERESEN 0x10 2535102681Sgibbs field SDONEMSKDIS 0x08 2536102681Sgibbs field DFFACTCLR 0x04 2537102681Sgibbs field SHVALIDSTDIS 0x02 2538102681Sgibbs field LSTSGCLRDIS 0x01 2539102681Sgibbs} 2540102681Sgibbs 2541107441Sscottlconst AHD_ANNEXCOL_PER_DEV0 4 2542107441Sscottlconst AHD_NUM_PER_DEV_ANNEXCOLS 4 2543107441Sscottlconst AHD_ANNEXCOL_PRECOMP_SLEW 4 254497883Sgibbsconst AHD_PRECOMP_MASK 0x07 2545107441Sscottlconst AHD_PRECOMP_SHIFT 0 254697883Sgibbsconst AHD_PRECOMP_CUTBACK_17 0x04 254797883Sgibbsconst AHD_PRECOMP_CUTBACK_29 0x06 254897883Sgibbsconst AHD_PRECOMP_CUTBACK_37 0x07 2549107441Sscottlconst AHD_SLEWRATE_MASK 0x78 2550107441Sscottlconst AHD_SLEWRATE_SHIFT 3 2551107441Sscottl/* 2552112641Sscottl * Rev A has only a single bit (high bit of field) of slew adjustment. 2553112641Sscottl * Rev B has 4 bits. The current default happens to be the same for both. 2554107441Sscottl */ 2555112641Sscottlconst AHD_SLEWRATE_DEF_REVA 0x08 2556107441Sscottlconst AHD_SLEWRATE_DEF_REVB 0x08 255797883Sgibbs 2558107441Sscottl/* Rev A does not have any amplitude setting. */ 2559107441Sscottlconst AHD_ANNEXCOL_AMPLITUDE 6 2560107441Sscottlconst AHD_AMPLITUDE_MASK 0x7 2561107441Sscottlconst AHD_AMPLITUDE_SHIFT 0 2562107441Sscottlconst AHD_AMPLITUDE_DEF 0x7 2563107441Sscottl 256497883Sgibbs/* 256597883Sgibbs * Negotiation Table Annex Data Port. 256697883Sgibbs */ 256797883Sgibbsregister ANNEXDAT { 256897883Sgibbs address 0x066 256997883Sgibbs access_mode RW 257097883Sgibbs modes M_SCSI 257197883Sgibbs} 257297883Sgibbs 257397883Sgibbs/* 257497883Sgibbs * Initiator's Own Id. 257597883Sgibbs * The SCSI ID to use for Selection Out and seen during a reselection.. 257697883Sgibbs */ 257797883Sgibbsregister IOWNID { 257897883Sgibbs address 0x067 257997883Sgibbs access_mode RW 258097883Sgibbs modes M_SCSI 258197883Sgibbs} 258297883Sgibbs 258397883Sgibbs/* 258497883Sgibbs * 960MHz Phase-Locked Loop Control 0 258597883Sgibbs */ 258697883Sgibbsregister PLL960CTL0 { 258797883Sgibbs address 0x068 258897883Sgibbs access_mode RW 258997883Sgibbs modes M_CFG 2590102681Sgibbs field PLL_VCOSEL 0x80 2591102681Sgibbs field PLL_PWDN 0x40 2592102681Sgibbs field PLL_NS 0x30 2593102681Sgibbs field PLL_ENLUD 0x08 2594102681Sgibbs field PLL_ENLPF 0x04 2595102681Sgibbs field PLL_DLPF 0x02 2596102681Sgibbs field PLL_ENFBM 0x01 259797883Sgibbs} 259897883Sgibbs 259997883Sgibbs/* 260097883Sgibbs * Target Own Id 260197883Sgibbs */ 260297883Sgibbsregister TOWNID { 260397883Sgibbs address 0x069 260497883Sgibbs access_mode RW 260597883Sgibbs modes M_SCSI 260697883Sgibbs} 260797883Sgibbs 260897883Sgibbs/* 260997883Sgibbs * 960MHz Phase-Locked Loop Control 1 261097883Sgibbs */ 261197883Sgibbsregister PLL960CTL1 { 261297883Sgibbs address 0x069 261397883Sgibbs access_mode RW 261497883Sgibbs modes M_CFG 2615102681Sgibbs field PLL_CNTEN 0x80 2616102681Sgibbs field PLL_CNTCLR 0x40 2617102681Sgibbs field PLL_RST 0x01 261897883Sgibbs} 261997883Sgibbs 262097883Sgibbs/* 262197883Sgibbs * Expander Signature 262297883Sgibbs */ 262397883Sgibbsregister XSIG { 262497883Sgibbs address 0x06A 262597883Sgibbs access_mode RW 262697883Sgibbs modes M_SCSI 262797883Sgibbs} 262897883Sgibbs 262997883Sgibbs/* 263097883Sgibbs * Shadow Byte Count 263197883Sgibbs */ 263297883Sgibbsregister SHCNT { 263397883Sgibbs address 0x068 263497883Sgibbs access_mode RW 263597883Sgibbs size 3 263697883Sgibbs modes M_DFF0, M_DFF1 263797883Sgibbs} 263897883Sgibbs 263997883Sgibbs/* 264097883Sgibbs * Selection Out ID 264197883Sgibbs */ 264297883Sgibbsregister SELOID { 264397883Sgibbs address 0x06B 264497883Sgibbs access_mode RW 264597883Sgibbs modes M_SCSI 264697883Sgibbs} 264797883Sgibbs 264897883Sgibbs/* 264997883Sgibbs * 960-MHz Phase-Locked Loop Test Count 265097883Sgibbs */ 265197883Sgibbsregister PLL960CNT0 { 265297883Sgibbs address 0x06A 265397883Sgibbs access_mode RO 265497883Sgibbs size 2 265597883Sgibbs modes M_CFG 265697883Sgibbs} 265797883Sgibbs 265897883Sgibbs/* 265997883Sgibbs * 400-MHz Phase-Locked Loop Control 0 266097883Sgibbs */ 266197883Sgibbsregister PLL400CTL0 { 266297883Sgibbs address 0x06C 266397883Sgibbs access_mode RW 266497883Sgibbs modes M_CFG 2665102681Sgibbs field PLL_VCOSEL 0x80 2666102681Sgibbs field PLL_PWDN 0x40 2667102681Sgibbs field PLL_NS 0x30 2668102681Sgibbs field PLL_ENLUD 0x08 2669102681Sgibbs field PLL_ENLPF 0x04 2670102681Sgibbs field PLL_DLPF 0x02 2671102681Sgibbs field PLL_ENFBM 0x01 267297883Sgibbs} 267397883Sgibbs 267497883Sgibbs/* 267597883Sgibbs * Arbitration Fairness 267697883Sgibbs */ 267797883Sgibbsregister FAIRNESS { 267897883Sgibbs address 0x06C 267997883Sgibbs access_mode RW 268097883Sgibbs size 2 268197883Sgibbs modes M_SCSI 268297883Sgibbs} 268397883Sgibbs 268497883Sgibbs/* 268597883Sgibbs * 400-MHz Phase-Locked Loop Control 1 268697883Sgibbs */ 268797883Sgibbsregister PLL400CTL1 { 268897883Sgibbs address 0x06D 268997883Sgibbs access_mode RW 269097883Sgibbs modes M_CFG 2691102681Sgibbs field PLL_CNTEN 0x80 2692102681Sgibbs field PLL_CNTCLR 0x40 2693102681Sgibbs field PLL_RST 0x01 269497883Sgibbs} 269597883Sgibbs 269697883Sgibbs/* 269797883Sgibbs * Arbitration Unfairness 269897883Sgibbs */ 269997883Sgibbsregister UNFAIRNESS { 270097883Sgibbs address 0x06E 270197883Sgibbs access_mode RW 270297883Sgibbs size 2 270397883Sgibbs modes M_SCSI 270497883Sgibbs} 270597883Sgibbs 270697883Sgibbs/* 270797883Sgibbs * 400-MHz Phase-Locked Loop Test Count 270897883Sgibbs */ 270997883Sgibbsregister PLL400CNT0 { 271097883Sgibbs address 0x06E 271197883Sgibbs access_mode RO 271297883Sgibbs size 2 271397883Sgibbs modes M_CFG 271497883Sgibbs} 271597883Sgibbs 271697883Sgibbs/* 271797883Sgibbs * SCB Page Pointer 271897883Sgibbs */ 271997883Sgibbsregister SCBPTR { 272097883Sgibbs address 0x0A8 272197883Sgibbs access_mode RW 272297883Sgibbs size 2 272397883Sgibbs modes M_DFF0, M_DFF1, M_CCHAN, M_SCSI 272497883Sgibbs} 272597883Sgibbs 272697883Sgibbs/* 272797883Sgibbs * CMC SCB Array Count 272897883Sgibbs * Number of bytes to transfer between CMC SCB memory and SCBRAM. 272997883Sgibbs * Transfers must be 8byte aligned and sized. 273097883Sgibbs */ 273197883Sgibbsregister CCSCBACNT { 273297883Sgibbs address 0x0AB 273397883Sgibbs access_mode RW 273497883Sgibbs modes M_CCHAN 273597883Sgibbs} 273697883Sgibbs 273797883Sgibbs/* 273897883Sgibbs * SCB Autopointer 273997883Sgibbs * SCB-Next Address Snooping logic. When an SCB is transferred to 274097883Sgibbs * the card, the next SCB address to be used by the CMC array can 274197883Sgibbs * be autoloaded from that transfer. 274297883Sgibbs */ 274397883Sgibbsregister SCBAUTOPTR { 274497883Sgibbs address 0x0AB 274597883Sgibbs access_mode RW 274697883Sgibbs modes M_CFG 2747102681Sgibbs field AUSCBPTR_EN 0x80 2748102681Sgibbs field SCBPTR_ADDR 0x38 2749102681Sgibbs field SCBPTR_OFF 0x07 275097883Sgibbs} 275197883Sgibbs 275297883Sgibbs/* 275397883Sgibbs * CMC SG Ram Address Pointer 275497883Sgibbs */ 275597883Sgibbsregister CCSGADDR { 275697883Sgibbs address 0x0AC 275797883Sgibbs access_mode RW 275897883Sgibbs modes M_DFF0, M_DFF1 275997883Sgibbs} 276097883Sgibbs 276197883Sgibbs/* 276297883Sgibbs * CMC SCB RAM Address Pointer 276397883Sgibbs */ 276497883Sgibbsregister CCSCBADDR { 276597883Sgibbs address 0x0AC 276697883Sgibbs access_mode RW 276797883Sgibbs modes M_CCHAN 276897883Sgibbs} 276997883Sgibbs 277097883Sgibbs/* 277197883Sgibbs * CMC SCB Ram Back-up Address Pointer 277297883Sgibbs * Indicates the true stop location of transfers halted prior 277397883Sgibbs * to SCBHCNT going to 0. 277497883Sgibbs */ 277597883Sgibbsregister CCSCBADR_BK { 277697883Sgibbs address 0x0AC 277797883Sgibbs access_mode RO 277897883Sgibbs modes M_CFG 277997883Sgibbs} 278097883Sgibbs 278197883Sgibbs/* 278297883Sgibbs * CMC SG Control 278397883Sgibbs */ 278497883Sgibbsregister CCSGCTL { 278597883Sgibbs address 0x0AD 278697883Sgibbs access_mode RW 278797883Sgibbs modes M_DFF0, M_DFF1 2788102681Sgibbs field CCSGDONE 0x80 2789102681Sgibbs field SG_CACHE_AVAIL 0x10 2790107441Sscottl field CCSGENACK 0x08 2791107441Sscottl mask CCSGEN 0x0C 2792102681Sgibbs field SG_FETCH_REQ 0x02 2793102681Sgibbs field CCSGRESET 0x01 279497883Sgibbs} 279597883Sgibbs 279697883Sgibbs/* 279797883Sgibbs * CMD SCB Control 279897883Sgibbs */ 279997883Sgibbsregister CCSCBCTL { 280097883Sgibbs address 0x0AD 280197883Sgibbs access_mode RW 280297883Sgibbs modes M_CCHAN 2803102681Sgibbs field CCSCBDONE 0x80 2804102681Sgibbs field ARRDONE 0x40 2805102681Sgibbs field CCARREN 0x10 2806102681Sgibbs field CCSCBEN 0x08 2807102681Sgibbs field CCSCBDIR 0x04 2808102681Sgibbs field CCSCBRESET 0x01 280997883Sgibbs} 281097883Sgibbs 281197883Sgibbs/* 281297883Sgibbs * CMC Ram BIST 281397883Sgibbs */ 281497883Sgibbsregister CMC_RAMBIST { 281597883Sgibbs address 0x0AD 281697883Sgibbs access_mode RW 281797883Sgibbs modes M_CFG 2818102681Sgibbs field SG_ELEMENT_SIZE 0x80 2819102681Sgibbs field SCBRAMBIST_FAIL 0x40 2820102681Sgibbs field SG_BIST_FAIL 0x20 2821102681Sgibbs field SG_BIST_EN 0x10 2822102681Sgibbs field CMC_BUFFER_BIST_FAIL 0x02 2823102681Sgibbs field CMC_BUFFER_BIST_EN 0x01 282497883Sgibbs} 282597883Sgibbs 282697883Sgibbs/* 282797883Sgibbs * CMC SG RAM Data Port 282897883Sgibbs */ 282997883Sgibbsregister CCSGRAM { 283097883Sgibbs address 0x0B0 283197883Sgibbs access_mode RW 283297883Sgibbs modes M_DFF0, M_DFF1 283397883Sgibbs} 283497883Sgibbs 283597883Sgibbs/* 283697883Sgibbs * CMC SCB RAM Data Port 283797883Sgibbs */ 283897883Sgibbsregister CCSCBRAM { 283997883Sgibbs address 0x0B0 284097883Sgibbs access_mode RW 284197883Sgibbs modes M_CCHAN 284297883Sgibbs} 284397883Sgibbs 284497883Sgibbs/* 284597883Sgibbs * Flex DMA Address. 284697883Sgibbs */ 284797883Sgibbsregister FLEXADR { 284897883Sgibbs address 0x0B0 284997883Sgibbs access_mode RW 285097883Sgibbs size 3 285197883Sgibbs modes M_SCSI 285297883Sgibbs} 285397883Sgibbs 285497883Sgibbs/* 285597883Sgibbs * Flex DMA Byte Count 285697883Sgibbs */ 285797883Sgibbsregister FLEXCNT { 285897883Sgibbs address 0x0B3 285997883Sgibbs access_mode RW 286097883Sgibbs size 2 286197883Sgibbs modes M_SCSI 286297883Sgibbs} 286397883Sgibbs 286497883Sgibbs/* 286597883Sgibbs * Flex DMA Status 286697883Sgibbs */ 286797883Sgibbsregister FLEXDMASTAT { 286897883Sgibbs address 0x0B5 286997883Sgibbs access_mode RW 287097883Sgibbs modes M_SCSI 2871102681Sgibbs field FLEXDMAERR 0x02 2872102681Sgibbs field FLEXDMADONE 0x01 287397883Sgibbs} 287497883Sgibbs 287597883Sgibbs/* 287697883Sgibbs * Flex DMA Data Port 287797883Sgibbs */ 287897883Sgibbsregister FLEXDATA { 287997883Sgibbs address 0x0B6 288097883Sgibbs access_mode RW 288197883Sgibbs modes M_SCSI 288297883Sgibbs} 288397883Sgibbs 288497883Sgibbs/* 288597883Sgibbs * Board Data 288697883Sgibbs */ 288797883Sgibbsregister BRDDAT { 288897883Sgibbs address 0x0B8 288997883Sgibbs access_mode RW 289097883Sgibbs modes M_SCSI 289197883Sgibbs} 289297883Sgibbs 289397883Sgibbs/* 289497883Sgibbs * Board Control 289597883Sgibbs */ 289697883Sgibbsregister BRDCTL { 289797883Sgibbs address 0x0B9 289897883Sgibbs access_mode RW 289997883Sgibbs modes M_SCSI 2900102681Sgibbs field FLXARBACK 0x80 2901102681Sgibbs field FLXARBREQ 0x40 2902102681Sgibbs field BRDADDR 0x38 2903102681Sgibbs field BRDEN 0x04 2904102681Sgibbs field BRDRW 0x02 2905102681Sgibbs field BRDSTB 0x01 290697883Sgibbs} 290797883Sgibbs 290897883Sgibbs/* 290997883Sgibbs * Serial EEPROM Address 291097883Sgibbs */ 291197883Sgibbsregister SEEADR { 291297883Sgibbs address 0x0BA 291397883Sgibbs access_mode RW 291497883Sgibbs modes M_SCSI 291597883Sgibbs} 291697883Sgibbs 291797883Sgibbs/* 291897883Sgibbs * Serial EEPROM Data 291997883Sgibbs */ 292097883Sgibbsregister SEEDAT { 292197883Sgibbs address 0x0BC 292297883Sgibbs access_mode RW 292397883Sgibbs size 2 292497883Sgibbs modes M_SCSI 292597883Sgibbs} 292697883Sgibbs 292797883Sgibbs/* 292897883Sgibbs * Serial EEPROM Status 292997883Sgibbs */ 293097883Sgibbsregister SEESTAT { 293197883Sgibbs address 0x0BE 293297883Sgibbs access_mode RO 293397883Sgibbs modes M_SCSI 2934102681Sgibbs field INIT_DONE 0x80 2935102681Sgibbs field SEEOPCODE 0x70 2936102681Sgibbs field LDALTID_L 0x08 2937102681Sgibbs field SEEARBACK 0x04 2938102681Sgibbs field SEEBUSY 0x02 2939102681Sgibbs field SEESTART 0x01 294097883Sgibbs} 294197883Sgibbs 294297883Sgibbs/* 294397883Sgibbs * Serial EEPROM Control 294497883Sgibbs */ 294597883Sgibbsregister SEECTL { 294697883Sgibbs address 0x0BE 294797883Sgibbs access_mode RW 294897883Sgibbs modes M_SCSI 2949102681Sgibbs field SEEOPCODE 0x70 { 2950102681Sgibbs SEEOP_ERASE 0x70, 2951102681Sgibbs SEEOP_READ 0x60, 2952102681Sgibbs SEEOP_WRITE 0x50, 295397883Sgibbs /* 295497883Sgibbs * The following four commands use special 295597883Sgibbs * addresses for differentiation. 295697883Sgibbs */ 2957102681Sgibbs SEEOP_ERAL 0x40 2958102681Sgibbs } 295997883Sgibbs mask SEEOP_EWEN 0x40 296097883Sgibbs mask SEEOP_WALL 0x40 296197883Sgibbs mask SEEOP_EWDS 0x40 2962102681Sgibbs field SEERST 0x02 2963102681Sgibbs field SEESTART 0x01 296497883Sgibbs} 296597883Sgibbs 296697883Sgibbsconst SEEOP_ERAL_ADDR 0x80 296797883Sgibbsconst SEEOP_EWEN_ADDR 0xC0 296897883Sgibbsconst SEEOP_WRAL_ADDR 0x40 296997883Sgibbsconst SEEOP_EWDS_ADDR 0x00 297097883Sgibbs 297197883Sgibbs/* 297297883Sgibbs * SCB Counter 297397883Sgibbs */ 297497883Sgibbsregister SCBCNT { 297597883Sgibbs address 0x0BF 297697883Sgibbs access_mode RW 297797883Sgibbs modes M_SCSI 297897883Sgibbs} 297997883Sgibbs 298097883Sgibbs/* 298197883Sgibbs * Data FIFO Write Address 298297883Sgibbs * Pointer to the next QWD location to be written to the data FIFO. 298397883Sgibbs */ 298497883Sgibbsregister DFWADDR { 298597883Sgibbs address 0x0C0 298697883Sgibbs access_mode RW 298797883Sgibbs size 2 298897883Sgibbs modes M_DFF0, M_DFF1 298997883Sgibbs} 299097883Sgibbs 299197883Sgibbs/* 299297883Sgibbs * DSP Filter Control 299397883Sgibbs */ 299497883Sgibbsregister DSPFLTRCTL { 299597883Sgibbs address 0x0C0 299697883Sgibbs access_mode RW 299797883Sgibbs modes M_CFG 2998102681Sgibbs field FLTRDISABLE 0x20 2999102681Sgibbs field EDGESENSE 0x10 3000102681Sgibbs field DSPFCNTSEL 0x0F 300197883Sgibbs} 300297883Sgibbs 300397883Sgibbs/* 300497883Sgibbs * DSP Data Channel Control 300597883Sgibbs */ 300697883Sgibbsregister DSPDATACTL { 300797883Sgibbs address 0x0C1 300897883Sgibbs access_mode RW 300997883Sgibbs modes M_CFG 3010102681Sgibbs field BYPASSENAB 0x80 3011102681Sgibbs field DESQDIS 0x10 3012102681Sgibbs field RCVROFFSTDIS 0x04 3013102681Sgibbs field XMITOFFSTDIS 0x02 301497883Sgibbs} 301597883Sgibbs 301697883Sgibbs/* 301797883Sgibbs * Data FIFO Read Address 301897883Sgibbs * Pointer to the next QWD location to be read from the data FIFO. 301997883Sgibbs */ 302097883Sgibbsregister DFRADDR { 302197883Sgibbs address 0x0C2 302297883Sgibbs access_mode RW 302397883Sgibbs size 2 302497883Sgibbs modes M_DFF0, M_DFF1 302597883Sgibbs} 302697883Sgibbs 302797883Sgibbs/* 302897883Sgibbs * DSP REQ Control 302997883Sgibbs */ 303097883Sgibbsregister DSPREQCTL { 303197883Sgibbs address 0x0C2 303297883Sgibbs access_mode RW 303397883Sgibbs modes M_CFG 3034102681Sgibbs field MANREQCTL 0xC0 3035102681Sgibbs field MANREQDLY 0x3F 303697883Sgibbs} 303797883Sgibbs 303897883Sgibbs/* 303997883Sgibbs * DSP ACK Control 304097883Sgibbs */ 304197883Sgibbsregister DSPACKCTL { 304297883Sgibbs address 0x0C3 304397883Sgibbs access_mode RW 304497883Sgibbs modes M_CFG 3045102681Sgibbs field MANACKCTL 0xC0 3046102681Sgibbs field MANACKDLY 0x3F 304797883Sgibbs} 304897883Sgibbs 304997883Sgibbs/* 305097883Sgibbs * Data FIFO Data 305197883Sgibbs * Read/Write byte port into the data FIFO. The read and write 305297883Sgibbs * FIFO pointers increment with each read and write respectively 305397883Sgibbs * to this port. 305497883Sgibbs */ 305597883Sgibbsregister DFDAT { 305697883Sgibbs address 0x0C4 305797883Sgibbs access_mode RW 305897883Sgibbs modes M_DFF0, M_DFF1 305997883Sgibbs} 306097883Sgibbs 306197883Sgibbs/* 306297883Sgibbs * DSP Channel Select 306397883Sgibbs */ 306497883Sgibbsregister DSPSELECT { 306597883Sgibbs address 0x0C4 306697883Sgibbs access_mode RW 306797883Sgibbs modes M_CFG 3068102681Sgibbs field AUTOINCEN 0x80 3069102681Sgibbs field DSPSEL 0x1F 307097883Sgibbs} 307197883Sgibbs 307297883Sgibbsconst NUMDSPS 0x14 307397883Sgibbs 307497883Sgibbs/* 307597883Sgibbs * Write Bias Control 307697883Sgibbs */ 307797883Sgibbsregister WRTBIASCTL { 307897883Sgibbs address 0x0C5 307997883Sgibbs access_mode WO 308097883Sgibbs modes M_CFG 3081102681Sgibbs field AUTOXBCDIS 0x80 3082102681Sgibbs field XMITMANVAL 0x3F 308397883Sgibbs} 308497883Sgibbs 3085107441Sscottl/* 3086107441Sscottl * Currently the WRTBIASCTL is the same as the default. 3087107441Sscottl */ 3088107441Sscottlconst WRTBIASCTL_HP_DEFAULT 0x0 308997883Sgibbs 309097883Sgibbs/* 309197883Sgibbs * Receiver Bias Control 309297883Sgibbs */ 309397883Sgibbsregister RCVRBIOSCTL { 309497883Sgibbs address 0x0C6 309597883Sgibbs access_mode WO 309697883Sgibbs modes M_CFG 3097102681Sgibbs field AUTORBCDIS 0x80 3098102681Sgibbs field RCVRMANVAL 0x3F 309997883Sgibbs} 310097883Sgibbs 310197883Sgibbs/* 310297883Sgibbs * Write Bias Calculator 310397883Sgibbs */ 310497883Sgibbsregister WRTBIASCALC { 310597883Sgibbs address 0x0C7 310697883Sgibbs access_mode RO 310797883Sgibbs modes M_CFG 310897883Sgibbs} 310997883Sgibbs 311097883Sgibbs/* 311197883Sgibbs * Data FIFO Pointers 311297883Sgibbs * Contains the byte offset from DFWADDR and DWRADDR to the current 311397883Sgibbs * FIFO write/read locations. 311497883Sgibbs */ 311597883Sgibbsregister DFPTRS { 311697883Sgibbs address 0x0C8 311797883Sgibbs access_mode RW 311897883Sgibbs modes M_DFF0, M_DFF1 311997883Sgibbs} 312097883Sgibbs 312197883Sgibbs/* 312297883Sgibbs * Receiver Bias Calculator 312397883Sgibbs */ 312497883Sgibbsregister RCVRBIASCALC { 312597883Sgibbs address 0x0C8 312697883Sgibbs access_mode RO 312797883Sgibbs modes M_CFG 312897883Sgibbs} 312997883Sgibbs 313097883Sgibbs/* 313197883Sgibbs * Data FIFO Backup Read Pointer 313297883Sgibbs * Contains the data FIFO address to be restored if the last 313397883Sgibbs * data accessed from the data FIFO was not transferred successfully. 313497883Sgibbs */ 313597883Sgibbsregister DFBKPTR { 313697883Sgibbs address 0x0C9 313797883Sgibbs access_mode RW 313897883Sgibbs size 2 313997883Sgibbs modes M_DFF0, M_DFF1 314097883Sgibbs} 314197883Sgibbs 314297883Sgibbs/* 314397883Sgibbs * Skew Calculator 314497883Sgibbs */ 314597883Sgibbsregister SKEWCALC { 314697883Sgibbs address 0x0C9 314797883Sgibbs access_mode RO 314897883Sgibbs modes M_CFG 314997883Sgibbs} 315097883Sgibbs 315197883Sgibbs/* 3152109588Sgibbs * Data FIFO Debug Control 3153109588Sgibbs */ 3154109588Sgibbsregister DFDBCTL { 3155109588Sgibbs address 0x0CB 3156109588Sgibbs access_mode RW 3157109588Sgibbs modes M_DFF0, M_DFF1 3158109588Sgibbs field DFF_CIO_WR_RDY 0x20 3159109588Sgibbs field DFF_CIO_RD_RDY 0x10 3160109588Sgibbs field DFF_DIR_ERR 0x08 3161109588Sgibbs field DFF_RAMBIST_FAIL 0x04 3162109588Sgibbs field DFF_RAMBIST_DONE 0x02 3163109588Sgibbs field DFF_RAMBIST_EN 0x01 3164109588Sgibbs} 3165109588Sgibbs 3166109588Sgibbs/* 316797883Sgibbs * Data FIFO Space Count 316897883Sgibbs * Number of FIFO locations that are free. 316997883Sgibbs */ 317097883Sgibbsregister DFSCNT { 317197883Sgibbs address 0x0CC 317297883Sgibbs access_mode RO 317397883Sgibbs size 2 317497883Sgibbs modes M_DFF0, M_DFF1 317597883Sgibbs} 317697883Sgibbs 317797883Sgibbs/* 317897883Sgibbs * Data FIFO Byte Count 317997883Sgibbs * Number of filled FIFO locations. 318097883Sgibbs */ 318197883Sgibbsregister DFBCNT { 318297883Sgibbs address 0x0CE 318397883Sgibbs access_mode RO 318497883Sgibbs size 2 318597883Sgibbs modes M_DFF0, M_DFF1 318697883Sgibbs} 318797883Sgibbs 318897883Sgibbs/* 318997883Sgibbs * Sequencer Program Overlay Address. 319097883Sgibbs * Low address must be written prior to high address. 319197883Sgibbs */ 319297883Sgibbsregister OVLYADDR { 319397883Sgibbs address 0x0D4 319497883Sgibbs modes M_SCSI 319597883Sgibbs size 2 319697883Sgibbs access_mode RW 319797883Sgibbs} 319897883Sgibbs 319997883Sgibbs/* 320097883Sgibbs * Sequencer Control 0 320197883Sgibbs * Error detection mode, speed configuration, 320297883Sgibbs * single step, breakpoints and program load. 320397883Sgibbs */ 320497883Sgibbsregister SEQCTL0 { 320597883Sgibbs address 0x0D6 320697883Sgibbs access_mode RW 3207102681Sgibbs field PERRORDIS 0x80 3208102681Sgibbs field PAUSEDIS 0x40 3209102681Sgibbs field FAILDIS 0x20 3210102681Sgibbs field FASTMODE 0x10 3211102681Sgibbs field BRKADRINTEN 0x08 3212102681Sgibbs field STEP 0x04 3213102681Sgibbs field SEQRESET 0x02 3214102681Sgibbs field LOADRAM 0x01 321597883Sgibbs} 321697883Sgibbs 321797883Sgibbs/* 321897883Sgibbs * Sequencer Control 1 321997883Sgibbs * Instruction RAM Diagnostics 322097883Sgibbs */ 322197883Sgibbsregister SEQCTL1 { 322297883Sgibbs address 0x0D7 322397883Sgibbs access_mode RW 3224102681Sgibbs field OVRLAY_DATA_CHK 0x08 3225102681Sgibbs field RAMBIST_DONE 0x04 3226102681Sgibbs field RAMBIST_FAIL 0x02 3227102681Sgibbs field RAMBIST_EN 0x01 322897883Sgibbs} 322997883Sgibbs 323097883Sgibbs/* 323197883Sgibbs * Sequencer Flags 323297883Sgibbs * Zero and Carry state of the ALU. 323397883Sgibbs */ 323497883Sgibbsregister FLAGS { 323597883Sgibbs address 0x0D8 323697883Sgibbs access_mode RO 3237102681Sgibbs field ZERO 0x02 3238102681Sgibbs field CARRY 0x01 323997883Sgibbs} 324097883Sgibbs 324197883Sgibbs/* 324297883Sgibbs * Sequencer Interrupt Control 324397883Sgibbs */ 324497883Sgibbsregister SEQINTCTL { 324597883Sgibbs address 0x0D9 324697883Sgibbs access_mode RW 3247102681Sgibbs field INTVEC1DSL 0x80 3248102681Sgibbs field INT1_CONTEXT 0x20 3249102681Sgibbs field SCS_SEQ_INT1M1 0x10 3250102681Sgibbs field SCS_SEQ_INT1M0 0x08 3251109588Sgibbs field INTMASK2 0x04 3252109588Sgibbs field INTMASK1 0x02 3253102681Sgibbs field IRET 0x01 325497883Sgibbs} 325597883Sgibbs 325697883Sgibbs/* 325797883Sgibbs * Sequencer RAM Data Port 325897883Sgibbs * Single byte window into the Sequencer Instruction Ram area starting 325997883Sgibbs * at the address specified by OVLYADDR. To write a full instruction word, 326097883Sgibbs * simply write four bytes in succession. OVLYADDR will increment after the 326197883Sgibbs * most significant instrution byte (the byte with the parity bit) is written. 326297883Sgibbs */ 326397883Sgibbsregister SEQRAM { 326497883Sgibbs address 0x0DA 326597883Sgibbs access_mode RW 326697883Sgibbs} 326797883Sgibbs 326897883Sgibbs/* 326997883Sgibbs * Sequencer Program Counter 327097883Sgibbs * Low byte must be written prior to high byte. 327197883Sgibbs */ 327297883Sgibbsregister PRGMCNT { 327397883Sgibbs address 0x0DE 327497883Sgibbs access_mode RW 327597883Sgibbs size 2 327697883Sgibbs} 327797883Sgibbs 327897883Sgibbs/* 327997883Sgibbs * Accumulator 328097883Sgibbs */ 328197883Sgibbsregister ACCUM { 328297883Sgibbs address 0x0E0 328397883Sgibbs access_mode RW 328497883Sgibbs accumulator 328597883Sgibbs} 328697883Sgibbs 328797883Sgibbs/* 328897883Sgibbs * Source Index Register 328997883Sgibbs * Incrementing index for reads of SINDIR and the destination (low byte only) 329097883Sgibbs * for any immediate operands passed in jmp, jc, jnc, call instructions. 329197883Sgibbs * Example: 329297883Sgibbs * mvi 0xFF call some_routine; 329397883Sgibbs * 329497883Sgibbs * Will set SINDEX[0] to 0xFF and call the routine "some_routine. 329597883Sgibbs */ 329697883Sgibbsregister SINDEX { 329797883Sgibbs address 0x0E2 329897883Sgibbs access_mode RW 329997883Sgibbs size 2 330097883Sgibbs sindex 330197883Sgibbs} 330297883Sgibbs 330397883Sgibbs/* 330497883Sgibbs * Destination Index Register 330597883Sgibbs * Incrementing index for writes to DINDIR. Can be used as a scratch register. 330697883Sgibbs */ 330797883Sgibbsregister DINDEX { 330897883Sgibbs address 0x0E4 330997883Sgibbs access_mode RW 331097883Sgibbs size 2 331197883Sgibbs} 331297883Sgibbs 331397883Sgibbs/* 331497883Sgibbs * Break Address 331597883Sgibbs * Sequencer instruction breakpoint address address. 331697883Sgibbs */ 331797883Sgibbsregister BRKADDR0 { 331897883Sgibbs address 0x0E6 331997883Sgibbs access_mode RW 332097883Sgibbs} 332197883Sgibbs 332297883Sgibbsregister BRKADDR1 { 332397883Sgibbs address 0x0E6 332497883Sgibbs access_mode RW 3325102681Sgibbs field BRKDIS 0x80 /* Disable Breakpoint */ 332697883Sgibbs} 332797883Sgibbs 332897883Sgibbs/* 332997883Sgibbs * All Ones 333097883Sgibbs * All reads to this register return the value 0xFF. 333197883Sgibbs */ 333297883Sgibbsregister ALLONES { 333397883Sgibbs address 0x0E8 333497883Sgibbs access_mode RO 333597883Sgibbs allones 333697883Sgibbs} 333797883Sgibbs 333897883Sgibbs/* 333997883Sgibbs * All Zeros 334097883Sgibbs * All reads to this register return the value 0. 334197883Sgibbs */ 334297883Sgibbsregister ALLZEROS { 334397883Sgibbs address 0x0EA 334497883Sgibbs access_mode RO 334597883Sgibbs allzeros 334697883Sgibbs} 334797883Sgibbs 334897883Sgibbs/* 334997883Sgibbs * No Destination 335097883Sgibbs * Writes to this register have no effect. 335197883Sgibbs */ 335297883Sgibbsregister NONE { 335397883Sgibbs address 0x0EA 335497883Sgibbs access_mode WO 335597883Sgibbs none 335697883Sgibbs} 335797883Sgibbs 335897883Sgibbs/* 335997883Sgibbs * Source Index Indirect 336097883Sgibbs * Reading this register is equivalent to reading (register_base + SINDEX) and 336197883Sgibbs * incrementing SINDEX by 1. 336297883Sgibbs */ 336397883Sgibbsregister SINDIR { 336497883Sgibbs address 0x0EC 336597883Sgibbs access_mode RO 336697883Sgibbs} 336797883Sgibbs 336897883Sgibbs/* 336997883Sgibbs * Destination Index Indirect 337097883Sgibbs * Writing this register is equivalent to writing to (register_base + DINDEX) 337197883Sgibbs * and incrementing DINDEX by 1. 337297883Sgibbs */ 337397883Sgibbsregister DINDIR { 337497883Sgibbs address 0x0ED 337597883Sgibbs access_mode WO 337697883Sgibbs} 337797883Sgibbs 337897883Sgibbs/* 337997883Sgibbs * Function One 338097883Sgibbs * 2's complement to bit value conversion. Write the 2's complement value 338197883Sgibbs * (0-7 only) to the top nibble and retrieve the bit indexed by that value 338297883Sgibbs * on the next read of this register. 338397883Sgibbs * Example: 338497883Sgibbs * Write 0x60 338597883Sgibbs * Read 0x40 338697883Sgibbs */ 338797883Sgibbsregister FUNCTION1 { 338897883Sgibbs address 0x0F0 338997883Sgibbs access_mode RW 339097883Sgibbs} 339197883Sgibbs 339297883Sgibbs/* 339397883Sgibbs * Stack 339497883Sgibbs * Window into the stack. Each stack location is 10 bits wide reported 339597883Sgibbs * low byte followed by high byte. There are 8 stack locations. 339697883Sgibbs */ 339797883Sgibbsregister STACK { 339897883Sgibbs address 0x0F2 339997883Sgibbs access_mode RW 340097883Sgibbs} 340197883Sgibbs 340297883Sgibbs/* 340397883Sgibbs * Interrupt Vector 1 Address 340497883Sgibbs * Interrupt branch address for SCS SEQ_INT1 mode 0 and 1 interrupts. 340597883Sgibbs */ 340697883Sgibbsregister INTVEC1_ADDR { 340797883Sgibbs address 0x0F4 340897883Sgibbs access_mode RW 340997883Sgibbs size 2 341097883Sgibbs modes M_CFG 341197883Sgibbs} 341297883Sgibbs 341397883Sgibbs/* 341497883Sgibbs * Current Address 341597883Sgibbs * Address of the SEQRAM instruction currently executing instruction. 341697883Sgibbs */ 341797883Sgibbsregister CURADDR { 341897883Sgibbs address 0x0F4 341997883Sgibbs access_mode RW 342097883Sgibbs size 2 342197883Sgibbs modes M_SCSI 342297883Sgibbs} 342397883Sgibbs 342497883Sgibbs/* 342597883Sgibbs * Interrupt Vector 2 Address 342697883Sgibbs * Interrupt branch address for HST_SEQ_INT2 interrupts. 342797883Sgibbs */ 342897883Sgibbsregister INTVEC2_ADDR { 342997883Sgibbs address 0x0F6 343097883Sgibbs access_mode RW 343197883Sgibbs size 2 343297883Sgibbs modes M_CFG 343397883Sgibbs} 343497883Sgibbs 343597883Sgibbs/* 343697883Sgibbs * Last Address 343797883Sgibbs * Address of the SEQRAM instruction executed prior to the current instruction. 343897883Sgibbs */ 343997883Sgibbsregister LASTADDR { 344097883Sgibbs address 0x0F6 344197883Sgibbs access_mode RW 344297883Sgibbs size 2 344397883Sgibbs modes M_SCSI 344497883Sgibbs} 344597883Sgibbs 344697883Sgibbsregister AHD_PCI_CONFIG_BASE { 344797883Sgibbs address 0x100 344897883Sgibbs access_mode RW 344997883Sgibbs size 256 345097883Sgibbs modes M_CFG 345197883Sgibbs} 345297883Sgibbs 345397883Sgibbs/* ---------------------- Scratch RAM Offsets ------------------------- */ 345497883Sgibbsscratch_ram { 345597883Sgibbs /* Mode Specific */ 345697883Sgibbs address 0x0A0 345797883Sgibbs size 8 345897883Sgibbs modes 0, 1, 2, 3 345997883Sgibbs REG0 { 346097883Sgibbs size 2 346197883Sgibbs } 346297883Sgibbs REG1 { 346397883Sgibbs size 2 346497883Sgibbs } 3465104023Sgibbs REG_ISR { 346697883Sgibbs size 2 346797883Sgibbs } 346897883Sgibbs SG_STATE { 346997883Sgibbs size 1 3470102681Sgibbs field SEGS_AVAIL 0x01 3471102681Sgibbs field LOADING_NEEDED 0x02 3472102681Sgibbs field FETCH_INPROG 0x04 347397883Sgibbs } 347497883Sgibbs /* 347597883Sgibbs * Track whether the transfer byte count for 347697883Sgibbs * the current data phase is odd. 347797883Sgibbs */ 347897883Sgibbs DATA_COUNT_ODD { 347997883Sgibbs size 1 348097883Sgibbs } 348197883Sgibbs} 348297883Sgibbs 348397883Sgibbsscratch_ram { 348497883Sgibbs /* Mode Specific */ 348597883Sgibbs address 0x0F8 348697883Sgibbs size 8 348797883Sgibbs modes 0, 1, 2, 3 348897883Sgibbs LONGJMP_ADDR { 348997883Sgibbs size 2 349097883Sgibbs } 349197883Sgibbs ACCUM_SAVE { 349297883Sgibbs size 1 349397883Sgibbs } 349497883Sgibbs} 349597883Sgibbs 349697883Sgibbs 349797883Sgibbsscratch_ram { 349897883Sgibbs address 0x100 349997883Sgibbs size 128 350097883Sgibbs modes 0, 1, 2, 3 350197883Sgibbs /* 350297883Sgibbs * Per "other-id" execution queues. We use an array of 350397883Sgibbs * tail pointers into lists of SCBs sorted by "other-id". 350497883Sgibbs * The execution head pointer threads the head SCBs for 350597883Sgibbs * each list. 350697883Sgibbs */ 350797883Sgibbs WAITING_SCB_TAILS { 350897883Sgibbs size 32 350997883Sgibbs } 351097883Sgibbs WAITING_TID_HEAD { 351197883Sgibbs size 2 351297883Sgibbs } 351397883Sgibbs WAITING_TID_TAIL { 351497883Sgibbs size 2 351597883Sgibbs } 351697883Sgibbs /* 351797883Sgibbs * SCBID of the next SCB in the new SCB queue. 351897883Sgibbs */ 351997883Sgibbs NEXT_QUEUED_SCB_ADDR { 352097883Sgibbs size 4 352197883Sgibbs } 352297883Sgibbs /* 352397883Sgibbs * head of list of SCBs that have 352497883Sgibbs * completed but have not been 352597883Sgibbs * put into the qoutfifo. 352697883Sgibbs */ 352797883Sgibbs COMPLETE_SCB_HEAD { 352897883Sgibbs size 2 352997883Sgibbs } 353097883Sgibbs /* 353197883Sgibbs * The list of completed SCBs in 353297883Sgibbs * the active DMA. 353397883Sgibbs */ 353497883Sgibbs COMPLETE_SCB_DMAINPROG_HEAD { 353597883Sgibbs size 2 353697883Sgibbs } 353797883Sgibbs /* 353897883Sgibbs * head of list of SCBs that have 353997883Sgibbs * completed but need to be uploaded 354097883Sgibbs * to the host prior to being completed. 354197883Sgibbs */ 354297883Sgibbs COMPLETE_DMA_SCB_HEAD { 354397883Sgibbs size 2 354497883Sgibbs } 354597883Sgibbs /* Counting semaphore to prevent new select-outs */ 354697883Sgibbs QFREEZE_COUNT { 354797883Sgibbs size 2 354897883Sgibbs } 354997883Sgibbs /* 3550107441Sscottl * Mode to restore on legacy idle loop exit. 355197883Sgibbs */ 355297883Sgibbs SAVED_MODE { 355397883Sgibbs size 1 355497883Sgibbs } 355597883Sgibbs /* 355697883Sgibbs * Single byte buffer used to designate the type or message 355797883Sgibbs * to send to a target. 355897883Sgibbs */ 355997883Sgibbs MSG_OUT { 356097883Sgibbs size 1 356197883Sgibbs } 356297883Sgibbs /* Parameters for DMA Logic */ 356397883Sgibbs DMAPARAMS { 356497883Sgibbs size 1 3565102681Sgibbs field PRELOADEN 0x80 3566102681Sgibbs field WIDEODD 0x40 3567102681Sgibbs field SCSIEN 0x20 3568102681Sgibbs field SDMAEN 0x10 3569102681Sgibbs field SDMAENACK 0x10 3570102681Sgibbs field HDMAEN 0x08 3571102681Sgibbs field HDMAENACK 0x08 3572102681Sgibbs field DIRECTION 0x04 /* Set indicates PCI->SCSI */ 3573102681Sgibbs field FIFOFLUSH 0x02 3574102681Sgibbs field FIFORESET 0x01 357597883Sgibbs } 357697883Sgibbs SEQ_FLAGS { 357797883Sgibbs size 1 3578102681Sgibbs field NOT_IDENTIFIED 0x80 3579104023Sgibbs field NO_CDB_SENT 0x40 3580102681Sgibbs field TARGET_CMD_IS_TAGGED 0x40 3581102681Sgibbs field DPHASE 0x20 358297883Sgibbs /* Target flags */ 3583102681Sgibbs field TARG_CMD_PENDING 0x10 3584102681Sgibbs field CMDPHASE_PENDING 0x08 3585102681Sgibbs field DPHASE_PENDING 0x04 3586102681Sgibbs field SPHASE_PENDING 0x02 3587102681Sgibbs field NO_DISCONNECT 0x01 358897883Sgibbs } 358997883Sgibbs /* 359097883Sgibbs * Temporary storage for the 359197883Sgibbs * target/channel/lun of a 359297883Sgibbs * reconnecting target 359397883Sgibbs */ 359497883Sgibbs SAVED_SCSIID { 359597883Sgibbs size 1 359697883Sgibbs } 359797883Sgibbs SAVED_LUN { 359897883Sgibbs size 1 359997883Sgibbs } 360097883Sgibbs /* 360197883Sgibbs * The last bus phase as seen by the sequencer. 360297883Sgibbs */ 360397883Sgibbs LASTPHASE { 360497883Sgibbs size 1 3605102681Sgibbs field CDI 0x80 3606102681Sgibbs field IOI 0x40 3607102681Sgibbs field MSGI 0x20 3608104023Sgibbs field P_BUSFREE 0x01 3609102681Sgibbs enum PHASE_MASK CDO|IOO|MSGO { 3610102681Sgibbs P_DATAOUT 0x0, 3611102681Sgibbs P_DATAIN IOO, 3612102681Sgibbs P_DATAOUT_DT P_DATAOUT|MSGO, 3613102681Sgibbs P_DATAIN_DT P_DATAIN|MSGO, 3614102681Sgibbs P_COMMAND CDO, 3615102681Sgibbs P_MESGOUT CDO|MSGO, 3616102681Sgibbs P_STATUS CDO|IOO, 3617104023Sgibbs P_MESGIN CDO|IOO|MSGO 3618102681Sgibbs } 361997883Sgibbs } 362097883Sgibbs /* 3621107441Sscottl * Value to "or" into the SCBPTR[1] value to 3622107441Sscottl * indicate that an entry in the QINFIFO is valid. 3623107441Sscottl */ 3624107441Sscottl QOUTFIFO_ENTRY_VALID_TAG { 3625107441Sscottl size 1 3626107441Sscottl } 3627107441Sscottl /* 362897883Sgibbs * Base address of our shared data with the kernel driver in host 362997883Sgibbs * memory. This includes the qoutfifo and target mode 363097883Sgibbs * incoming command queue. 363197883Sgibbs */ 363297883Sgibbs SHARED_DATA_ADDR { 363397883Sgibbs size 4 363497883Sgibbs } 363597883Sgibbs /* 363697883Sgibbs * Pointer to location in host memory for next 363797883Sgibbs * position in the qoutfifo. 363897883Sgibbs */ 363997883Sgibbs QOUTFIFO_NEXT_ADDR { 364097883Sgibbs size 4 364197883Sgibbs } 364297883Sgibbs /* 364397883Sgibbs * Kernel and sequencer offsets into the queue of 364497883Sgibbs * incoming target mode command descriptors. The 364597883Sgibbs * queue is full when the KERNEL_TQINPOS == TQINPOS. 364697883Sgibbs */ 364797883Sgibbs KERNEL_TQINPOS { 364897883Sgibbs size 1 364997883Sgibbs } 365097883Sgibbs TQINPOS { 365197883Sgibbs size 1 365297883Sgibbs } 365397883Sgibbs ARG_1 { 365497883Sgibbs size 1 365597883Sgibbs mask SEND_MSG 0x80 365697883Sgibbs mask SEND_SENSE 0x40 365797883Sgibbs mask SEND_REJ 0x20 365897883Sgibbs mask MSGOUT_PHASEMIS 0x10 365997883Sgibbs mask EXIT_MSG_LOOP 0x08 366097883Sgibbs mask CONT_MSG_LOOP_WRITE 0x04 366197883Sgibbs mask CONT_MSG_LOOP_READ 0x03 366297883Sgibbs mask CONT_MSG_LOOP_TARG 0x02 366397883Sgibbs alias RETURN_1 366497883Sgibbs } 366597883Sgibbs ARG_2 { 366697883Sgibbs size 1 366797883Sgibbs alias RETURN_2 366897883Sgibbs } 366997883Sgibbs 367097883Sgibbs /* 367197883Sgibbs * Snapshot of MSG_OUT taken after each message is sent. 367297883Sgibbs */ 367397883Sgibbs LAST_MSG { 367497883Sgibbs size 1 367597883Sgibbs } 367697883Sgibbs 367797883Sgibbs /* 367897883Sgibbs * Sequences the kernel driver has okayed for us. This allows 367997883Sgibbs * the driver to do things like prevent initiator or target 368097883Sgibbs * operations. 368197883Sgibbs */ 368297883Sgibbs SCSISEQ_TEMPLATE { 368397883Sgibbs size 1 3684102681Sgibbs field MANUALCTL 0x40 3685102681Sgibbs field ENSELI 0x20 3686102681Sgibbs field ENRSELI 0x10 3687102681Sgibbs field MANUALP 0x0C 3688102681Sgibbs field ENAUTOATNP 0x02 3689102681Sgibbs field ALTSTIM 0x01 369097883Sgibbs } 369197883Sgibbs 369297883Sgibbs /* 369397883Sgibbs * The initiator specified tag for this target mode transaction. 369497883Sgibbs */ 369597883Sgibbs INITIATOR_TAG { 369697883Sgibbs size 1 369797883Sgibbs } 369897883Sgibbs 369997883Sgibbs SEQ_FLAGS2 { 370097883Sgibbs size 1 3701102681Sgibbs field TARGET_MSG_PENDING 0x02 3702102681Sgibbs field SELECTOUT_QFROZEN 0x04 370397883Sgibbs } 3704104023Sgibbs 3705104023Sgibbs ALLOCFIFO_SCBPTR { 3706104023Sgibbs size 2 3707104023Sgibbs } 3708104023Sgibbs 370997883Sgibbs /* 3710115329Sgibbs * The maximum amount of time to wait, when interrupt coalescing 3711109588Sgibbs * is enabled, before issueing a CMDCMPLT interrupt for a completed 3712109588Sgibbs * command. 3713109588Sgibbs */ 3714115329Sgibbs INT_COALESCING_TIMER { 3715109588Sgibbs size 2 3716109588Sgibbs } 3717109588Sgibbs 3718109588Sgibbs /* 3719115329Sgibbs * The maximum number of commands to coalesce into a single interrupt. 3720109588Sgibbs * Actually the 2's complement of that value to simplify sequencer 3721109588Sgibbs * code. 3722109588Sgibbs */ 3723115329Sgibbs INT_COALESCING_MAXCMDS { 3724109588Sgibbs size 1 3725109588Sgibbs } 3726109588Sgibbs 3727109588Sgibbs /* 3728109588Sgibbs * The minimum number of commands still outstanding required 3729115329Sgibbs * to continue coalescing (2's complement of value). 3730109588Sgibbs */ 3731115329Sgibbs INT_COALESCING_MINCMDS { 3732109588Sgibbs size 1 3733109588Sgibbs } 3734109588Sgibbs 3735109588Sgibbs /* 3736109588Sgibbs * Number of commands "in-flight". 3737109588Sgibbs */ 3738109588Sgibbs CMDS_PENDING { 3739109588Sgibbs size 2 3740109588Sgibbs } 3741109588Sgibbs 3742109588Sgibbs /* 3743115329Sgibbs * The count of commands that have been coalesced. 3744109588Sgibbs */ 3745115329Sgibbs INT_COALESCING_CMDCOUNT { 3746109588Sgibbs size 1 3747109588Sgibbs } 3748109588Sgibbs 3749109588Sgibbs /* 3750109588Sgibbs * Since the HS_MAIBOX is self clearing, copy its contents to 3751109588Sgibbs * this position in scratch ram every time it changes. 3752109588Sgibbs */ 3753109588Sgibbs LOCAL_HS_MAILBOX { 3754109588Sgibbs size 1 3755109588Sgibbs } 3756109588Sgibbs /* 375797883Sgibbs * Target-mode CDB type to CDB length table used 375897883Sgibbs * in non-packetized operation. 375997883Sgibbs */ 376097883Sgibbs CMDSIZE_TABLE { 376197883Sgibbs size 8 376297883Sgibbs } 376397883Sgibbs} 376497883Sgibbs 376597883Sgibbs/************************* Hardware SCB Definition ****************************/ 376697883Sgibbsscb { 376797883Sgibbs address 0x180 376897883Sgibbs size 64 376997883Sgibbs modes 0, 1, 2, 3 377097883Sgibbs SCB_RESIDUAL_DATACNT { 377197883Sgibbs size 4 377297883Sgibbs alias SCB_CDB_STORE 3773111653Sgibbs alias SCB_HOST_CDB_PTR 377497883Sgibbs } 377597883Sgibbs SCB_RESIDUAL_SGPTR { 377697883Sgibbs size 4 3777102681Sgibbs field SG_ADDR_MASK 0xf8 /* In the last byte */ 3778102681Sgibbs field SG_OVERRUN_RESID 0x02 /* In the first byte */ 3779102681Sgibbs field SG_LIST_NULL 0x01 /* In the first byte */ 378097883Sgibbs } 378197883Sgibbs SCB_SCSI_STATUS { 378297883Sgibbs size 1 3783111653Sgibbs alias SCB_HOST_CDB_LEN 378497883Sgibbs } 378597883Sgibbs SCB_TARGET_PHASES { 378697883Sgibbs size 1 378797883Sgibbs } 378897883Sgibbs SCB_TARGET_DATA_DIR { 378997883Sgibbs size 1 379097883Sgibbs } 379197883Sgibbs SCB_TARGET_ITAG { 379297883Sgibbs size 1 379397883Sgibbs } 379497883Sgibbs SCB_SENSE_BUSADDR { 379597883Sgibbs /* 379697883Sgibbs * Only valid if CDB length is less than 13 bytes or 379797883Sgibbs * we are using a CDB pointer. Otherwise contains 379897883Sgibbs * the last 4 bytes of embedded cdb information. 379997883Sgibbs */ 380097883Sgibbs size 4 380197883Sgibbs alias SCB_NEXT_COMPLETE 380297883Sgibbs } 3803115407Sscottl SCB_TAG { 3804115407Sscottl alias SCB_FIFO_USE_COUNT 3805114623Sgibbs size 2 3806114623Sgibbs } 380797883Sgibbs SCB_CONTROL { 380897883Sgibbs size 1 3809102681Sgibbs field TARGET_SCB 0x80 3810102681Sgibbs field DISCENB 0x40 3811102681Sgibbs field TAG_ENB 0x20 3812102681Sgibbs field MK_MESSAGE 0x10 3813102681Sgibbs field STATUS_RCVD 0x08 3814102681Sgibbs field DISCONNECTED 0x04 3815102681Sgibbs field SCB_TAG_TYPE 0x03 381697883Sgibbs } 381797883Sgibbs SCB_SCSIID { 381897883Sgibbs size 1 3819102681Sgibbs field TID 0xF0 3820102681Sgibbs field OID 0x0F 382197883Sgibbs } 382297883Sgibbs SCB_LUN { 382397883Sgibbs size 1 3824115335Sgibbs field LID 0xff 382597883Sgibbs } 382697883Sgibbs SCB_TASK_ATTRIBUTE { 382797883Sgibbs size 1 3828115335Sgibbs /* 3829115335Sgibbs * Overloaded field for non-packetized 3830115335Sgibbs * ignore wide residue message handling. 3831115335Sgibbs */ 3832115335Sgibbs field SCB_XFERLEN_ODD 0x01 383397883Sgibbs } 3834114623Sgibbs SCB_CDB_LEN { 3835114623Sgibbs size 1 3836114623Sgibbs field SCB_CDB_LEN_PTR 0x80 /* CDB in host memory */ 383797883Sgibbs } 3838114623Sgibbs SCB_TASK_MANAGEMENT { 3839114623Sgibbs size 1 3840114623Sgibbs } 3841115407Sscottl SCB_DATAPTR { 3842115407Sscottl size 8 3843115407Sscottl } 3844115407Sscottl SCB_DATACNT { 3845115407Sscottl /* 3846115407Sscottl * The last byte is really the high address bits for 3847115407Sscottl * the data address. 3848115407Sscottl */ 3849115407Sscottl size 4 3850115407Sscottl field SG_LAST_SEG 0x80 /* In the fourth byte */ 3851115407Sscottl field SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */ 3852115407Sscottl } 3853115407Sscottl SCB_SGPTR { 3854115407Sscottl size 4 3855115407Sscottl field SG_STATUS_VALID 0x04 /* In the first byte */ 3856115407Sscottl field SG_FULL_RESID 0x02 /* In the first byte */ 3857115407Sscottl field SG_LIST_NULL 0x01 /* In the first byte */ 3858115407Sscottl } 3859115407Sscottl SCB_BUSADDR { 3860115407Sscottl size 4 3861115407Sscottl } 3862115407Sscottl SCB_NEXT { 3863115407Sscottl alias SCB_NEXT_SCB_BUSADDR 3864114623Sgibbs size 2 3865114623Sgibbs } 3866115407Sscottl SCB_NEXT2 { 3867115407Sscottl size 2 3868115407Sscottl } 3869102681Sgibbs SCB_SPARE { 3870102681Sgibbs size 8 3871102681Sgibbs alias SCB_PKT_LUN 3872102681Sgibbs } 387397883Sgibbs SCB_DISCONNECTED_LISTS { 3874102681Sgibbs size 8 387597883Sgibbs } 387697883Sgibbs} 387797883Sgibbs 387897883Sgibbs/*********************************** Constants ********************************/ 387997883Sgibbsconst MK_MESSAGE_BIT_OFFSET 4 388097883Sgibbsconst TID_SHIFT 4 388197883Sgibbsconst TARGET_CMD_CMPLT 0xfe 388297883Sgibbsconst INVALID_ADDR 0x80 388397883Sgibbs#define SCB_LIST_NULL 0xff 3884102681Sgibbs#define QOUTFIFO_ENTRY_VALID_TOGGLE 0x80 388597883Sgibbs 388697883Sgibbsconst CCSGADDR_MAX 0x80 388797883Sgibbsconst CCSCBADDR_MAX 0x80 388897883Sgibbsconst CCSGRAM_MAXSEGS 16 388997883Sgibbs 389097883Sgibbs/* Selection Timeout Timer Constants */ 389197883Sgibbsconst STIMESEL_SHIFT 3 389297883Sgibbsconst STIMESEL_MIN 0x18 389397883Sgibbsconst STIMESEL_BUG_ADJ 0x8 389497883Sgibbs 389597883Sgibbs/* WDTR Message values */ 389697883Sgibbsconst BUS_8_BIT 0x00 389797883Sgibbsconst BUS_16_BIT 0x01 389897883Sgibbsconst BUS_32_BIT 0x02 389997883Sgibbs 390097883Sgibbs/* Offset maximums */ 390197883Sgibbsconst MAX_OFFSET 0xfe 3902107441Sscottlconst MAX_OFFSET_PACED 0xfe 3903107441Sscottlconst MAX_OFFSET_PACED_BUG 0x7f 3904107441Sscottl/* 3905107441Sscottl * Some 160 devices incorrectly accept 0xfe as a 3906107441Sscottl * sync offset, but will overrun this value. Limit 3907107441Sscottl * to 0x7f for speed lower than U320 which will 3908107441Sscottl * avoid the persistent sync offset overruns. 3909107441Sscottl */ 3910107441Sscottlconst MAX_OFFSET_NON_PACED 0x7f 391197883Sgibbsconst HOST_MSG 0xff 391297883Sgibbs 391397883Sgibbs/* 391497883Sgibbs * The size of our sense buffers. 391597883Sgibbs * Sense buffer mapping can be handled in either of two ways. 391697883Sgibbs * The first is to allocate a dmamap for each transaction. 391797883Sgibbs * Depending on the architecture, dmamaps can be costly. The 391897883Sgibbs * alternative is to statically map the buffers in much the same 391997883Sgibbs * way we handle our scatter gather lists. The driver implements 392097883Sgibbs * the later. 392197883Sgibbs */ 392297883Sgibbsconst AHD_SENSE_BUFSIZE 256 392397883Sgibbs 392497883Sgibbs/* Target mode command processing constants */ 392597883Sgibbsconst CMD_GROUP_CODE_SHIFT 0x05 392697883Sgibbs 392797883Sgibbsconst STATUS_BUSY 0x08 392897883Sgibbsconst STATUS_QUEUE_FULL 0x28 392997883Sgibbsconst STATUS_PKT_SENSE 0xFF 393097883Sgibbsconst TARGET_DATA_IN 1 393197883Sgibbs 3932102681Sgibbsconst SCB_TRANSFER_SIZE_FULL_LUN 56 3933102681Sgibbsconst SCB_TRANSFER_SIZE_1BYTE_LUN 48 393497883Sgibbs/* PKT_OVERRUN_BUFSIZE must be a multiple of 256 less than 64K */ 393597883Sgibbsconst PKT_OVERRUN_BUFSIZE 512 393697883Sgibbs 393797883Sgibbs/* 3938109588Sgibbs * Timer parameters. 3939109588Sgibbs */ 3940109588Sgibbsconst AHD_TIMER_US_PER_TICK 25 3941109588Sgibbsconst AHD_TIMER_MAX_TICKS 0xFFFF 3942109709Sgibbsconst AHD_TIMER_MAX_US (AHD_TIMER_MAX_TICKS * AHD_TIMER_US_PER_TICK) 3943109588Sgibbs 3944109588Sgibbs/* 394597883Sgibbs * Downloaded (kernel inserted) constants 394697883Sgibbs */ 394797883Sgibbsconst SG_PREFETCH_CNT download 394897883Sgibbsconst SG_PREFETCH_CNT_LIMIT download 394997883Sgibbsconst SG_PREFETCH_ALIGN_MASK download 395097883Sgibbsconst SG_PREFETCH_ADDR_MASK download 395197883Sgibbsconst SG_SIZEOF download 395297883Sgibbsconst PKT_OVERRUN_BUFOFFSET download 3953102681Sgibbsconst SCB_TRANSFER_SIZE download 395497883Sgibbs 395597883Sgibbs/* 395697883Sgibbs * BIOS SCB offsets 395797883Sgibbs */ 395897883Sgibbsconst NVRAM_SCB_OFFSET 0x2C 3959