aic79xx.reg revision 114623 
1/*
2 * Aic79xx register and scratch ram definitions.
3 *
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions, and the following disclaimer,
13 *    without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 *    substantially similar to the "NO WARRANTY" disclaimer below
16 *    ("Disclaimer") and any redistribution must be conditioned upon
17 *    including a substantially similar Disclaimer requirement for further
18 *    binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 *    of any contributors may be used to endorse or promote products derived
21 *    from this software without specific prior written permission.
22 *
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
26 *
27 * NO WARRANTY
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
40 * $FreeBSD: head/sys/dev/aic7xxx/aic79xx.reg 114623 2003-05-04 00:20:07Z gibbs $
41 */
42VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#67 $"
43
44/*
45 * This file is processed by the aic7xxx_asm utility for use in assembling
46 * firmware for the aic79xx family of SCSI host adapters as well as to generate
47 * a C header file for use in the kernel portion of the Aic79xx driver.
48 */
49
50/* Register window Modes */
51#define M_DFF0		0
52#define M_DFF1		1
53#define M_CCHAN		2
54#define M_SCSI		3
55#define M_CFG		4
56#define M_DST_SHIFT	4
57
58#define MK_MODE(src, dst) ((src) | ((dst) << M_DST_SHIFT))
59#define SET_MODE(src, dst)						\
60	SET_SRC_MODE	src;						\
61	SET_DST_MODE	dst;						\
62	if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) {			\
63		mvi	MK_MODE(src, dst) call set_mode_work_around;	\
64	} else {							\
65		mvi	MODE_PTR, MK_MODE(src, dst);			\
66	}
67
68#define TOGGLE_DFF_MODE							\
69	if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) {			\
70		call	toggle_dff_mode_work_around;			\
71	} else {							\
72		xor	MODE_PTR, MK_MODE(M_DFF1, M_DFF1);		\
73	}
74	
75#define RESTORE_MODE(mode)						\
76	if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) {			\
77		mov	mode call set_mode_work_around;			\
78	} else {							\
79		mov	MODE_PTR, mode;					\
80	}
81
82#define SET_SEQINTCODE(code)						\
83	if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {			\
84		mvi	code call set_seqint_work_around;		\
85	} else {							\
86		mvi	SEQINTCODE, code;				\
87	}
88
89/*
90 * Mode Pointer
91 * Controls which of the 5, 512byte, address spaces should be used
92 * as the source and destination of any register accesses in our
93 * register window.
94 */
95register MODE_PTR {
96	address			0x000
97	access_mode	RW
98	field	DST_MODE	0x70
99	field	SRC_MODE	0x07
100	mode_pointer
101}
102
103const SRC_MODE_SHIFT	0
104const DST_MODE_SHIFT	4
105
106/*
107 * Host Interrupt Status
108 */
109register INTSTAT {
110	address			0x001
111	access_mode	RW
112	field	HWERRINT	0x80
113	field	BRKADRINT	0x40
114	field	SWTMINT		0x20
115	field	PCIINT		0x10
116	field	SCSIINT		0x08
117	field	SEQINT		0x04
118	field	CMDCMPLT	0x02
119	field	SPLTINT		0x01
120	mask	INT_PEND 0xFF
121}
122
123/*
124 * Sequencer Interrupt Code
125 */
126register SEQINTCODE {
127	address			0x002
128	access_mode	RW
129	field {
130		NO_SEQINT,			/* No seqint pending. */
131		BAD_PHASE,			/* unknown scsi bus phase */
132		SEND_REJECT,			/* sending a message reject */
133		PROTO_VIOLATION, 		/* Protocol Violation */
134		NO_MATCH,			/* no cmd match for reconnect */
135		IGN_WIDE_RES,			/* Complex IGN Wide Res Msg */
136		PDATA_REINIT,			/*
137						 * Returned to data phase
138						 * that requires data
139						 * transfer pointers to be
140						 * recalculated from the
141						 * transfer residual.
142						 */
143		HOST_MSG_LOOP,			/*
144						 * The bus is ready for the
145						 * host to perform another
146						 * message transaction.  This
147						 * mechanism is used for things
148						 * like sync/wide negotiation
149						 * that require a kernel based
150						 * message state engine.
151						 */
152		BAD_STATUS,			/* Bad status from target */
153		DATA_OVERRUN,			/*
154						 * Target attempted to write
155						 * beyond the bounds of its
156						 * command.
157						 */
158		MKMSG_FAILED,			/*
159						 * Target completed command
160						 * without honoring our ATN
161						 * request to issue a message. 
162						 */
163		MISSED_BUSFREE,			/*
164						 * The sequencer never saw
165						 * the bus go free after
166						 * either a command complete
167						 * or disconnect message.
168						 */
169		DUMP_CARD_STATE,
170		ILLEGAL_PHASE,
171		INVALID_SEQINT,
172		CFG4ISTAT_INTR,
173		STATUS_OVERRUN,
174		CFG4OVERRUN,
175		ENTERING_NONPACK,
176		TASKMGMT_FUNC_COMPLETE,		/*
177						 * Task management function
178						 * request completed with
179						 * an expected busfree.
180						 */
181		TASKMGMT_CMD_CMPLT_OKAY,	/*
182						 * A command with a non-zero
183						 * task management function
184						 * has completed via the normal
185						 * command completion method
186						 * for commands with a zero
187						 * task management function.
188						 * This happens when an attempt
189						 * to abort a command loses
190						 * the race for the command to
191						 * complete normally.
192						 */
193		TRACEPOINT0,
194		TRACEPOINT1,
195		TRACEPOINT2,
196		TRACEPOINT3,
197		SAW_HWERR,
198		BAD_SCB_STATUS
199	}
200}
201
202/*
203 * Clear Host Interrupt
204 */
205register CLRINT {
206	address			0x003
207	access_mode	WO
208	field	CLRHWERRINT	0x80 /* Rev B or greater */
209	field	CLRBRKADRINT	0x40
210	field	CLRSWTMINT	0x20
211	field	CLRPCIINT	0x10
212	field	CLRSCSIINT	0x08
213	field	CLRSEQINT	0x04
214	field	CLRCMDINT	0x02
215	field	CLRSPLTINT	0x01
216}
217
218/*
219 * Error Register
220 */
221register ERROR {
222	address			0x004
223	access_mode	RO
224	field	CIOPARERR	0x80
225	field	CIOACCESFAIL	0x40 /* Rev B or greater */
226	field	MPARERR		0x20
227	field	DPARERR		0x10
228	field	SQPARERR	0x08
229	field	ILLOPCODE	0x04
230	field	DSCTMOUT	0x02
231}
232
233/*
234 * Clear Error
235 */
236register CLRERR {
237	address			0x004
238	access_mode 	WO
239	field	CLRCIOPARERR	0x80
240	field	CLRCIOACCESFAIL	0x40 /* Rev B or greater */
241	field	CLRMPARERR	0x20
242	field	CLRDPARERR	0x10
243	field	CLRSQPARERR	0x08
244	field	CLRILLOPCODE	0x04
245	field	CLRDSCTMOUT	0x02
246}
247
248/*
249 * Host Control Register
250 * Overall host control of the device.
251 */
252register HCNTRL {
253	address			0x005
254	access_mode	RW
255	field	SEQ_RESET	0x80 /* Rev B or greater */
256	field	POWRDN		0x40
257	field	SWINT		0x10
258	field	SWTIMER_START_B	0x08 /* Rev B or greater */
259	field	PAUSE		0x04
260	field	INTEN		0x02
261	field	CHIPRST		0x01
262	field	CHIPRSTACK	0x01
263}
264
265/*
266 * Host New SCB Queue Offset
267 */
268register HNSCB_QOFF {
269	address			0x006
270	access_mode	RW
271	size		2
272}
273
274/*
275 * Host Empty SCB Queue Offset
276 */
277register HESCB_QOFF {
278	address			0x008
279	access_mode	RW
280}
281
282/*
283 * Host Mailbox
284 */
285register HS_MAILBOX {
286	address			0x00B
287	access_mode	RW
288	mask	HOST_TQINPOS	0x80	/* Boundary at either 0 or 128 */
289	mask	ENINT_COALESS	0x40	/* Perform interrupt coalessing */
290}
291
292/*
293 * Sequencer Interupt Status
294 */
295register SEQINTSTAT {
296	address			0x00C
297	access_mode	RO
298	field	SEQ_SWTMRTO	0x10
299	field	SEQ_SEQINT	0x08
300	field	SEQ_SCSIINT	0x04
301	field	SEQ_PCIINT	0x02
302	field	SEQ_SPLTINT	0x01
303}
304
305/*
306 * Clear SEQ Interrupt
307 */
308register CLRSEQINTSTAT {
309	address			0x00C
310	access_mode	WO
311	field	CLRSEQ_SWTMRTO	0x10
312	field	CLRSEQ_SEQINT	0x08
313	field	CLRSEQ_SCSIINT	0x04
314	field	CLRSEQ_PCIINT	0x02
315	field	CLRSEQ_SPLTINT	0x01
316}
317
318/*
319 * Software Timer
320 */
321register SWTIMER {
322	address			0x00E
323	access_mode	RW
324	size		2
325}
326
327/*
328 * SEQ New SCB Queue Offset
329 */
330register SNSCB_QOFF {
331	address			0x010
332	access_mode	RW
333	size		2
334	modes		M_CCHAN
335}
336
337/*
338 * SEQ Empty SCB Queue Offset
339 */
340register SESCB_QOFF {
341	address			0x012
342	access_mode	RW
343	modes		M_CCHAN
344}
345
346/*
347 * SEQ Done SCB Queue Offset
348 */
349register SDSCB_QOFF {
350	address			0x014
351	access_mode	RW
352	modes		M_CCHAN
353	size		2
354}
355
356/*
357 * Queue Offset Control & Status
358 */
359register QOFF_CTLSTA {
360	address			0x016
361	access_mode	RW
362	modes		M_CCHAN
363	field	EMPTY_SCB_AVAIL	0x80
364	field	NEW_SCB_AVAIL	0x40
365	field	SDSCB_ROLLOVR	0x20
366	field	HS_MAILBOX_ACT	0x10
367	field	SCB_QSIZE	0x0F {
368		SCB_QSIZE_4,
369		SCB_QSIZE_8,
370		SCB_QSIZE_16,
371		SCB_QSIZE_32,
372		SCB_QSIZE_64,
373		SCB_QSIZE_128,
374		SCB_QSIZE_256,
375		SCB_QSIZE_512,
376		SCB_QSIZE_1024,
377		SCB_QSIZE_2048,
378		SCB_QSIZE_4096,
379		SCB_QSIZE_8192,
380		SCB_QSIZE_16384
381	}
382}
383
384/*
385 * Interrupt Control
386 */
387register INTCTL {
388	address			0x018
389	access_mode	RW
390	field	SWTMINTMASK	0x80
391	field	SWTMINTEN	0x40
392	field	SWTIMER_START	0x20
393	field	AUTOCLRCMDINT	0x10
394	field	PCIINTEN	0x08
395	field	SCSIINTEN	0x04
396	field	SEQINTEN	0x02
397	field	SPLTINTEN	0x01
398}
399
400/*
401 * Data FIFO Control
402 */
403register DFCNTRL {
404	address			0x019
405	access_mode	RW
406	modes		M_DFF0, M_DFF1
407	field	PRELOADEN	0x80
408	field	SCSIENWRDIS	0x40	/* Rev B only. */
409	field	SCSIEN		0x20
410	field	SCSIENACK	0x20
411	field	HDMAEN		0x08
412	field	HDMAENACK	0x08
413	field	DIRECTION	0x04
414	field	DIRECTIONACK	0x04
415	field	FIFOFLUSH	0x02
416	field	FIFOFLUSHACK	0x02
417	field	DIRECTIONEN	0x01
418}
419
420/*
421 * Device Space Command 0
422 */
423register DSCOMMAND0 {
424	address			0x019
425	access_mode	RW
426	modes		M_CFG
427	field	CACHETHEN	0x80	/* Cache Threshold enable */
428	field	DPARCKEN	0x40	/* Data Parity Check Enable */
429	field	MPARCKEN	0x20	/* Memory Parity Check Enable */
430	field	EXTREQLCK	0x10	/* External Request Lock */
431	field	DISABLE_TWATE	0x02	/* Rev B or greater */
432	field	CIOPARCKEN	0x01	/* Internal bus parity error enable */
433}
434
435/*
436 * Data FIFO Status
437 */
438register DFSTATUS {
439	address			0x01A
440	access_mode	RO
441	modes		M_DFF0, M_DFF1
442	field	PRELOAD_AVAIL		0x80
443	field	PKT_PRELOAD_AVAIL	0x40
444	field	MREQPEND		0x10
445	field	HDONE			0x08
446	field	DFTHRESH		0x04
447	field	FIFOFULL		0x02
448	field	FIFOEMP			0x01
449}
450
451/*
452 * S/G Cache Pointer
453 */
454register SG_CACHE_PRE {
455	address			0x01B
456	access_mode	WO
457	modes		M_DFF0, M_DFF1
458	field	SG_ADDR_MASK	0xf8
459	field	ODD_SEG		0x04
460	field	LAST_SEG	0x02
461}
462
463register SG_CACHE_SHADOW {
464	address			0x01B
465	access_mode	RO
466	modes		M_DFF0, M_DFF1
467	field	SG_ADDR_MASK	0xf8
468	field	ODD_SEG		0x04
469	field	LAST_SEG	0x02
470	field	LAST_SEG_DONE	0x01
471}
472
473/*
474 * Arbiter Control
475 */
476register ARBCTL {
477	address			0x01B
478	access_mode	RW
479	modes		M_CFG
480	field	RESET_HARB	0x80
481	field	RETRY_SWEN	0x08
482	field	USE_TIME	0x07
483}
484
485/*
486 * Data Channel Host Address
487 */
488register HADDR {
489	address			0x070
490	access_mode	RW
491	size		8
492	modes		M_DFF0, M_DFF1
493}
494
495/*
496 * Host Overlay DMA Address
497 */
498register HODMAADR {
499	address			0x070
500	access_mode	RW
501	size		8
502	modes		M_SCSI
503}
504
505/*
506 * PCI PLL Delay.
507 */
508register PLLDELAY {
509	address			0x070
510	access_mode	RW
511	size		1
512	modes		M_CFG
513	field	SPLIT_DROP_REQ	0x80
514}
515
516/*
517 * Data Channel Host Count
518 */
519register HCNT {
520	address			0x078
521	access_mode	RW
522	size		3
523	modes		M_DFF0, M_DFF1
524}
525
526/*
527 * Host Overlay DMA Count
528 */
529register HODMACNT {
530	address			0x078
531	access_mode	RW
532	size		2
533	modes		M_SCSI
534}
535
536/*
537 * Host Overlay DMA Enable
538 */
539register HODMAEN {
540	address			0x07A
541	access_mode	RW
542	modes		M_SCSI
543}
544
545/*
546 * Scatter/Gather Host Address
547 */
548register SGHADDR {
549	address			0x07C
550	access_mode	RW
551	size		8
552	modes		M_DFF0, M_DFF1
553}
554
555/*
556 * SCB Host Address
557 */
558register SCBHADDR {
559	address			0x07C
560	access_mode	RW
561	size		8
562	modes		M_CCHAN
563}
564
565/*
566 * Scatter/Gather Host Count
567 */
568register SGHCNT {
569	address			0x084
570	access_mode	RW
571	modes		M_DFF0, M_DFF1
572}
573
574/*
575 * SCB Host Count
576 */
577register SCBHCNT {
578	address			0x084
579	access_mode	RW
580	modes		M_CCHAN
581}
582
583/*
584 * Data FIFO Threshold
585 */
586register DFF_THRSH {
587	address			0x088
588	access_mode	RW
589	modes		M_CFG
590	field	WR_DFTHRSH	0x70 {
591		WR_DFTHRSH_MIN,
592		WR_DFTHRSH_25,
593		WR_DFTHRSH_50,
594		WR_DFTHRSH_63,
595		WR_DFTHRSH_75,
596		WR_DFTHRSH_85,
597		WR_DFTHRSH_90,
598		WR_DFTHRSH_MAX
599	}
600	field	RD_DFTHRSH	0x07 {
601		RD_DFTHRSH_MIN,
602		RD_DFTHRSH_25,
603		RD_DFTHRSH_50,
604		RD_DFTHRSH_63,
605		RD_DFTHRSH_75,
606		RD_DFTHRSH_85,
607		RD_DFTHRSH_90,
608		RD_DFTHRSH_MAX
609	}
610}
611
612/*
613 * ROM Address
614 */
615register ROMADDR {
616	address			0x08A
617	access_mode	RW
618	size		3
619}
620
621/*
622 * ROM Control
623 */
624register ROMCNTRL {
625	address			0x08D
626	access_mode	RW
627	field	ROMOP		0xE0
628	field	ROMSPD		0x18
629	field	REPEAT		0x02
630	field	RDY		0x01
631}
632
633/*
634 * ROM Data
635 */
636register ROMDATA {
637	address			0x08E
638	access_mode	RW
639}
640
641/*
642 * Data Channel Receive Message 0
643 */
644register DCHRXMSG0 {
645	address			0x090
646	access_mode	RO
647	modes		M_DFF0, M_DFF1
648	field		CDNUM	0xF8
649	field		CFNUM	0x07
650}
651
652/*
653 * CMC Recieve Message 0
654 */
655register CMCRXMSG0 {
656	address			0x090
657	access_mode	RO
658	modes		M_CCHAN
659	field		CDNUM	0xF8
660	field		CFNUM	0x07
661}
662
663/*
664 * Overlay Recieve Message 0
665 */
666register OVLYRXMSG0 {
667	address			0x090
668	access_mode	RO
669	modes		M_SCSI
670	field		CDNUM	0xF8
671	field		CFNUM	0x07
672}
673
674/*
675 * Relaxed Order Enable
676 */
677register ROENABLE {
678	address			0x090
679	access_mode	RW
680	modes		M_CFG
681	field	MSIROEN		0x20
682	field	OVLYROEN	0x10
683	field	CMCROEN		0x08
684	field	SGROEN		0x04
685	field	DCH1ROEN	0x02
686	field	DCH0ROEN	0x01
687}
688
689/*
690 * Data Channel Receive Message 1
691 */
692register DCHRXMSG1 {
693	address			0x091
694	access_mode	RO
695	modes		M_DFF0, M_DFF1
696	field	CBNUM		0xFF
697}
698
699/*
700 * CMC Recieve Message 1
701 */
702register CMCRXMSG1 {
703	address			0x091
704	access_mode	RO
705	modes		M_CCHAN
706	field	CBNUM		0xFF
707}
708
709/*
710 * Overlay Recieve Message 1
711 */
712register OVLYRXMSG1 {
713	address			0x091
714	access_mode	RO
715	modes		M_SCSI
716	field	CBNUM		0xFF
717}
718
719/*
720 * No Snoop Enable
721 */
722register NSENABLE {
723	address			0x091
724	access_mode	RW
725	modes		M_CFG
726	field	MSINSEN		0x20
727	field	OVLYNSEN	0x10
728	field	CMCNSEN		0x08
729	field	SGNSEN		0x04
730	field	DCH1NSEN	0x02
731	field	DCH0NSEN	0x01
732}
733
734/*
735 * Data Channel Receive Message 2
736 */
737register DCHRXMSG2 {
738	address			0x092
739	access_mode	RO
740	modes		M_DFF0, M_DFF1
741	field	MINDEX		0xFF
742}
743
744/*
745 * CMC Recieve Message 2
746 */
747register CMCRXMSG2 {
748	address			0x092
749	access_mode	RO
750	modes		M_CCHAN
751	field	MINDEX		0xFF
752}
753
754/*
755 * Overlay Recieve Message 2
756 */
757register OVLYRXMSG2 {
758	address			0x092
759	access_mode	RO
760	modes		M_SCSI
761	field	MINDEX		0xFF
762}
763
764/*
765 * Outstanding Split Transactions
766 */
767register OST {
768	address			0x092
769	access_mode	RW
770	modes		M_CFG
771}
772
773/*
774 * Data Channel Receive Message 3
775 */
776register DCHRXMSG3 {
777	address			0x093
778	access_mode	RO
779	modes		M_DFF0, M_DFF1
780	field	MCLASS		0x0F
781}
782
783/*
784 * CMC Recieve Message 3
785 */
786register CMCRXMSG3 {
787	address			0x093
788	access_mode	RO
789	modes		M_CCHAN
790	field	MCLASS		0x0F
791}
792
793/*
794 * Overlay Recieve Message 3
795 */
796register OVLYRXMSG3 {
797	address			0x093
798	access_mode	RO
799	modes		M_SCSI
800	field	MCLASS		0x0F
801}
802
803/*
804 * PCI-X Control
805 */
806register PCIXCTL {
807	address			0x093
808	access_mode	RW
809	modes		M_CFG
810	field	SERRPULSE	0x80
811	field	UNEXPSCIEN	0x20
812	field	SPLTSMADIS	0x10
813	field	SPLTSTADIS	0x08
814	field	SRSPDPEEN	0x04
815	field	TSCSERREN	0x02
816	field	CMPABCDIS	0x01
817}
818
819/*
820 * CMC Sequencer Byte Count
821 */
822register CMCSEQBCNT {
823	address			0x094
824	access_mode	RO
825	modes		M_CCHAN
826}
827
828/*
829 * Overlay Sequencer Byte Count
830 */
831register OVLYSEQBCNT {
832	address			0x094
833	access_mode	RO
834	modes		M_SCSI
835}
836
837/*
838 * Data Channel Sequencer Byte Count
839 */
840register DCHSEQBCNT {
841	address			0x094
842	access_mode	RO
843	size		2
844	modes		M_DFF0, M_DFF1
845}
846
847/*
848 * Data Channel Split Status 0
849 */
850register DCHSPLTSTAT0 {
851	address			0x096
852	access_mode	RW
853	modes		M_DFF0, M_DFF1
854	field	STAETERM	0x80
855	field	SCBCERR		0x40
856	field	SCADERR		0x20
857	field	SCDATBUCKET	0x10
858	field	CNTNOTCMPLT	0x08
859	field	RXOVRUN		0x04
860	field	RXSCEMSG	0x02
861	field	RXSPLTRSP	0x01
862}
863
864/*
865 * CMC Split Status 0
866 */
867register CMCSPLTSTAT0 {
868	address			0x096
869	access_mode	RW
870	modes		M_CCHAN
871	field	STAETERM	0x80
872	field	SCBCERR		0x40
873	field	SCADERR		0x20
874	field	SCDATBUCKET	0x10
875	field	CNTNOTCMPLT	0x08
876	field	RXOVRUN		0x04
877	field	RXSCEMSG	0x02
878	field	RXSPLTRSP	0x01
879}
880
881/*
882 * Overlay Split Status 0
883 */
884register OVLYSPLTSTAT0 {
885	address			0x096
886	access_mode	RW
887	modes		M_SCSI
888	field	STAETERM	0x80
889	field	SCBCERR		0x40
890	field	SCADERR		0x20
891	field	SCDATBUCKET	0x10
892	field	CNTNOTCMPLT	0x08
893	field	RXOVRUN		0x04
894	field	RXSCEMSG	0x02
895	field	RXSPLTRSP	0x01
896}
897
898/*
899 * Data Channel Split Status 1
900 */
901register DCHSPLTSTAT1 {
902	address			0x097
903	access_mode	RW
904	modes		M_DFF0, M_DFF1
905	field	RXDATABUCKET	0x01
906}
907
908/*
909 * CMC Split Status 1
910 */
911register CMCSPLTSTAT1 {
912	address			0x097
913	access_mode	RW
914	modes		M_CCHAN
915	field	RXDATABUCKET	0x01
916}
917
918/*
919 * Overlay Split Status 1
920 */
921register OVLYSPLTSTAT1 {
922	address			0x097
923	access_mode	RW
924	modes		M_SCSI
925	field	RXDATABUCKET	0x01
926}
927
928/*
929 * S/G Receive Message 0
930 */
931register SGRXMSG0 {
932	address			0x098
933	access_mode	RO
934	modes		M_DFF0, M_DFF1
935	field		CDNUM	0xF8
936	field		CFNUM	0x07
937}
938
939/*
940 * S/G Receive Message 1
941 */
942register SGRXMSG1 {
943	address			0x099
944	access_mode	RO
945	modes		M_DFF0, M_DFF1
946	field	CBNUM		0xFF
947}
948
949/*
950 * S/G Receive Message 2
951 */
952register SGRXMSG2 {
953	address			0x09A
954	access_mode	RO
955	modes		M_DFF0, M_DFF1
956	field	MINDEX		0xFF
957}
958
959/*
960 * S/G Receive Message 3
961 */
962register SGRXMSG3 {
963	address			0x09B
964	access_mode	RO
965	modes		M_DFF0, M_DFF1
966	field	MCLASS		0x0F
967}
968
969/*
970 * Slave Split Out Address 0
971 */
972register SLVSPLTOUTADR0 {
973	address			0x098
974	access_mode	RO
975	modes		M_SCSI
976	field	LOWER_ADDR	0x7F
977}
978
979/*
980 * Slave Split Out Address 1
981 */
982register SLVSPLTOUTADR1 {
983	address			0x099
984	access_mode	RO
985	modes		M_SCSI
986	field	REQ_DNUM	0xF8
987	field	REQ_FNUM	0x07
988}
989
990/*
991 * Slave Split Out Address 2
992 */
993register SLVSPLTOUTADR2 {
994	address			0x09A
995	access_mode	RO
996	modes		M_SCSI
997	field	REQ_BNUM	0xFF
998}
999
1000/*
1001 * Slave Split Out Address 3
1002 */
1003register SLVSPLTOUTADR3 {
1004	address			0x09B
1005	access_mode	RO
1006	modes		M_SCSI
1007	field	RLXORD		020
1008	field	TAG_NUM		0x1F
1009}
1010
1011/*
1012 * SG Sequencer Byte Count
1013 */
1014register SGSEQBCNT {
1015	address			0x09C
1016	access_mode	RO
1017	modes		M_DFF0, M_DFF1
1018}
1019
1020/*
1021 * Slave Split Out Attribute 0
1022 */
1023register SLVSPLTOUTATTR0 {
1024	address			0x09C
1025	access_mode	RO
1026	modes		M_SCSI
1027	field	LOWER_BCNT	0xFF
1028}
1029
1030/*
1031 * Slave Split Out Attribute 1
1032 */
1033register SLVSPLTOUTATTR1 {
1034	address			0x09D
1035	access_mode	RO
1036	modes		M_SCSI
1037	field	CMPLT_DNUM	0xF8
1038	field	CMPLT_FNUM	0x07
1039}
1040
1041/*
1042 * Slave Split Out Attribute 2
1043 */
1044register SLVSPLTOUTATTR2 {
1045	address			0x09E
1046	access_mode	RO
1047	size		2
1048	modes		M_SCSI
1049	field	CMPLT_BNUM	0xFF
1050}
1051/*
1052 * S/G Split Status 0
1053 */
1054register SGSPLTSTAT0 {
1055	address			0x09E
1056	access_mode	RW
1057	modes		M_DFF0, M_DFF1
1058	field	STAETERM	0x80
1059	field	SCBCERR		0x40
1060	field	SCADERR		0x20
1061	field	SCDATBUCKET	0x10
1062	field	CNTNOTCMPLT	0x08
1063	field	RXOVRUN		0x04
1064	field	RXSCEMSG	0x02
1065	field	RXSPLTRSP	0x01
1066}
1067
1068/*
1069 * S/G Split Status 1
1070 */
1071register SGSPLTSTAT1 {
1072	address			0x09F
1073	access_mode	RW
1074	modes		M_DFF0, M_DFF1
1075	field	RXDATABUCKET	0x01
1076}
1077
1078/*
1079 * Special Function
1080 */
1081register SFUNCT {
1082	address			0x09f
1083	access_mode	RW
1084	modes		M_CFG
1085	field	TEST_GROUP	0xF0
1086	field	TEST_NUM	0x0F
1087}
1088
1089/*
1090 * Data FIFO 0 PCI Status 
1091 */
1092register DF0PCISTAT {
1093	address			0x0A0
1094	access_mode	RW
1095	modes		M_CFG
1096	field	DPE		0x80
1097	field	SSE		0x40
1098	field	RMA		0x20
1099	field	RTA		0x10
1100	field	SCAAPERR	0x08
1101	field	RDPERR		0x04
1102	field	TWATERR		0x02
1103	field	DPR		0x01
1104}
1105
1106/*
1107 * Data FIFO 1 PCI Status 
1108 */
1109register DF1PCISTAT {
1110	address			0x0A1
1111	access_mode	RW
1112	modes		M_CFG
1113	field	DPE		0x80
1114	field	SSE		0x40
1115	field	RMA		0x20
1116	field	RTA		0x10
1117	field	SCAAPERR	0x08
1118	field	RDPERR		0x04
1119	field	TWATERR		0x02
1120	field	DPR		0x01
1121}
1122
1123/*
1124 * S/G PCI Status 
1125 */
1126register SGPCISTAT {
1127	address			0x0A2
1128	access_mode	RW
1129	modes		M_CFG
1130	field	DPE		0x80
1131	field	SSE		0x40
1132	field	RMA		0x20
1133	field	RTA		0x10
1134	field	SCAAPERR	0x08
1135	field	RDPERR		0x04
1136	field	DPR		0x01
1137}
1138
1139/*
1140 * CMC PCI Status 
1141 */
1142register CMCPCISTAT {
1143	address			0x0A3
1144	access_mode	RW
1145	modes		M_CFG
1146	field	DPE		0x80
1147	field	SSE		0x40
1148	field	RMA		0x20
1149	field	RTA		0x10
1150	field	SCAAPERR	0x08
1151	field	RDPERR		0x04
1152	field	TWATERR		0x02
1153	field	DPR		0x01
1154}
1155
1156/*
1157 * Overlay PCI Status 
1158 */
1159register OVLYPCISTAT {
1160	address			0x0A4
1161	access_mode	RW
1162	modes		M_CFG
1163	field	DPE		0x80
1164	field	SSE		0x40
1165	field	RMA		0x20
1166	field	RTA		0x10
1167	field	SCAAPERR	0x08
1168	field	RDPERR		0x04
1169	field	DPR		0x01
1170}
1171
1172/*
1173 * PCI Status for MSI Master DMA Transfer
1174 */
1175register MSIPCISTAT {
1176	address			0x0A6
1177	access_mode	RW
1178	modes		M_CFG
1179	field	SSE		0x40
1180	field	RMA		0x20
1181	field	RTA		0x10
1182	field	CLRPENDMSI	0x08
1183	field	TWATERR		0x02
1184	field	DPR		0x01
1185}
1186
1187/*
1188 * PCI Status for Target
1189 */
1190register TARGPCISTAT {
1191	address			0x0A7
1192	access_mode	RW
1193	modes		M_CFG
1194	field	DPE		0x80
1195	field	SSE		0x40
1196	field	STA		0x08
1197	field	TWATERR		0x02
1198}
1199
1200/*
1201 * LQ Packet In
1202 * The last LQ Packet recieved
1203 */
1204register LQIN {
1205	address			0x020
1206	access_mode	RW
1207	size		20
1208	modes		M_DFF0, M_DFF1, M_SCSI
1209}
1210
1211/*
1212 * SCB Type Pointer
1213 * SCB offset for Target Mode SCB type information
1214 */
1215register TYPEPTR {
1216	address			0x020
1217	access_mode	RW
1218	modes		M_CFG
1219}
1220
1221/*
1222 * Queue Tag Pointer
1223 * SCB offset to the Two Byte tag identifier used for target mode.
1224 */
1225register TAGPTR {
1226	address			0x021
1227	access_mode	RW
1228	modes		M_CFG
1229}
1230
1231/*
1232 * Logical Unit Number Pointer
1233 * SCB offset to the LSB (little endian) of the lun field.
1234 */
1235register LUNPTR {
1236	address			0x022
1237	access_mode	RW
1238	modes		M_CFG
1239}
1240
1241/*
1242 * Data Length Pointer
1243 * SCB offset for the 4 byte data length field in target mode.
1244 */
1245register DATALENPTR {
1246	address			0x023
1247	access_mode	RW
1248	modes		M_CFG
1249}
1250
1251/*
1252 * Status Length Pointer
1253 * SCB offset to the two byte status field in target SCBs.
1254 */
1255register STATLENPTR {
1256	address			0x024
1257	access_mode	RW
1258	modes		M_CFG
1259}
1260
1261/*
1262 * Command Length Pointer
1263 * Scb offset for the CDB length field in initiator SCBs.
1264 */
1265register CMDLENPTR {
1266	address			0x025
1267	access_mode	RW
1268	modes		M_CFG
1269}
1270
1271/*
1272 * Task Attribute Pointer
1273 * Scb offset for the byte field specifying the attribute byte
1274 * to be used in command packets.
1275 */ 
1276register ATTRPTR {
1277	address			0x026
1278	access_mode	RW
1279	modes		M_CFG
1280}
1281
1282/*
1283 * Task Management Flags Pointer
1284 * Scb offset for the byte field specifying the attribute flags
1285 * byte to be used in command packets.
1286 */ 
1287register FLAGPTR {
1288	address			0x027
1289	access_mode	RW
1290	modes		M_CFG
1291}
1292
1293/*
1294 * Command Pointer
1295 * Scb offset for the first byte in the CDB for initiator SCBs.
1296 */
1297register CMDPTR {
1298	address			0x028
1299	access_mode	RW
1300	modes		M_CFG
1301}
1302
1303/*
1304 * Queue Next Pointer
1305 * Scb offset for the 2 byte "next scb link".
1306 */
1307register QNEXTPTR {
1308	address			0x029
1309	access_mode	RW
1310	modes		M_CFG
1311}
1312
1313/*
1314 * SCSI ID Pointer
1315 * Scb offset to the value to place in the SCSIID register
1316 * during target mode connections.
1317 */
1318register IDPTR {
1319	address			0x02A
1320	access_mode	RW
1321	modes		M_CFG
1322}
1323
1324/*
1325 * Command Aborted Byte Pointer
1326 * Offset to the SCB flags field that includes the
1327 * "SCB aborted" status bit.
1328 */
1329register ABRTBYTEPTR {
1330	address			0x02B
1331	access_mode	RW
1332	modes		M_CFG
1333}
1334
1335/*
1336 * Command Aborted Bit Pointer
1337 * Bit offset in the SCB flags field for "SCB aborted" status.
1338 */
1339register ABRTBITPTR {
1340	address			0x02C
1341	access_mode	RW
1342	modes		M_CFG
1343}
1344
1345/*
1346 * Rev B or greater.
1347 */
1348register MAXCMDBYTES {
1349	address			0x02D
1350	access_mode	RW
1351	modes		M_CFG
1352}
1353
1354/*
1355 * Rev B or greater.
1356 */
1357register MAXCMD2RCV {
1358	address			0x02E
1359	access_mode	RW
1360	modes		M_CFG
1361}
1362
1363/*
1364 * Rev B or greater.
1365 */
1366register SHORTTHRESH {
1367	address			0x02F
1368	access_mode	RW
1369	modes		M_CFG
1370}
1371
1372/*
1373 * Logical Unit Number Length
1374 * The length, in bytes, of the SCB lun field.
1375 */
1376register LUNLEN {
1377	address			0x030
1378	access_mode	RW
1379	modes		M_CFG
1380}
1381
1382/*
1383 * CDB Limit
1384 * The size, in bytes, of the embedded CDB field in initator SCBs.
1385 */
1386register CDBLIMIT {
1387	address			0x031
1388	access_mode	RW
1389	modes		M_CFG
1390}
1391
1392/*
1393 * Maximum Commands
1394 * The maximum number of commands to issue during a
1395 * single packetized connection.
1396 */
1397register MAXCMD {
1398	address			0x032
1399	access_mode	RW
1400	modes		M_CFG
1401}
1402
1403/*
1404 * Maximum Command Counter
1405 * The number of commands already sent during this connection
1406 */
1407register MAXCMDCNT {
1408	address			0x033
1409	access_mode	RW
1410	modes		M_CFG
1411}
1412
1413/*
1414 * LQ Packet Reserved Bytes
1415 * The bytes to be sent in the currently reserved fileds
1416 * of all LQ packets.
1417 */
1418register LQRSVD01 {
1419	address			0x034
1420	access_mode	RW
1421	modes		M_SCSI
1422}
1423register LQRSVD16 {
1424	address			0x035
1425	access_mode	RW
1426	modes		M_SCSI
1427}
1428register LQRSVD17 {
1429	address			0x036
1430	access_mode	RW
1431	modes		M_SCSI
1432}
1433
1434/*
1435 * Command Reserved 0
1436 * The byte to be sent for the reserved byte 0 of
1437 * outgoing command packets.
1438 */
1439register CMDRSVD0 {
1440	address			0x037
1441	access_mode	RW
1442	modes		M_CFG
1443}
1444
1445/*
1446 * LQ Manager Control 0
1447 */
1448register LQCTL0 {
1449	address			0x038
1450	access_mode	RW
1451	modes		M_CFG
1452	field	LQITARGCLT	0xC0
1453	field	LQIINITGCLT	0x30
1454	field	LQ0TARGCLT	0x0C
1455	field	LQ0INITGCLT	0x03
1456}
1457
1458/*
1459 * LQ Manager Control 1
1460 */
1461register LQCTL1 {
1462	address			0x038
1463	access_mode	RW
1464	modes		M_DFF0, M_DFF1, M_SCSI
1465	field	PCI2PCI		0x04
1466	field	SINGLECMD	0x02
1467	field	ABORTPENDING	0x01
1468}
1469
1470/*
1471 * LQ Manager Control 2
1472 */
1473register LQCTL2 {
1474	address			0x039
1475	access_mode	RW
1476	modes		M_DFF0, M_DFF1, M_SCSI
1477	field	LQIRETRY	0x80
1478	field	LQICONTINUE	0x40
1479	field	LQITOIDLE	0x20
1480	field	LQIPAUSE	0x10
1481	field	LQORETRY	0x08
1482	field	LQOCONTINUE	0x04
1483	field	LQOTOIDLE	0x02
1484	field	LQOPAUSE	0x01
1485}
1486
1487/*
1488 * SCSI RAM BIST0
1489 */
1490register SCSBIST0 {
1491	address			0x039
1492	access_mode	RW
1493	modes		M_CFG
1494	field	GSBISTERR	0x40
1495	field	GSBISTDONE	0x20
1496	field	GSBISTRUN	0x10
1497	field	OSBISTERR	0x04
1498	field	OSBISTDONE	0x02
1499	field	OSBISTRUN	0x01
1500}
1501
1502/*
1503 * SCSI Sequence Control0
1504 */
1505register SCSISEQ0 {
1506	address			0x03A
1507	access_mode	RW
1508	modes		M_DFF0, M_DFF1, M_SCSI
1509	field	TEMODEO		0x80
1510	field	ENSELO		0x40
1511	field	ENARBO		0x20
1512	field	FORCEBUSFREE	0x10
1513	field	SCSIRSTO	0x01
1514}
1515
1516/*
1517 * SCSI RAM BIST 1
1518 */
1519register SCSBIST1 {
1520	address			0x03A
1521	access_mode	RW
1522	modes		M_CFG
1523	field	NTBISTERR	0x04
1524	field	NTBISTDONE	0x02
1525	field	NTBISTRUN	0x01
1526}
1527
1528/*
1529 * SCSI Sequence Control 1
1530 */
1531register SCSISEQ1 {
1532	address			0x03B
1533	access_mode	RW
1534	modes		M_DFF0, M_DFF1, M_SCSI
1535	field	MANUALCTL	0x40
1536	field	ENSELI		0x20
1537	field	ENRSELI		0x10
1538	field	MANUALP		0x0C
1539	field	ENAUTOATNP	0x02
1540	field	ALTSTIM		0x01
1541}
1542
1543/*
1544 * SCSI Transfer Control 0
1545 */
1546register SXFRCTL0 {
1547	address			0x03C
1548	access_mode	RW
1549	modes		M_SCSI
1550	field	DFON		0x80
1551	field	DFPEXP		0x40
1552	field	BIOSCANCELEN	0x10
1553	field	SPIOEN		0x08
1554}
1555
1556/*
1557 * SCSI Transfer Control 1
1558 */
1559register SXFRCTL1 {
1560	address			0x03D
1561	access_mode	RW
1562	modes		M_SCSI
1563	field	BITBUCKET	0x80
1564	field	ENSACHK		0x40
1565	field	ENSPCHK		0x20
1566	field	STIMESEL	0x18
1567	field	ENSTIMER	0x04
1568	field	ACTNEGEN	0x02
1569	field	STPWEN		0x01
1570}
1571
1572/*
1573 * SCSI Transfer Control 2
1574 */
1575register SXFRCTL2 {
1576	address			0x03E
1577	access_mode	RW
1578	modes		M_SCSI
1579	field	AUTORSTDIS	0x10
1580	field	CMDDMAEN	0x08
1581	field	ASU		0x07
1582}
1583
1584/*
1585 * SCSI Bus Initiator IDs
1586 * Bitmask of observed initiators on the bus.
1587 */
1588register BUSINITID {
1589	address			0x03C
1590	access_mode	RW
1591	modes		M_CFG
1592	size		2
1593}
1594
1595/*
1596 * Data Length Counters
1597 * Packet byte counter.
1598 */
1599register DLCOUNT {
1600	address			0x03C
1601	access_mode	RW
1602	modes		M_DFF0, M_DFF1
1603	size		3
1604}
1605
1606/*
1607 * Data FIFO Status
1608 */
1609register DFFSTAT {
1610	address			0x03F
1611	access_mode	RW
1612	modes		M_SCSI
1613	field	FIFO1FREE	0x20
1614	field	FIFO0FREE	0x10
1615	/*
1616	 * On the B, this enum only works
1617	 * in the read direction.  For writes,
1618	 * you must use the B version of the
1619	 * CURRFIFO_0 definition which is defined
1620	 * as a constant outside of this register
1621	 * definition to avoid confusing the
1622	 * register pretty printing code.
1623	 */
1624	enum	CURRFIFO	0x03 {
1625		CURRFIFO_0,
1626		CURRFIFO_1,
1627		CURRFIFO_NONE	0x3
1628	}
1629}
1630
1631const B_CURRFIFO_0 0x2
1632
1633/*
1634 * SCSI Bus Target IDs
1635 * Bitmask of observed targets on the bus.
1636 */
1637register BUSTARGID {
1638	address			0x03E
1639	access_mode	RW
1640	modes		M_CFG
1641	size		2
1642}
1643
1644/*
1645 * SCSI Control Signal Out
1646 */
1647register SCSISIGO {
1648	address			0x040
1649	access_mode	RW
1650	modes		M_DFF0, M_DFF1, M_SCSI
1651	field	CDO		0x80
1652	field	IOO		0x40
1653	field	MSGO		0x20
1654	field	ATNO		0x10
1655	field	SELO		0x08
1656	field	BSYO		0x04
1657	field	REQO		0x02
1658	field	ACKO		0x01
1659/*
1660 * Possible phases to write into SCSISIG0
1661 */
1662	enum	PHASE_MASK  CDO|IOO|MSGO {
1663		P_DATAOUT	0x0,
1664		P_DATAIN	IOO,
1665		P_DATAOUT_DT	P_DATAOUT|MSGO,
1666		P_DATAIN_DT	P_DATAIN|MSGO,
1667		P_COMMAND	CDO,
1668		P_MESGOUT	CDO|MSGO,
1669		P_STATUS	CDO|IOO,
1670		P_MESGIN	CDO|IOO|MSGO
1671	}
1672}
1673
1674register SCSISIGI {
1675	address			0x041
1676	access_mode	RO
1677	modes		M_DFF0, M_DFF1, M_SCSI
1678	field	CDI		0x80
1679	field	IOI		0x40
1680	field	MSGI		0x20
1681	field	ATNI		0x10
1682	field	SELI		0x08
1683	field	BSYI		0x04
1684	field	REQI		0x02
1685	field	ACKI		0x01
1686/*
1687 * Possible phases in SCSISIGI
1688 */
1689	enum	PHASE_MASK  CDO|IOO|MSGO {
1690		P_DATAOUT	0x0,
1691		P_DATAIN	IOO,
1692		P_DATAOUT_DT	P_DATAOUT|MSGO,
1693		P_DATAIN_DT	P_DATAIN|MSGO,
1694		P_COMMAND	CDO,
1695		P_MESGOUT	CDO|MSGO,
1696		P_STATUS	CDO|IOO,
1697		P_MESGIN	CDO|IOO|MSGO
1698	}
1699}
1700
1701/*
1702 * Multiple Target IDs
1703 * Bitmask of ids to respond as a target.
1704 */
1705register MULTARGID {
1706	address			0x040
1707	access_mode	RW
1708	modes		M_CFG
1709	size		2
1710}
1711
1712/*
1713 * SCSI Phase
1714 */
1715register SCSIPHASE {
1716	address			0x042
1717	access_mode	RO
1718	modes		M_DFF0, M_DFF1, M_SCSI
1719	field	STATUS_PHASE	0x20
1720	field	COMMAND_PHASE	0x10
1721	field	MSG_IN_PHASE	0x08
1722	field	MSG_OUT_PHASE	0x04
1723	field	DATA_PHASE_MASK	0x03 {
1724		DATA_OUT_PHASE	0x01,
1725		DATA_IN_PHASE	0x02
1726	}
1727}
1728
1729/*
1730 * SCSI Data 0 Image
1731 */
1732register SCSIDAT0_IMG {
1733	address			0x043
1734	access_mode	RW
1735	modes		M_DFF0, M_DFF1, M_SCSI
1736}
1737
1738/*
1739 * SCSI Latched Data
1740 */
1741register SCSIDAT {
1742	address			0x044
1743	access_mode	RW
1744	modes		M_DFF0, M_DFF1, M_SCSI
1745	size		2
1746}
1747
1748/*
1749 * SCSI Data Bus
1750 */
1751register SCSIBUS {
1752	address			0x046
1753	access_mode	RW
1754	modes		M_DFF0, M_DFF1, M_SCSI
1755	size		2
1756}
1757
1758/*
1759 * Target ID In
1760 */
1761register TARGIDIN {
1762	address			0x048
1763	access_mode	RO
1764	modes		M_DFF0, M_DFF1, M_SCSI
1765	field	CLKOUT		0x80
1766	field	TARGID		0x0F
1767}
1768
1769/*
1770 * Selection/Reselection ID
1771 * Upper four bits are the device id.  The ONEBIT is set when the re/selecting
1772 * device did not set its own ID.
1773 */
1774register SELID {
1775	address			0x049
1776	access_mode	RW
1777	modes		M_DFF0, M_DFF1, M_SCSI
1778	field	SELID_MASK	0xf0
1779	field	ONEBIT		0x08
1780}
1781
1782/*
1783 * SCSI Block Control
1784 * Controls Bus type and channel selection.  SELWIDE allows for the
1785 * coexistence of 8bit and 16bit devices on a wide bus.
1786 */
1787register SBLKCTL {
1788	address			0x04A
1789	access_mode	RW
1790	modes		M_DFF0, M_DFF1, M_SCSI
1791	field	DIAGLEDEN	0x80
1792	field	DIAGLEDON	0x40
1793	field	ENAB40		0x08	/* LVD transceiver active */
1794	field	ENAB20		0x04	/* SE/HVD transceiver active */
1795	field	SELWIDE		0x02
1796}
1797
1798/*
1799 * Option Mode
1800 */
1801register OPTIONMODE {
1802	address			0x04A
1803	access_mode	RW
1804	modes		M_CFG
1805	field	BIOSCANCTL		0x80
1806	field	AUTOACKEN		0x40
1807	field	BIASCANCTL		0x20
1808	field	BUSFREEREV		0x10
1809	field	ENDGFORMCHK		0x04
1810	field	AUTO_MSGOUT_DE		0x02
1811	mask	OPTIONMODE_DEFAULTS	AUTO_MSGOUT_DE
1812}
1813
1814/*
1815 * SCSI Status 0
1816 */
1817register SSTAT0	{
1818	address			0x04B
1819	access_mode	RO
1820	modes		M_DFF0, M_DFF1, M_SCSI
1821	field	TARGET		0x80	/* Board acting as target */
1822	field	SELDO		0x40	/* Selection Done */
1823	field	SELDI		0x20	/* Board has been selected */
1824	field	SELINGO		0x10	/* Selection In Progress */
1825	field	IOERR		0x08	/* LVD Tranceiver mode changed */
1826	field	OVERRUN		0x04	/* SCSI Offset overrun detected */
1827	field	SPIORDY		0x02	/* SCSI PIO Ready */
1828	field	ARBDO		0x01	/* Arbitration Done Out */
1829}
1830
1831/*
1832 * Clear SCSI Interrupt 0
1833 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0.
1834 */
1835register CLRSINT0 {
1836	address			0x04B
1837	access_mode	WO
1838	modes		M_DFF0, M_DFF1, M_SCSI
1839	field	CLRSELDO	0x40
1840	field	CLRSELDI	0x20
1841	field	CLRSELINGO	0x10
1842	field	CLRIOERR	0x08
1843	field	CLROVERRUN	0x04
1844	field	CLRSPIORDY	0x02
1845	field	CLRARBDO	0x01
1846}
1847
1848/*
1849 * SCSI Interrupt Mode 0
1850 * Setting any bit will enable the corresponding function
1851 * in SIMODE0 to interrupt via the IRQ pin.
1852 */
1853register SIMODE0 {
1854	address			0x04B
1855	access_mode	RW
1856	modes		M_CFG
1857	field	ENSELDO		0x40
1858	field	ENSELDI		0x20
1859	field	ENSELINGO	0x10
1860	field	ENIOERR		0x08
1861	field	ENOVERRUN	0x04
1862	field	ENSPIORDY	0x02
1863	field	ENARBDO		0x01
1864}
1865
1866/*
1867 * SCSI Status 1
1868 */
1869register SSTAT1 {
1870	address			0x04C
1871	access_mode	RO
1872	modes		M_DFF0, M_DFF1, M_SCSI
1873	field	SELTO		0x80
1874	field	ATNTARG 	0x40
1875	field	SCSIRSTI	0x20
1876	field	PHASEMIS	0x10
1877	field	BUSFREE		0x08
1878	field	SCSIPERR	0x04
1879	field	STRB2FAST	0x02
1880	field	REQINIT		0x01
1881}
1882
1883/*
1884 * Clear SCSI Interrupt 1
1885 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.
1886 */
1887register CLRSINT1 {
1888	address			0x04C
1889	access_mode	WO
1890	modes		M_DFF0, M_DFF1, M_SCSI
1891	field	CLRSELTIMEO	0x80
1892	field	CLRATNO		0x40
1893	field	CLRSCSIRSTI	0x20
1894	field	CLRBUSFREE	0x08
1895	field	CLRSCSIPERR	0x04
1896	field	CLRSTRB2FAST	0x02
1897	field	CLRREQINIT	0x01
1898}
1899
1900/*
1901 * SCSI Status 2
1902 */
1903register SSTAT2 {
1904	address			0x04d
1905	access_mode	RO
1906	modes		M_DFF0, M_DFF1, M_SCSI
1907	field	BUSFREETIME	0xc0 {
1908		BUSFREE_LQO	0x40,
1909		BUSFREE_DFF0	0x80,
1910		BUSFREE_DFF1	0xC0
1911	}
1912	field	NONPACKREQ	0x20
1913	field	EXP_ACTIVE	0x10	/* SCSI Expander Active */
1914	field	BSYX		0x08	/* Busy Expander */
1915	field	WIDE_RES	0x04	/* Modes 0 and 1 only */
1916	field	SDONE		0x02	/* Modes 0 and 1 only */
1917	field	DMADONE		0x01	/* Modes 0 and 1 only */
1918}
1919
1920/*
1921 * Clear SCSI Interrupt 2
1922 */
1923register CLRSINT2 {
1924	address			0x04D
1925	access_mode	WO
1926	modes		M_DFF0, M_DFF1, M_SCSI
1927	field	CLRNONPACKREQ	0x20
1928	field	CLRWIDE_RES	0x04	/* Modes 0 and 1 only */
1929	field	CLRSDONE	0x02	/* Modes 0 and 1 only */
1930	field	CLRDMADONE	0x01	/* Modes 0 and 1 only */
1931}
1932
1933/*
1934 * SCSI Interrupt Mode 2
1935 */
1936register SIMODE2 {
1937	address			0x04D
1938	access_mode	RW
1939	modes		M_CFG
1940	field	ENWIDE_RES	0x04
1941	field	ENSDONE		0x02
1942	field	ENDMADONE	0x01
1943}
1944
1945/*
1946 * Physical Error Diagnosis
1947 */
1948register PERRDIAG {
1949	address			0x04E
1950	access_mode	RO
1951	modes		M_DFF0, M_DFF1, M_SCSI
1952	field	HIZERO		0x80
1953	field	HIPERR		0x40
1954	field	PREVPHASE	0x20
1955	field	PARITYERR	0x10
1956	field	AIPERR		0x08
1957	field	CRCERR		0x04
1958	field	DGFORMERR	0x02
1959	field	DTERR		0x01
1960}
1961
1962/*
1963 * LQI Manager Current State
1964 */
1965register LQISTATE {
1966	address			0x04E
1967	access_mode	RO
1968	modes		M_CFG
1969}
1970
1971/*
1972 * SCSI Offset Count
1973 */
1974register SOFFCNT {
1975	address			0x04F
1976	access_mode	RO
1977	modes		M_DFF0, M_DFF1, M_SCSI
1978}
1979
1980/*
1981 * LQO Manager Current State
1982 */
1983register LQOSTATE {
1984	address			0x04F
1985	access_mode	RO
1986	modes		M_CFG
1987}
1988
1989/*
1990 * LQI Manager Status
1991 */
1992register LQISTAT0 {
1993	address			0x050
1994	access_mode	RO
1995	modes		M_DFF0, M_DFF1, M_SCSI
1996	field	LQIATNQAS	0x20
1997	field	LQICRCT1	0x10
1998	field	LQICRCT2	0x08
1999	field	LQIBADLQT	0x04
2000	field	LQIATNLQ	0x02
2001	field	LQIATNCMD	0x01
2002}
2003
2004/*
2005 * Clear LQI Interrupts 0
2006 */
2007register CLRLQIINT0 {
2008	address			0x050
2009	access_mode	WO
2010	modes		M_DFF0, M_DFF1, M_SCSI
2011	field	CLRLQIATNQAS	0x20
2012	field	CLRLQICRCT1	0x10
2013	field	CLRLQICRCT2	0x08
2014	field	CLRLQIBADLQT	0x04
2015	field	CLRLQIATNLQ	0x02
2016	field	CLRLQIATNCMD	0x01
2017}
2018
2019/*
2020 * LQI Manager Interrupt Mode 0
2021 */
2022register LQIMODE0 {
2023	address			0x050
2024	access_mode	RW
2025	modes		M_CFG
2026	field	ENLQIATNQASK	0x20
2027	field	ENLQICRCT1	0x10
2028	field	ENLQICRCT2	0x08
2029	field	ENLQIBADLQT	0x04
2030	field	ENLQIATNLQ	0x02
2031	field	ENLQIATNCMD	0x01
2032}
2033
2034/*
2035 * LQI Manager Status 1
2036 */
2037register LQISTAT1 {
2038	address			0x051
2039	access_mode	RO
2040	modes		M_DFF0, M_DFF1, M_SCSI
2041	field	LQIPHASE_LQ	0x80
2042	field	LQIPHASE_NLQ	0x40
2043	field	LQIABORT	0x20
2044	field	LQICRCI_LQ	0x10
2045	field	LQICRCI_NLQ	0x08
2046	field	LQIBADLQI	0x04
2047	field	LQIOVERI_LQ	0x02
2048	field	LQIOVERI_NLQ	0x01
2049}
2050
2051/*
2052 * Clear LQI Manager Interrupts1
2053 */
2054register CLRLQIINT1 {
2055	address			0x051
2056	access_mode	WO
2057	modes		M_DFF0, M_DFF1, M_SCSI
2058	field	CLRLQIPHASE_LQ	0x80
2059	field	CLRLQIPHASE_NLQ	0x40
2060	field	CLRLIQABORT	0x20
2061	field	CLRLQICRCI_LQ	0x10
2062	field	CLRLQICRCI_NLQ	0x08
2063	field	CLRLQIBADLQI	0x04
2064	field	CLRLQIOVERI_LQ	0x02
2065	field	CLRLQIOVERI_NLQ	0x01
2066}
2067
2068/*
2069 * LQI Manager Interrupt Mode 1
2070 */
2071register LQIMODE1 {
2072	address			0x051
2073	access_mode	RW
2074	modes		M_CFG
2075	field	ENLQIPHASE_LQ	0x80	/* LQIPHASE1 */
2076	field	ENLQIPHASE_NLQ	0x40	/* LQIPHASE2 */
2077	field	ENLIQABORT	0x20
2078	field	ENLQICRCI_LQ	0x10	/* LQICRCI1 */
2079	field	ENLQICRCI_NLQ	0x08	/* LQICRCI2 */
2080	field	ENLQIBADLQI	0x04
2081	field	ENLQIOVERI_LQ	0x02	/* LQIOVERI1 */
2082	field	ENLQIOVERI_NLQ	0x01	/* LQIOVERI2 */
2083}
2084
2085/*
2086 * LQI Manager Status 2
2087 */
2088register LQISTAT2 {
2089	address			0x052
2090	access_mode	RO
2091	modes		M_DFF0, M_DFF1, M_SCSI
2092	field	PACKETIZED	0x80
2093	field	LQIPHASE_OUTPKT	0x40
2094	field	LQIWORKONLQ	0x20
2095	field	LQIWAITFIFO	0x10
2096	field	LQISTOPPKT	0x08
2097	field	LQISTOPLQ	0x04
2098	field	LQISTOPCMD	0x02
2099	field	LQIGSAVAIL	0x01
2100}
2101
2102/*
2103 * SCSI Status 3
2104 */
2105register SSTAT3 {
2106	address			0x053
2107	access_mode	RO
2108	modes		M_DFF0, M_DFF1, M_SCSI
2109	field	NTRAMPERR	0x02
2110	field	OSRAMPERR	0x01
2111}
2112
2113/*
2114 * Clear SCSI Status 3
2115 */
2116register CLRSINT3 {
2117	address			0x053
2118	access_mode	WO
2119	modes		M_DFF0, M_DFF1, M_SCSI
2120	field	CLRNTRAMPERR	0x02
2121	field	CLROSRAMPERR	0x01
2122}
2123
2124/*
2125 * SCSI Interrupt Mode 3
2126 */
2127register SIMODE3 {
2128	address			0x053
2129	access_mode	RW
2130	modes		M_CFG
2131	field	ENNTRAMPERR	0x02
2132	field	ENOSRAMPERR	0x01
2133}
2134
2135/*
2136 * LQO Manager Status 0
2137 */
2138register LQOSTAT0 {
2139	address			0x054
2140	access_mode	RO
2141	modes		M_DFF0, M_DFF1, M_SCSI
2142	field	LQOTARGSCBPERR	0x10
2143	field	LQOSTOPT2	0x08
2144	field	LQOATNLQ	0x04
2145	field	LQOATNPKT	0x02
2146	field	LQOTCRC		0x01
2147}
2148
2149/*
2150 * Clear LQO Manager interrupt 0
2151 */
2152register CLRLQOINT0 {
2153	address			0x054
2154	access_mode	WO
2155	modes		M_DFF0, M_DFF1, M_SCSI
2156	field	CLRLQOTARGSCBPERR	0x10
2157	field	CLRLQOSTOPT2		0x08
2158	field	CLRLQOATNLQ		0x04
2159	field	CLRLQOATNPKT		0x02
2160	field	CLRLQOTCRC		0x01
2161}
2162
2163/*
2164 * LQO Manager Interrupt Mode 0
2165 */
2166register LQOMODE0 {
2167	address			0x054
2168	access_mode	RW
2169	modes		M_CFG
2170	field	ENLQOTARGSCBPERR	0x10
2171	field	ENLQOSTOPT2		0x08
2172	field	ENLQOATNLQ		0x04
2173	field	ENLQOATNPKT		0x02
2174	field	ENLQOTCRC		0x01
2175}
2176
2177/*
2178 * LQO Manager Status 1
2179 */
2180register LQOSTAT1 {
2181	address			0x055
2182	access_mode	RO
2183	modes		M_DFF0, M_DFF1, M_SCSI
2184	field	LQOINITSCBPERR	0x10
2185	field	LQOSTOPI2	0x08
2186	field	LQOBADQAS	0x04
2187	field	LQOBUSFREE	0x02
2188	field	LQOPHACHGINPKT	0x01
2189}
2190
2191/*
2192 * Clear LOQ Interrupt 1
2193 */
2194register CLRLQOINT1 {
2195	address			0x055
2196	access_mode	WO
2197	modes		M_DFF0, M_DFF1, M_SCSI
2198	field	CLRLQOINITSCBPERR	0x10
2199	field	CLRLQOSTOPI2		0x08
2200	field	CLRLQOBADQAS		0x04
2201	field	CLRLQOBUSFREE		0x02
2202	field	CLRLQOPHACHGINPKT	0x01
2203}
2204
2205/*
2206 * LQO Manager Interrupt Mode 1
2207 */
2208register LQOMODE1 {
2209	address			0x055
2210	access_mode	RW
2211	modes		M_CFG
2212	field	ENLQOINITSCBPERR	0x10
2213	field	ENLQOSTOPI2		0x08
2214	field	ENLQOBADQAS		0x04
2215	field	ENLQOBUSFREE		0x02
2216	field	ENLQOPHACHGINPKT	0x01
2217}
2218
2219/*
2220 * LQO Manager Status 2
2221 */
2222register LQOSTAT2 {
2223	address			0x056
2224	access_mode	RO
2225	modes		M_DFF0, M_DFF1, M_SCSI
2226	field	LQOPKT		0xE0
2227	field	LQOWAITFIFO	0x10
2228	field	LQOPHACHGOUTPKT	0x02	/* outside of packet boundaries. */
2229	field	LQOSTOP0	0x01	/* Stopped after sending all packets */
2230}
2231
2232/*
2233 * Output Synchronizer Space Count
2234 */
2235register OS_SPACE_CNT {
2236	address			0x056
2237	access_mode	RO
2238	modes		M_CFG
2239}
2240
2241/*
2242 * SCSI Interrupt Mode 1
2243 * Setting any bit will enable the corresponding function
2244 * in SIMODE1 to interrupt via the IRQ pin.
2245 */
2246register SIMODE1 {
2247	address			0x057
2248	access_mode	RW
2249	modes		M_DFF0, M_DFF1, M_SCSI
2250	field	ENSELTIMO	0x80
2251	field	ENATNTARG	0x40
2252	field	ENSCSIRST	0x20
2253	field	ENPHASEMIS	0x10
2254	field	ENBUSFREE	0x08
2255	field	ENSCSIPERR	0x04
2256	field	ENSTRB2FAST	0x02
2257	field	ENREQINIT	0x01
2258}
2259
2260/*
2261 * Good Status FIFO
2262 */
2263register GSFIFO {
2264	address			0x058
2265	access_mode	RO
2266	size		2
2267	modes		M_DFF0, M_DFF1, M_SCSI
2268}
2269
2270/*
2271 * Data FIFO SCSI Transfer Control
2272 */
2273register DFFSXFRCTL {
2274	address			0x05A
2275	access_mode	RW
2276	modes		M_DFF0, M_DFF1
2277	field	DFFBITBUCKET	0x08
2278	field	CLRSHCNT	0x04
2279	field	CLRCHN		0x02
2280	field	RSTCHN		0x01
2281}
2282
2283/*
2284 * Next SCSI Control Block
2285 */
2286register NEXTSCB {
2287	address			0x05A
2288	access_mode	RW
2289	size		2
2290	modes		M_SCSI
2291}
2292
2293/* Rev B only. */
2294register LQOSCSCTL {
2295	address			0x05A
2296	access_mode	RW
2297	size		1
2298	modes		M_CFG
2299	field		LQOH2A_VERSION	0x80
2300	field		LQONOCHKOVER	0x01
2301}
2302
2303/*
2304 * SEQ Interrupts
2305 */
2306register SEQINTSRC {
2307	address			0x05B
2308	access_mode	RO
2309	modes		M_DFF0, M_DFF1
2310	field	CTXTDONE	0x40
2311	field	SAVEPTRS	0x20
2312	field	CFG4DATA	0x10
2313	field	CFG4ISTAT	0x08
2314	field	CFG4TSTAT	0x04
2315	field	CFG4ICMD	0x02
2316	field	CFG4TCMD	0x01
2317}
2318
2319/*
2320 * Clear Arp Interrupts
2321 */
2322register CLRSEQINTSRC {
2323	address			0x05B
2324	access_mode	WO
2325	modes		M_DFF0, M_DFF1
2326	field	CLRCTXTDONE	0x40
2327	field	CLRSAVEPTRS	0x20
2328	field	CLRCFG4DATA	0x10
2329	field	CLRCFG4ISTAT	0x08
2330	field	CLRCFG4TSTAT	0x04
2331	field	CLRCFG4ICMD	0x02
2332	field	CLRCFG4TCMD	0x01
2333}
2334
2335/*
2336 * SEQ Interrupt Enabled (Shared)
2337 */
2338register SEQIMODE {
2339	address			0x05C
2340	access_mode	RW
2341	modes		M_DFF0, M_DFF1
2342	field	ENCTXTDONE	0x40
2343	field	ENSAVEPTRS	0x20
2344	field	ENCFG4DATA	0x10
2345	field	ENCFG4ISTAT	0x08
2346	field	ENCFG4TSTAT	0x04
2347	field	ENCFG4ICMD	0x02
2348	field	ENCFG4TCMD	0x01
2349}
2350
2351/*
2352 * Current SCSI Control Block
2353 */
2354register CURRSCB {
2355	address			0x05C
2356	access_mode	RW
2357	size		2
2358	modes		M_SCSI
2359}
2360
2361/*
2362 * Data FIFO Status
2363 */
2364register MDFFSTAT {
2365	address			0x05D
2366	access_mode	RO
2367	modes		M_DFF0, M_DFF1
2368	field	SHCNTNEGATIVE	0x40 /* Rev B or higher */
2369	field	SHCNTMINUS1	0x20 /* Rev B or higher */
2370	field	LASTSDONE	0x10
2371	field	SHVALID		0x08
2372	field	DLZERO		0x04 /* FIFO data ends on packet boundary. */
2373	field	DATAINFIFO	0x02
2374	field	FIFOFREE	0x01
2375}
2376
2377/*
2378 * CRC Control
2379 */
2380register CRCCONTROL {
2381	address			0x05d
2382	access_mode	RW
2383	modes		M_CFG
2384	field	CRCVALCHKEN		0x40
2385}
2386
2387/*
2388 * SCSI Test Control
2389 */
2390register SCSITEST {
2391	address			0x05E
2392	access_mode	RW
2393	modes		M_CFG
2394	field	CNTRTEST	0x08
2395	field	SEL_TXPLL_DEBUG	0x04
2396}
2397
2398/*
2399 * Data FIFO Queue Tag
2400 */
2401register DFFTAG {
2402	address			0x05E
2403	access_mode	RW
2404	size		2
2405	modes		M_DFF0, M_DFF1
2406}
2407
2408/*
2409 * Last SCSI Control Block
2410 */
2411register LASTSCB {
2412	address			0x05E
2413	access_mode	RW
2414	size		2
2415	modes		M_SCSI
2416}
2417
2418/*
2419 * SCSI I/O Cell Power-down Control
2420 */
2421register IOPDNCTL {
2422	address			0x05F
2423	access_mode	RW
2424	modes		M_CFG
2425	field	DISABLE_OE	0x80
2426	field	PDN_IDIST	0x04
2427	field	PDN_DIFFSENSE	0x01
2428}
2429
2430/*
2431 * Shaddow Host Address.
2432 */
2433register SHADDR {
2434	address			0x060
2435	access_mode	RO
2436	size		8
2437	modes		M_DFF0, M_DFF1
2438}
2439
2440/*
2441 * Data Group CRC Interval.
2442 */
2443register DGRPCRCI {
2444	address			0x060
2445	access_mode	RW
2446	size		2
2447	modes		M_CFG
2448}
2449
2450/*
2451 * Data Transfer Negotiation Address
2452 */
2453register NEGOADDR {
2454	address			0x060
2455	access_mode	RW
2456	modes		M_SCSI
2457}
2458
2459/*
2460 * Data Transfer Negotiation Data - Period Byte
2461 */
2462register NEGPERIOD {
2463	address			0x061
2464	access_mode	RW
2465	modes		M_SCSI
2466}
2467
2468/*
2469 * Packetized CRC Interval
2470 */
2471register PACKCRCI {
2472	address			0x062
2473	access_mode	RW
2474	size		2
2475	modes		M_CFG
2476}
2477
2478/*
2479 * Data Transfer Negotiation Data - Offset Byte
2480 */
2481register NEGOFFSET {
2482	address			0x062
2483	access_mode	RW
2484	modes		M_SCSI
2485}
2486
2487/*
2488 * Data Transfer Negotiation Data - PPR Options
2489 */
2490register NEGPPROPTS {
2491	address			0x063
2492	access_mode	RW
2493	modes		M_SCSI
2494	field	PPROPT_PACE	0x08
2495	field	PPROPT_QAS	0x04
2496	field	PPROPT_DT	0x02
2497	field	PPROPT_IUT	0x01
2498}
2499
2500/*
2501 * Data Transfer Negotiation Data -  Connection Options
2502 */
2503register NEGCONOPTS {
2504	address			0x064
2505	access_mode	RW
2506	modes		M_SCSI
2507	field	ENSNAPSHOT	0x40
2508	field	RTI_WRTDIS	0x20
2509	field	RTI_OVRDTRN	0x10
2510	field	ENSLOWCRC	0x08
2511	field	ENAUTOATNI	0x04
2512	field	ENAUTOATNO	0x02
2513	field	WIDEXFER	0x01
2514}
2515
2516/*
2517 * Negotiation Table Annex Column Index.
2518 */
2519register ANNEXCOL {
2520	address			0x065
2521	access_mode	RW
2522	modes		M_SCSI
2523}
2524
2525register SCSCHKN {
2526	address			0x066
2527	access_mode	RW
2528	modes		M_CFG
2529	field	STSELSKIDDIS	0x40
2530	field	CURRFIFODEF	0x20
2531	field	WIDERESEN	0x10
2532	field	SDONEMSKDIS	0x08
2533	field	DFFACTCLR	0x04
2534	field	SHVALIDSTDIS	0x02
2535	field	LSTSGCLRDIS	0x01
2536}
2537
2538const AHD_ANNEXCOL_PER_DEV0	4
2539const AHD_NUM_PER_DEV_ANNEXCOLS	4
2540const AHD_ANNEXCOL_PRECOMP_SLEW	4
2541const	AHD_PRECOMP_MASK	0x07
2542const	AHD_PRECOMP_SHIFT	0
2543const	AHD_PRECOMP_CUTBACK_17	0x04
2544const	AHD_PRECOMP_CUTBACK_29	0x06
2545const	AHD_PRECOMP_CUTBACK_37	0x07
2546const	AHD_SLEWRATE_MASK	0x78
2547const	AHD_SLEWRATE_SHIFT	3
2548/*
2549 * Rev A has only a single bit (high bit of field) of slew adjustment.
2550 * Rev B has 4 bits.  The current default happens to be the same for both.
2551 */
2552const	AHD_SLEWRATE_DEF_REVA	0x08
2553const	AHD_SLEWRATE_DEF_REVB	0x08
2554
2555/* Rev A does not have any amplitude setting. */
2556const AHD_ANNEXCOL_AMPLITUDE	6
2557const	AHD_AMPLITUDE_MASK	0x7
2558const	AHD_AMPLITUDE_SHIFT	0
2559const	AHD_AMPLITUDE_DEF	0x7
2560
2561/*
2562 * Negotiation Table Annex Data Port.
2563 */
2564register ANNEXDAT {
2565	address			0x066
2566	access_mode	RW
2567	modes		M_SCSI
2568}
2569
2570/*
2571 * Initiator's Own Id.
2572 * The SCSI ID to use for Selection Out and seen during a reselection..
2573 */
2574register IOWNID {
2575	address			0x067
2576	access_mode	RW
2577	modes		M_SCSI
2578}
2579
2580/*
2581 * 960MHz Phase-Locked Loop Control 0
2582 */
2583register PLL960CTL0 {
2584	address			0x068
2585	access_mode	RW
2586	modes		M_CFG
2587	field	PLL_VCOSEL	0x80
2588	field	PLL_PWDN	0x40
2589	field	PLL_NS		0x30
2590	field	PLL_ENLUD	0x08
2591	field	PLL_ENLPF	0x04
2592	field	PLL_DLPF	0x02
2593	field	PLL_ENFBM	0x01
2594}
2595
2596/*
2597 * Target Own Id
2598 */
2599register TOWNID {
2600	address			0x069
2601	access_mode	RW
2602	modes		M_SCSI
2603}
2604
2605/*
2606 * 960MHz Phase-Locked Loop Control 1
2607 */
2608register PLL960CTL1 {
2609	address			0x069
2610	access_mode	RW
2611	modes		M_CFG
2612	field	PLL_CNTEN	0x80
2613	field	PLL_CNTCLR	0x40
2614	field	PLL_RST		0x01
2615}
2616
2617/*
2618 * Expander Signature
2619 */
2620register XSIG {
2621	address			0x06A
2622	access_mode	RW
2623	modes		M_SCSI
2624}
2625
2626/*
2627 * Shadow Byte Count
2628 */
2629register SHCNT {
2630	address			0x068
2631	access_mode	RW
2632	size		3
2633	modes		M_DFF0, M_DFF1
2634}
2635
2636/*
2637 * Selection Out ID
2638 */
2639register SELOID {
2640	address			0x06B
2641	access_mode	RW
2642	modes		M_SCSI
2643}
2644
2645/*
2646 * 960-MHz Phase-Locked Loop Test Count
2647 */
2648register PLL960CNT0 {
2649	address			0x06A
2650	access_mode	RO
2651	size		2
2652	modes		M_CFG
2653}
2654
2655/*
2656 * 400-MHz Phase-Locked Loop Control 0
2657 */
2658register PLL400CTL0 {
2659	address			0x06C
2660	access_mode	RW
2661	modes		M_CFG
2662	field	PLL_VCOSEL	0x80
2663	field	PLL_PWDN	0x40
2664	field	PLL_NS		0x30
2665	field	PLL_ENLUD	0x08
2666	field	PLL_ENLPF	0x04
2667	field	PLL_DLPF	0x02
2668	field	PLL_ENFBM	0x01
2669}
2670
2671/*
2672 * Arbitration Fairness
2673 */
2674register FAIRNESS {
2675	address			0x06C
2676	access_mode	RW
2677	size		2
2678	modes		M_SCSI
2679}
2680
2681/*
2682 * 400-MHz Phase-Locked Loop Control 1
2683 */
2684register PLL400CTL1 {
2685	address			0x06D
2686	access_mode	RW
2687	modes		M_CFG
2688	field	PLL_CNTEN	0x80
2689	field	PLL_CNTCLR	0x40
2690	field	PLL_RST		0x01
2691}
2692
2693/*
2694 * Arbitration Unfairness
2695 */
2696register UNFAIRNESS {
2697	address			0x06E
2698	access_mode	RW
2699	size		2
2700	modes		M_SCSI
2701}
2702
2703/*
2704 * 400-MHz Phase-Locked Loop Test Count
2705 */
2706register PLL400CNT0 {
2707	address			0x06E
2708	access_mode	RO
2709	size		2
2710	modes		M_CFG
2711}
2712
2713/*
2714 * SCB Page Pointer
2715 */
2716register SCBPTR {
2717	address			0x0A8
2718	access_mode	RW
2719	size		2
2720	modes		M_DFF0, M_DFF1, M_CCHAN, M_SCSI
2721}
2722
2723/*
2724 * CMC SCB Array Count
2725 * Number of bytes to transfer between CMC SCB memory and SCBRAM.
2726 * Transfers must be 8byte aligned and sized.
2727 */
2728register CCSCBACNT {
2729	address			0x0AB
2730	access_mode	RW
2731	modes		M_CCHAN
2732}
2733
2734/*
2735 * SCB Autopointer
2736 * SCB-Next Address Snooping logic.  When an SCB is transferred to
2737 * the card, the next SCB address to be used by the CMC array can
2738 * be autoloaded from that transfer.
2739 */
2740register SCBAUTOPTR {
2741	address			0x0AB
2742	access_mode	RW
2743	modes		M_CFG
2744	field	AUSCBPTR_EN	0x80
2745	field	SCBPTR_ADDR	0x38
2746	field	SCBPTR_OFF	0x07
2747}
2748
2749/*
2750 * CMC SG Ram Address Pointer
2751 */
2752register CCSGADDR {
2753	address			0x0AC
2754	access_mode	RW
2755	modes		M_DFF0, M_DFF1
2756}
2757
2758/*
2759 * CMC SCB RAM Address Pointer
2760 */
2761register CCSCBADDR {
2762	address			0x0AC
2763	access_mode	RW
2764	modes		M_CCHAN
2765}
2766
2767/*
2768 * CMC SCB Ram Back-up Address Pointer
2769 * Indicates the true stop location of transfers halted prior
2770 * to SCBHCNT going to 0.
2771 */
2772register CCSCBADR_BK {
2773	address			0x0AC
2774	access_mode	RO
2775	modes		M_CFG
2776}
2777
2778/*
2779 * CMC SG Control
2780 */
2781register CCSGCTL {
2782	address			0x0AD
2783	access_mode	RW
2784	modes		M_DFF0, M_DFF1
2785	field	CCSGDONE	0x80
2786	field	SG_CACHE_AVAIL	0x10
2787	field	CCSGENACK	0x08
2788	mask	CCSGEN		0x0C
2789	field	SG_FETCH_REQ	0x02
2790	field	CCSGRESET	0x01
2791}
2792
2793/*
2794 * CMD SCB Control
2795 */
2796register CCSCBCTL {
2797	address			0x0AD
2798	access_mode	RW
2799	modes		M_CCHAN
2800	field	CCSCBDONE	0x80
2801	field	ARRDONE		0x40
2802	field	CCARREN		0x10
2803	field	CCSCBEN		0x08
2804	field	CCSCBDIR	0x04
2805	field	CCSCBRESET	0x01
2806}
2807
2808/*
2809 * CMC Ram BIST
2810 */
2811register CMC_RAMBIST {
2812	address			0x0AD
2813	access_mode	RW
2814	modes		M_CFG
2815	field	SG_ELEMENT_SIZE		0x80
2816	field	SCBRAMBIST_FAIL		0x40
2817	field	SG_BIST_FAIL		0x20
2818	field	SG_BIST_EN		0x10
2819	field	CMC_BUFFER_BIST_FAIL	0x02
2820	field	CMC_BUFFER_BIST_EN	0x01
2821}
2822
2823/*
2824 * CMC SG RAM Data Port
2825 */
2826register CCSGRAM {
2827	address			0x0B0
2828	access_mode	RW
2829	modes		M_DFF0, M_DFF1
2830}
2831
2832/*
2833 * CMC SCB RAM Data Port
2834 */
2835register CCSCBRAM {
2836	address			0x0B0
2837	access_mode	RW
2838	modes		M_CCHAN
2839}
2840
2841/*
2842 * Flex DMA Address.
2843 */
2844register FLEXADR {
2845	address			0x0B0
2846	access_mode	RW
2847	size		3
2848	modes		M_SCSI
2849}
2850
2851/*
2852 * Flex DMA Byte Count
2853 */
2854register FLEXCNT {
2855	address			0x0B3
2856	access_mode	RW
2857	size		2
2858	modes		M_SCSI
2859}
2860
2861/*
2862 * Flex DMA Status
2863 */
2864register FLEXDMASTAT {
2865	address			0x0B5
2866	access_mode	RW
2867	modes		M_SCSI
2868	field	FLEXDMAERR	0x02
2869	field	FLEXDMADONE	0x01
2870}
2871
2872/*
2873 * Flex DMA Data Port
2874 */
2875register FLEXDATA {
2876	address			0x0B6
2877	access_mode	RW
2878	modes		M_SCSI
2879}
2880
2881/*
2882 * Board Data
2883 */
2884register BRDDAT {
2885	address			0x0B8
2886	access_mode	RW
2887	modes		M_SCSI
2888}
2889
2890/*
2891 * Board Control
2892 */
2893register BRDCTL {
2894	address			0x0B9
2895	access_mode	RW
2896	modes		M_SCSI
2897	field	FLXARBACK	0x80
2898	field	FLXARBREQ	0x40
2899	field	BRDADDR		0x38
2900	field	BRDEN		0x04
2901	field	BRDRW		0x02
2902	field	BRDSTB		0x01
2903}
2904
2905/*
2906 * Serial EEPROM Address
2907 */
2908register SEEADR {
2909	address			0x0BA
2910	access_mode	RW
2911	modes		M_SCSI
2912}
2913
2914/*
2915 * Serial EEPROM Data
2916 */
2917register SEEDAT {
2918	address			0x0BC
2919	access_mode	RW
2920	size		2
2921	modes		M_SCSI
2922}
2923
2924/*
2925 * Serial EEPROM Status
2926 */
2927register SEESTAT {
2928	address			0x0BE
2929	access_mode	RO
2930	modes		M_SCSI
2931	field	INIT_DONE	0x80
2932	field	SEEOPCODE	0x70
2933	field	LDALTID_L	0x08
2934	field	SEEARBACK	0x04
2935	field	SEEBUSY		0x02
2936	field	SEESTART	0x01
2937}
2938
2939/*
2940 * Serial EEPROM Control
2941 */
2942register SEECTL {
2943	address			0x0BE
2944	access_mode	RW
2945	modes		M_SCSI
2946	field	SEEOPCODE	0x70 {
2947		SEEOP_ERASE	0x70,
2948		SEEOP_READ	0x60,
2949		SEEOP_WRITE	0x50,
2950	/*
2951	 * The following four commands use special
2952	 * addresses for differentiation.
2953	 */
2954		SEEOP_ERAL	0x40
2955	}
2956	mask	SEEOP_EWEN	0x40
2957	mask	SEEOP_WALL	0x40
2958	mask	SEEOP_EWDS	0x40
2959	field	SEERST		0x02
2960	field	SEESTART	0x01
2961}
2962
2963const SEEOP_ERAL_ADDR	0x80
2964const SEEOP_EWEN_ADDR	0xC0
2965const SEEOP_WRAL_ADDR	0x40
2966const SEEOP_EWDS_ADDR	0x00
2967
2968/*
2969 * SCB Counter
2970 */
2971register SCBCNT {
2972	address			0x0BF
2973	access_mode	RW
2974	modes		M_SCSI
2975}
2976
2977/*
2978 * Data FIFO Write Address
2979 * Pointer to the next QWD location to be written to the data FIFO.
2980 */
2981register DFWADDR {
2982	address			0x0C0
2983	access_mode	RW
2984	size		2
2985	modes		M_DFF0, M_DFF1
2986}
2987
2988/*
2989 * DSP Filter Control
2990 */
2991register DSPFLTRCTL {
2992	address			0x0C0
2993	access_mode	RW
2994	modes		M_CFG
2995	field	FLTRDISABLE	0x20
2996	field	EDGESENSE	0x10
2997	field	DSPFCNTSEL	0x0F
2998}
2999
3000/*
3001 * DSP Data Channel Control
3002 */
3003register DSPDATACTL {
3004	address			0x0C1
3005	access_mode	RW
3006	modes		M_CFG
3007	field	BYPASSENAB	0x80
3008	field	DESQDIS		0x10
3009	field	RCVROFFSTDIS	0x04
3010	field	XMITOFFSTDIS	0x02
3011}
3012
3013/*
3014 * Data FIFO Read Address
3015 * Pointer to the next QWD location to be read from the data FIFO.
3016 */
3017register DFRADDR {
3018	address			0x0C2
3019	access_mode	RW
3020	size		2
3021	modes		M_DFF0, M_DFF1
3022}
3023
3024/*
3025 * DSP REQ Control
3026 */
3027register DSPREQCTL {
3028	address			0x0C2
3029	access_mode	RW
3030	modes		M_CFG
3031	field	MANREQCTL	0xC0
3032	field	MANREQDLY	0x3F
3033}
3034
3035/*
3036 * DSP ACK Control
3037 */
3038register DSPACKCTL {
3039	address			0x0C3
3040	access_mode	RW
3041	modes		M_CFG
3042	field	MANACKCTL	0xC0
3043	field	MANACKDLY	0x3F
3044}
3045
3046/*
3047 * Data FIFO Data
3048 * Read/Write byte port into the data FIFO.  The read and write
3049 * FIFO pointers increment with each read and write respectively
3050 * to this port.
3051 */
3052register DFDAT {
3053	address			0x0C4
3054	access_mode	RW
3055	modes		M_DFF0, M_DFF1
3056}
3057
3058/*
3059 * DSP Channel Select
3060 */
3061register DSPSELECT {
3062	address			0x0C4
3063	access_mode	RW
3064	modes		M_CFG
3065	field	AUTOINCEN	0x80
3066	field	DSPSEL		0x1F
3067}
3068
3069const NUMDSPS 0x14
3070
3071/*
3072 * Write Bias Control
3073 */
3074register WRTBIASCTL {
3075	address			0x0C5
3076	access_mode	WO
3077	modes		M_CFG
3078	field	AUTOXBCDIS	0x80
3079	field	XMITMANVAL	0x3F
3080}
3081
3082/*
3083 * Currently the WRTBIASCTL is the same as the default.
3084 */
3085const WRTBIASCTL_HP_DEFAULT 0x0
3086
3087/*
3088 * Receiver Bias Control
3089 */
3090register RCVRBIOSCTL {
3091	address			0x0C6
3092	access_mode	WO
3093	modes		M_CFG
3094	field	AUTORBCDIS	0x80
3095	field	RCVRMANVAL	0x3F
3096}
3097
3098/*
3099 * Write Bias Calculator
3100 */
3101register WRTBIASCALC {
3102	address			0x0C7
3103	access_mode	RO
3104	modes		M_CFG
3105}
3106
3107/*
3108 * Data FIFO Pointers
3109 * Contains the byte offset from DFWADDR and DWRADDR to the current
3110 * FIFO write/read locations.
3111 */
3112register DFPTRS {
3113	address			0x0C8
3114	access_mode	RW
3115	modes		M_DFF0, M_DFF1
3116}
3117
3118/*
3119 * Receiver Bias Calculator
3120 */
3121register RCVRBIASCALC {
3122	address			0x0C8
3123	access_mode	RO
3124	modes		M_CFG
3125}
3126
3127/*
3128 * Data FIFO Backup Read Pointer
3129 * Contains the data FIFO address to be restored if the last
3130 * data accessed from the data FIFO was not transferred successfully.
3131 */
3132register DFBKPTR {
3133	address			0x0C9
3134	access_mode	RW
3135	size		2
3136	modes		M_DFF0, M_DFF1
3137}
3138
3139/*
3140 * Skew Calculator
3141 */
3142register SKEWCALC {
3143	address			0x0C9
3144	access_mode	RO
3145	modes		M_CFG
3146}
3147
3148/*
3149 * Data FIFO Debug Control
3150 */
3151register DFDBCTL {
3152	address				0x0CB
3153	access_mode	RW
3154	modes		M_DFF0, M_DFF1
3155	field	DFF_CIO_WR_RDY		0x20
3156	field	DFF_CIO_RD_RDY		0x10
3157	field	DFF_DIR_ERR		0x08
3158	field	DFF_RAMBIST_FAIL	0x04
3159	field	DFF_RAMBIST_DONE	0x02
3160	field	DFF_RAMBIST_EN		0x01
3161}
3162
3163/*
3164 * Data FIFO Space Count
3165 * Number of FIFO locations that are free.
3166 */
3167register DFSCNT {
3168	address			0x0CC
3169	access_mode	RO
3170	size		2
3171	modes		M_DFF0, M_DFF1
3172}
3173
3174/*
3175 * Data FIFO Byte Count
3176 * Number of filled FIFO locations.
3177 */
3178register DFBCNT {
3179	address			0x0CE
3180	access_mode	RO
3181	size		2
3182	modes		M_DFF0, M_DFF1
3183}
3184
3185/*
3186 * Sequencer Program Overlay Address.
3187 * Low address must be written prior to high address.
3188 */
3189register OVLYADDR {
3190	address			0x0D4
3191	modes		M_SCSI
3192	size		2
3193	access_mode	RW
3194}
3195
3196/*
3197 * Sequencer Control 0
3198 * Error detection mode, speed configuration,
3199 * single step, breakpoints and program load.
3200 */
3201register SEQCTL0 {
3202	address			0x0D6
3203	access_mode RW
3204	field	PERRORDIS	0x80
3205	field	PAUSEDIS	0x40
3206	field	FAILDIS		0x20
3207	field	FASTMODE	0x10
3208	field	BRKADRINTEN	0x08
3209	field	STEP		0x04
3210	field	SEQRESET	0x02
3211	field	LOADRAM		0x01
3212}
3213
3214/*
3215 * Sequencer Control 1
3216 * Instruction RAM Diagnostics
3217 */
3218register SEQCTL1 {
3219	address			0x0D7
3220	access_mode RW
3221	field	OVRLAY_DATA_CHK	0x08
3222	field	RAMBIST_DONE	0x04
3223	field	RAMBIST_FAIL	0x02
3224	field	RAMBIST_EN	0x01
3225}
3226
3227/*
3228 * Sequencer Flags
3229 * Zero and Carry state of the ALU.
3230 */
3231register FLAGS {
3232	address			0x0D8
3233	access_mode RO
3234	field	ZERO		0x02
3235	field	CARRY		0x01
3236}
3237
3238/*
3239 * Sequencer Interrupt Control
3240 */ 
3241register SEQINTCTL {
3242	address			0x0D9
3243	access_mode RW
3244	field	INTVEC1DSL	0x80
3245	field	INT1_CONTEXT	0x20
3246	field	SCS_SEQ_INT1M1	0x10
3247	field	SCS_SEQ_INT1M0	0x08
3248	field	INTMASK2	0x04
3249	field	INTMASK1	0x02
3250	field	IRET		0x01
3251}
3252
3253/*
3254 * Sequencer RAM Data Port
3255 * Single byte window into the Sequencer Instruction Ram area starting
3256 * at the address specified by OVLYADDR.  To write a full instruction word,
3257 * simply write four bytes in succession.  OVLYADDR will increment after the
3258 * most significant instrution byte (the byte with the parity bit) is written.
3259 */
3260register SEQRAM {
3261	address			0x0DA
3262	access_mode RW
3263}
3264
3265/*
3266 * Sequencer Program Counter
3267 * Low byte must be written prior to high byte.
3268 */
3269register PRGMCNT {
3270	address			0x0DE
3271	access_mode	RW
3272	size		2
3273}
3274
3275/*
3276 * Accumulator
3277 */
3278register ACCUM {
3279	address			0x0E0
3280	access_mode RW
3281	accumulator
3282}
3283
3284/*
3285 * Source Index Register
3286 * Incrementing index for reads of SINDIR and the destination (low byte only)
3287 * for any immediate operands passed in jmp, jc, jnc, call instructions.
3288 * Example:
3289 *		mvi	0xFF	call some_routine;
3290 *
3291 *  Will set SINDEX[0] to 0xFF and call the routine "some_routine.
3292 */
3293register SINDEX	{
3294	address			0x0E2
3295	access_mode	RW
3296	size		2
3297	sindex
3298}
3299
3300/*
3301 * Destination Index Register
3302 * Incrementing index for writes to DINDIR.  Can be used as a scratch register.
3303 */
3304register DINDEX {
3305	address			0x0E4
3306	access_mode	RW
3307	size		2
3308}
3309
3310/*
3311 * Break Address
3312 * Sequencer instruction breakpoint address address.
3313 */
3314register BRKADDR0 {
3315	address			0x0E6
3316	access_mode	RW
3317}
3318
3319register BRKADDR1 {
3320	address			0x0E6
3321	access_mode	RW
3322	field	BRKDIS		0x80	/* Disable Breakpoint */
3323}
3324
3325/*
3326 * All Ones
3327 * All reads to this register return the value 0xFF.
3328 */
3329register ALLONES {
3330	address			0x0E8
3331	access_mode RO
3332	allones
3333}
3334
3335/*
3336 * All Zeros
3337 * All reads to this register return the value 0.
3338 */
3339register ALLZEROS {
3340	address			0x0EA
3341	access_mode RO
3342	allzeros
3343}
3344
3345/*
3346 * No Destination
3347 * Writes to this register have no effect.
3348 */
3349register NONE {
3350	address			0x0EA
3351	access_mode WO
3352	none
3353}
3354
3355/*
3356 * Source Index Indirect
3357 * Reading this register is equivalent to reading (register_base + SINDEX) and
3358 * incrementing SINDEX by 1.
3359 */
3360register SINDIR	{
3361	address			0x0EC
3362	access_mode RO
3363}
3364
3365/*
3366 * Destination Index Indirect
3367 * Writing this register is equivalent to writing to (register_base + DINDEX)
3368 * and incrementing DINDEX by 1.
3369 */
3370register DINDIR	 {
3371	address			0x0ED
3372	access_mode WO
3373}
3374
3375/*
3376 * Function One
3377 * 2's complement to bit value conversion.  Write the 2's complement value
3378 * (0-7 only) to the top nibble and retrieve the bit indexed by that value
3379 * on the next read of this register. 
3380 * Example:
3381 *	Write	0x60
3382 *	Read	0x40
3383 */
3384register FUNCTION1 {
3385	address			0x0F0
3386	access_mode RW
3387}
3388
3389/*
3390 * Stack
3391 * Window into the stack.  Each stack location is 10 bits wide reported
3392 * low byte followed by high byte.  There are 8 stack locations.
3393 */
3394register STACK {
3395	address			0x0F2
3396	access_mode RW
3397}
3398
3399/*
3400 * Interrupt Vector 1 Address
3401 * Interrupt branch address for SCS SEQ_INT1 mode 0 and 1 interrupts.
3402 */
3403register INTVEC1_ADDR {
3404	address			0x0F4
3405	access_mode	RW
3406	size		2
3407	modes		M_CFG
3408}
3409
3410/*
3411 * Current Address
3412 * Address of the SEQRAM instruction currently executing instruction.
3413 */
3414register CURADDR {
3415	address			0x0F4
3416	access_mode	RW
3417	size		2
3418	modes		M_SCSI
3419}
3420
3421/*
3422 * Interrupt Vector 2 Address
3423 * Interrupt branch address for HST_SEQ_INT2 interrupts.
3424 */
3425register INTVEC2_ADDR {
3426	address			0x0F6
3427	access_mode	RW
3428	size		2
3429	modes		M_CFG
3430}
3431
3432/*
3433 * Last Address
3434 * Address of the SEQRAM instruction executed prior to the current instruction.
3435 */
3436register LASTADDR {
3437	address			0x0F6
3438	access_mode	RW
3439	size		2
3440	modes		M_SCSI
3441}
3442
3443register AHD_PCI_CONFIG_BASE {
3444	address			0x100
3445	access_mode	RW
3446	size		256
3447	modes		M_CFG
3448}
3449
3450/* ---------------------- Scratch RAM Offsets ------------------------- */
3451scratch_ram {
3452	/* Mode Specific */
3453	address			0x0A0
3454	size	8
3455	modes	0, 1, 2, 3
3456	REG0 {
3457		size		2
3458	}
3459	REG1 {
3460		size		2
3461	}
3462	REG_ISR {
3463		size		2
3464	}
3465	SG_STATE {
3466		size		1
3467		field	SEGS_AVAIL	0x01
3468		field	LOADING_NEEDED	0x02
3469		field	FETCH_INPROG	0x04
3470	}
3471	/*
3472	 * Track whether the transfer byte count for
3473	 * the current data phase is odd.
3474	 */
3475	DATA_COUNT_ODD {
3476		size		1
3477	}
3478}
3479
3480scratch_ram {
3481	/* Mode Specific */
3482	address			0x0F8
3483	size	8
3484	modes	0, 1, 2, 3
3485	LONGJMP_ADDR {
3486		size		2
3487	}
3488	ACCUM_SAVE {
3489		size		1
3490	}
3491}
3492
3493
3494scratch_ram {
3495	address			0x100
3496	size	128
3497	modes	0, 1, 2, 3
3498	/*
3499	 * Per "other-id" execution queues.  We use an array of
3500	 * tail pointers into lists of SCBs sorted by "other-id".
3501	 * The execution head pointer threads the head SCBs for
3502	 * each list.
3503	 */
3504	WAITING_SCB_TAILS {
3505		size		32
3506	}
3507	WAITING_TID_HEAD {
3508		size		2
3509	}
3510	WAITING_TID_TAIL {
3511		size		2
3512	}
3513	/*
3514	 * SCBID of the next SCB in the new SCB queue.
3515	 */
3516	NEXT_QUEUED_SCB_ADDR {
3517		size		4
3518	}
3519	/*
3520	 * head of list of SCBs that have
3521	 * completed but have not been
3522	 * put into the qoutfifo.
3523	 */
3524	COMPLETE_SCB_HEAD {
3525		size		2
3526	}
3527	/*
3528	 * The list of completed SCBs in
3529	 * the active DMA.
3530	 */
3531	COMPLETE_SCB_DMAINPROG_HEAD {
3532		size		2
3533	}
3534	/*
3535	 * head of list of SCBs that have
3536	 * completed but need to be uploaded
3537	 * to the host prior to being completed.
3538	 */
3539	COMPLETE_DMA_SCB_HEAD {
3540		size		2
3541	}
3542	/* Counting semaphore to prevent new select-outs */
3543	QFREEZE_COUNT {
3544		size		2
3545	}
3546	/*
3547	 * Mode to restore on legacy idle loop exit.
3548	 */
3549	SAVED_MODE {
3550		size		1
3551	}
3552	/*
3553	 * Single byte buffer used to designate the type or message
3554	 * to send to a target.
3555	 */
3556	MSG_OUT {
3557		size		1
3558	}
3559	/* Parameters for DMA Logic */
3560	DMAPARAMS {
3561		size		1
3562		field	PRELOADEN	0x80
3563		field	WIDEODD		0x40
3564		field	SCSIEN		0x20
3565		field	SDMAEN		0x10
3566		field	SDMAENACK	0x10
3567		field	HDMAEN		0x08
3568		field	HDMAENACK	0x08
3569		field	DIRECTION	0x04	/* Set indicates PCI->SCSI */
3570		field	FIFOFLUSH	0x02
3571		field	FIFORESET	0x01
3572	}
3573	SEQ_FLAGS {
3574		size		1
3575		field	NOT_IDENTIFIED		0x80
3576		field	NO_CDB_SENT		0x40
3577		field	TARGET_CMD_IS_TAGGED	0x40
3578		field	DPHASE			0x20
3579		/* Target flags */
3580		field	TARG_CMD_PENDING	0x10
3581		field	CMDPHASE_PENDING	0x08
3582		field	DPHASE_PENDING		0x04
3583		field	SPHASE_PENDING		0x02
3584		field	NO_DISCONNECT		0x01
3585	}
3586	/*
3587	 * Temporary storage for the
3588	 * target/channel/lun of a
3589	 * reconnecting target
3590	 */
3591	SAVED_SCSIID {
3592		size		1
3593	}
3594	SAVED_LUN {
3595		size		1
3596	}
3597	/*
3598	 * The last bus phase as seen by the sequencer. 
3599	 */
3600	LASTPHASE {
3601		size		1
3602		field	CDI		0x80
3603		field	IOI		0x40
3604		field	MSGI		0x20
3605		field	P_BUSFREE	0x01
3606		enum	PHASE_MASK  CDO|IOO|MSGO {
3607			P_DATAOUT	0x0,
3608			P_DATAIN	IOO,
3609			P_DATAOUT_DT	P_DATAOUT|MSGO,
3610			P_DATAIN_DT	P_DATAIN|MSGO,
3611			P_COMMAND	CDO,
3612			P_MESGOUT	CDO|MSGO,
3613			P_STATUS	CDO|IOO,
3614			P_MESGIN	CDO|IOO|MSGO
3615		}
3616	}
3617	/*
3618	 * Value to "or" into the SCBPTR[1] value to
3619	 * indicate that an entry in the QINFIFO is valid.
3620	 */
3621	QOUTFIFO_ENTRY_VALID_TAG {
3622		size		1
3623	}
3624	/*
3625	 * Base address of our shared data with the kernel driver in host
3626	 * memory.  This includes the qoutfifo and target mode
3627	 * incoming command queue.
3628	 */
3629	SHARED_DATA_ADDR {
3630		size		4
3631	}
3632	/*
3633	 * Pointer to location in host memory for next
3634	 * position in the qoutfifo.
3635	 */
3636	QOUTFIFO_NEXT_ADDR {
3637		size		4
3638	}
3639	/*
3640	 * Kernel and sequencer offsets into the queue of
3641	 * incoming target mode command descriptors.  The
3642	 * queue is full when the KERNEL_TQINPOS == TQINPOS.
3643	 */
3644	KERNEL_TQINPOS {
3645		size		1
3646	}
3647	TQINPOS {                
3648		size		1
3649	}
3650	ARG_1 {
3651		size		1
3652		mask	SEND_MSG		0x80
3653		mask	SEND_SENSE		0x40
3654		mask	SEND_REJ		0x20
3655		mask	MSGOUT_PHASEMIS		0x10
3656		mask	EXIT_MSG_LOOP		0x08
3657		mask	CONT_MSG_LOOP_WRITE	0x04
3658		mask	CONT_MSG_LOOP_READ	0x03
3659		mask	CONT_MSG_LOOP_TARG	0x02
3660		alias	RETURN_1
3661	}
3662	ARG_2 {
3663		size		1
3664		alias	RETURN_2
3665	}
3666
3667	/*
3668	 * Snapshot of MSG_OUT taken after each message is sent.
3669	 */
3670	LAST_MSG {
3671		size		1
3672	}
3673
3674	/*
3675	 * Sequences the kernel driver has okayed for us.  This allows
3676	 * the driver to do things like prevent initiator or target
3677	 * operations.
3678	 */
3679	SCSISEQ_TEMPLATE {
3680		size		1
3681		field	MANUALCTL	0x40
3682		field	ENSELI		0x20
3683		field	ENRSELI		0x10
3684		field	MANUALP		0x0C
3685		field	ENAUTOATNP	0x02
3686		field	ALTSTIM		0x01
3687	}
3688
3689	/*
3690	 * The initiator specified tag for this target mode transaction.
3691	 */
3692	INITIATOR_TAG {
3693		size		1
3694	}
3695
3696	SEQ_FLAGS2 {
3697		size		1
3698		field	TARGET_MSG_PENDING	  0x02
3699		field	SELECTOUT_QFROZEN	  0x04
3700	}
3701
3702	ALLOCFIFO_SCBPTR {
3703		size		2
3704	}
3705
3706	/*
3707	 * The maximum amount of time to wait, when interrupt coalessing
3708	 * is enabled, before issueing a CMDCMPLT interrupt for a completed
3709	 * command.
3710	 */
3711	INT_COALESSING_TIMER {
3712		size		2
3713	}
3714
3715	/*
3716	 * The maximum number of commands to coaless into a single interrupt.
3717	 * Actually the 2's complement of that value to simplify sequencer
3718	 * code.
3719	 */
3720	INT_COALESSING_MAXCMDS {
3721		size		1
3722	}
3723
3724	/*
3725	 * The minimum number of commands still outstanding required
3726	 * to continue coalessing (2's complement of value).
3727	 */
3728	INT_COALESSING_MINCMDS {
3729		size		1
3730	}
3731
3732	/*
3733	 * Number of commands "in-flight".
3734	 */
3735	CMDS_PENDING {
3736		size		2
3737	}
3738
3739	/*
3740	 * The count of commands that have been coalessed.
3741	 */
3742	INT_COALESSING_CMDCOUNT {
3743		size		1
3744	}
3745
3746	/*
3747	 * Since the HS_MAIBOX is self clearing, copy its contents to
3748	 * this position in scratch ram every time it changes.
3749	 */
3750	LOCAL_HS_MAILBOX {
3751		size		1
3752	}
3753	/*
3754	 * Target-mode CDB type to CDB length table used
3755	 * in non-packetized operation.
3756	 */
3757	CMDSIZE_TABLE {
3758		size		8
3759	}
3760}
3761
3762/************************* Hardware SCB Definition ****************************/
3763scb {
3764	address			0x180
3765	size	64
3766	modes	0, 1, 2, 3
3767	SCB_RESIDUAL_DATACNT {
3768		size	4
3769		alias	SCB_CDB_STORE
3770		alias	SCB_HOST_CDB_PTR
3771	}
3772	SCB_RESIDUAL_SGPTR {
3773		size	4
3774		field	SG_ADDR_MASK		0xf8	/* In the last byte */
3775		field	SG_OVERRUN_RESID	0x02	/* In the first byte */
3776		field	SG_LIST_NULL		0x01	/* In the first byte */
3777	}
3778	SCB_SCSI_STATUS {
3779		size	1
3780		alias	SCB_HOST_CDB_LEN
3781	}
3782	SCB_TARGET_PHASES {
3783		size	1
3784	}
3785	SCB_TARGET_DATA_DIR {
3786		size	1
3787	}
3788	SCB_TARGET_ITAG {
3789		size	1
3790	}
3791	SCB_SENSE_BUSADDR {
3792		/*
3793		 * Only valid if CDB length is less than 13 bytes or
3794		 * we are using a CDB pointer.  Otherwise contains
3795		 * the last 4 bytes of embedded cdb information.
3796		 */
3797		size	4
3798		alias	SCB_NEXT_COMPLETE
3799	}
3800	SCB_DATAPTR {
3801		size	8
3802	}
3803	SCB_DATACNT {
3804		/*
3805		 * The last byte is really the high address bits for
3806		 * the data address.
3807		 */
3808		size	4
3809		field	SG_LAST_SEG		0x80	/* In the fourth byte */
3810		field	SG_HIGH_ADDR_BITS	0x7F	/* In the fourth byte */
3811	}
3812	SCB_SGPTR {
3813		size	4
3814		field	SG_STATUS_VALID	0x04	/* In the first byte */
3815		field	SG_FULL_RESID	0x02	/* In the first byte */
3816		field	SG_LIST_NULL	0x01	/* In the first byte */
3817	}
3818	SCB_BUSADDR {
3819		size	4
3820	}
3821	SCB_NEXT {
3822		alias	SCB_NEXT_SCB_BUSADDR
3823		size	2
3824	}
3825	SCB_NEXT2 {
3826		size	2
3827	}
3828	SCB_CONTROL {
3829		size	1
3830		field	TARGET_SCB	0x80
3831		field	DISCENB		0x40
3832		field	TAG_ENB		0x20
3833		field	MK_MESSAGE	0x10
3834		field	STATUS_RCVD	0x08
3835		field	DISCONNECTED	0x04
3836		field	SCB_TAG_TYPE	0x03
3837	}
3838	SCB_SCSIID {
3839		size	1
3840		field	TID	0xF0
3841		field	OID	0x0F
3842	}
3843	SCB_LUN {
3844		size	1
3845		field	LID				0xff
3846	}
3847	SCB_TASK_ATTRIBUTE {
3848		size	1
3849	}
3850	SCB_CDB_LEN {
3851		size	1
3852		field	SCB_CDB_LEN_PTR	0x80	/* CDB in host memory */
3853	}
3854	SCB_TASK_MANAGEMENT {
3855		size	1
3856	}
3857	SCB_TAG {
3858		alias	SCB_FIFO_USE_COUNT
3859		size	2
3860	}
3861	SCB_SPARE {
3862		size	8
3863		alias	SCB_PKT_LUN
3864	}
3865	SCB_DISCONNECTED_LISTS {
3866		size	8
3867	}
3868}
3869
3870/*********************************** Constants ********************************/
3871const MK_MESSAGE_BIT_OFFSET	4
3872const TID_SHIFT		4
3873const TARGET_CMD_CMPLT	0xfe
3874const INVALID_ADDR	0x80
3875#define SCB_LIST_NULL	0xff
3876#define QOUTFIFO_ENTRY_VALID_TOGGLE	0x80
3877
3878const CCSGADDR_MAX	0x80
3879const CCSCBADDR_MAX	0x80
3880const CCSGRAM_MAXSEGS	16
3881
3882/* Selection Timeout Timer Constants */
3883const STIMESEL_SHIFT	3
3884const STIMESEL_MIN	0x18
3885const STIMESEL_BUG_ADJ	0x8
3886
3887/* WDTR Message values */
3888const BUS_8_BIT			0x00
3889const BUS_16_BIT		0x01
3890const BUS_32_BIT		0x02
3891
3892/* Offset maximums */
3893const MAX_OFFSET		0xfe
3894const MAX_OFFSET_PACED		0xfe
3895const MAX_OFFSET_PACED_BUG	0x7f
3896/*
3897 * Some 160 devices incorrectly accept 0xfe as a
3898 * sync offset, but will overrun this value.  Limit
3899 * to 0x7f for speed lower than U320 which will
3900 * avoid the persistent sync offset overruns.
3901 */
3902const MAX_OFFSET_NON_PACED	0x7f
3903const HOST_MSG			0xff
3904
3905/*
3906 * The size of our sense buffers.
3907 * Sense buffer mapping can be handled in either of two ways.
3908 * The first is to allocate a dmamap for each transaction.
3909 * Depending on the architecture, dmamaps can be costly. The
3910 * alternative is to statically map the buffers in much the same
3911 * way we handle our scatter gather lists.  The driver implements
3912 * the later.
3913 */
3914const AHD_SENSE_BUFSIZE		256
3915
3916/* Target mode command processing constants */
3917const CMD_GROUP_CODE_SHIFT	0x05
3918
3919const STATUS_BUSY		0x08
3920const STATUS_QUEUE_FULL		0x28
3921const STATUS_PKT_SENSE		0xFF
3922const TARGET_DATA_IN		1
3923
3924const SCB_TRANSFER_SIZE_FULL_LUN	56
3925const SCB_TRANSFER_SIZE_1BYTE_LUN	48
3926/* PKT_OVERRUN_BUFSIZE must be a multiple of 256 less than 64K */
3927const PKT_OVERRUN_BUFSIZE	512
3928
3929/*
3930 * Timer parameters.
3931 */
3932const AHD_TIMER_US_PER_TICK	25
3933const AHD_TIMER_MAX_TICKS	0xFFFF
3934const AHD_TIMER_MAX_US		(AHD_TIMER_MAX_TICKS * AHD_TIMER_US_PER_TICK)
3935
3936/*
3937 * Downloaded (kernel inserted) constants
3938 */
3939const SG_PREFETCH_CNT download
3940const SG_PREFETCH_CNT_LIMIT download
3941const SG_PREFETCH_ALIGN_MASK download
3942const SG_PREFETCH_ADDR_MASK download
3943const SG_SIZEOF download
3944const PKT_OVERRUN_BUFOFFSET download
3945const SCB_TRANSFER_SIZE	download
3946
3947/*
3948 * BIOS SCB offsets
3949 */
3950const NVRAM_SCB_OFFSET	0x2C
3951