aic79xx.reg revision 107623
197883Sgibbs/* 297883Sgibbs * Aic79xx register and scratch ram definitions. 397883Sgibbs * 497883Sgibbs * Copyright (c) 1994-2001 Justin T. Gibbs. 5102681Sgibbs * Copyright (c) 2000-2002 Adaptec Inc. 697883Sgibbs * All rights reserved. 797883Sgibbs * 897883Sgibbs * Redistribution and use in source and binary forms, with or without 997883Sgibbs * modification, are permitted provided that the following conditions 1097883Sgibbs * are met: 1197883Sgibbs * 1. Redistributions of source code must retain the above copyright 1297883Sgibbs * notice, this list of conditions, and the following disclaimer, 1397883Sgibbs * without modification. 1497883Sgibbs * 2. Redistributions in binary form must reproduce at minimum a disclaimer 1597883Sgibbs * substantially similar to the "NO WARRANTY" disclaimer below 1697883Sgibbs * ("Disclaimer") and any redistribution must be conditioned upon 1797883Sgibbs * including a substantially similar Disclaimer requirement for further 1897883Sgibbs * binary redistribution. 1997883Sgibbs * 3. Neither the names of the above-listed copyright holders nor the names 2097883Sgibbs * of any contributors may be used to endorse or promote products derived 2197883Sgibbs * from this software without specific prior written permission. 2297883Sgibbs * 2397883Sgibbs * Alternatively, this software may be distributed under the terms of the 2497883Sgibbs * GNU General Public License ("GPL") version 2 as published by the Free 2597883Sgibbs * Software Foundation. 2697883Sgibbs * 2797883Sgibbs * NO WARRANTY 2897883Sgibbs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2997883Sgibbs * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3097883Sgibbs * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 3197883Sgibbs * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3297883Sgibbs * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 3397883Sgibbs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 3497883Sgibbs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 3597883Sgibbs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 3697883Sgibbs * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 3797883Sgibbs * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3897883Sgibbs * POSSIBILITY OF SUCH DAMAGES. 3997883Sgibbs * 4097883Sgibbs * $FreeBSD: head/sys/dev/aic7xxx/aic79xx.reg 107623 2002-12-04 22:51:29Z scottl $ 4197883Sgibbs */ 42107623SscottlVERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#56 $" 4397883Sgibbs 4497883Sgibbs/* 4597883Sgibbs * This file is processed by the aic7xxx_asm utility for use in assembling 4697883Sgibbs * firmware for the aic79xx family of SCSI host adapters as well as to generate 4797883Sgibbs * a C header file for use in the kernel portion of the Aic79xx driver. 4897883Sgibbs */ 4997883Sgibbs 5097883Sgibbs/* Register window Modes */ 5197883Sgibbs#define M_DFF0 0 5297883Sgibbs#define M_DFF1 1 5397883Sgibbs#define M_CCHAN 2 5497883Sgibbs#define M_SCSI 3 5597883Sgibbs#define M_CFG 4 5697883Sgibbs#define M_DST_SHIFT 4 5797883Sgibbs 5897883Sgibbs#define MK_MODE(src, dst) ((src) | ((dst) << M_DST_SHIFT)) 59104023Sgibbs#define SET_MODE(src, dst) \ 60104023Sgibbs SET_SRC_MODE src; \ 61104023Sgibbs SET_DST_MODE dst; \ 62104023Sgibbs if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ 63104023Sgibbs mvi MK_MODE(src, dst) call set_mode_work_around; \ 64104023Sgibbs } else { \ 65104023Sgibbs mvi MODE_PTR, MK_MODE(src, dst); \ 66104023Sgibbs } 6797883Sgibbs 68104023Sgibbs#define TOGGLE_DFF_MODE \ 69104023Sgibbs if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ 70104023Sgibbs call toggle_dff_mode_work_around; \ 71104023Sgibbs } else { \ 72104023Sgibbs xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1); \ 73104023Sgibbs } 74104023Sgibbs 75107441Sscottl#define RESTORE_MODE(mode) \ 76107441Sscottl if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ 77107441Sscottl mov mode call set_mode_work_around; \ 78107441Sscottl } else { \ 79107441Sscottl mov MODE_PTR, mode; \ 80107441Sscottl } 81104023Sgibbs 82107441Sscottl#define SET_SEQINTCODE(code) \ 83107441Sscottl if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { \ 84107441Sscottl mvi code call set_seqint_work_around; \ 85107441Sscottl } else { \ 86107441Sscottl mvi SEQINTCODE, code; \ 87107441Sscottl } 88107441Sscottl 8997883Sgibbs/* 9097883Sgibbs * Mode Pointer 9197883Sgibbs * Controls which of the 5, 512byte, address spaces should be used 9297883Sgibbs * as the source and destination of any register accesses in our 9397883Sgibbs * register window. 9497883Sgibbs */ 9597883Sgibbsregister MODE_PTR { 9697883Sgibbs address 0x000 9797883Sgibbs access_mode RW 98102681Sgibbs field DST_MODE 0x70 99102681Sgibbs field SRC_MODE 0x07 10097883Sgibbs mode_pointer 10197883Sgibbs} 10297883Sgibbs 10397883Sgibbsconst SRC_MODE_SHIFT 0 10497883Sgibbsconst DST_MODE_SHIFT 4 10597883Sgibbs 10697883Sgibbs/* 10797883Sgibbs * Host Interrupt Status 10897883Sgibbs */ 10997883Sgibbsregister INTSTAT { 11097883Sgibbs address 0x001 11197883Sgibbs access_mode RW 112102681Sgibbs field HWERRINT 0x80 113102681Sgibbs field BRKADRINT 0x40 114102681Sgibbs field SWTMINT 0x20 115102681Sgibbs field PCIINT 0x10 116102681Sgibbs field SCSIINT 0x08 117102681Sgibbs field SEQINT 0x04 118102681Sgibbs field CMDCMPLT 0x02 119102681Sgibbs field SPLTINT 0x01 12097883Sgibbs mask INT_PEND 0xFF 12197883Sgibbs} 12297883Sgibbs 12397883Sgibbs/* 12497883Sgibbs * Sequencer Interrupt Code 12597883Sgibbs */ 12697883Sgibbsregister SEQINTCODE { 12797883Sgibbs address 0x002 12897883Sgibbs access_mode RW 129102681Sgibbs field { 130107441Sscottl NO_SEQINT, /* No seqint pending. */ 131107441Sscottl BAD_PHASE, /* unknown scsi bus phase */ 132102681Sgibbs SEND_REJECT, /* sending a message reject */ 133102681Sgibbs PROTO_VIOLATION, /* Protocol Violation */ 134102681Sgibbs NO_MATCH, /* no cmd match for reconnect */ 135102681Sgibbs IGN_WIDE_RES, /* Complex IGN Wide Res Msg */ 136102681Sgibbs PDATA_REINIT, /* 13797883Sgibbs * Returned to data phase 13897883Sgibbs * that requires data 13997883Sgibbs * transfer pointers to be 14097883Sgibbs * recalculated from the 14197883Sgibbs * transfer residual. 14297883Sgibbs */ 143102681Sgibbs HOST_MSG_LOOP, /* 14497883Sgibbs * The bus is ready for the 14597883Sgibbs * host to perform another 14697883Sgibbs * message transaction. This 14797883Sgibbs * mechanism is used for things 14897883Sgibbs * like sync/wide negotiation 14997883Sgibbs * that require a kernel based 15097883Sgibbs * message state engine. 15197883Sgibbs */ 152102681Sgibbs BAD_STATUS, /* Bad status from target */ 153102681Sgibbs DATA_OVERRUN, /* 15497883Sgibbs * Target attempted to write 15597883Sgibbs * beyond the bounds of its 15697883Sgibbs * command. 15797883Sgibbs */ 158102681Sgibbs MKMSG_FAILED, /* 15997883Sgibbs * Target completed command 16097883Sgibbs * without honoring our ATN 16197883Sgibbs * request to issue a message. 16297883Sgibbs */ 163102681Sgibbs MISSED_BUSFREE, /* 16497883Sgibbs * The sequencer never saw 16597883Sgibbs * the bus go free after 16697883Sgibbs * either a command complete 16797883Sgibbs * or disconnect message. 16897883Sgibbs */ 169102681Sgibbs DUMP_CARD_STATE, 170102681Sgibbs ILLEGAL_PHASE, 171102681Sgibbs INVALID_SEQINT, 172102681Sgibbs CFG4ISTAT_INTR, 173102681Sgibbs STATUS_OVERRUN, 174102681Sgibbs CFG4OVERRUN, 175107441Sscottl ENTERING_NONPACK, 176107441Sscottl TRACEPOINT0, 177107441Sscottl TRACEPOINT1, 178107441Sscottl TRACEPOINT2, 179107441Sscottl TRACEPOINT3, 180107441Sscottl SAW_HWERR 181102681Sgibbs } 18297883Sgibbs} 18397883Sgibbs 18497883Sgibbs/* 18597883Sgibbs * Clear Host Interrupt 18697883Sgibbs */ 18797883Sgibbsregister CLRINT { 18897883Sgibbs address 0x003 18997883Sgibbs access_mode WO 190102681Sgibbs field CLRHWERRINT 0x80 /* Rev B or greater */ 191102681Sgibbs field CLRBRKADRINT 0x40 192102681Sgibbs field CLRSWTMINT 0x20 193107623Sscottl field CLRPCIINT 0x10 194102681Sgibbs field CLRSCSIINT 0x08 195102681Sgibbs field CLRSEQINT 0x04 196102681Sgibbs field CLRCMDINT 0x02 197102681Sgibbs field CLRSPLTINT 0x01 19897883Sgibbs} 19997883Sgibbs 20097883Sgibbs/* 20197883Sgibbs * Error Register 20297883Sgibbs */ 20397883Sgibbsregister ERROR { 20497883Sgibbs address 0x004 20597883Sgibbs access_mode RO 206102681Sgibbs field CIOPARERR 0x80 207102681Sgibbs field CIOACCESFAIL 0x40 /* Rev B or greater */ 208102681Sgibbs field MPARERR 0x20 209102681Sgibbs field DPARERR 0x10 210102681Sgibbs field SQPARERR 0x08 211102681Sgibbs field ILLOPCODE 0x04 212102681Sgibbs field DSCTMOUT 0x02 21397883Sgibbs} 21497883Sgibbs 21597883Sgibbs/* 21697883Sgibbs * Clear Error 21797883Sgibbs */ 21897883Sgibbsregister CLRERR { 21997883Sgibbs address 0x004 22097883Sgibbs access_mode WO 221102681Sgibbs field CLRCIOPARERR 0x80 222102681Sgibbs field CLRCIOACCESFAIL 0x40 /* Rev B or greater */ 223102681Sgibbs field CLRMPARERR 0x20 224102681Sgibbs field CLRDPARERR 0x10 225102681Sgibbs field CLRSQPARERR 0x08 226102681Sgibbs field CLRILLOPCODE 0x04 227102681Sgibbs field CLRDSCTMOUT 0x02 22897883Sgibbs} 22997883Sgibbs 23097883Sgibbs/* 23197883Sgibbs * Host Control Register 23297883Sgibbs * Overall host control of the device. 23397883Sgibbs */ 23497883Sgibbsregister HCNTRL { 23597883Sgibbs address 0x005 23697883Sgibbs access_mode RW 237102681Sgibbs field SEQ_RESET 0x80 /* Rev B or greater */ 238102681Sgibbs field POWRDN 0x40 239102681Sgibbs field SWINT 0x10 240102681Sgibbs field SWTIMER_START_B 0x08 /* Rev B or greater */ 241102681Sgibbs field PAUSE 0x04 242102681Sgibbs field INTEN 0x02 243102681Sgibbs field CHIPRST 0x01 244102681Sgibbs field CHIPRSTACK 0x01 24597883Sgibbs} 24697883Sgibbs 24797883Sgibbs/* 24897883Sgibbs * Host New SCB Queue Offset 24997883Sgibbs */ 25097883Sgibbsregister HNSCB_QOFF { 25197883Sgibbs address 0x006 25297883Sgibbs access_mode RW 25397883Sgibbs size 2 25497883Sgibbs} 25597883Sgibbs 25697883Sgibbs/* 25797883Sgibbs * Host Empty SCB Queue Offset 25897883Sgibbs */ 25997883Sgibbsregister HESCB_QOFF { 26097883Sgibbs address 0x008 26197883Sgibbs access_mode RW 26297883Sgibbs} 26397883Sgibbs 26497883Sgibbs/* 26597883Sgibbs * Host Mailbox 26697883Sgibbs */ 26797883Sgibbsregister HS_MAILBOX { 26897883Sgibbs address 0x0B 26997883Sgibbs access_mode RW 27097883Sgibbs mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */ 27197883Sgibbs} 27297883Sgibbs 27397883Sgibbs/* 27497883Sgibbs * Sequencer Interupt Status 27597883Sgibbs */ 27697883Sgibbsregister SEQINTSTAT { 27797883Sgibbs address 0x0C 27897883Sgibbs access_mode RO 279102681Sgibbs field SEQ_SWTMRTO 0x10 280102681Sgibbs field SEQ_SEQINT 0x08 281102681Sgibbs field SEQ_SCSIINT 0x04 282102681Sgibbs field SEQ_PCIINT 0x02 283102681Sgibbs field SEQ_SPLTINT 0x01 28497883Sgibbs} 28597883Sgibbs 28697883Sgibbs/* 28797883Sgibbs * Clear SEQ Interrupt 28897883Sgibbs */ 28997883Sgibbsregister CLRSEQINTSTAT { 29097883Sgibbs address 0x0C0 29197883Sgibbs access_mode WO 292102681Sgibbs field CLRSEQ_SWTMRTO 0x10 293102681Sgibbs field CLRSEQ_SEQINT 0x08 294102681Sgibbs field CLRSEQ_SCSIINT 0x04 295102681Sgibbs field CLRSEQ_PCIINT 0x02 296102681Sgibbs field CLRSEQ_SPLTINT 0x01 29797883Sgibbs} 29897883Sgibbs 29997883Sgibbs/* 30097883Sgibbs * Software Timer 30197883Sgibbs */ 30297883Sgibbsregister SWTIMER { 30397883Sgibbs address 0x0E0 30497883Sgibbs access_mode RW 30597883Sgibbs size 2 30697883Sgibbs} 30797883Sgibbs 30897883Sgibbs/* 30997883Sgibbs * SEQ New SCB Queue Offset 31097883Sgibbs */ 31197883Sgibbsregister SNSCB_QOFF { 31297883Sgibbs address 0x010 31397883Sgibbs access_mode RW 31497883Sgibbs size 2 31597883Sgibbs modes M_CCHAN 31697883Sgibbs} 31797883Sgibbs 31897883Sgibbs/* 31997883Sgibbs * SEQ Empty SCB Queue Offset 32097883Sgibbs */ 32197883Sgibbsregister SESCB_QOFF { 32297883Sgibbs address 0x012 32397883Sgibbs access_mode RW 32497883Sgibbs modes M_CCHAN 32597883Sgibbs} 32697883Sgibbs 32797883Sgibbs/* 32897883Sgibbs * SEQ Done SCB Queue Offset 32997883Sgibbs */ 33097883Sgibbsregister SDSCB_QOFF { 33197883Sgibbs address 0x014 33297883Sgibbs access_mode RW 33397883Sgibbs modes M_CCHAN 33497883Sgibbs size 2 33597883Sgibbs} 33697883Sgibbs 33797883Sgibbs/* 33897883Sgibbs * Queue Offset Control & Status 33997883Sgibbs */ 34097883Sgibbsregister QOFF_CTLSTA { 34197883Sgibbs address 0x016 34297883Sgibbs access_mode RW 34397883Sgibbs modes M_CCHAN 344102681Sgibbs field EMPTY_SCB_AVAIL 0x80 345102681Sgibbs field NEW_SCB_AVAIL 0x40 346102681Sgibbs field SDSCB_ROLLOVR 0x20 347102681Sgibbs field HS_MAILBOX_ACT 0x10 348102681Sgibbs field SCB_QSIZE 0x0F { 349102681Sgibbs SCB_QSIZE_4, 350102681Sgibbs SCB_QSIZE_8, 351102681Sgibbs SCB_QSIZE_16, 352102681Sgibbs SCB_QSIZE_32, 353102681Sgibbs SCB_QSIZE_64, 354102681Sgibbs SCB_QSIZE_128, 355102681Sgibbs SCB_QSIZE_256, 356102681Sgibbs SCB_QSIZE_512, 357102681Sgibbs SCB_QSIZE_1024, 358102681Sgibbs SCB_QSIZE_2048, 359102681Sgibbs SCB_QSIZE_4096, 360102681Sgibbs SCB_QSIZE_8192, 361102681Sgibbs SCB_QSIZE_16384 362102681Sgibbs } 36397883Sgibbs} 36497883Sgibbs 36597883Sgibbs/* 36697883Sgibbs * Interrupt Control 36797883Sgibbs */ 36897883Sgibbsregister INTCTL { 36997883Sgibbs address 0x018 37097883Sgibbs access_mode RW 371102681Sgibbs field SWTMINTMASK 0x80 372102681Sgibbs field SWTMINTEN 0x40 373102681Sgibbs field SWTIMER_START 0x20 374102681Sgibbs field AUTOCLRCMDINT 0x10 375102681Sgibbs field PCIINTEN 0x08 376102681Sgibbs field SCSIINTEN 0x04 377102681Sgibbs field SEQINTEN 0x02 378102681Sgibbs field SPLTINTEN 0x01 37997883Sgibbs} 38097883Sgibbs 38197883Sgibbs/* 38297883Sgibbs * Data FIFO Control 38397883Sgibbs */ 38497883Sgibbsregister DFCNTRL { 38597883Sgibbs address 0x019 38697883Sgibbs access_mode RW 38797883Sgibbs modes M_DFF0, M_DFF1 388102681Sgibbs field PRELOADEN 0x80 389107441Sscottl field SCSIENWRDIS 0x40 /* Rev B only. */ 390102681Sgibbs field SCSIEN 0x20 391102681Sgibbs field SCSIENACK 0x20 392102681Sgibbs field HDMAEN 0x08 393102681Sgibbs field HDMAENACK 0x08 394102681Sgibbs field DIRECTION 0x04 395102681Sgibbs field DIRECTIONACK 0x04 396102681Sgibbs field FIFOFLUSH 0x02 397102681Sgibbs field FIFOFLUSHACK 0x02 398102681Sgibbs field DIRECTIONEN 0x01 39997883Sgibbs} 40097883Sgibbs 40197883Sgibbs/* 40297883Sgibbs * Device Space Command 0 40397883Sgibbs */ 40497883Sgibbsregister DSCOMMAND0 { 40597883Sgibbs address 0x019 40697883Sgibbs access_mode RW 40797883Sgibbs modes M_CFG 408102681Sgibbs field CACHETHEN 0x80 /* Cache Threshold enable */ 409102681Sgibbs field DPARCKEN 0x40 /* Data Parity Check Enable */ 410102681Sgibbs field MPARCKEN 0x20 /* Memory Parity Check Enable */ 411102681Sgibbs field EXTREQLCK 0x10 /* External Request Lock */ 412102681Sgibbs field DISABLE_TWATE 0x02 /* Rev B or greater */ 413102681Sgibbs field CIOPARCKEN 0x01 /* Internal bus parity error enable */ 41497883Sgibbs} 41597883Sgibbs 41697883Sgibbs/* 41797883Sgibbs * Data FIFO Status 41897883Sgibbs */ 41997883Sgibbsregister DFSTATUS { 42097883Sgibbs address 0x01A 42197883Sgibbs access_mode RO 42297883Sgibbs modes M_DFF0, M_DFF1 423102681Sgibbs field PRELOAD_AVAIL 0x80 424102681Sgibbs field PKT_PRELOAD_AVAIL 0x40 425102681Sgibbs field MREQPEND 0x10 426102681Sgibbs field HDONE 0x08 427102681Sgibbs field DFTHRESH 0x04 428102681Sgibbs field FIFOFULL 0x02 429102681Sgibbs field FIFOEMP 0x01 43097883Sgibbs} 43197883Sgibbs 43297883Sgibbs/* 43397883Sgibbs * S/G Cache Pointer 43497883Sgibbs */ 43597883Sgibbsregister SG_CACHE_PRE { 43697883Sgibbs address 0x01B 43797883Sgibbs access_mode WO 43897883Sgibbs modes M_DFF0, M_DFF1 439102681Sgibbs field SG_ADDR_MASK 0xf8 440102681Sgibbs field ODD_SEG 0x04 441102681Sgibbs field LAST_SEG 0x02 44297883Sgibbs} 44397883Sgibbs 44497883Sgibbsregister SG_CACHE_SHADOW { 44597883Sgibbs address 0x01B 44697883Sgibbs access_mode RO 44797883Sgibbs modes M_DFF0, M_DFF1 448102681Sgibbs field SG_ADDR_MASK 0xf8 449102681Sgibbs field ODD_SEG 0x04 450102681Sgibbs field LAST_SEG 0x02 451102681Sgibbs field LAST_SEG_DONE 0x01 45297883Sgibbs} 45397883Sgibbs 45497883Sgibbs/* 45597883Sgibbs * Arbiter Control 45697883Sgibbs */ 45797883Sgibbsregister ARBCTL { 45897883Sgibbs address 0x01B 45997883Sgibbs access_mode RW 46097883Sgibbs modes M_CFG 461102681Sgibbs field RESET_HARB 0x80 462102681Sgibbs field RETRY_SWEN 0x08 463102681Sgibbs field USE_TIME 0x07 46497883Sgibbs} 46597883Sgibbs 46697883Sgibbs/* 46797883Sgibbs * Data Channel Host Address 46897883Sgibbs */ 46997883Sgibbsregister HADDR { 47097883Sgibbs address 0x070 47197883Sgibbs access_mode RW 47297883Sgibbs size 8 47397883Sgibbs modes M_DFF0, M_DFF1 47497883Sgibbs} 47597883Sgibbs 47697883Sgibbs/* 47797883Sgibbs * Host Overlay DMA Address 47897883Sgibbs */ 47997883Sgibbsregister HODMAADR { 48097883Sgibbs address 0x070 48197883Sgibbs access_mode RW 48297883Sgibbs size 8 48397883Sgibbs modes M_SCSI 48497883Sgibbs} 48597883Sgibbs 48697883Sgibbs/* 487107441Sscottl * PCI PLL Delay. 488107441Sscottl */ 489107441Sscottlregister PLLDELAY { 490107441Sscottl address 0x070 491107441Sscottl access_mode RW 492107441Sscottl size 1 493107441Sscottl modes M_CFG 494107441Sscottl field SPLIT_DROP_REQ 0x80 495107441Sscottl} 496107441Sscottl 497107441Sscottl/* 49897883Sgibbs * Data Channel Host Count 49997883Sgibbs */ 50097883Sgibbsregister HCNT { 50197883Sgibbs address 0x078 50297883Sgibbs access_mode RW 50397883Sgibbs size 3 50497883Sgibbs modes M_DFF0, M_DFF1 50597883Sgibbs} 50697883Sgibbs 50797883Sgibbs/* 50897883Sgibbs * Host Overlay DMA Count 50997883Sgibbs */ 51097883Sgibbsregister HODMACNT { 51197883Sgibbs address 0x078 51297883Sgibbs access_mode RW 51397883Sgibbs size 2 51497883Sgibbs modes M_SCSI 51597883Sgibbs} 51697883Sgibbs 51797883Sgibbs/* 51897883Sgibbs * Host Overlay DMA Enable 51997883Sgibbs */ 52097883Sgibbsregister HODMAEN { 52197883Sgibbs address 0x07A 52297883Sgibbs access_mode RW 52397883Sgibbs modes M_SCSI 52497883Sgibbs} 52597883Sgibbs 52697883Sgibbs/* 52797883Sgibbs * Scatter/Gather Host Address 52897883Sgibbs */ 52997883Sgibbsregister SGHADDR { 53097883Sgibbs address 0x07C 53197883Sgibbs access_mode RW 53297883Sgibbs size 8 53397883Sgibbs modes M_DFF0, M_DFF1 53497883Sgibbs} 53597883Sgibbs 53697883Sgibbs/* 53797883Sgibbs * SCB Host Address 53897883Sgibbs */ 53997883Sgibbsregister SCBHADDR { 54097883Sgibbs address 0x07C 54197883Sgibbs access_mode RW 54297883Sgibbs size 8 54397883Sgibbs modes M_CCHAN 54497883Sgibbs} 54597883Sgibbs 54697883Sgibbs/* 54797883Sgibbs * Scatter/Gather Host Count 54897883Sgibbs */ 54997883Sgibbsregister SGHCNT { 55097883Sgibbs address 0x084 55197883Sgibbs access_mode RW 55297883Sgibbs modes M_DFF0, M_DFF1 55397883Sgibbs} 55497883Sgibbs 55597883Sgibbs/* 55697883Sgibbs * SCB Host Count 55797883Sgibbs */ 55897883Sgibbsregister SCBHCNT { 55997883Sgibbs address 0x084 56097883Sgibbs access_mode RW 56197883Sgibbs modes M_CCHAN 56297883Sgibbs} 56397883Sgibbs 56497883Sgibbs/* 56597883Sgibbs * Data FIFO Threshold 56697883Sgibbs */ 56797883Sgibbsregister DFF_THRSH { 56897883Sgibbs address 0x088 56997883Sgibbs access_mode RW 57097883Sgibbs modes M_CFG 571102681Sgibbs field WR_DFTHRSH 0x70 { 572102681Sgibbs WR_DFTHRSH_MIN, 573102681Sgibbs WR_DFTHRSH_25, 574102681Sgibbs WR_DFTHRSH_50, 575102681Sgibbs WR_DFTHRSH_63, 576102681Sgibbs WR_DFTHRSH_75, 577102681Sgibbs WR_DFTHRSH_85, 578102681Sgibbs WR_DFTHRSH_90, 579102681Sgibbs WR_DFTHRSH_MAX 580102681Sgibbs } 581102681Sgibbs field RD_DFTHRSH 0x07 { 582102681Sgibbs RD_DFTHRSH_MIN, 583102681Sgibbs RD_DFTHRSH_25, 584102681Sgibbs RD_DFTHRSH_50, 585102681Sgibbs RD_DFTHRSH_63, 586102681Sgibbs RD_DFTHRSH_75, 587102681Sgibbs RD_DFTHRSH_85, 588102681Sgibbs RD_DFTHRSH_90, 589102681Sgibbs RD_DFTHRSH_MAX 590102681Sgibbs } 59197883Sgibbs} 59297883Sgibbs 59397883Sgibbs/* 59497883Sgibbs * ROM Address 59597883Sgibbs */ 59697883Sgibbsregister ROMADDR { 59797883Sgibbs address 0x08A 59897883Sgibbs access_mode RW 59997883Sgibbs size 3 60097883Sgibbs} 60197883Sgibbs 60297883Sgibbs/* 60397883Sgibbs * ROM Control 60497883Sgibbs */ 60597883Sgibbsregister ROMCNTRL { 60697883Sgibbs address 0x08D 60797883Sgibbs access_mode RW 608102681Sgibbs field ROMOP 0xE0 609102681Sgibbs field ROMSPD 0x18 610102681Sgibbs field REPEAT 0x02 611102681Sgibbs field RDY 0x01 61297883Sgibbs} 61397883Sgibbs 61497883Sgibbs/* 61597883Sgibbs * ROM Data 61697883Sgibbs */ 61797883Sgibbsregister ROMDATA { 61897883Sgibbs address 0x08E 61997883Sgibbs access_mode RW 62097883Sgibbs} 62197883Sgibbs 62297883Sgibbs/* 62397883Sgibbs * Data Channel Receive Message 0 62497883Sgibbs */ 62597883Sgibbsregister DCHRXMSG0 { 62697883Sgibbs address 0x090 62797883Sgibbs access_mode RO 62897883Sgibbs modes M_DFF0, M_DFF1 629102681Sgibbs field CDNUM 0xF8 630102681Sgibbs field CFNUM 0x07 63197883Sgibbs} 63297883Sgibbs 63397883Sgibbs/* 63497883Sgibbs * CMC Recieve Message 0 63597883Sgibbs */ 63697883Sgibbsregister CMCRXMSG0 { 63797883Sgibbs address 0x090 63897883Sgibbs access_mode RO 63997883Sgibbs modes M_CCHAN 640102681Sgibbs field CDNUM 0xF8 641102681Sgibbs field CFNUM 0x07 64297883Sgibbs} 64397883Sgibbs 64497883Sgibbs/* 64597883Sgibbs * Overlay Recieve Message 0 64697883Sgibbs */ 64797883Sgibbsregister OVLYRXMSG0 { 64897883Sgibbs address 0x090 64997883Sgibbs access_mode RO 65097883Sgibbs modes M_SCSI 651102681Sgibbs field CDNUM 0xF8 652102681Sgibbs field CFNUM 0x07 65397883Sgibbs} 65497883Sgibbs 65597883Sgibbs/* 65697883Sgibbs * Relaxed Order Enable 65797883Sgibbs */ 65897883Sgibbsregister ROENABLE { 65997883Sgibbs address 0x090 66097883Sgibbs access_mode RW 66197883Sgibbs modes M_CFG 662102681Sgibbs field MSIROEN 0x20 663102681Sgibbs field OVLYROEN 0x10 664102681Sgibbs field CMCROEN 0x08 665102681Sgibbs field SGROEN 0x04 666102681Sgibbs field DCH1ROEN 0x02 667102681Sgibbs field DCH0ROEN 0x01 66897883Sgibbs} 66997883Sgibbs 67097883Sgibbs/* 67197883Sgibbs * Data Channel Receive Message 1 67297883Sgibbs */ 67397883Sgibbsregister DCHRXMSG1 { 67497883Sgibbs address 0x091 67597883Sgibbs access_mode RO 67697883Sgibbs modes M_DFF0, M_DFF1 677102681Sgibbs field CBNUM 0xFF 67897883Sgibbs} 67997883Sgibbs 68097883Sgibbs/* 68197883Sgibbs * CMC Recieve Message 1 68297883Sgibbs */ 68397883Sgibbsregister CMCRXMSG1 { 68497883Sgibbs address 0x091 68597883Sgibbs access_mode RO 68697883Sgibbs modes M_CCHAN 687102681Sgibbs field CBNUM 0xFF 68897883Sgibbs} 68997883Sgibbs 69097883Sgibbs/* 69197883Sgibbs * Overlay Recieve Message 1 69297883Sgibbs */ 69397883Sgibbsregister OVLYRXMSG1 { 69497883Sgibbs address 0x091 69597883Sgibbs access_mode RO 69697883Sgibbs modes M_SCSI 697102681Sgibbs field CBNUM 0xFF 69897883Sgibbs} 69997883Sgibbs 70097883Sgibbs/* 70197883Sgibbs * No Snoop Enable 70297883Sgibbs */ 70397883Sgibbsregister NSENABLE { 70497883Sgibbs address 0x091 70597883Sgibbs access_mode RW 70697883Sgibbs modes M_CFG 707102681Sgibbs field MSINSEN 0x20 708102681Sgibbs field OVLYNSEN 0x10 709102681Sgibbs field CMCNSEN 0x08 710102681Sgibbs field SGNSEN 0x04 711102681Sgibbs field DCH1NSEN 0x02 712102681Sgibbs field DCH0NSEN 0x01 71397883Sgibbs} 71497883Sgibbs 71597883Sgibbs/* 71697883Sgibbs * Data Channel Receive Message 2 71797883Sgibbs */ 71897883Sgibbsregister DCHRXMSG2 { 71997883Sgibbs address 0x092 72097883Sgibbs access_mode RO 72197883Sgibbs modes M_DFF0, M_DFF1 722102681Sgibbs field MINDEX 0xFF 72397883Sgibbs} 72497883Sgibbs 72597883Sgibbs/* 72697883Sgibbs * CMC Recieve Message 2 72797883Sgibbs */ 72897883Sgibbsregister CMCRXMSG2 { 72997883Sgibbs address 0x092 73097883Sgibbs access_mode RO 73197883Sgibbs modes M_CCHAN 732102681Sgibbs field MINDEX 0xFF 73397883Sgibbs} 73497883Sgibbs 73597883Sgibbs/* 73697883Sgibbs * Overlay Recieve Message 2 73797883Sgibbs */ 73897883Sgibbsregister OVLYRXMSG2 { 73997883Sgibbs address 0x092 74097883Sgibbs access_mode RO 74197883Sgibbs modes M_SCSI 742102681Sgibbs field MINDEX 0xFF 74397883Sgibbs} 74497883Sgibbs 74597883Sgibbs/* 74697883Sgibbs * Outstanding Split Transactions 74797883Sgibbs */ 74897883Sgibbsregister OST { 74997883Sgibbs address 0x092 75097883Sgibbs access_mode RW 75197883Sgibbs modes M_CFG 75297883Sgibbs} 75397883Sgibbs 75497883Sgibbs/* 75597883Sgibbs * Data Channel Receive Message 3 75697883Sgibbs */ 75797883Sgibbsregister DCHRXMSG3 { 75897883Sgibbs address 0x093 75997883Sgibbs access_mode RO 76097883Sgibbs modes M_DFF0, M_DFF1 761102681Sgibbs field MCLASS 0x0F 76297883Sgibbs} 76397883Sgibbs 76497883Sgibbs/* 76597883Sgibbs * CMC Recieve Message 3 76697883Sgibbs */ 76797883Sgibbsregister CMCRXMSG3 { 76897883Sgibbs address 0x093 76997883Sgibbs access_mode RO 77097883Sgibbs modes M_CCHAN 771102681Sgibbs field MCLASS 0x0F 77297883Sgibbs} 77397883Sgibbs 77497883Sgibbs/* 77597883Sgibbs * Overlay Recieve Message 3 77697883Sgibbs */ 77797883Sgibbsregister OVLYRXMSG3 { 77897883Sgibbs address 0x093 77997883Sgibbs access_mode RO 78097883Sgibbs modes M_SCSI 781102681Sgibbs field MCLASS 0x0F 78297883Sgibbs} 78397883Sgibbs 78497883Sgibbs/* 78597883Sgibbs * PCI-X Control 78697883Sgibbs */ 78797883Sgibbsregister PCIXCTL { 78897883Sgibbs address 0x093 78997883Sgibbs access_mode RW 79097883Sgibbs modes M_CFG 791102681Sgibbs field SERRPULSE 0x80 792102681Sgibbs field UNEXPSCIEN 0x20 793102681Sgibbs field SPLTSMADIS 0x10 794102681Sgibbs field SPLTSTADIS 0x08 795102681Sgibbs field SRSPDPEEN 0x04 796102681Sgibbs field TSCSERREN 0x02 797102681Sgibbs field CMPABCDIS 0x01 79897883Sgibbs} 79997883Sgibbs 80097883Sgibbs/* 80197883Sgibbs * CMC Sequencer Byte Count 80297883Sgibbs */ 80397883Sgibbsregister CMCSEQBCNT { 80497883Sgibbs address 0x094 80597883Sgibbs access_mode RO 80697883Sgibbs modes M_CCHAN 80797883Sgibbs} 80897883Sgibbs 80997883Sgibbs/* 81097883Sgibbs * Overlay Sequencer Byte Count 81197883Sgibbs */ 81297883Sgibbsregister OVLYSEQBCNT { 81397883Sgibbs address 0x094 81497883Sgibbs access_mode RO 81597883Sgibbs modes M_SCSI 81697883Sgibbs} 81797883Sgibbs 81897883Sgibbs/* 81997883Sgibbs * Data Channel Sequencer Byte Count 82097883Sgibbs */ 82197883Sgibbsregister DCHSEQBCNT { 82297883Sgibbs address 0x094 82397883Sgibbs access_mode RO 82497883Sgibbs size 2 82597883Sgibbs modes M_DFF0, M_DFF1 82697883Sgibbs} 82797883Sgibbs 82897883Sgibbs/* 82997883Sgibbs * Data Channel Split Status 0 83097883Sgibbs */ 83197883Sgibbsregister DCHSPLTSTAT0 { 83297883Sgibbs address 0x096 83397883Sgibbs access_mode RW 83497883Sgibbs modes M_DFF0, M_DFF1 835102681Sgibbs field STAETERM 0x80 836102681Sgibbs field SCBCERR 0x40 837102681Sgibbs field SCADERR 0x20 838102681Sgibbs field SCDATBUCKET 0x10 839102681Sgibbs field CNTNOTCMPLT 0x08 840102681Sgibbs field RXOVRUN 0x04 841102681Sgibbs field RXSCEMSG 0x02 842102681Sgibbs field RXSPLTRSP 0x01 84397883Sgibbs} 84497883Sgibbs 84597883Sgibbs/* 84697883Sgibbs * CMC Split Status 0 84797883Sgibbs */ 84897883Sgibbsregister CMCSPLTSTAT0 { 84997883Sgibbs address 0x096 85097883Sgibbs access_mode RW 85197883Sgibbs modes M_CCHAN 852102681Sgibbs field STAETERM 0x80 853102681Sgibbs field SCBCERR 0x40 854102681Sgibbs field SCADERR 0x20 855102681Sgibbs field SCDATBUCKET 0x10 856102681Sgibbs field CNTNOTCMPLT 0x08 857102681Sgibbs field RXOVRUN 0x04 858102681Sgibbs field RXSCEMSG 0x02 859102681Sgibbs field RXSPLTRSP 0x01 86097883Sgibbs} 86197883Sgibbs 86297883Sgibbs/* 86397883Sgibbs * Overlay Split Status 0 86497883Sgibbs */ 86597883Sgibbsregister OVLYSPLTSTAT0 { 86697883Sgibbs address 0x096 86797883Sgibbs access_mode RW 86897883Sgibbs modes M_SCSI 869102681Sgibbs field STAETERM 0x80 870102681Sgibbs field SCBCERR 0x40 871102681Sgibbs field SCADERR 0x20 872102681Sgibbs field SCDATBUCKET 0x10 873102681Sgibbs field CNTNOTCMPLT 0x08 874102681Sgibbs field RXOVRUN 0x04 875102681Sgibbs field RXSCEMSG 0x02 876102681Sgibbs field RXSPLTRSP 0x01 87797883Sgibbs} 87897883Sgibbs 87997883Sgibbs/* 88097883Sgibbs * Data Channel Split Status 1 88197883Sgibbs */ 88297883Sgibbsregister DCHSPLTSTAT1 { 88397883Sgibbs address 0x097 88497883Sgibbs access_mode RW 88597883Sgibbs modes M_DFF0, M_DFF1 886102681Sgibbs field RXDATABUCKET 0x01 88797883Sgibbs} 88897883Sgibbs 88997883Sgibbs/* 89097883Sgibbs * CMC Split Status 1 89197883Sgibbs */ 89297883Sgibbsregister CMCSPLTSTAT1 { 89397883Sgibbs address 0x097 89497883Sgibbs access_mode RW 89597883Sgibbs modes M_CCHAN 896102681Sgibbs field RXDATABUCKET 0x01 89797883Sgibbs} 89897883Sgibbs 89997883Sgibbs/* 90097883Sgibbs * Overlay Split Status 1 90197883Sgibbs */ 90297883Sgibbsregister OVLYSPLTSTAT1 { 90397883Sgibbs address 0x097 90497883Sgibbs access_mode RW 90597883Sgibbs modes M_SCSI 906102681Sgibbs field RXDATABUCKET 0x01 90797883Sgibbs} 90897883Sgibbs 90997883Sgibbs/* 91097883Sgibbs * S/G Receive Message 0 91197883Sgibbs */ 91297883Sgibbsregister SGRXMSG0 { 91397883Sgibbs address 0x098 91497883Sgibbs access_mode RO 91597883Sgibbs modes M_DFF0, M_DFF1 916102681Sgibbs field CDNUM 0xF8 917102681Sgibbs field CFNUM 0x07 91897883Sgibbs} 91997883Sgibbs 92097883Sgibbs/* 92197883Sgibbs * S/G Receive Message 1 92297883Sgibbs */ 92397883Sgibbsregister SGRXMSG1 { 92497883Sgibbs address 0x099 92597883Sgibbs access_mode RO 92697883Sgibbs modes M_DFF0, M_DFF1 927102681Sgibbs field CBNUM 0xFF 92897883Sgibbs} 92997883Sgibbs 93097883Sgibbs/* 93197883Sgibbs * S/G Receive Message 2 93297883Sgibbs */ 93397883Sgibbsregister SGRXMSG2 { 93497883Sgibbs address 0x09A 93597883Sgibbs access_mode RO 93697883Sgibbs modes M_DFF0, M_DFF1 937102681Sgibbs field MINDEX 0xFF 93897883Sgibbs} 93997883Sgibbs 94097883Sgibbs/* 94197883Sgibbs * S/G Receive Message 3 94297883Sgibbs */ 94397883Sgibbsregister SGRXMSG3 { 94497883Sgibbs address 0x09B 94597883Sgibbs access_mode RO 94697883Sgibbs modes M_DFF0, M_DFF1 947102681Sgibbs field MCLASS 0x0F 94897883Sgibbs} 94997883Sgibbs 95097883Sgibbs/* 95197883Sgibbs * Slave Split Out Address 0 95297883Sgibbs */ 95397883Sgibbsregister SLVSPLTOUTADR0 { 95497883Sgibbs address 0x098 95597883Sgibbs access_mode RO 95697883Sgibbs modes M_SCSI 957102681Sgibbs field LOWER_ADDR 0x7F 95897883Sgibbs} 95997883Sgibbs 96097883Sgibbs/* 96197883Sgibbs * Slave Split Out Address 1 96297883Sgibbs */ 96397883Sgibbsregister SLVSPLTOUTADR1 { 96497883Sgibbs address 0x099 96597883Sgibbs access_mode RO 96697883Sgibbs modes M_SCSI 967102681Sgibbs field REQ_DNUM 0xF8 968102681Sgibbs field REQ_FNUM 0x07 96997883Sgibbs} 97097883Sgibbs 97197883Sgibbs/* 97297883Sgibbs * Slave Split Out Address 2 97397883Sgibbs */ 97497883Sgibbsregister SLVSPLTOUTADR2 { 97597883Sgibbs address 0x09A 97697883Sgibbs access_mode RO 97797883Sgibbs modes M_SCSI 978102681Sgibbs field REQ_BNUM 0xFF 97997883Sgibbs} 98097883Sgibbs 98197883Sgibbs/* 98297883Sgibbs * Slave Split Out Address 3 98397883Sgibbs */ 98497883Sgibbsregister SLVSPLTOUTADR3 { 98597883Sgibbs address 0x09B 98697883Sgibbs access_mode RO 98797883Sgibbs modes M_SCSI 988102681Sgibbs field RLXORD 020 989102681Sgibbs field TAG_NUM 0x1F 99097883Sgibbs} 99197883Sgibbs 99297883Sgibbs/* 99397883Sgibbs * SG Sequencer Byte Count 99497883Sgibbs */ 99597883Sgibbsregister SGSEQBCNT { 99697883Sgibbs address 0x09C 99797883Sgibbs access_mode RO 99897883Sgibbs modes M_DFF0, M_DFF1 99997883Sgibbs} 100097883Sgibbs 100197883Sgibbs/* 100297883Sgibbs * Slave Split Out Attribute 0 100397883Sgibbs */ 100497883Sgibbsregister SLVSPLTOUTATTR0 { 100597883Sgibbs address 0x09C 100697883Sgibbs access_mode RO 100797883Sgibbs modes M_SCSI 1008102681Sgibbs field LOWER_BCNT 0xFF 100997883Sgibbs} 101097883Sgibbs 101197883Sgibbs/* 101297883Sgibbs * Slave Split Out Attribute 1 101397883Sgibbs */ 101497883Sgibbsregister SLVSPLTOUTATTR1 { 101597883Sgibbs address 0x09D 101697883Sgibbs access_mode RO 101797883Sgibbs modes M_SCSI 1018102681Sgibbs field CMPLT_DNUM 0xF8 1019102681Sgibbs field CMPLT_FNUM 0x07 102097883Sgibbs} 102197883Sgibbs 102297883Sgibbs/* 102397883Sgibbs * Slave Split Out Attribute 2 102497883Sgibbs */ 102597883Sgibbsregister SLVSPLTOUTATTR2 { 102697883Sgibbs address 0x09E 102797883Sgibbs access_mode RO 102897883Sgibbs size 2 102997883Sgibbs modes M_SCSI 1030102681Sgibbs field CMPLT_BNUM 0xFF 103197883Sgibbs} 103297883Sgibbs/* 103397883Sgibbs * S/G Split Status 0 103497883Sgibbs */ 103597883Sgibbsregister SGSPLTSTAT0 { 103697883Sgibbs address 0x09E 103797883Sgibbs access_mode RW 103897883Sgibbs modes M_DFF0, M_DFF1 1039102681Sgibbs field STAETERM 0x80 1040102681Sgibbs field SCBCERR 0x40 1041102681Sgibbs field SCADERR 0x20 1042102681Sgibbs field SCDATBUCKET 0x10 1043102681Sgibbs field CNTNOTCMPLT 0x08 1044102681Sgibbs field RXOVRUN 0x04 1045102681Sgibbs field RXSCEMSG 0x02 1046102681Sgibbs field RXSPLTRSP 0x01 104797883Sgibbs} 104897883Sgibbs 104997883Sgibbs/* 105097883Sgibbs * S/G Split Status 1 105197883Sgibbs */ 105297883Sgibbsregister SGSPLTSTAT1 { 105397883Sgibbs address 0x09F 105497883Sgibbs access_mode RW 105597883Sgibbs modes M_DFF0, M_DFF1 1056102681Sgibbs field RXDATABUCKET 0x01 105797883Sgibbs} 105897883Sgibbs 105997883Sgibbs/* 106097883Sgibbs * Special Function 106197883Sgibbs */ 106297883Sgibbsregister SFUNCT { 106397883Sgibbs address 0x09f 106497883Sgibbs access_mode RW 106597883Sgibbs modes M_CFG 1066102681Sgibbs field TEST_GROUP 0xF0 1067102681Sgibbs field TEST_NUM 0x0F 106897883Sgibbs} 106997883Sgibbs 107097883Sgibbs/* 107197883Sgibbs * Data FIFO 0 PCI Status 107297883Sgibbs */ 107397883Sgibbsregister DF0PCISTAT { 107497883Sgibbs address 0x0A0 107597883Sgibbs access_mode RW 107697883Sgibbs modes M_CFG 1077102681Sgibbs field DPE 0x80 1078102681Sgibbs field SSE 0x40 1079102681Sgibbs field RMA 0x20 1080102681Sgibbs field RTA 0x10 1081102681Sgibbs field SCAAPERR 0x08 1082102681Sgibbs field RDPERR 0x04 1083102681Sgibbs field TWATERR 0x02 1084102681Sgibbs field DPR 0x01 108597883Sgibbs} 108697883Sgibbs 108797883Sgibbs/* 108897883Sgibbs * Data FIFO 1 PCI Status 108997883Sgibbs */ 109097883Sgibbsregister DF1PCISTAT { 109197883Sgibbs address 0x0A1 109297883Sgibbs access_mode RW 109397883Sgibbs modes M_CFG 1094102681Sgibbs field DPE 0x80 1095102681Sgibbs field SSE 0x40 1096102681Sgibbs field RMA 0x20 1097102681Sgibbs field RTA 0x10 1098102681Sgibbs field SCAAPERR 0x08 1099102681Sgibbs field RDPERR 0x04 1100102681Sgibbs field TWATERR 0x02 1101102681Sgibbs field DPR 0x01 110297883Sgibbs} 110397883Sgibbs 110497883Sgibbs/* 110597883Sgibbs * S/G PCI Status 110697883Sgibbs */ 110797883Sgibbsregister SGPCISTAT { 110897883Sgibbs address 0x0A2 110997883Sgibbs access_mode RW 111097883Sgibbs modes M_CFG 1111102681Sgibbs field DPE 0x80 1112102681Sgibbs field SSE 0x40 1113102681Sgibbs field RMA 0x20 1114102681Sgibbs field RTA 0x10 1115102681Sgibbs field SCAAPERR 0x08 1116102681Sgibbs field RDPERR 0x04 1117102681Sgibbs field DPR 0x01 111897883Sgibbs} 111997883Sgibbs 112097883Sgibbs/* 112197883Sgibbs * CMC PCI Status 112297883Sgibbs */ 112397883Sgibbsregister CMCPCISTAT { 112497883Sgibbs address 0x0A3 112597883Sgibbs access_mode RW 112697883Sgibbs modes M_CFG 1127102681Sgibbs field DPE 0x80 1128102681Sgibbs field SSE 0x40 1129102681Sgibbs field RMA 0x20 1130102681Sgibbs field RTA 0x10 1131102681Sgibbs field SCAAPERR 0x08 1132102681Sgibbs field RDPERR 0x04 1133102681Sgibbs field TWATERR 0x02 1134102681Sgibbs field DPR 0x01 113597883Sgibbs} 113697883Sgibbs 113797883Sgibbs/* 113897883Sgibbs * Overlay PCI Status 113997883Sgibbs */ 114097883Sgibbsregister OVLYPCISTAT { 114197883Sgibbs address 0x0A4 114297883Sgibbs access_mode RW 114397883Sgibbs modes M_CFG 1144102681Sgibbs field DPE 0x80 1145102681Sgibbs field SSE 0x40 1146102681Sgibbs field RMA 0x20 1147102681Sgibbs field RTA 0x10 1148102681Sgibbs field SCAAPERR 0x08 1149102681Sgibbs field RDPERR 0x04 1150102681Sgibbs field DPR 0x01 115197883Sgibbs} 115297883Sgibbs 115397883Sgibbs/* 115497883Sgibbs * PCI Status for MSI Master DMA Transfer 115597883Sgibbs */ 115697883Sgibbsregister MSIPCISTAT { 115797883Sgibbs address 0x0A6 115897883Sgibbs access_mode RW 115997883Sgibbs modes M_CFG 1160102681Sgibbs field SSE 0x40 1161102681Sgibbs field RMA 0x20 1162102681Sgibbs field RTA 0x10 1163102681Sgibbs field CLRPENDMSI 0x08 1164102681Sgibbs field TWATERR 0x02 1165102681Sgibbs field DPR 0x01 116697883Sgibbs} 116797883Sgibbs 116897883Sgibbs/* 116997883Sgibbs * PCI Status for Target 117097883Sgibbs */ 117197883Sgibbsregister TARGPCISTAT { 1172107623Sscottl address 0x0A7 117397883Sgibbs access_mode RW 117497883Sgibbs modes M_CFG 1175102681Sgibbs field DPE 0x80 1176102681Sgibbs field SSE 0x40 1177102681Sgibbs field STA 0x08 1178102681Sgibbs field TWATERR 0x02 117997883Sgibbs} 118097883Sgibbs 118197883Sgibbs/* 118297883Sgibbs * LQ Packet In 118397883Sgibbs * The last LQ Packet recieved 118497883Sgibbs */ 118597883Sgibbsregister LQIN { 118697883Sgibbs address 0x020 118797883Sgibbs access_mode RW 118897883Sgibbs size 20 118997883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 119097883Sgibbs} 119197883Sgibbs 119297883Sgibbs/* 119397883Sgibbs * SCB Type Pointer 119497883Sgibbs * SCB offset for Target Mode SCB type information 119597883Sgibbs */ 119697883Sgibbsregister TYPEPTR { 119797883Sgibbs address 0x020 119897883Sgibbs access_mode RW 119997883Sgibbs modes M_CFG 120097883Sgibbs} 120197883Sgibbs 120297883Sgibbs/* 120397883Sgibbs * Queue Tag Pointer 120497883Sgibbs * SCB offset to the Two Byte tag identifier used for target mode. 120597883Sgibbs */ 120697883Sgibbsregister TAGPTR { 120797883Sgibbs address 0x021 120897883Sgibbs access_mode RW 120997883Sgibbs modes M_CFG 121097883Sgibbs} 121197883Sgibbs 121297883Sgibbs/* 121397883Sgibbs * Logical Unit Number Pointer 121497883Sgibbs * SCB offset to the LSB (little endian) of the lun field. 121597883Sgibbs */ 121697883Sgibbsregister LUNPTR { 121797883Sgibbs address 0x022 121897883Sgibbs access_mode RW 121997883Sgibbs modes M_CFG 122097883Sgibbs} 122197883Sgibbs 122297883Sgibbs/* 122397883Sgibbs * Data Length Pointer 122497883Sgibbs * SCB offset for the 4 byte data length field in target mode. 122597883Sgibbs */ 122697883Sgibbsregister DATALENPTR { 122797883Sgibbs address 0x023 122897883Sgibbs access_mode RW 122997883Sgibbs modes M_CFG 123097883Sgibbs} 123197883Sgibbs 123297883Sgibbs/* 123397883Sgibbs * Status Length Pointer 123497883Sgibbs * SCB offset to the two byte status field in target SCBs. 123597883Sgibbs */ 123697883Sgibbsregister STATLENPTR { 123797883Sgibbs address 0x024 123897883Sgibbs access_mode RW 123997883Sgibbs modes M_CFG 124097883Sgibbs} 124197883Sgibbs 124297883Sgibbs/* 124397883Sgibbs * Command Length Pointer 124497883Sgibbs * Scb offset for the CDB length field in initiator SCBs. 124597883Sgibbs */ 124697883Sgibbsregister CMDLENPTR { 124797883Sgibbs address 0x025 124897883Sgibbs access_mode RW 124997883Sgibbs modes M_CFG 125097883Sgibbs} 125197883Sgibbs 125297883Sgibbs/* 125397883Sgibbs * Task Attribute Pointer 125497883Sgibbs * Scb offset for the byte field specifying the attribute byte 125597883Sgibbs * to be used in command packets. 125697883Sgibbs */ 125797883Sgibbsregister ATTRPTR { 125897883Sgibbs address 0x026 125997883Sgibbs access_mode RW 126097883Sgibbs modes M_CFG 126197883Sgibbs} 126297883Sgibbs 126397883Sgibbs/* 126497883Sgibbs * Task Management Flags Pointer 126597883Sgibbs * Scb offset for the byte field specifying the attribute flags 126697883Sgibbs * byte to be used in command packets. 126797883Sgibbs */ 126897883Sgibbsregister FLAGPTR { 126997883Sgibbs address 0x027 127097883Sgibbs access_mode RW 127197883Sgibbs modes M_CFG 127297883Sgibbs} 127397883Sgibbs 127497883Sgibbs/* 127597883Sgibbs * Command Pointer 127697883Sgibbs * Scb offset for the first byte in the CDB for initiator SCBs. 127797883Sgibbs */ 127897883Sgibbsregister CMDPTR { 127997883Sgibbs address 0x028 128097883Sgibbs access_mode RW 128197883Sgibbs modes M_CFG 128297883Sgibbs} 128397883Sgibbs 128497883Sgibbs/* 128597883Sgibbs * Queue Next Pointer 128697883Sgibbs * Scb offset for the 2 byte "next scb link". 128797883Sgibbs */ 128897883Sgibbsregister QNEXTPTR { 128997883Sgibbs address 0x029 129097883Sgibbs access_mode RW 129197883Sgibbs modes M_CFG 129297883Sgibbs} 129397883Sgibbs 129497883Sgibbs/* 129597883Sgibbs * SCSI ID Pointer 129697883Sgibbs * Scb offset to the value to place in the SCSIID register 129797883Sgibbs * during target mode connections. 129897883Sgibbs */ 129997883Sgibbsregister IDPTR { 130097883Sgibbs address 0x02A 130197883Sgibbs access_mode RW 130297883Sgibbs modes M_CFG 130397883Sgibbs} 130497883Sgibbs 130597883Sgibbs/* 130697883Sgibbs * Command Aborted Byte Pointer 130797883Sgibbs * Offset to the SCB flags field that includes the 130897883Sgibbs * "SCB aborted" status bit. 130997883Sgibbs */ 131097883Sgibbsregister ABRTBYTEPTR { 131197883Sgibbs address 0x02B 131297883Sgibbs access_mode RW 131397883Sgibbs modes M_CFG 131497883Sgibbs} 131597883Sgibbs 131697883Sgibbs/* 131797883Sgibbs * Command Aborted Bit Pointer 131897883Sgibbs * Bit offset in the SCB flags field for "SCB aborted" status. 131997883Sgibbs */ 132097883Sgibbsregister ABRTBITPTR { 132197883Sgibbs address 0x02C 132297883Sgibbs access_mode RW 132397883Sgibbs modes M_CFG 132497883Sgibbs} 132597883Sgibbs 132697883Sgibbs/* 1327102681Sgibbs * Rev B or greater. 1328102681Sgibbs */ 1329102681Sgibbsregister MAXCMDBYTES { 1330102681Sgibbs address 0x02D 1331102681Sgibbs access_mode RW 1332102681Sgibbs modes M_CFG 1333102681Sgibbs} 1334102681Sgibbs 1335102681Sgibbs/* 1336102681Sgibbs * Rev B or greater. 1337102681Sgibbs */ 1338102681Sgibbsregister MAXCMD2RCV { 1339102681Sgibbs address 0x02E 1340102681Sgibbs access_mode RW 1341102681Sgibbs modes M_CFG 1342102681Sgibbs} 1343102681Sgibbs 1344102681Sgibbs/* 1345102681Sgibbs * Rev B or greater. 1346102681Sgibbs */ 1347102681Sgibbsregister SHORTTHRESH { 1348102681Sgibbs address 0x02F 1349102681Sgibbs access_mode RW 1350102681Sgibbs modes M_CFG 1351102681Sgibbs} 1352102681Sgibbs 1353102681Sgibbs/* 135497883Sgibbs * Logical Unit Number Length 135597883Sgibbs * The length, in bytes, of the SCB lun field. 135697883Sgibbs */ 135797883Sgibbsregister LUNLEN { 135897883Sgibbs address 0x030 135997883Sgibbs access_mode RW 136097883Sgibbs modes M_CFG 136197883Sgibbs} 136297883Sgibbs 136397883Sgibbs/* 136497883Sgibbs * CDB Limit 136597883Sgibbs * The size, in bytes, of the embedded CDB field in initator SCBs. 136697883Sgibbs */ 136797883Sgibbsregister CDBLIMIT { 136897883Sgibbs address 0x031 136997883Sgibbs access_mode RW 137097883Sgibbs modes M_CFG 137197883Sgibbs} 137297883Sgibbs 137397883Sgibbs/* 137497883Sgibbs * Maximum Commands 137597883Sgibbs * The maximum number of commands to issue during a 137697883Sgibbs * single packetized connection. 137797883Sgibbs */ 137897883Sgibbsregister MAXCMD { 137997883Sgibbs address 0x032 138097883Sgibbs access_mode RW 138197883Sgibbs modes M_CFG 138297883Sgibbs} 138397883Sgibbs 138497883Sgibbs/* 138597883Sgibbs * Maximum Command Counter 138697883Sgibbs * The number of commands already sent during this connection 138797883Sgibbs */ 138897883Sgibbsregister MAXCMDCNT { 138997883Sgibbs address 0x033 139097883Sgibbs access_mode RW 139197883Sgibbs modes M_CFG 139297883Sgibbs} 139397883Sgibbs 139497883Sgibbs/* 139597883Sgibbs * LQ Packet Reserved Bytes 139697883Sgibbs * The bytes to be sent in the currently reserved fileds 139797883Sgibbs * of all LQ packets. 139897883Sgibbs */ 139997883Sgibbsregister LQRSVD01 { 140097883Sgibbs address 0x034 140197883Sgibbs access_mode RW 140297883Sgibbs modes M_SCSI 140397883Sgibbs} 140497883Sgibbsregister LQRSVD16 { 140597883Sgibbs address 0x035 140697883Sgibbs access_mode RW 140797883Sgibbs modes M_SCSI 140897883Sgibbs} 140997883Sgibbsregister LQRSVD17 { 141097883Sgibbs address 0x036 141197883Sgibbs access_mode RW 141297883Sgibbs modes M_SCSI 141397883Sgibbs} 141497883Sgibbs 141597883Sgibbs/* 141697883Sgibbs * Command Reserved 0 141797883Sgibbs * The byte to be sent for the reserved byte 0 of 141897883Sgibbs * outgoing command packets. 141997883Sgibbs */ 142097883Sgibbsregister CMDRSVD0 { 142197883Sgibbs address 0x037 142297883Sgibbs access_mode RW 142397883Sgibbs modes M_CFG 142497883Sgibbs} 142597883Sgibbs 142697883Sgibbs/* 142797883Sgibbs * LQ Manager Control 0 142897883Sgibbs */ 142997883Sgibbsregister LQCTL0 { 143097883Sgibbs address 0x038 143197883Sgibbs access_mode RW 143297883Sgibbs modes M_CFG 1433102681Sgibbs field LQITARGCLT 0xC0 1434102681Sgibbs field LQIINITGCLT 0x30 1435102681Sgibbs field LQ0TARGCLT 0x0C 1436102681Sgibbs field LQ0INITGCLT 0x03 143797883Sgibbs} 143897883Sgibbs 143997883Sgibbs/* 144097883Sgibbs * LQ Manager Control 1 144197883Sgibbs */ 144297883Sgibbsregister LQCTL1 { 144397883Sgibbs address 0x038 144497883Sgibbs access_mode RW 144597883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1446102681Sgibbs field PCI2PCI 0x04 1447102681Sgibbs field SINGLECMD 0x02 1448102681Sgibbs field ABORTPENDING 0x01 144997883Sgibbs} 145097883Sgibbs 145197883Sgibbs/* 145297883Sgibbs * LQ Manager Control 2 145397883Sgibbs */ 145497883Sgibbsregister LQCTL2 { 145597883Sgibbs address 0x039 145697883Sgibbs access_mode RW 145797883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1458102681Sgibbs field LQIRETRY 0x80 1459102681Sgibbs field LQICONTINUE 0x40 1460102681Sgibbs field LQITOIDLE 0x20 1461102681Sgibbs field LQIPAUSE 0x10 1462102681Sgibbs field LQORETRY 0x08 1463102681Sgibbs field LQOCONTINUE 0x04 1464102681Sgibbs field LQOTOIDLE 0x02 1465102681Sgibbs field LQOPAUSE 0x01 146697883Sgibbs} 146797883Sgibbs 146897883Sgibbs/* 146997883Sgibbs * SCSI RAM BIST0 147097883Sgibbs */ 147197883Sgibbsregister SCSBIST0 { 147297883Sgibbs address 0x039 147397883Sgibbs access_mode RW 147497883Sgibbs modes M_CFG 1475102681Sgibbs field GSBISTERR 0x40 1476102681Sgibbs field GSBISTDONE 0x20 1477102681Sgibbs field GSBISTRUN 0x10 1478102681Sgibbs field OSBISTERR 0x04 1479102681Sgibbs field OSBISTDONE 0x02 1480102681Sgibbs field OSBISTRUN 0x01 148197883Sgibbs} 148297883Sgibbs 148397883Sgibbs/* 148497883Sgibbs * SCSI Sequence Control0 148597883Sgibbs */ 148697883Sgibbsregister SCSISEQ0 { 148797883Sgibbs address 0x03A 148897883Sgibbs access_mode RW 148997883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1490102681Sgibbs field TEMODEO 0x80 1491102681Sgibbs field ENSELO 0x40 1492102681Sgibbs field ENARBO 0x20 1493102681Sgibbs field FORCEBUSFREE 0x10 1494102681Sgibbs field SCSIRSTO 0x01 149597883Sgibbs} 149697883Sgibbs 149797883Sgibbs/* 149897883Sgibbs * SCSI RAM BIST 1 149997883Sgibbs */ 150097883Sgibbsregister SCSBIST1 { 150197883Sgibbs address 0x03A 150297883Sgibbs access_mode RW 150397883Sgibbs modes M_CFG 1504102681Sgibbs field NTBISTERR 0x04 1505102681Sgibbs field NTBISTDONE 0x02 1506102681Sgibbs field NTBISTRUN 0x01 150797883Sgibbs} 150897883Sgibbs 150997883Sgibbs/* 151097883Sgibbs * SCSI Sequence Control 1 151197883Sgibbs */ 151297883Sgibbsregister SCSISEQ1 { 151397883Sgibbs address 0x03B 151497883Sgibbs access_mode RW 151597883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1516102681Sgibbs field MANUALCTL 0x40 1517102681Sgibbs field ENSELI 0x20 1518102681Sgibbs field ENRSELI 0x10 1519102681Sgibbs field MANUALP 0x0C 1520102681Sgibbs field ENAUTOATNP 0x02 1521102681Sgibbs field ALTSTIM 0x01 152297883Sgibbs} 152397883Sgibbs 152497883Sgibbs/* 152597883Sgibbs * SCSI Transfer Control 0 152697883Sgibbs */ 152797883Sgibbsregister SXFRCTL0 { 152897883Sgibbs address 0x03C 152997883Sgibbs access_mode RW 153097883Sgibbs modes M_SCSI 1531102681Sgibbs field DFON 0x80 1532102681Sgibbs field DFPEXP 0x40 1533102681Sgibbs field BIOSCANCELEN 0x10 1534102681Sgibbs field SPIOEN 0x08 153597883Sgibbs} 153697883Sgibbs 153797883Sgibbs/* 153897883Sgibbs * SCSI Transfer Control 1 153997883Sgibbs */ 154097883Sgibbsregister SXFRCTL1 { 154197883Sgibbs address 0x03D 154297883Sgibbs access_mode RW 154397883Sgibbs modes M_SCSI 1544102681Sgibbs field BITBUCKET 0x80 1545102681Sgibbs field ENSACHK 0x40 1546102681Sgibbs field ENSPCHK 0x20 1547102681Sgibbs field STIMESEL 0x18 1548102681Sgibbs field ENSTIMER 0x04 1549102681Sgibbs field ACTNEGEN 0x02 1550102681Sgibbs field STPWEN 0x01 155197883Sgibbs} 155297883Sgibbs 155397883Sgibbs/* 155497883Sgibbs * SCSI Transfer Control 2 155597883Sgibbs */ 155697883Sgibbsregister SXFRCTL2 { 155797883Sgibbs address 0x03E 155897883Sgibbs access_mode RW 155997883Sgibbs modes M_SCSI 1560102681Sgibbs field AUTORSTDIS 0x10 1561102681Sgibbs field CMDDMAEN 0x08 1562102681Sgibbs field ASU 0x07 156397883Sgibbs} 156497883Sgibbs 156597883Sgibbs/* 156697883Sgibbs * SCSI Bus Initiator IDs 156797883Sgibbs * Bitmask of observed initiators on the bus. 156897883Sgibbs */ 156997883Sgibbsregister BUSINITID { 157097883Sgibbs address 0x03C 157197883Sgibbs access_mode RW 157297883Sgibbs modes M_CFG 157397883Sgibbs size 2 157497883Sgibbs} 157597883Sgibbs 157697883Sgibbs/* 157797883Sgibbs * Data Length Counters 157897883Sgibbs * Packet byte counter. 157997883Sgibbs */ 158097883Sgibbsregister DLCOUNT { 158197883Sgibbs address 0x03C 158297883Sgibbs access_mode RW 158397883Sgibbs modes M_DFF0, M_DFF1 158497883Sgibbs size 3 158597883Sgibbs} 158697883Sgibbs 158797883Sgibbs/* 158897883Sgibbs * Data FIFO Status 158997883Sgibbs */ 159097883Sgibbsregister DFFSTAT { 159197883Sgibbs address 0x03F 159297883Sgibbs access_mode RW 159397883Sgibbs modes M_SCSI 1594102681Sgibbs field FIFO1FREE 0x20 1595102681Sgibbs field FIFO0FREE 0x10 1596107441Sscottl /* 1597107441Sscottl * On the B, this enum only works 1598107441Sscottl * in the read direction. For writes, 1599107441Sscottl * you must use the B version of the 1600107441Sscottl * CURRFIFO_0 definition which is defined 1601107441Sscottl * as a constant outside of this register 1602107441Sscottl * definition to avoid confusing the 1603107441Sscottl * register pretty printing code. 1604107441Sscottl */ 1605107441Sscottl enum CURRFIFO 0x03 { 1606107441Sscottl CURRFIFO_0, 1607107441Sscottl CURRFIFO_1, 1608107441Sscottl CURRFIFO_NONE 0x3 1609107441Sscottl } 161097883Sgibbs} 161197883Sgibbs 1612107441Sscottlconst B_CURRFIFO_0 0x2 1613107441Sscottl 161497883Sgibbs/* 161597883Sgibbs * SCSI Bus Target IDs 161697883Sgibbs * Bitmask of observed targets on the bus. 161797883Sgibbs */ 161897883Sgibbsregister BUSTARGID { 161997883Sgibbs address 0x03E 162097883Sgibbs access_mode RW 162197883Sgibbs modes M_CFG 162297883Sgibbs size 2 162397883Sgibbs} 162497883Sgibbs 162597883Sgibbs/* 162697883Sgibbs * SCSI Control Signal Out 162797883Sgibbs */ 162897883Sgibbsregister SCSISIGO { 162997883Sgibbs address 0x040 163097883Sgibbs access_mode RW 163197883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1632102681Sgibbs field CDO 0x80 1633102681Sgibbs field IOO 0x40 1634102681Sgibbs field MSGO 0x20 1635102681Sgibbs field ATNO 0x10 1636102681Sgibbs field SELO 0x08 1637102681Sgibbs field BSYO 0x04 1638102681Sgibbs field REQO 0x02 1639102681Sgibbs field ACKO 0x01 164097883Sgibbs/* 164197883Sgibbs * Possible phases to write into SCSISIG0 164297883Sgibbs */ 1643102681Sgibbs enum PHASE_MASK CDO|IOO|MSGO { 1644102681Sgibbs P_DATAOUT 0x0, 1645102681Sgibbs P_DATAIN IOO, 1646102681Sgibbs P_DATAOUT_DT P_DATAOUT|MSGO, 1647102681Sgibbs P_DATAIN_DT P_DATAIN|MSGO, 1648102681Sgibbs P_COMMAND CDO, 1649102681Sgibbs P_MESGOUT CDO|MSGO, 1650102681Sgibbs P_STATUS CDO|IOO, 1651102681Sgibbs P_MESGIN CDO|IOO|MSGO 1652102681Sgibbs } 165397883Sgibbs} 165497883Sgibbs 165597883Sgibbsregister SCSISIGI { 165697883Sgibbs address 0x041 165797883Sgibbs access_mode RO 165897883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1659102681Sgibbs field CDI 0x80 1660102681Sgibbs field IOI 0x40 1661102681Sgibbs field MSGI 0x20 1662102681Sgibbs field ATNI 0x10 1663102681Sgibbs field SELI 0x08 1664102681Sgibbs field BSYI 0x04 1665102681Sgibbs field REQI 0x02 1666102681Sgibbs field ACKI 0x01 166797883Sgibbs/* 166897883Sgibbs * Possible phases in SCSISIGI 166997883Sgibbs */ 1670102681Sgibbs enum PHASE_MASK CDO|IOO|MSGO { 1671102681Sgibbs P_DATAOUT 0x0, 1672102681Sgibbs P_DATAIN IOO, 1673102681Sgibbs P_DATAOUT_DT P_DATAOUT|MSGO, 1674102681Sgibbs P_DATAIN_DT P_DATAIN|MSGO, 1675102681Sgibbs P_COMMAND CDO, 1676102681Sgibbs P_MESGOUT CDO|MSGO, 1677102681Sgibbs P_STATUS CDO|IOO, 1678102681Sgibbs P_MESGIN CDO|IOO|MSGO 1679102681Sgibbs } 168097883Sgibbs} 168197883Sgibbs 168297883Sgibbs/* 168397883Sgibbs * Multiple Target IDs 168497883Sgibbs * Bitmask of ids to respond as a target. 168597883Sgibbs */ 168697883Sgibbsregister MULTARGID { 168797883Sgibbs address 0x040 168897883Sgibbs access_mode RW 168997883Sgibbs modes M_CFG 169097883Sgibbs size 2 169197883Sgibbs} 169297883Sgibbs 169397883Sgibbs/* 169497883Sgibbs * SCSI Phase 169597883Sgibbs */ 169697883Sgibbsregister SCSIPHASE { 169797883Sgibbs address 0x042 169897883Sgibbs access_mode RO 169997883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1700102681Sgibbs field STATUS_PHASE 0x20 1701102681Sgibbs field COMMAND_PHASE 0x10 1702102681Sgibbs field MSG_IN_PHASE 0x08 1703102681Sgibbs field MSG_OUT_PHASE 0x04 1704102681Sgibbs field DATA_PHASE_MASK 0x03 { 1705102681Sgibbs DATA_OUT_PHASE 0x01, 1706102681Sgibbs DATA_IN_PHASE 0x02 1707102681Sgibbs } 170897883Sgibbs} 170997883Sgibbs 171097883Sgibbs/* 171197883Sgibbs * SCSI Data 0 Image 171297883Sgibbs */ 171397883Sgibbsregister SCSIDAT0_IMG { 171497883Sgibbs address 0x043 171597883Sgibbs access_mode RW 171697883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 171797883Sgibbs} 171897883Sgibbs 171997883Sgibbs/* 172097883Sgibbs * SCSI Latched Data 172197883Sgibbs */ 172297883Sgibbsregister SCSIDAT { 172397883Sgibbs address 0x044 172497883Sgibbs access_mode RW 172597883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 172697883Sgibbs size 2 172797883Sgibbs} 172897883Sgibbs 172997883Sgibbs/* 173097883Sgibbs * SCSI Data Bus 173197883Sgibbs */ 173297883Sgibbsregister SCSIBUS { 173397883Sgibbs address 0x046 173497883Sgibbs access_mode RW 173597883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 173697883Sgibbs size 2 173797883Sgibbs} 173897883Sgibbs 173997883Sgibbs/* 174097883Sgibbs * Target ID In 174197883Sgibbs */ 174297883Sgibbsregister TARGIDIN { 174397883Sgibbs address 0x048 174497883Sgibbs access_mode RO 174597883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1746102681Sgibbs field CLKOUT 0x80 1747102681Sgibbs field TARGID 0x0F 174897883Sgibbs} 174997883Sgibbs 175097883Sgibbs/* 175197883Sgibbs * Selection/Reselection ID 175297883Sgibbs * Upper four bits are the device id. The ONEBIT is set when the re/selecting 175397883Sgibbs * device did not set its own ID. 175497883Sgibbs */ 175597883Sgibbsregister SELID { 175697883Sgibbs address 0x049 175797883Sgibbs access_mode RW 175897883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1759102681Sgibbs field SELID_MASK 0xf0 1760102681Sgibbs field ONEBIT 0x08 176197883Sgibbs} 176297883Sgibbs 176397883Sgibbs/* 176497883Sgibbs * SCSI Block Control 176597883Sgibbs * Controls Bus type and channel selection. SELWIDE allows for the 176697883Sgibbs * coexistence of 8bit and 16bit devices on a wide bus. 176797883Sgibbs */ 176897883Sgibbsregister SBLKCTL { 176997883Sgibbs address 0x04A 177097883Sgibbs access_mode RW 177197883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1772102681Sgibbs field DIAGLEDEN 0x80 1773102681Sgibbs field DIAGLEDON 0x40 1774102681Sgibbs field ENAB40 0x08 /* LVD transceiver active */ 1775102681Sgibbs field ENAB20 0x04 /* SE/HVD transceiver active */ 1776102681Sgibbs field SELWIDE 0x02 177797883Sgibbs} 177897883Sgibbs 177997883Sgibbs/* 178097883Sgibbs * Option Mode 178197883Sgibbs */ 178297883Sgibbsregister OPTIONMODE { 178397883Sgibbs address 0x04A 178497883Sgibbs access_mode RW 178597883Sgibbs modes M_CFG 1786102681Sgibbs field BIOSCANCTL 0x80 1787102681Sgibbs field AUTOACKEN 0x40 1788102681Sgibbs field BIASCANCTL 0x20 1789102681Sgibbs field BUSFREEREV 0x10 1790102681Sgibbs field ENDGFORMCHK 0x04 1791102681Sgibbs field AUTO_MSGOUT_DE 0x02 179297883Sgibbs mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE 179397883Sgibbs} 179497883Sgibbs 179597883Sgibbs/* 179697883Sgibbs * SCSI Status 0 179797883Sgibbs */ 179897883Sgibbsregister SSTAT0 { 179997883Sgibbs address 0x04B 180097883Sgibbs access_mode RO 180197883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1802102681Sgibbs field TARGET 0x80 /* Board acting as target */ 1803102681Sgibbs field SELDO 0x40 /* Selection Done */ 1804102681Sgibbs field SELDI 0x20 /* Board has been selected */ 1805102681Sgibbs field SELINGO 0x10 /* Selection In Progress */ 1806102681Sgibbs field IOERR 0x08 /* LVD Tranceiver mode changed */ 1807102681Sgibbs field OVERRUN 0x04 /* SCSI Offset overrun detected */ 1808102681Sgibbs field SPIORDY 0x02 /* SCSI PIO Ready */ 1809102681Sgibbs field ARBDO 0x01 /* Arbitration Done Out */ 181097883Sgibbs} 181197883Sgibbs 181297883Sgibbs/* 181397883Sgibbs * Clear SCSI Interrupt 0 181497883Sgibbs * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 181597883Sgibbs */ 181697883Sgibbsregister CLRSINT0 { 181797883Sgibbs address 0x04B 181897883Sgibbs access_mode WO 181997883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1820102681Sgibbs field CLRSELDO 0x40 1821102681Sgibbs field CLRSELDI 0x20 1822102681Sgibbs field CLRSELINGO 0x10 1823102681Sgibbs field CLRIOERR 0x08 1824102681Sgibbs field CLROVERRUN 0x04 1825102681Sgibbs field CLRSPIORDY 0x02 1826102681Sgibbs field CLRARBDO 0x01 182797883Sgibbs} 182897883Sgibbs 182997883Sgibbs/* 183097883Sgibbs * SCSI Interrupt Mode 0 183197883Sgibbs * Setting any bit will enable the corresponding function 183297883Sgibbs * in SIMODE0 to interrupt via the IRQ pin. 183397883Sgibbs */ 183497883Sgibbsregister SIMODE0 { 183597883Sgibbs address 0x04B 183697883Sgibbs access_mode RW 183797883Sgibbs modes M_CFG 1838102681Sgibbs field ENSELDO 0x40 1839102681Sgibbs field ENSELDI 0x20 1840102681Sgibbs field ENSELINGO 0x10 1841102681Sgibbs field ENIOERR 0x08 1842102681Sgibbs field ENOVERRUN 0x04 1843102681Sgibbs field ENSPIORDY 0x02 1844102681Sgibbs field ENARBDO 0x01 184597883Sgibbs} 184697883Sgibbs 184797883Sgibbs/* 184897883Sgibbs * SCSI Status 1 184997883Sgibbs */ 185097883Sgibbsregister SSTAT1 { 185197883Sgibbs address 0x04C 185297883Sgibbs access_mode RO 185397883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1854102681Sgibbs field SELTO 0x80 1855102681Sgibbs field ATNTARG 0x40 1856102681Sgibbs field SCSIRSTI 0x20 1857102681Sgibbs field PHASEMIS 0x10 1858102681Sgibbs field BUSFREE 0x08 1859102681Sgibbs field SCSIPERR 0x04 1860102681Sgibbs field STRB2FAST 0x02 1861102681Sgibbs field REQINIT 0x01 186297883Sgibbs} 186397883Sgibbs 186497883Sgibbs/* 186597883Sgibbs * Clear SCSI Interrupt 1 186697883Sgibbs * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 186797883Sgibbs */ 186897883Sgibbsregister CLRSINT1 { 1869104023Sgibbs address 0x04C 187097883Sgibbs access_mode WO 187197883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1872102681Sgibbs field CLRSELTIMEO 0x80 1873102681Sgibbs field CLRATNO 0x40 1874102681Sgibbs field CLRSCSIRSTI 0x20 1875102681Sgibbs field CLRBUSFREE 0x08 1876102681Sgibbs field CLRSCSIPERR 0x04 1877102681Sgibbs field CLRSTRB2FAST 0x02 1878102681Sgibbs field CLRREQINIT 0x01 187997883Sgibbs} 188097883Sgibbs 188197883Sgibbs/* 188297883Sgibbs * SCSI Status 2 188397883Sgibbs */ 188497883Sgibbsregister SSTAT2 { 188597883Sgibbs address 0x04d 188697883Sgibbs access_mode RO 188797883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1888102681Sgibbs field BUSFREETIME 0xc0 { 1889102681Sgibbs BUSFREE_LQO 0x40, 1890102681Sgibbs BUSFREE_DFF0 0x80, 1891102681Sgibbs BUSFREE_DFF1 0xC0 1892102681Sgibbs } 1893102681Sgibbs field NONPACKREQ 0x20 1894102681Sgibbs field EXP_ACTIVE 0x10 /* SCSI Expander Active */ 1895102681Sgibbs field BSYX 0x08 /* Busy Expander */ 1896102681Sgibbs field WIDE_RES 0x04 /* Modes 0 and 1 only */ 1897102681Sgibbs field SDONE 0x02 /* Modes 0 and 1 only */ 1898102681Sgibbs field DMADONE 0x01 /* Modes 0 and 1 only */ 189997883Sgibbs} 190097883Sgibbs 190197883Sgibbs/* 190297883Sgibbs * Clear SCSI Interrupt 2 190397883Sgibbs */ 190497883Sgibbsregister CLRSINT2 { 190597883Sgibbs address 0x04D 190697883Sgibbs access_mode WO 190797883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1908102681Sgibbs field CLRNONPACKREQ 0x20 1909102681Sgibbs field CLRWIDE_RES 0x04 /* Modes 0 and 1 only */ 1910102681Sgibbs field CLRSDONE 0x02 /* Modes 0 and 1 only */ 1911102681Sgibbs field CLRDMADONE 0x01 /* Modes 0 and 1 only */ 191297883Sgibbs} 191397883Sgibbs 191497883Sgibbs/* 191597883Sgibbs * SCSI Interrupt Mode 2 191697883Sgibbs */ 191797883Sgibbsregister SIMODE2 { 191897883Sgibbs address 0x04D 191997883Sgibbs access_mode RW 192097883Sgibbs modes M_CFG 1921102681Sgibbs field ENWIDE_RES 0x04 1922102681Sgibbs field ENSDONE 0x02 1923102681Sgibbs field ENDMADONE 0x01 192497883Sgibbs} 192597883Sgibbs 192697883Sgibbs/* 192797883Sgibbs * Physical Error Diagnosis 192897883Sgibbs */ 192997883Sgibbsregister PERRDIAG { 193097883Sgibbs address 0x04E 193197883Sgibbs access_mode RO 193297883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1933102681Sgibbs field HIZERO 0x80 1934102681Sgibbs field HIPERR 0x40 1935102681Sgibbs field PREVPHASE 0x20 1936102681Sgibbs field PARITYERR 0x10 1937102681Sgibbs field AIPERR 0x08 1938102681Sgibbs field CRCERR 0x04 1939102681Sgibbs field DGFORMERR 0x02 1940102681Sgibbs field DTERR 0x01 194197883Sgibbs} 194297883Sgibbs 194397883Sgibbs/* 194497883Sgibbs * LQI Manager Current State 194597883Sgibbs */ 194697883Sgibbsregister LQISTATE { 194797883Sgibbs address 0x04E 194897883Sgibbs access_mode RO 194997883Sgibbs modes M_CFG 195097883Sgibbs} 195197883Sgibbs 195297883Sgibbs/* 195397883Sgibbs * SCSI Offset Count 195497883Sgibbs */ 195597883Sgibbsregister SOFFCNT { 195697883Sgibbs address 0x04F 195797883Sgibbs access_mode RO 195897883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 195997883Sgibbs} 196097883Sgibbs 196197883Sgibbs/* 196297883Sgibbs * LQO Manager Current State 196397883Sgibbs */ 196497883Sgibbsregister LQOSTATE { 196597883Sgibbs address 0x04F 196697883Sgibbs access_mode RO 196797883Sgibbs modes M_CFG 196897883Sgibbs} 196997883Sgibbs 197097883Sgibbs/* 197197883Sgibbs * LQI Manager Status 197297883Sgibbs */ 197397883Sgibbsregister LQISTAT0 { 197497883Sgibbs address 0x050 197597883Sgibbs access_mode RO 197697883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1977102681Sgibbs field LQIATNQAS 0x20 1978102681Sgibbs field LQICRCT1 0x10 1979102681Sgibbs field LQICRCT2 0x08 1980102681Sgibbs field LQIBADLQT 0x04 1981102681Sgibbs field LQIATNLQ 0x02 1982102681Sgibbs field LQIATNCMD 0x01 198397883Sgibbs} 198497883Sgibbs 198597883Sgibbs/* 198697883Sgibbs * Clear LQI Interrupts 0 198797883Sgibbs */ 1988102681Sgibbsregister CLRLQIINT0 { 198997883Sgibbs address 0x050 199097883Sgibbs access_mode WO 199197883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1992102681Sgibbs field CLRLQIATNQAS 0x20 1993102681Sgibbs field CLRLQICRCT1 0x10 1994102681Sgibbs field CLRLQICRCT2 0x08 1995102681Sgibbs field CLRLQIBADLQT 0x04 1996102681Sgibbs field CLRLQIATNLQ 0x02 1997102681Sgibbs field CLRLQIATNCMD 0x01 199897883Sgibbs} 199997883Sgibbs 200097883Sgibbs/* 200197883Sgibbs * LQI Manager Interrupt Mode 0 200297883Sgibbs */ 200397883Sgibbsregister LQIMODE0 { 200497883Sgibbs address 0x050 200597883Sgibbs access_mode RW 200697883Sgibbs modes M_CFG 2007102681Sgibbs field ENLQIATNQASK 0x20 2008102681Sgibbs field ENLQICRCT1 0x10 2009102681Sgibbs field ENLQICRCT2 0x08 2010102681Sgibbs field ENLQIBADLQT 0x04 2011102681Sgibbs field ENLQIATNLQ 0x02 2012102681Sgibbs field ENLQIATNCMD 0x01 201397883Sgibbs} 201497883Sgibbs 201597883Sgibbs/* 201697883Sgibbs * LQI Manager Status 1 201797883Sgibbs */ 201897883Sgibbsregister LQISTAT1 { 201997883Sgibbs address 0x051 202097883Sgibbs access_mode RO 202197883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2022102681Sgibbs field LQIPHASE_LQ 0x80 2023102681Sgibbs field LQIPHASE_NLQ 0x40 2024102681Sgibbs field LQIABORT 0x20 2025102681Sgibbs field LQICRCI_LQ 0x10 2026102681Sgibbs field LQICRCI_NLQ 0x08 2027102681Sgibbs field LQIBADLQI 0x04 2028102681Sgibbs field LQIOVERI_LQ 0x02 2029102681Sgibbs field LQIOVERI_NLQ 0x01 203097883Sgibbs} 203197883Sgibbs 203297883Sgibbs/* 203397883Sgibbs * Clear LQI Manager Interrupts1 203497883Sgibbs */ 203597883Sgibbsregister CLRLQIINT1 { 203697883Sgibbs address 0x051 203797883Sgibbs access_mode WO 203897883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2039102681Sgibbs field CLRLQIPHASE_LQ 0x80 2040102681Sgibbs field CLRLQIPHASE_NLQ 0x40 2041102681Sgibbs field CLRLIQABORT 0x20 2042102681Sgibbs field CLRLQICRCI_LQ 0x10 2043102681Sgibbs field CLRLQICRCI_NLQ 0x08 2044102681Sgibbs field CLRLQIBADLQI 0x04 2045102681Sgibbs field CLRLQIOVERI_LQ 0x02 2046102681Sgibbs field CLRLQIOVERI_NLQ 0x01 204797883Sgibbs} 204897883Sgibbs 204997883Sgibbs/* 205097883Sgibbs * LQI Manager Interrupt Mode 1 205197883Sgibbs */ 205297883Sgibbsregister LQIMODE1 { 205397883Sgibbs address 0x051 205497883Sgibbs access_mode RW 205597883Sgibbs modes M_CFG 2056102681Sgibbs field ENLQIPHASE_LQ 0x80 2057102681Sgibbs field ENLQIPHASE_NLQ 0x40 2058102681Sgibbs field ENLIQABORT 0x20 2059102681Sgibbs field ENLQICRCI_LQ 0x10 2060102681Sgibbs field ENLQICRCI_NLQ 0x08 2061102681Sgibbs field ENLQIBADLQI 0x04 2062102681Sgibbs field ENLQIOVERI_LQ 0x02 2063102681Sgibbs field ENLQIOVERI_NLQ 0x01 206497883Sgibbs} 206597883Sgibbs 206697883Sgibbs/* 206797883Sgibbs * LQI Manager Status 2 206897883Sgibbs */ 206997883Sgibbsregister LQISTAT2 { 207097883Sgibbs address 0x052 207197883Sgibbs access_mode RO 207297883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2073102681Sgibbs field PACKETIZED 0x80 2074102681Sgibbs field LQIPHASE_OUTPKT 0x40 2075102681Sgibbs field LQIWORKONLQ 0x20 2076102681Sgibbs field LQIWAITFIFO 0x10 2077102681Sgibbs field LQISTOPPKT 0x08 2078102681Sgibbs field LQISTOPLQ 0x04 2079102681Sgibbs field LQISTOPCMD 0x02 2080102681Sgibbs field LQIGSAVAIL 0x01 208197883Sgibbs} 208297883Sgibbs 208397883Sgibbs/* 208497883Sgibbs * SCSI Status 3 208597883Sgibbs */ 208697883Sgibbsregister SSTAT3 { 208797883Sgibbs address 0x053 208897883Sgibbs access_mode RO 208997883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2090102681Sgibbs field NTRAMPERR 0x02 2091102681Sgibbs field OSRAMPERR 0x01 209297883Sgibbs} 209397883Sgibbs 209497883Sgibbs/* 209597883Sgibbs * Clear SCSI Status 3 209697883Sgibbs */ 209797883Sgibbsregister CLRSINT3 { 209897883Sgibbs address 0x053 209997883Sgibbs access_mode WO 210097883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2101102681Sgibbs field CLRNTRAMPERR 0x02 2102102681Sgibbs field CLROSRAMPERR 0x01 210397883Sgibbs} 210497883Sgibbs 210597883Sgibbs/* 210697883Sgibbs * SCSI Interrupt Mode 3 210797883Sgibbs */ 210897883Sgibbsregister SIMODE3 { 210997883Sgibbs address 0x053 211097883Sgibbs access_mode RW 211197883Sgibbs modes M_CFG 2112102681Sgibbs field ENNTRAMPERR 0x02 2113102681Sgibbs field ENOSRAMPERR 0x01 211497883Sgibbs} 211597883Sgibbs 211697883Sgibbs/* 211797883Sgibbs * LQO Manager Status 0 211897883Sgibbs */ 211997883Sgibbsregister LQOSTAT0 { 212097883Sgibbs address 0x054 212197883Sgibbs access_mode RO 212297883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2123102681Sgibbs field LQOTARGSCBPERR 0x10 2124102681Sgibbs field LQOSTOPT2 0x08 2125102681Sgibbs field LQOATNLQ 0x04 2126102681Sgibbs field LQOATNPKT 0x02 2127102681Sgibbs field LQOTCRC 0x01 212897883Sgibbs} 212997883Sgibbs 213097883Sgibbs/* 213197883Sgibbs * Clear LQO Manager interrupt 0 213297883Sgibbs */ 213397883Sgibbsregister CLRLQOINT0 { 213497883Sgibbs address 0x054 213597883Sgibbs access_mode WO 213697883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2137102681Sgibbs field CLRLQOTARGSCBPERR 0x10 2138102681Sgibbs field CLRLQOSTOPT2 0x08 2139102681Sgibbs field CLRLQOATNLQ 0x04 2140102681Sgibbs field CLRLQOATNPKT 0x02 2141102681Sgibbs field CLRLQOTCRC 0x01 214297883Sgibbs} 214397883Sgibbs 214497883Sgibbs/* 214597883Sgibbs * LQO Manager Interrupt Mode 0 214697883Sgibbs */ 214797883Sgibbsregister LQOMODE0 { 214897883Sgibbs address 0x054 214997883Sgibbs access_mode RW 215097883Sgibbs modes M_CFG 2151102681Sgibbs field ENLQOTARGSCBPERR 0x10 2152102681Sgibbs field ENLQOSTOPT2 0x08 2153102681Sgibbs field ENLQOATNLQ 0x04 2154102681Sgibbs field ENLQOATNPKT 0x02 2155102681Sgibbs field ENLQOTCRC 0x01 215697883Sgibbs} 215797883Sgibbs 215897883Sgibbs/* 215997883Sgibbs * LQO Manager Status 1 216097883Sgibbs */ 216197883Sgibbsregister LQOSTAT1 { 216297883Sgibbs address 0x055 216397883Sgibbs access_mode RO 216497883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2165102681Sgibbs field LQOINITSCBPERR 0x10 2166102681Sgibbs field LQOSTOPI2 0x08 2167102681Sgibbs field LQOBADQAS 0x04 2168102681Sgibbs field LQOBUSFREE 0x02 2169102681Sgibbs field LQOPHACHGINPKT 0x01 217097883Sgibbs} 217197883Sgibbs 217297883Sgibbs/* 217397883Sgibbs * Clear LOQ Interrupt 1 217497883Sgibbs */ 217597883Sgibbsregister CLRLQOINT1 { 217697883Sgibbs address 0x055 217797883Sgibbs access_mode WO 217897883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2179102681Sgibbs field CLRLQOINITSCBPERR 0x10 2180102681Sgibbs field CLRLQOSTOPI2 0x08 2181102681Sgibbs field CLRLQOBADQAS 0x04 2182102681Sgibbs field CLRLQOBUSFREE 0x02 2183102681Sgibbs field CLRLQOPHACHGINPKT 0x01 218497883Sgibbs} 218597883Sgibbs 218697883Sgibbs/* 218797883Sgibbs * LQO Manager Interrupt Mode 1 218897883Sgibbs */ 218997883Sgibbsregister LQOMODE1 { 219097883Sgibbs address 0x055 219197883Sgibbs access_mode RW 219297883Sgibbs modes M_CFG 2193102681Sgibbs field ENLQOINITSCBPERR 0x10 2194102681Sgibbs field ENLQOSTOPI2 0x08 2195102681Sgibbs field ENLQOBADQAS 0x04 2196102681Sgibbs field ENLQOBUSFREE 0x02 2197102681Sgibbs field ENLQOPHACHGINPKT 0x01 219897883Sgibbs} 219997883Sgibbs 220097883Sgibbs/* 220197883Sgibbs * LQO Manager Status 2 220297883Sgibbs */ 220397883Sgibbsregister LQOSTAT2 { 220497883Sgibbs address 0x056 220597883Sgibbs access_mode RO 220697883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2207102681Sgibbs field LQOPKT 0xE0 2208102681Sgibbs field LQOWAITFIFO 0x10 2209102681Sgibbs field LQOPHACHGOUTPKT 0x02 /* outside of packet boundaries. */ 2210102681Sgibbs field LQOSTOP0 0x01 /* Stopped after sending all packets */ 221197883Sgibbs} 221297883Sgibbs 221397883Sgibbs/* 221497883Sgibbs * Output Synchronizer Space Count 221597883Sgibbs */ 221697883Sgibbsregister OS_SPACE_CNT { 221797883Sgibbs address 0x056 221897883Sgibbs access_mode RO 221997883Sgibbs modes M_CFG 222097883Sgibbs} 222197883Sgibbs 222297883Sgibbs/* 222397883Sgibbs * SCSI Interrupt Mode 1 222497883Sgibbs * Setting any bit will enable the corresponding function 222597883Sgibbs * in SIMODE1 to interrupt via the IRQ pin. 222697883Sgibbs */ 222797883Sgibbsregister SIMODE1 { 222897883Sgibbs address 0x057 222997883Sgibbs access_mode RW 223097883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2231102681Sgibbs field ENSELTIMO 0x80 2232102681Sgibbs field ENATNTARG 0x40 2233102681Sgibbs field ENSCSIRST 0x20 2234102681Sgibbs field ENPHASEMIS 0x10 2235102681Sgibbs field ENBUSFREE 0x08 2236102681Sgibbs field ENSCSIPERR 0x04 2237102681Sgibbs field ENSTRB2FAST 0x02 2238102681Sgibbs field ENREQINIT 0x01 223997883Sgibbs} 224097883Sgibbs 224197883Sgibbs/* 224297883Sgibbs * Good Status FIFO 224397883Sgibbs */ 224497883Sgibbsregister GSFIFO { 224597883Sgibbs address 0x058 224697883Sgibbs access_mode RO 224797883Sgibbs size 2 224897883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 224997883Sgibbs} 225097883Sgibbs 225197883Sgibbs/* 225297883Sgibbs * Data FIFO SCSI Transfer Control 225397883Sgibbs */ 225497883Sgibbsregister DFFSXFRCTL { 225597883Sgibbs address 0x05A 225697883Sgibbs access_mode RW 225797883Sgibbs modes M_DFF0, M_DFF1 2258107441Sscottl field DFFBITBUCKET 0x08 2259102681Sgibbs field CLRSHCNT 0x04 2260102681Sgibbs field CLRCHN 0x02 2261102681Sgibbs field RSTCHN 0x01 226297883Sgibbs} 226397883Sgibbs 226497883Sgibbs/* 226597883Sgibbs * Next SCSI Control Block 226697883Sgibbs */ 226797883Sgibbsregister NEXTSCB { 226897883Sgibbs address 0x05A 226997883Sgibbs access_mode RW 227097883Sgibbs size 2 227197883Sgibbs modes M_SCSI 227297883Sgibbs} 2273107441Sscottl 2274107441Sscottl/* Rev B only. */ 2275107441Sscottlregister LQOSCSCTL { 2276107441Sscottl address 0x05A 2277107441Sscottl access_mode RW 2278107441Sscottl size 1 2279107441Sscottl modes M_CFG 2280107441Sscottl field LQOH2A_VERSION 0x80 2281107441Sscottl field LQONOCHKOVER 0x01 2282107441Sscottl} 2283107441Sscottl 228497883Sgibbs/* 228597883Sgibbs * SEQ Interrupts 228697883Sgibbs */ 228797883Sgibbsregister SEQINTSRC { 228897883Sgibbs address 0x05B 228997883Sgibbs access_mode RO 229097883Sgibbs modes M_DFF0, M_DFF1 2291102681Sgibbs field CTXTDONE 0x40 2292102681Sgibbs field SAVEPTRS 0x20 2293102681Sgibbs field CFG4DATA 0x10 2294102681Sgibbs field CFG4ISTAT 0x08 2295102681Sgibbs field CFG4TSTAT 0x04 2296102681Sgibbs field CFG4ICMD 0x02 2297102681Sgibbs field CFG4TCMD 0x01 229897883Sgibbs} 229997883Sgibbs 230097883Sgibbs/* 230197883Sgibbs * Clear Arp Interrupts 230297883Sgibbs */ 230397883Sgibbsregister CLRSEQINTSRC { 230497883Sgibbs address 0x05B 230597883Sgibbs access_mode WO 230697883Sgibbs modes M_DFF0, M_DFF1 2307102681Sgibbs field CLRCTXTDONE 0x40 2308102681Sgibbs field CLRSAVEPTRS 0x20 2309102681Sgibbs field CLRCFG4DATA 0x10 2310102681Sgibbs field CLRCFG4ISTAT 0x08 2311102681Sgibbs field CLRCFG4TSTAT 0x04 2312102681Sgibbs field CLRCFG4ICMD 0x02 2313102681Sgibbs field CLRCFG4TCMD 0x01 231497883Sgibbs} 231597883Sgibbs 231697883Sgibbs/* 231797883Sgibbs * SEQ Interrupt Enabled (Shared) 231897883Sgibbs */ 231997883Sgibbsregister SEQIMODE { 232097883Sgibbs address 0x05C 232197883Sgibbs access_mode RW 232297883Sgibbs modes M_DFF0, M_DFF1 2323102681Sgibbs field ENCTXTDONE 0x40 2324102681Sgibbs field ENSAVEPTRS 0x20 2325102681Sgibbs field ENCFG4DATA 0x10 2326102681Sgibbs field ENCFG4ISTAT 0x08 2327102681Sgibbs field ENCFG4TSTAT 0x04 2328102681Sgibbs field ENCFG4ICMD 0x02 2329102681Sgibbs field ENCFG4TCMD 0x01 233097883Sgibbs} 233197883Sgibbs 233297883Sgibbs/* 233397883Sgibbs * Current SCSI Control Block 233497883Sgibbs */ 233597883Sgibbsregister CURRSCB { 233697883Sgibbs address 0x05C 233797883Sgibbs access_mode RW 233897883Sgibbs size 2 233997883Sgibbs modes M_SCSI 234097883Sgibbs} 234197883Sgibbs 234297883Sgibbs/* 234397883Sgibbs * Data FIFO Status 234497883Sgibbs */ 234597883Sgibbsregister MDFFSTAT { 234697883Sgibbs address 0x05D 234797883Sgibbs access_mode RO 234897883Sgibbs modes M_DFF0, M_DFF1 2349102681Sgibbs field SHCNTNEGATIVE 0x40 /* Rev B or higher */ 2350102681Sgibbs field SHCNTMINUS1 0x20 /* Rev B or higher */ 2351102681Sgibbs field LASTSDONE 0x10 2352102681Sgibbs field SHVALID 0x08 2353102681Sgibbs field DLZERO 0x04 /* FIFO data ends on packet boundary. */ 2354102681Sgibbs field DATAINFIFO 0x02 2355102681Sgibbs field FIFOFREE 0x01 235697883Sgibbs} 235797883Sgibbs 235897883Sgibbs/* 235997883Sgibbs * CRC Control 236097883Sgibbs */ 236197883Sgibbsregister CRCCONTROL { 236297883Sgibbs address 0x05d 236397883Sgibbs access_mode RW 236497883Sgibbs modes M_CFG 2365102681Sgibbs field CRCVALCHKEN 0x40 236697883Sgibbs} 236797883Sgibbs 236897883Sgibbs/* 236997883Sgibbs * SCSI Test Control 237097883Sgibbs */ 237197883Sgibbsregister SCSITEST { 237297883Sgibbs address 0x05E 237397883Sgibbs access_mode RW 237497883Sgibbs modes M_CFG 2375102681Sgibbs field CNTRTEST 0x08 2376102681Sgibbs field SEL_TXPLL_DEBUG 0x04 237797883Sgibbs} 237897883Sgibbs 237997883Sgibbs/* 238097883Sgibbs * Data FIFO Queue Tag 238197883Sgibbs */ 238297883Sgibbsregister DFFTAG { 238397883Sgibbs address 0x05E 238497883Sgibbs access_mode RW 238597883Sgibbs size 2 238697883Sgibbs modes M_DFF0, M_DFF1 238797883Sgibbs} 238897883Sgibbs 238997883Sgibbs/* 239097883Sgibbs * Last SCSI Control Block 239197883Sgibbs */ 239297883Sgibbsregister LASTSCB { 239397883Sgibbs address 0x05E 239497883Sgibbs access_mode RW 239597883Sgibbs size 2 239697883Sgibbs modes M_SCSI 239797883Sgibbs} 239897883Sgibbs 239997883Sgibbs/* 240097883Sgibbs * SCSI I/O Cell Power-down Control 240197883Sgibbs */ 240297883Sgibbsregister IOPDNCTL { 240397883Sgibbs address 0x05F 240497883Sgibbs access_mode RW 240597883Sgibbs modes M_CFG 2406102681Sgibbs field DISABLE_OE 0x80 2407102681Sgibbs field PDN_IDIST 0x04 2408102681Sgibbs field PDN_DIFFSENSE 0x01 240997883Sgibbs} 241097883Sgibbs 241197883Sgibbs/* 241297883Sgibbs * Shaddow Host Address. 241397883Sgibbs */ 241497883Sgibbsregister SHADDR { 241597883Sgibbs address 0x060 241697883Sgibbs access_mode RO 241797883Sgibbs size 8 241897883Sgibbs modes M_DFF0, M_DFF1 241997883Sgibbs} 242097883Sgibbs 242197883Sgibbs/* 242297883Sgibbs * Data Group CRC Interval. 242397883Sgibbs */ 242497883Sgibbsregister DGRPCRCI { 242597883Sgibbs address 0x060 242697883Sgibbs access_mode RW 242797883Sgibbs size 2 242897883Sgibbs modes M_CFG 242997883Sgibbs} 243097883Sgibbs 243197883Sgibbs/* 243297883Sgibbs * Data Transfer Negotiation Address 243397883Sgibbs */ 243497883Sgibbsregister NEGOADDR { 243597883Sgibbs address 0x060 243697883Sgibbs access_mode RW 243797883Sgibbs modes M_SCSI 243897883Sgibbs} 243997883Sgibbs 244097883Sgibbs/* 244197883Sgibbs * Data Transfer Negotiation Data - Period Byte 244297883Sgibbs */ 244397883Sgibbsregister NEGPERIOD { 244497883Sgibbs address 0x061 244597883Sgibbs access_mode RW 244697883Sgibbs modes M_SCSI 244797883Sgibbs} 244897883Sgibbs 244997883Sgibbs/* 245097883Sgibbs * Packetized CRC Interval 245197883Sgibbs */ 245297883Sgibbsregister PACKCRCI { 245397883Sgibbs address 0x062 245497883Sgibbs access_mode RW 245597883Sgibbs size 2 245697883Sgibbs modes M_CFG 245797883Sgibbs} 245897883Sgibbs 245997883Sgibbs/* 246097883Sgibbs * Data Transfer Negotiation Data - Offset Byte 246197883Sgibbs */ 246297883Sgibbsregister NEGOFFSET { 246397883Sgibbs address 0x062 246497883Sgibbs access_mode RW 246597883Sgibbs modes M_SCSI 246697883Sgibbs} 246797883Sgibbs 246897883Sgibbs/* 246997883Sgibbs * Data Transfer Negotiation Data - PPR Options 247097883Sgibbs */ 247197883Sgibbsregister NEGPPROPTS { 247297883Sgibbs address 0x063 247397883Sgibbs access_mode RW 247497883Sgibbs modes M_SCSI 2475102681Sgibbs field PPROPT_PACE 0x08 2476102681Sgibbs field PPROPT_QAS 0x04 2477102681Sgibbs field PPROPT_DT 0x02 2478102681Sgibbs field PPROPT_IUT 0x01 247997883Sgibbs} 248097883Sgibbs 248197883Sgibbs/* 248297883Sgibbs * Data Transfer Negotiation Data - Connection Options 248397883Sgibbs */ 248497883Sgibbsregister NEGCONOPTS { 248597883Sgibbs address 0x064 248697883Sgibbs access_mode RW 248797883Sgibbs modes M_SCSI 2488107441Sscottl field ENSNAPSHOT 0x40 2489107441Sscottl field RTI_WRTDIS 0x20 2490107441Sscottl field RTI_OVRDTRN 0x10 2491107441Sscottl field ENSLOWCRC 0x08 2492102681Sgibbs field ENAUTOATNI 0x04 2493102681Sgibbs field ENAUTOATNO 0x02 2494102681Sgibbs field WIDEXFER 0x01 249597883Sgibbs} 249697883Sgibbs 249797883Sgibbs/* 249897883Sgibbs * Negotiation Table Annex Column Index. 249997883Sgibbs */ 250097883Sgibbsregister ANNEXCOL { 250197883Sgibbs address 0x065 250297883Sgibbs access_mode RW 250397883Sgibbs modes M_SCSI 250497883Sgibbs} 250597883Sgibbs 2506102681Sgibbsregister SCSCHKN { 2507102681Sgibbs address 0x066 2508102681Sgibbs access_mode RW 2509102681Sgibbs modes M_CFG 2510102681Sgibbs field STSELSKIDDIS 0x40 2511107441Sscottl field CURRFIFODEF 0x20 2512102681Sgibbs field WIDERESEN 0x10 2513102681Sgibbs field SDONEMSKDIS 0x08 2514102681Sgibbs field DFFACTCLR 0x04 2515102681Sgibbs field SHVALIDSTDIS 0x02 2516102681Sgibbs field LSTSGCLRDIS 0x01 2517102681Sgibbs} 2518102681Sgibbs 2519107441Sscottlconst AHD_ANNEXCOL_PER_DEV0 4 2520107441Sscottlconst AHD_NUM_PER_DEV_ANNEXCOLS 4 2521107441Sscottlconst AHD_ANNEXCOL_PRECOMP_SLEW 4 252297883Sgibbsconst AHD_PRECOMP_MASK 0x07 2523107441Sscottlconst AHD_PRECOMP_SHIFT 0 252497883Sgibbsconst AHD_PRECOMP_CUTBACK_17 0x04 252597883Sgibbsconst AHD_PRECOMP_CUTBACK_29 0x06 252697883Sgibbsconst AHD_PRECOMP_CUTBACK_37 0x07 2527107441Sscottlconst AHD_SLEWRATE_MASK 0x78 2528107441Sscottlconst AHD_SLEWRATE_SHIFT 3 2529107441Sscottl/* 2530107441Sscottl * Rev A has only a single bit of slew adjustment. 2531107441Sscottl * Rev B has 4 bits. 2532107441Sscottl */ 2533107441Sscottlconst AHD_SLEWRATE_DEF_REVA 0x01 2534107441Sscottlconst AHD_SLEWRATE_DEF_REVB 0x08 253597883Sgibbs 2536107441Sscottl/* Rev A does not have any amplitude setting. */ 2537107441Sscottlconst AHD_ANNEXCOL_AMPLITUDE 6 2538107441Sscottlconst AHD_AMPLITUDE_MASK 0x7 2539107441Sscottlconst AHD_AMPLITUDE_SHIFT 0 2540107441Sscottlconst AHD_AMPLITUDE_DEF 0x7 2541107441Sscottl 254297883Sgibbs/* 254397883Sgibbs * Negotiation Table Annex Data Port. 254497883Sgibbs */ 254597883Sgibbsregister ANNEXDAT { 254697883Sgibbs address 0x066 254797883Sgibbs access_mode RW 254897883Sgibbs modes M_SCSI 254997883Sgibbs} 255097883Sgibbs 255197883Sgibbs/* 255297883Sgibbs * Initiator's Own Id. 255397883Sgibbs * The SCSI ID to use for Selection Out and seen during a reselection.. 255497883Sgibbs */ 255597883Sgibbsregister IOWNID { 255697883Sgibbs address 0x067 255797883Sgibbs access_mode RW 255897883Sgibbs modes M_SCSI 255997883Sgibbs} 256097883Sgibbs 256197883Sgibbs/* 256297883Sgibbs * 960MHz Phase-Locked Loop Control 0 256397883Sgibbs */ 256497883Sgibbsregister PLL960CTL0 { 256597883Sgibbs address 0x068 256697883Sgibbs access_mode RW 256797883Sgibbs modes M_CFG 2568102681Sgibbs field PLL_VCOSEL 0x80 2569102681Sgibbs field PLL_PWDN 0x40 2570102681Sgibbs field PLL_NS 0x30 2571102681Sgibbs field PLL_ENLUD 0x08 2572102681Sgibbs field PLL_ENLPF 0x04 2573102681Sgibbs field PLL_DLPF 0x02 2574102681Sgibbs field PLL_ENFBM 0x01 257597883Sgibbs} 257697883Sgibbs 257797883Sgibbs/* 257897883Sgibbs * Target Own Id 257997883Sgibbs */ 258097883Sgibbsregister TOWNID { 258197883Sgibbs address 0x069 258297883Sgibbs access_mode RW 258397883Sgibbs modes M_SCSI 258497883Sgibbs} 258597883Sgibbs 258697883Sgibbs/* 258797883Sgibbs * 960MHz Phase-Locked Loop Control 1 258897883Sgibbs */ 258997883Sgibbsregister PLL960CTL1 { 259097883Sgibbs address 0x069 259197883Sgibbs access_mode RW 259297883Sgibbs modes M_CFG 2593102681Sgibbs field PLL_CNTEN 0x80 2594102681Sgibbs field PLL_CNTCLR 0x40 2595102681Sgibbs field PLL_RST 0x01 259697883Sgibbs} 259797883Sgibbs 259897883Sgibbs/* 259997883Sgibbs * Expander Signature 260097883Sgibbs */ 260197883Sgibbsregister XSIG { 260297883Sgibbs address 0x06A 260397883Sgibbs access_mode RW 260497883Sgibbs modes M_SCSI 260597883Sgibbs} 260697883Sgibbs 260797883Sgibbs/* 260897883Sgibbs * Shadow Byte Count 260997883Sgibbs */ 261097883Sgibbsregister SHCNT { 261197883Sgibbs address 0x068 261297883Sgibbs access_mode RW 261397883Sgibbs size 3 261497883Sgibbs modes M_DFF0, M_DFF1 261597883Sgibbs} 261697883Sgibbs 261797883Sgibbs/* 261897883Sgibbs * Selection Out ID 261997883Sgibbs */ 262097883Sgibbsregister SELOID { 262197883Sgibbs address 0x06B 262297883Sgibbs access_mode RW 262397883Sgibbs modes M_SCSI 262497883Sgibbs} 262597883Sgibbs 262697883Sgibbs/* 262797883Sgibbs * 960-MHz Phase-Locked Loop Test Count 262897883Sgibbs */ 262997883Sgibbsregister PLL960CNT0 { 263097883Sgibbs address 0x06A 263197883Sgibbs access_mode RO 263297883Sgibbs size 2 263397883Sgibbs modes M_CFG 263497883Sgibbs} 263597883Sgibbs 263697883Sgibbs/* 263797883Sgibbs * 400-MHz Phase-Locked Loop Control 0 263897883Sgibbs */ 263997883Sgibbsregister PLL400CTL0 { 264097883Sgibbs address 0x06C 264197883Sgibbs access_mode RW 264297883Sgibbs modes M_CFG 2643102681Sgibbs field PLL_VCOSEL 0x80 2644102681Sgibbs field PLL_PWDN 0x40 2645102681Sgibbs field PLL_NS 0x30 2646102681Sgibbs field PLL_ENLUD 0x08 2647102681Sgibbs field PLL_ENLPF 0x04 2648102681Sgibbs field PLL_DLPF 0x02 2649102681Sgibbs field PLL_ENFBM 0x01 265097883Sgibbs} 265197883Sgibbs 265297883Sgibbs/* 265397883Sgibbs * Arbitration Fairness 265497883Sgibbs */ 265597883Sgibbsregister FAIRNESS { 265697883Sgibbs address 0x06C 265797883Sgibbs access_mode RW 265897883Sgibbs size 2 265997883Sgibbs modes M_SCSI 266097883Sgibbs} 266197883Sgibbs 266297883Sgibbs/* 266397883Sgibbs * 400-MHz Phase-Locked Loop Control 1 266497883Sgibbs */ 266597883Sgibbsregister PLL400CTL1 { 266697883Sgibbs address 0x06D 266797883Sgibbs access_mode RW 266897883Sgibbs modes M_CFG 2669102681Sgibbs field PLL_CNTEN 0x80 2670102681Sgibbs field PLL_CNTCLR 0x40 2671102681Sgibbs field PLL_RST 0x01 267297883Sgibbs} 267397883Sgibbs 267497883Sgibbs/* 267597883Sgibbs * Arbitration Unfairness 267697883Sgibbs */ 267797883Sgibbsregister UNFAIRNESS { 267897883Sgibbs address 0x06E 267997883Sgibbs access_mode RW 268097883Sgibbs size 2 268197883Sgibbs modes M_SCSI 268297883Sgibbs} 268397883Sgibbs 268497883Sgibbs/* 268597883Sgibbs * 400-MHz Phase-Locked Loop Test Count 268697883Sgibbs */ 268797883Sgibbsregister PLL400CNT0 { 268897883Sgibbs address 0x06E 268997883Sgibbs access_mode RO 269097883Sgibbs size 2 269197883Sgibbs modes M_CFG 269297883Sgibbs} 269397883Sgibbs 269497883Sgibbs/* 269597883Sgibbs * SCB Page Pointer 269697883Sgibbs */ 269797883Sgibbsregister SCBPTR { 269897883Sgibbs address 0x0A8 269997883Sgibbs access_mode RW 270097883Sgibbs size 2 270197883Sgibbs modes M_DFF0, M_DFF1, M_CCHAN, M_SCSI 270297883Sgibbs} 270397883Sgibbs 270497883Sgibbs/* 270597883Sgibbs * CMC SCB Array Count 270697883Sgibbs * Number of bytes to transfer between CMC SCB memory and SCBRAM. 270797883Sgibbs * Transfers must be 8byte aligned and sized. 270897883Sgibbs */ 270997883Sgibbsregister CCSCBACNT { 271097883Sgibbs address 0x0AB 271197883Sgibbs access_mode RW 271297883Sgibbs modes M_CCHAN 271397883Sgibbs} 271497883Sgibbs 271597883Sgibbs/* 271697883Sgibbs * SCB Autopointer 271797883Sgibbs * SCB-Next Address Snooping logic. When an SCB is transferred to 271897883Sgibbs * the card, the next SCB address to be used by the CMC array can 271997883Sgibbs * be autoloaded from that transfer. 272097883Sgibbs */ 272197883Sgibbsregister SCBAUTOPTR { 272297883Sgibbs address 0x0AB 272397883Sgibbs access_mode RW 272497883Sgibbs modes M_CFG 2725102681Sgibbs field AUSCBPTR_EN 0x80 2726102681Sgibbs field SCBPTR_ADDR 0x38 2727102681Sgibbs field SCBPTR_OFF 0x07 272897883Sgibbs} 272997883Sgibbs 273097883Sgibbs/* 273197883Sgibbs * CMC SG Ram Address Pointer 273297883Sgibbs */ 273397883Sgibbsregister CCSGADDR { 273497883Sgibbs address 0x0AC 273597883Sgibbs access_mode RW 273697883Sgibbs modes M_DFF0, M_DFF1 273797883Sgibbs} 273897883Sgibbs 273997883Sgibbs/* 274097883Sgibbs * CMC SCB RAM Address Pointer 274197883Sgibbs */ 274297883Sgibbsregister CCSCBADDR { 274397883Sgibbs address 0x0AC 274497883Sgibbs access_mode RW 274597883Sgibbs modes M_CCHAN 274697883Sgibbs} 274797883Sgibbs 274897883Sgibbs/* 274997883Sgibbs * CMC SCB Ram Back-up Address Pointer 275097883Sgibbs * Indicates the true stop location of transfers halted prior 275197883Sgibbs * to SCBHCNT going to 0. 275297883Sgibbs */ 275397883Sgibbsregister CCSCBADR_BK { 275497883Sgibbs address 0x0AC 275597883Sgibbs access_mode RO 275697883Sgibbs modes M_CFG 275797883Sgibbs} 275897883Sgibbs 275997883Sgibbs/* 276097883Sgibbs * CMC SG Control 276197883Sgibbs */ 276297883Sgibbsregister CCSGCTL { 276397883Sgibbs address 0x0AD 276497883Sgibbs access_mode RW 276597883Sgibbs modes M_DFF0, M_DFF1 2766102681Sgibbs field CCSGDONE 0x80 2767102681Sgibbs field SG_CACHE_AVAIL 0x10 2768107441Sscottl field CCSGENACK 0x08 2769107441Sscottl mask CCSGEN 0x0C 2770102681Sgibbs field SG_FETCH_REQ 0x02 2771102681Sgibbs field CCSGRESET 0x01 277297883Sgibbs} 277397883Sgibbs 277497883Sgibbs/* 277597883Sgibbs * CMD SCB Control 277697883Sgibbs */ 277797883Sgibbsregister CCSCBCTL { 277897883Sgibbs address 0x0AD 277997883Sgibbs access_mode RW 278097883Sgibbs modes M_CCHAN 2781102681Sgibbs field CCSCBDONE 0x80 2782102681Sgibbs field ARRDONE 0x40 2783102681Sgibbs field CCARREN 0x10 2784102681Sgibbs field CCSCBEN 0x08 2785102681Sgibbs field CCSCBDIR 0x04 2786102681Sgibbs field CCSCBRESET 0x01 278797883Sgibbs} 278897883Sgibbs 278997883Sgibbs/* 279097883Sgibbs * CMC Ram BIST 279197883Sgibbs */ 279297883Sgibbsregister CMC_RAMBIST { 279397883Sgibbs address 0x0AD 279497883Sgibbs access_mode RW 279597883Sgibbs modes M_CFG 2796102681Sgibbs field SG_ELEMENT_SIZE 0x80 2797102681Sgibbs field SCBRAMBIST_FAIL 0x40 2798102681Sgibbs field SG_BIST_FAIL 0x20 2799102681Sgibbs field SG_BIST_EN 0x10 2800102681Sgibbs field CMC_BUFFER_BIST_FAIL 0x02 2801102681Sgibbs field CMC_BUFFER_BIST_EN 0x01 280297883Sgibbs} 280397883Sgibbs 280497883Sgibbs/* 280597883Sgibbs * CMC SG RAM Data Port 280697883Sgibbs */ 280797883Sgibbsregister CCSGRAM { 280897883Sgibbs address 0x0B0 280997883Sgibbs access_mode RW 281097883Sgibbs modes M_DFF0, M_DFF1 281197883Sgibbs} 281297883Sgibbs 281397883Sgibbs/* 281497883Sgibbs * CMC SCB RAM Data Port 281597883Sgibbs */ 281697883Sgibbsregister CCSCBRAM { 281797883Sgibbs address 0x0B0 281897883Sgibbs access_mode RW 281997883Sgibbs modes M_CCHAN 282097883Sgibbs} 282197883Sgibbs 282297883Sgibbs/* 282397883Sgibbs * Flex DMA Address. 282497883Sgibbs */ 282597883Sgibbsregister FLEXADR { 282697883Sgibbs address 0x0B0 282797883Sgibbs access_mode RW 282897883Sgibbs size 3 282997883Sgibbs modes M_SCSI 283097883Sgibbs} 283197883Sgibbs 283297883Sgibbs/* 283397883Sgibbs * Flex DMA Byte Count 283497883Sgibbs */ 283597883Sgibbsregister FLEXCNT { 283697883Sgibbs address 0x0B3 283797883Sgibbs access_mode RW 283897883Sgibbs size 2 283997883Sgibbs modes M_SCSI 284097883Sgibbs} 284197883Sgibbs 284297883Sgibbs/* 284397883Sgibbs * Flex DMA Status 284497883Sgibbs */ 284597883Sgibbsregister FLEXDMASTAT { 284697883Sgibbs address 0x0B5 284797883Sgibbs access_mode RW 284897883Sgibbs modes M_SCSI 2849102681Sgibbs field FLEXDMAERR 0x02 2850102681Sgibbs field FLEXDMADONE 0x01 285197883Sgibbs} 285297883Sgibbs 285397883Sgibbs/* 285497883Sgibbs * Flex DMA Data Port 285597883Sgibbs */ 285697883Sgibbsregister FLEXDATA { 285797883Sgibbs address 0x0B6 285897883Sgibbs access_mode RW 285997883Sgibbs modes M_SCSI 286097883Sgibbs} 286197883Sgibbs 286297883Sgibbs/* 286397883Sgibbs * Board Data 286497883Sgibbs */ 286597883Sgibbsregister BRDDAT { 286697883Sgibbs address 0x0B8 286797883Sgibbs access_mode RW 286897883Sgibbs modes M_SCSI 286997883Sgibbs} 287097883Sgibbs 287197883Sgibbs/* 287297883Sgibbs * Board Control 287397883Sgibbs */ 287497883Sgibbsregister BRDCTL { 287597883Sgibbs address 0x0B9 287697883Sgibbs access_mode RW 287797883Sgibbs modes M_SCSI 2878102681Sgibbs field FLXARBACK 0x80 2879102681Sgibbs field FLXARBREQ 0x40 2880102681Sgibbs field BRDADDR 0x38 2881102681Sgibbs field BRDEN 0x04 2882102681Sgibbs field BRDRW 0x02 2883102681Sgibbs field BRDSTB 0x01 288497883Sgibbs} 288597883Sgibbs 288697883Sgibbs/* 288797883Sgibbs * Serial EEPROM Address 288897883Sgibbs */ 288997883Sgibbsregister SEEADR { 289097883Sgibbs address 0x0BA 289197883Sgibbs access_mode RW 289297883Sgibbs modes M_SCSI 289397883Sgibbs} 289497883Sgibbs 289597883Sgibbs/* 289697883Sgibbs * Serial EEPROM Data 289797883Sgibbs */ 289897883Sgibbsregister SEEDAT { 289997883Sgibbs address 0x0BC 290097883Sgibbs access_mode RW 290197883Sgibbs size 2 290297883Sgibbs modes M_SCSI 290397883Sgibbs} 290497883Sgibbs 290597883Sgibbs/* 290697883Sgibbs * Serial EEPROM Status 290797883Sgibbs */ 290897883Sgibbsregister SEESTAT { 290997883Sgibbs address 0x0BE 291097883Sgibbs access_mode RO 291197883Sgibbs modes M_SCSI 2912102681Sgibbs field INIT_DONE 0x80 2913102681Sgibbs field SEEOPCODE 0x70 2914102681Sgibbs field LDALTID_L 0x08 2915102681Sgibbs field SEEARBACK 0x04 2916102681Sgibbs field SEEBUSY 0x02 2917102681Sgibbs field SEESTART 0x01 291897883Sgibbs} 291997883Sgibbs 292097883Sgibbs/* 292197883Sgibbs * Serial EEPROM Control 292297883Sgibbs */ 292397883Sgibbsregister SEECTL { 292497883Sgibbs address 0x0BE 292597883Sgibbs access_mode RW 292697883Sgibbs modes M_SCSI 2927102681Sgibbs field SEEOPCODE 0x70 { 2928102681Sgibbs SEEOP_ERASE 0x70, 2929102681Sgibbs SEEOP_READ 0x60, 2930102681Sgibbs SEEOP_WRITE 0x50, 293197883Sgibbs /* 293297883Sgibbs * The following four commands use special 293397883Sgibbs * addresses for differentiation. 293497883Sgibbs */ 2935102681Sgibbs SEEOP_ERAL 0x40 2936102681Sgibbs } 293797883Sgibbs mask SEEOP_EWEN 0x40 293897883Sgibbs mask SEEOP_WALL 0x40 293997883Sgibbs mask SEEOP_EWDS 0x40 2940102681Sgibbs field SEERST 0x02 2941102681Sgibbs field SEESTART 0x01 294297883Sgibbs} 294397883Sgibbs 294497883Sgibbsconst SEEOP_ERAL_ADDR 0x80 294597883Sgibbsconst SEEOP_EWEN_ADDR 0xC0 294697883Sgibbsconst SEEOP_WRAL_ADDR 0x40 294797883Sgibbsconst SEEOP_EWDS_ADDR 0x00 294897883Sgibbs 294997883Sgibbs/* 295097883Sgibbs * SCB Counter 295197883Sgibbs */ 295297883Sgibbsregister SCBCNT { 295397883Sgibbs address 0x0BF 295497883Sgibbs access_mode RW 295597883Sgibbs modes M_SCSI 295697883Sgibbs} 295797883Sgibbs 295897883Sgibbs/* 295997883Sgibbs * Data FIFO Write Address 296097883Sgibbs * Pointer to the next QWD location to be written to the data FIFO. 296197883Sgibbs */ 296297883Sgibbsregister DFWADDR { 296397883Sgibbs address 0x0C0 296497883Sgibbs access_mode RW 296597883Sgibbs size 2 296697883Sgibbs modes M_DFF0, M_DFF1 296797883Sgibbs} 296897883Sgibbs 296997883Sgibbs/* 297097883Sgibbs * DSP Filter Control 297197883Sgibbs */ 297297883Sgibbsregister DSPFLTRCTL { 297397883Sgibbs address 0x0C0 297497883Sgibbs access_mode RW 297597883Sgibbs modes M_CFG 2976102681Sgibbs field FLTRDISABLE 0x20 2977102681Sgibbs field EDGESENSE 0x10 2978102681Sgibbs field DSPFCNTSEL 0x0F 297997883Sgibbs} 298097883Sgibbs 298197883Sgibbs/* 298297883Sgibbs * DSP Data Channel Control 298397883Sgibbs */ 298497883Sgibbsregister DSPDATACTL { 298597883Sgibbs address 0x0C1 298697883Sgibbs access_mode RW 298797883Sgibbs modes M_CFG 2988102681Sgibbs field BYPASSENAB 0x80 2989102681Sgibbs field DESQDIS 0x10 2990102681Sgibbs field RCVROFFSTDIS 0x04 2991102681Sgibbs field XMITOFFSTDIS 0x02 299297883Sgibbs} 299397883Sgibbs 299497883Sgibbs/* 299597883Sgibbs * Data FIFO Read Address 299697883Sgibbs * Pointer to the next QWD location to be read from the data FIFO. 299797883Sgibbs */ 299897883Sgibbsregister DFRADDR { 299997883Sgibbs address 0x0C2 300097883Sgibbs access_mode RW 300197883Sgibbs size 2 300297883Sgibbs modes M_DFF0, M_DFF1 300397883Sgibbs} 300497883Sgibbs 300597883Sgibbs/* 300697883Sgibbs * DSP REQ Control 300797883Sgibbs */ 300897883Sgibbsregister DSPREQCTL { 300997883Sgibbs address 0x0C2 301097883Sgibbs access_mode RW 301197883Sgibbs modes M_CFG 3012102681Sgibbs field MANREQCTL 0xC0 3013102681Sgibbs field MANREQDLY 0x3F 301497883Sgibbs} 301597883Sgibbs 301697883Sgibbs/* 301797883Sgibbs * DSP ACK Control 301897883Sgibbs */ 301997883Sgibbsregister DSPACKCTL { 302097883Sgibbs address 0x0C3 302197883Sgibbs access_mode RW 302297883Sgibbs modes M_CFG 3023102681Sgibbs field MANACKCTL 0xC0 3024102681Sgibbs field MANACKDLY 0x3F 302597883Sgibbs} 302697883Sgibbs 302797883Sgibbs/* 302897883Sgibbs * Data FIFO Data 302997883Sgibbs * Read/Write byte port into the data FIFO. The read and write 303097883Sgibbs * FIFO pointers increment with each read and write respectively 303197883Sgibbs * to this port. 303297883Sgibbs */ 303397883Sgibbsregister DFDAT { 303497883Sgibbs address 0x0C4 303597883Sgibbs access_mode RW 303697883Sgibbs modes M_DFF0, M_DFF1 303797883Sgibbs} 303897883Sgibbs 303997883Sgibbs/* 304097883Sgibbs * DSP Channel Select 304197883Sgibbs */ 304297883Sgibbsregister DSPSELECT { 304397883Sgibbs address 0x0C4 304497883Sgibbs access_mode RW 304597883Sgibbs modes M_CFG 3046102681Sgibbs field AUTOINCEN 0x80 3047102681Sgibbs field DSPSEL 0x1F 304897883Sgibbs} 304997883Sgibbs 305097883Sgibbsconst NUMDSPS 0x14 305197883Sgibbs 305297883Sgibbs/* 305397883Sgibbs * Write Bias Control 305497883Sgibbs */ 305597883Sgibbsregister WRTBIASCTL { 305697883Sgibbs address 0x0C5 305797883Sgibbs access_mode WO 305897883Sgibbs modes M_CFG 3059102681Sgibbs field AUTOXBCDIS 0x80 3060102681Sgibbs field XMITMANVAL 0x3F 306197883Sgibbs} 306297883Sgibbs 3063107441Sscottl/* 3064107441Sscottl * Currently the WRTBIASCTL is the same as the default. 3065107441Sscottl */ 3066107441Sscottlconst WRTBIASCTL_HP_DEFAULT 0x0 306797883Sgibbs 306897883Sgibbs/* 306997883Sgibbs * Receiver Bias Control 307097883Sgibbs */ 307197883Sgibbsregister RCVRBIOSCTL { 307297883Sgibbs address 0x0C6 307397883Sgibbs access_mode WO 307497883Sgibbs modes M_CFG 3075102681Sgibbs field AUTORBCDIS 0x80 3076102681Sgibbs field RCVRMANVAL 0x3F 307797883Sgibbs} 307897883Sgibbs 307997883Sgibbs/* 308097883Sgibbs * Write Bias Calculator 308197883Sgibbs */ 308297883Sgibbsregister WRTBIASCALC { 308397883Sgibbs address 0x0C7 308497883Sgibbs access_mode RO 308597883Sgibbs modes M_CFG 308697883Sgibbs} 308797883Sgibbs 308897883Sgibbs/* 308997883Sgibbs * Data FIFO Pointers 309097883Sgibbs * Contains the byte offset from DFWADDR and DWRADDR to the current 309197883Sgibbs * FIFO write/read locations. 309297883Sgibbs */ 309397883Sgibbsregister DFPTRS { 309497883Sgibbs address 0x0C8 309597883Sgibbs access_mode RW 309697883Sgibbs modes M_DFF0, M_DFF1 309797883Sgibbs} 309897883Sgibbs 309997883Sgibbs/* 310097883Sgibbs * Receiver Bias Calculator 310197883Sgibbs */ 310297883Sgibbsregister RCVRBIASCALC { 310397883Sgibbs address 0x0C8 310497883Sgibbs access_mode RO 310597883Sgibbs modes M_CFG 310697883Sgibbs} 310797883Sgibbs 310897883Sgibbs/* 310997883Sgibbs * Data FIFO Debug Control 311097883Sgibbs */ 311197883Sgibbsregister DFDBCTL { 311297883Sgibbs address 0x0C8 311397883Sgibbs access_mode RW 311497883Sgibbs modes M_DFF0, M_DFF1 3115102681Sgibbs field DFF_CIO_WR_RDY 0x20 3116102681Sgibbs field DFF_CIO_RD_RDY 0x10 3117102681Sgibbs field DFF_DIR_ERR 0x08 3118102681Sgibbs field DFF_RAMBIST_FAIL 0x04 3119102681Sgibbs field DFF_RAMBIST_DONE 0x02 3120102681Sgibbs field DFF_RAMBIST_EN 0x01 312197883Sgibbs} 312297883Sgibbs 312397883Sgibbs/* 312497883Sgibbs * Data FIFO Backup Read Pointer 312597883Sgibbs * Contains the data FIFO address to be restored if the last 312697883Sgibbs * data accessed from the data FIFO was not transferred successfully. 312797883Sgibbs */ 312897883Sgibbsregister DFBKPTR { 312997883Sgibbs address 0x0C9 313097883Sgibbs access_mode RW 313197883Sgibbs size 2 313297883Sgibbs modes M_DFF0, M_DFF1 313397883Sgibbs} 313497883Sgibbs 313597883Sgibbs/* 313697883Sgibbs * Skew Calculator 313797883Sgibbs */ 313897883Sgibbsregister SKEWCALC { 313997883Sgibbs address 0x0C9 314097883Sgibbs access_mode RO 314197883Sgibbs modes M_CFG 314297883Sgibbs} 314397883Sgibbs 314497883Sgibbs/* 314597883Sgibbs * Data FIFO Space Count 314697883Sgibbs * Number of FIFO locations that are free. 314797883Sgibbs */ 314897883Sgibbsregister DFSCNT { 314997883Sgibbs address 0x0CC 315097883Sgibbs access_mode RO 315197883Sgibbs size 2 315297883Sgibbs modes M_DFF0, M_DFF1 315397883Sgibbs} 315497883Sgibbs 315597883Sgibbs/* 315697883Sgibbs * Data FIFO Byte Count 315797883Sgibbs * Number of filled FIFO locations. 315897883Sgibbs */ 315997883Sgibbsregister DFBCNT { 316097883Sgibbs address 0x0CE 316197883Sgibbs access_mode RO 316297883Sgibbs size 2 316397883Sgibbs modes M_DFF0, M_DFF1 316497883Sgibbs} 316597883Sgibbs 316697883Sgibbs/* 316797883Sgibbs * Sequencer Program Overlay Address. 316897883Sgibbs * Low address must be written prior to high address. 316997883Sgibbs */ 317097883Sgibbsregister OVLYADDR { 317197883Sgibbs address 0x0D4 317297883Sgibbs modes M_SCSI 317397883Sgibbs size 2 317497883Sgibbs access_mode RW 317597883Sgibbs} 317697883Sgibbs 317797883Sgibbs/* 317897883Sgibbs * Sequencer Control 0 317997883Sgibbs * Error detection mode, speed configuration, 318097883Sgibbs * single step, breakpoints and program load. 318197883Sgibbs */ 318297883Sgibbsregister SEQCTL0 { 318397883Sgibbs address 0x0D6 318497883Sgibbs access_mode RW 3185102681Sgibbs field PERRORDIS 0x80 3186102681Sgibbs field PAUSEDIS 0x40 3187102681Sgibbs field FAILDIS 0x20 3188102681Sgibbs field FASTMODE 0x10 3189102681Sgibbs field BRKADRINTEN 0x08 3190102681Sgibbs field STEP 0x04 3191102681Sgibbs field SEQRESET 0x02 3192102681Sgibbs field LOADRAM 0x01 319397883Sgibbs} 319497883Sgibbs 319597883Sgibbs/* 319697883Sgibbs * Sequencer Control 1 319797883Sgibbs * Instruction RAM Diagnostics 319897883Sgibbs */ 319997883Sgibbsregister SEQCTL1 { 320097883Sgibbs address 0x0D7 320197883Sgibbs access_mode RW 3202102681Sgibbs field OVRLAY_DATA_CHK 0x08 3203102681Sgibbs field RAMBIST_DONE 0x04 3204102681Sgibbs field RAMBIST_FAIL 0x02 3205102681Sgibbs field RAMBIST_EN 0x01 320697883Sgibbs} 320797883Sgibbs 320897883Sgibbs/* 320997883Sgibbs * Sequencer Flags 321097883Sgibbs * Zero and Carry state of the ALU. 321197883Sgibbs */ 321297883Sgibbsregister FLAGS { 321397883Sgibbs address 0x0D8 321497883Sgibbs access_mode RO 3215102681Sgibbs field ZERO 0x02 3216102681Sgibbs field CARRY 0x01 321797883Sgibbs} 321897883Sgibbs 321997883Sgibbs/* 322097883Sgibbs * Sequencer Interrupt Control 322197883Sgibbs */ 322297883Sgibbsregister SEQINTCTL { 322397883Sgibbs address 0x0D9 322497883Sgibbs access_mode RW 3225102681Sgibbs field INTVEC1DSL 0x80 3226102681Sgibbs field INT1_CONTEXT 0x20 3227102681Sgibbs field SCS_SEQ_INT1M1 0x10 3228102681Sgibbs field SCS_SEQ_INT1M0 0x08 3229102681Sgibbs field INTMASK 0x06 3230102681Sgibbs field IRET 0x01 323197883Sgibbs} 323297883Sgibbs 323397883Sgibbs/* 323497883Sgibbs * Sequencer RAM Data Port 323597883Sgibbs * Single byte window into the Sequencer Instruction Ram area starting 323697883Sgibbs * at the address specified by OVLYADDR. To write a full instruction word, 323797883Sgibbs * simply write four bytes in succession. OVLYADDR will increment after the 323897883Sgibbs * most significant instrution byte (the byte with the parity bit) is written. 323997883Sgibbs */ 324097883Sgibbsregister SEQRAM { 324197883Sgibbs address 0x0DA 324297883Sgibbs access_mode RW 324397883Sgibbs} 324497883Sgibbs 324597883Sgibbs/* 324697883Sgibbs * Sequencer Program Counter 324797883Sgibbs * Low byte must be written prior to high byte. 324897883Sgibbs */ 324997883Sgibbsregister PRGMCNT { 325097883Sgibbs address 0x0DE 325197883Sgibbs access_mode RW 325297883Sgibbs size 2 325397883Sgibbs} 325497883Sgibbs 325597883Sgibbs/* 325697883Sgibbs * Accumulator 325797883Sgibbs */ 325897883Sgibbsregister ACCUM { 325997883Sgibbs address 0x0E0 326097883Sgibbs access_mode RW 326197883Sgibbs accumulator 326297883Sgibbs} 326397883Sgibbs 326497883Sgibbs/* 326597883Sgibbs * Source Index Register 326697883Sgibbs * Incrementing index for reads of SINDIR and the destination (low byte only) 326797883Sgibbs * for any immediate operands passed in jmp, jc, jnc, call instructions. 326897883Sgibbs * Example: 326997883Sgibbs * mvi 0xFF call some_routine; 327097883Sgibbs * 327197883Sgibbs * Will set SINDEX[0] to 0xFF and call the routine "some_routine. 327297883Sgibbs */ 327397883Sgibbsregister SINDEX { 327497883Sgibbs address 0x0E2 327597883Sgibbs access_mode RW 327697883Sgibbs size 2 327797883Sgibbs sindex 327897883Sgibbs} 327997883Sgibbs 328097883Sgibbs/* 328197883Sgibbs * Destination Index Register 328297883Sgibbs * Incrementing index for writes to DINDIR. Can be used as a scratch register. 328397883Sgibbs */ 328497883Sgibbsregister DINDEX { 328597883Sgibbs address 0x0E4 328697883Sgibbs access_mode RW 328797883Sgibbs size 2 328897883Sgibbs} 328997883Sgibbs 329097883Sgibbs/* 329197883Sgibbs * Break Address 329297883Sgibbs * Sequencer instruction breakpoint address address. 329397883Sgibbs */ 329497883Sgibbsregister BRKADDR0 { 329597883Sgibbs address 0x0E6 329697883Sgibbs access_mode RW 329797883Sgibbs} 329897883Sgibbs 329997883Sgibbsregister BRKADDR1 { 330097883Sgibbs address 0x0E6 330197883Sgibbs access_mode RW 3302102681Sgibbs field BRKDIS 0x80 /* Disable Breakpoint */ 330397883Sgibbs} 330497883Sgibbs 330597883Sgibbs/* 330697883Sgibbs * All Ones 330797883Sgibbs * All reads to this register return the value 0xFF. 330897883Sgibbs */ 330997883Sgibbsregister ALLONES { 331097883Sgibbs address 0x0E8 331197883Sgibbs access_mode RO 331297883Sgibbs allones 331397883Sgibbs} 331497883Sgibbs 331597883Sgibbs/* 331697883Sgibbs * All Zeros 331797883Sgibbs * All reads to this register return the value 0. 331897883Sgibbs */ 331997883Sgibbsregister ALLZEROS { 332097883Sgibbs address 0x0EA 332197883Sgibbs access_mode RO 332297883Sgibbs allzeros 332397883Sgibbs} 332497883Sgibbs 332597883Sgibbs/* 332697883Sgibbs * No Destination 332797883Sgibbs * Writes to this register have no effect. 332897883Sgibbs */ 332997883Sgibbsregister NONE { 333097883Sgibbs address 0x0EA 333197883Sgibbs access_mode WO 333297883Sgibbs none 333397883Sgibbs} 333497883Sgibbs 333597883Sgibbs/* 333697883Sgibbs * Source Index Indirect 333797883Sgibbs * Reading this register is equivalent to reading (register_base + SINDEX) and 333897883Sgibbs * incrementing SINDEX by 1. 333997883Sgibbs */ 334097883Sgibbsregister SINDIR { 334197883Sgibbs address 0x0EC 334297883Sgibbs access_mode RO 334397883Sgibbs} 334497883Sgibbs 334597883Sgibbs/* 334697883Sgibbs * Destination Index Indirect 334797883Sgibbs * Writing this register is equivalent to writing to (register_base + DINDEX) 334897883Sgibbs * and incrementing DINDEX by 1. 334997883Sgibbs */ 335097883Sgibbsregister DINDIR { 335197883Sgibbs address 0x0ED 335297883Sgibbs access_mode WO 335397883Sgibbs} 335497883Sgibbs 335597883Sgibbs/* 335697883Sgibbs * Function One 335797883Sgibbs * 2's complement to bit value conversion. Write the 2's complement value 335897883Sgibbs * (0-7 only) to the top nibble and retrieve the bit indexed by that value 335997883Sgibbs * on the next read of this register. 336097883Sgibbs * Example: 336197883Sgibbs * Write 0x60 336297883Sgibbs * Read 0x40 336397883Sgibbs */ 336497883Sgibbsregister FUNCTION1 { 336597883Sgibbs address 0x0F0 336697883Sgibbs access_mode RW 336797883Sgibbs} 336897883Sgibbs 336997883Sgibbs/* 337097883Sgibbs * Stack 337197883Sgibbs * Window into the stack. Each stack location is 10 bits wide reported 337297883Sgibbs * low byte followed by high byte. There are 8 stack locations. 337397883Sgibbs */ 337497883Sgibbsregister STACK { 337597883Sgibbs address 0x0F2 337697883Sgibbs access_mode RW 337797883Sgibbs} 337897883Sgibbs 337997883Sgibbs/* 338097883Sgibbs * Interrupt Vector 1 Address 338197883Sgibbs * Interrupt branch address for SCS SEQ_INT1 mode 0 and 1 interrupts. 338297883Sgibbs */ 338397883Sgibbsregister INTVEC1_ADDR { 338497883Sgibbs address 0x0F4 338597883Sgibbs access_mode RW 338697883Sgibbs size 2 338797883Sgibbs modes M_CFG 338897883Sgibbs} 338997883Sgibbs 339097883Sgibbs/* 339197883Sgibbs * Current Address 339297883Sgibbs * Address of the SEQRAM instruction currently executing instruction. 339397883Sgibbs */ 339497883Sgibbsregister CURADDR { 339597883Sgibbs address 0x0F4 339697883Sgibbs access_mode RW 339797883Sgibbs size 2 339897883Sgibbs modes M_SCSI 339997883Sgibbs} 340097883Sgibbs 340197883Sgibbs/* 340297883Sgibbs * Interrupt Vector 2 Address 340397883Sgibbs * Interrupt branch address for HST_SEQ_INT2 interrupts. 340497883Sgibbs */ 340597883Sgibbsregister INTVEC2_ADDR { 340697883Sgibbs address 0x0F6 340797883Sgibbs access_mode RW 340897883Sgibbs size 2 340997883Sgibbs modes M_CFG 341097883Sgibbs} 341197883Sgibbs 341297883Sgibbs/* 341397883Sgibbs * Last Address 341497883Sgibbs * Address of the SEQRAM instruction executed prior to the current instruction. 341597883Sgibbs */ 341697883Sgibbsregister LASTADDR { 341797883Sgibbs address 0x0F6 341897883Sgibbs access_mode RW 341997883Sgibbs size 2 342097883Sgibbs modes M_SCSI 342197883Sgibbs} 342297883Sgibbs 342397883Sgibbsregister AHD_PCI_CONFIG_BASE { 342497883Sgibbs address 0x100 342597883Sgibbs access_mode RW 342697883Sgibbs size 256 342797883Sgibbs modes M_CFG 342897883Sgibbs} 342997883Sgibbs 343097883Sgibbs/* ---------------------- Scratch RAM Offsets ------------------------- */ 343197883Sgibbsscratch_ram { 343297883Sgibbs /* Mode Specific */ 343397883Sgibbs address 0x0A0 343497883Sgibbs size 8 343597883Sgibbs modes 0, 1, 2, 3 343697883Sgibbs REG0 { 343797883Sgibbs size 2 343897883Sgibbs } 343997883Sgibbs REG1 { 344097883Sgibbs size 2 344197883Sgibbs } 3442104023Sgibbs REG_ISR { 344397883Sgibbs size 2 344497883Sgibbs } 344597883Sgibbs SG_STATE { 344697883Sgibbs size 1 3447102681Sgibbs field SEGS_AVAIL 0x01 3448102681Sgibbs field LOADING_NEEDED 0x02 3449102681Sgibbs field FETCH_INPROG 0x04 345097883Sgibbs } 345197883Sgibbs /* 345297883Sgibbs * Track whether the transfer byte count for 345397883Sgibbs * the current data phase is odd. 345497883Sgibbs */ 345597883Sgibbs DATA_COUNT_ODD { 345697883Sgibbs size 1 345797883Sgibbs } 345897883Sgibbs} 345997883Sgibbs 346097883Sgibbsscratch_ram { 346197883Sgibbs /* Mode Specific */ 346297883Sgibbs address 0x0F8 346397883Sgibbs size 8 346497883Sgibbs modes 0, 1, 2, 3 346597883Sgibbs LONGJMP_ADDR { 346697883Sgibbs size 2 346797883Sgibbs } 346897883Sgibbs LONGJMP_SCB { 346997883Sgibbs size 2 347097883Sgibbs } 347197883Sgibbs ACCUM_SAVE { 347297883Sgibbs size 1 347397883Sgibbs } 347497883Sgibbs} 347597883Sgibbs 347697883Sgibbs 347797883Sgibbsscratch_ram { 347897883Sgibbs address 0x100 347997883Sgibbs size 128 348097883Sgibbs modes 0, 1, 2, 3 348197883Sgibbs /* 348297883Sgibbs * Per "other-id" execution queues. We use an array of 348397883Sgibbs * tail pointers into lists of SCBs sorted by "other-id". 348497883Sgibbs * The execution head pointer threads the head SCBs for 348597883Sgibbs * each list. 348697883Sgibbs */ 348797883Sgibbs WAITING_SCB_TAILS { 348897883Sgibbs size 32 348997883Sgibbs } 349097883Sgibbs WAITING_TID_HEAD { 349197883Sgibbs size 2 349297883Sgibbs } 349397883Sgibbs WAITING_TID_TAIL { 349497883Sgibbs size 2 349597883Sgibbs } 349697883Sgibbs /* 349797883Sgibbs * SCBID of the next SCB in the new SCB queue. 349897883Sgibbs */ 349997883Sgibbs NEXT_QUEUED_SCB_ADDR { 350097883Sgibbs size 4 350197883Sgibbs } 350297883Sgibbs /* 350397883Sgibbs * head of list of SCBs that have 350497883Sgibbs * completed but have not been 350597883Sgibbs * put into the qoutfifo. 350697883Sgibbs */ 350797883Sgibbs COMPLETE_SCB_HEAD { 350897883Sgibbs size 2 350997883Sgibbs } 351097883Sgibbs /* 351197883Sgibbs * The list of completed SCBs in 351297883Sgibbs * the active DMA. 351397883Sgibbs */ 351497883Sgibbs COMPLETE_SCB_DMAINPROG_HEAD { 351597883Sgibbs size 2 351697883Sgibbs } 351797883Sgibbs /* 351897883Sgibbs * head of list of SCBs that have 351997883Sgibbs * completed but need to be uploaded 352097883Sgibbs * to the host prior to being completed. 352197883Sgibbs */ 352297883Sgibbs COMPLETE_DMA_SCB_HEAD { 352397883Sgibbs size 2 352497883Sgibbs } 352597883Sgibbs /* Counting semaphore to prevent new select-outs */ 352697883Sgibbs QFREEZE_COUNT { 352797883Sgibbs size 2 352897883Sgibbs } 352997883Sgibbs /* 3530107441Sscottl * Mode to restore on legacy idle loop exit. 353197883Sgibbs */ 353297883Sgibbs SAVED_MODE { 353397883Sgibbs size 1 353497883Sgibbs } 353597883Sgibbs /* 353697883Sgibbs * Single byte buffer used to designate the type or message 353797883Sgibbs * to send to a target. 353897883Sgibbs */ 353997883Sgibbs MSG_OUT { 354097883Sgibbs size 1 354197883Sgibbs } 354297883Sgibbs /* Parameters for DMA Logic */ 354397883Sgibbs DMAPARAMS { 354497883Sgibbs size 1 3545102681Sgibbs field PRELOADEN 0x80 3546102681Sgibbs field WIDEODD 0x40 3547102681Sgibbs field SCSIEN 0x20 3548102681Sgibbs field SDMAEN 0x10 3549102681Sgibbs field SDMAENACK 0x10 3550102681Sgibbs field HDMAEN 0x08 3551102681Sgibbs field HDMAENACK 0x08 3552102681Sgibbs field DIRECTION 0x04 /* Set indicates PCI->SCSI */ 3553102681Sgibbs field FIFOFLUSH 0x02 3554102681Sgibbs field FIFORESET 0x01 355597883Sgibbs } 355697883Sgibbs SEQ_FLAGS { 355797883Sgibbs size 1 3558102681Sgibbs field NOT_IDENTIFIED 0x80 3559104023Sgibbs field NO_CDB_SENT 0x40 3560102681Sgibbs field TARGET_CMD_IS_TAGGED 0x40 3561102681Sgibbs field DPHASE 0x20 356297883Sgibbs /* Target flags */ 3563102681Sgibbs field TARG_CMD_PENDING 0x10 3564102681Sgibbs field CMDPHASE_PENDING 0x08 3565102681Sgibbs field DPHASE_PENDING 0x04 3566102681Sgibbs field SPHASE_PENDING 0x02 3567102681Sgibbs field NO_DISCONNECT 0x01 356897883Sgibbs } 356997883Sgibbs /* 357097883Sgibbs * Temporary storage for the 357197883Sgibbs * target/channel/lun of a 357297883Sgibbs * reconnecting target 357397883Sgibbs */ 357497883Sgibbs SAVED_SCSIID { 357597883Sgibbs size 1 357697883Sgibbs } 357797883Sgibbs SAVED_LUN { 357897883Sgibbs size 1 357997883Sgibbs } 358097883Sgibbs /* 358197883Sgibbs * The last bus phase as seen by the sequencer. 358297883Sgibbs */ 358397883Sgibbs LASTPHASE { 358497883Sgibbs size 1 3585102681Sgibbs field CDI 0x80 3586102681Sgibbs field IOI 0x40 3587102681Sgibbs field MSGI 0x20 3588104023Sgibbs field P_BUSFREE 0x01 3589102681Sgibbs enum PHASE_MASK CDO|IOO|MSGO { 3590102681Sgibbs P_DATAOUT 0x0, 3591102681Sgibbs P_DATAIN IOO, 3592102681Sgibbs P_DATAOUT_DT P_DATAOUT|MSGO, 3593102681Sgibbs P_DATAIN_DT P_DATAIN|MSGO, 3594102681Sgibbs P_COMMAND CDO, 3595102681Sgibbs P_MESGOUT CDO|MSGO, 3596102681Sgibbs P_STATUS CDO|IOO, 3597104023Sgibbs P_MESGIN CDO|IOO|MSGO 3598102681Sgibbs } 359997883Sgibbs } 360097883Sgibbs /* 3601107441Sscottl * Value to "or" into the SCBPTR[1] value to 3602107441Sscottl * indicate that an entry in the QINFIFO is valid. 3603107441Sscottl */ 3604107441Sscottl QOUTFIFO_ENTRY_VALID_TAG { 3605107441Sscottl size 1 3606107441Sscottl } 3607107441Sscottl /* 360897883Sgibbs * Base address of our shared data with the kernel driver in host 360997883Sgibbs * memory. This includes the qoutfifo and target mode 361097883Sgibbs * incoming command queue. 361197883Sgibbs */ 361297883Sgibbs SHARED_DATA_ADDR { 361397883Sgibbs size 4 361497883Sgibbs } 361597883Sgibbs /* 361697883Sgibbs * Pointer to location in host memory for next 361797883Sgibbs * position in the qoutfifo. 361897883Sgibbs */ 361997883Sgibbs QOUTFIFO_NEXT_ADDR { 362097883Sgibbs size 4 362197883Sgibbs } 362297883Sgibbs /* 362397883Sgibbs * Kernel and sequencer offsets into the queue of 362497883Sgibbs * incoming target mode command descriptors. The 362597883Sgibbs * queue is full when the KERNEL_TQINPOS == TQINPOS. 362697883Sgibbs */ 362797883Sgibbs KERNEL_TQINPOS { 362897883Sgibbs size 1 362997883Sgibbs } 363097883Sgibbs TQINPOS { 363197883Sgibbs size 1 363297883Sgibbs } 363397883Sgibbs ARG_1 { 363497883Sgibbs size 1 363597883Sgibbs mask SEND_MSG 0x80 363697883Sgibbs mask SEND_SENSE 0x40 363797883Sgibbs mask SEND_REJ 0x20 363897883Sgibbs mask MSGOUT_PHASEMIS 0x10 363997883Sgibbs mask EXIT_MSG_LOOP 0x08 364097883Sgibbs mask CONT_MSG_LOOP_WRITE 0x04 364197883Sgibbs mask CONT_MSG_LOOP_READ 0x03 364297883Sgibbs mask CONT_MSG_LOOP_TARG 0x02 364397883Sgibbs alias RETURN_1 364497883Sgibbs } 364597883Sgibbs ARG_2 { 364697883Sgibbs size 1 364797883Sgibbs alias RETURN_2 364897883Sgibbs } 364997883Sgibbs 365097883Sgibbs /* 365197883Sgibbs * Snapshot of MSG_OUT taken after each message is sent. 365297883Sgibbs */ 365397883Sgibbs LAST_MSG { 365497883Sgibbs size 1 365597883Sgibbs } 365697883Sgibbs 365797883Sgibbs /* 365897883Sgibbs * Sequences the kernel driver has okayed for us. This allows 365997883Sgibbs * the driver to do things like prevent initiator or target 366097883Sgibbs * operations. 366197883Sgibbs */ 366297883Sgibbs SCSISEQ_TEMPLATE { 366397883Sgibbs size 1 3664102681Sgibbs field MANUALCTL 0x40 3665102681Sgibbs field ENSELI 0x20 3666102681Sgibbs field ENRSELI 0x10 3667102681Sgibbs field MANUALP 0x0C 3668102681Sgibbs field ENAUTOATNP 0x02 3669102681Sgibbs field ALTSTIM 0x01 367097883Sgibbs } 367197883Sgibbs 367297883Sgibbs /* 367397883Sgibbs * The initiator specified tag for this target mode transaction. 367497883Sgibbs */ 367597883Sgibbs INITIATOR_TAG { 367697883Sgibbs size 1 367797883Sgibbs } 367897883Sgibbs 367997883Sgibbs SEQ_FLAGS2 { 368097883Sgibbs size 1 3681102681Sgibbs field TARGET_MSG_PENDING 0x02 3682102681Sgibbs field SELECTOUT_QFROZEN 0x04 368397883Sgibbs } 3684104023Sgibbs 3685104023Sgibbs ALLOCFIFO_SCBPTR { 3686104023Sgibbs size 2 3687104023Sgibbs } 3688104023Sgibbs 368997883Sgibbs /* 369097883Sgibbs * Target-mode CDB type to CDB length table used 369197883Sgibbs * in non-packetized operation. 369297883Sgibbs */ 369397883Sgibbs CMDSIZE_TABLE { 369497883Sgibbs size 8 369597883Sgibbs } 369697883Sgibbs} 369797883Sgibbs 369897883Sgibbs/************************* Hardware SCB Definition ****************************/ 369997883Sgibbsscb { 370097883Sgibbs address 0x180 370197883Sgibbs size 64 370297883Sgibbs modes 0, 1, 2, 3 370397883Sgibbs SCB_RESIDUAL_DATACNT { 370497883Sgibbs size 4 370597883Sgibbs alias SCB_CDB_STORE 370697883Sgibbs } 370797883Sgibbs SCB_RESIDUAL_SGPTR { 370897883Sgibbs size 4 370997883Sgibbs alias SCB_CDB_PTR 3710102681Sgibbs field SG_ADDR_MASK 0xf8 /* In the last byte */ 3711102681Sgibbs field SG_OVERRUN_RESID 0x02 /* In the first byte */ 3712102681Sgibbs field SG_LIST_NULL 0x01 /* In the first byte */ 371397883Sgibbs } 371497883Sgibbs SCB_SCSI_STATUS { 371597883Sgibbs size 1 371697883Sgibbs } 371797883Sgibbs SCB_TARGET_PHASES { 371897883Sgibbs size 1 371997883Sgibbs } 372097883Sgibbs SCB_TARGET_DATA_DIR { 372197883Sgibbs size 1 372297883Sgibbs } 372397883Sgibbs SCB_TARGET_ITAG { 372497883Sgibbs size 1 372597883Sgibbs } 372697883Sgibbs SCB_SENSE_BUSADDR { 372797883Sgibbs /* 372897883Sgibbs * Only valid if CDB length is less than 13 bytes or 372997883Sgibbs * we are using a CDB pointer. Otherwise contains 373097883Sgibbs * the last 4 bytes of embedded cdb information. 373197883Sgibbs */ 373297883Sgibbs size 4 373397883Sgibbs alias SCB_NEXT_COMPLETE 373497883Sgibbs } 3735104023Sgibbs SCB_TAG { 3736104023Sgibbs size 2 3737104023Sgibbs } 373897883Sgibbs SCB_CDB_LEN { 373997883Sgibbs size 1 3740102681Sgibbs field SCB_CDB_LEN_PTR 0x80 /* CDB in host memory */ 374197883Sgibbs } 374297883Sgibbs SCB_TASK_MANAGEMENT { 374397883Sgibbs size 1 374497883Sgibbs } 374597883Sgibbs SCB_NEXT { 374697883Sgibbs alias SCB_NEXT_SCB_BUSADDR 374797883Sgibbs size 2 374897883Sgibbs } 374997883Sgibbs SCB_NEXT2 { 375097883Sgibbs size 2 375197883Sgibbs } 375297883Sgibbs SCB_DATAPTR { 375397883Sgibbs size 8 375497883Sgibbs } 375597883Sgibbs SCB_DATACNT { 375697883Sgibbs /* 375797883Sgibbs * The last byte is really the high address bits for 375897883Sgibbs * the data address. 375997883Sgibbs */ 376097883Sgibbs size 4 3761102681Sgibbs field SG_LAST_SEG 0x80 /* In the fourth byte */ 3762102681Sgibbs field SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */ 376397883Sgibbs } 376497883Sgibbs SCB_SGPTR { 376597883Sgibbs size 4 3766102681Sgibbs field SG_STATUS_VALID 0x04 /* In the first byte */ 3767102681Sgibbs field SG_FULL_RESID 0x02 /* In the first byte */ 3768102681Sgibbs field SG_LIST_NULL 0x01 /* In the first byte */ 376997883Sgibbs } 377097883Sgibbs SCB_CONTROL { 377197883Sgibbs size 1 3772102681Sgibbs field TARGET_SCB 0x80 3773102681Sgibbs field DISCENB 0x40 3774102681Sgibbs field TAG_ENB 0x20 3775102681Sgibbs field MK_MESSAGE 0x10 3776102681Sgibbs field STATUS_RCVD 0x08 3777102681Sgibbs field DISCONNECTED 0x04 3778102681Sgibbs field SCB_TAG_TYPE 0x03 377997883Sgibbs } 378097883Sgibbs SCB_SCSIID { 378197883Sgibbs size 1 3782102681Sgibbs field TID 0xF0 3783102681Sgibbs field OID 0x0F 378497883Sgibbs } 378597883Sgibbs SCB_LUN { 378697883Sgibbs size 1 3787102681Sgibbs field LID 0xff 378897883Sgibbs } 378997883Sgibbs SCB_TASK_ATTRIBUTE { 379097883Sgibbs size 1 379197883Sgibbs } 379297883Sgibbs SCB_BUSADDR { 379397883Sgibbs size 4 379497883Sgibbs } 3795102681Sgibbs SCB_SPARE { 3796102681Sgibbs size 8 3797102681Sgibbs alias SCB_PKT_LUN 3798102681Sgibbs } 379997883Sgibbs SCB_DISCONNECTED_LISTS { 3800102681Sgibbs size 8 380197883Sgibbs } 380297883Sgibbs} 380397883Sgibbs 380497883Sgibbs/*********************************** Constants ********************************/ 380597883Sgibbsconst MK_MESSAGE_BIT_OFFSET 4 380697883Sgibbsconst TID_SHIFT 4 380797883Sgibbsconst TARGET_CMD_CMPLT 0xfe 380897883Sgibbsconst INVALID_ADDR 0x80 380997883Sgibbs#define SCB_LIST_NULL 0xff 3810102681Sgibbs#define QOUTFIFO_ENTRY_VALID_TOGGLE 0x80 381197883Sgibbs 381297883Sgibbsconst CCSGADDR_MAX 0x80 381397883Sgibbsconst CCSCBADDR_MAX 0x80 381497883Sgibbsconst CCSGRAM_MAXSEGS 16 381597883Sgibbs 381697883Sgibbs/* Selection Timeout Timer Constants */ 381797883Sgibbsconst STIMESEL_SHIFT 3 381897883Sgibbsconst STIMESEL_MIN 0x18 381997883Sgibbsconst STIMESEL_BUG_ADJ 0x8 382097883Sgibbs 382197883Sgibbs/* WDTR Message values */ 382297883Sgibbsconst BUS_8_BIT 0x00 382397883Sgibbsconst BUS_16_BIT 0x01 382497883Sgibbsconst BUS_32_BIT 0x02 382597883Sgibbs 382697883Sgibbs/* Offset maximums */ 382797883Sgibbsconst MAX_OFFSET 0xfe 3828107441Sscottlconst MAX_OFFSET_PACED 0xfe 3829107441Sscottlconst MAX_OFFSET_PACED_BUG 0x7f 3830107441Sscottl/* 3831107441Sscottl * Some 160 devices incorrectly accept 0xfe as a 3832107441Sscottl * sync offset, but will overrun this value. Limit 3833107441Sscottl * to 0x7f for speed lower than U320 which will 3834107441Sscottl * avoid the persistent sync offset overruns. 3835107441Sscottl */ 3836107441Sscottlconst MAX_OFFSET_NON_PACED 0x7f 383797883Sgibbsconst HOST_MSG 0xff 383897883Sgibbs 383997883Sgibbs/* 384097883Sgibbs * The size of our sense buffers. 384197883Sgibbs * Sense buffer mapping can be handled in either of two ways. 384297883Sgibbs * The first is to allocate a dmamap for each transaction. 384397883Sgibbs * Depending on the architecture, dmamaps can be costly. The 384497883Sgibbs * alternative is to statically map the buffers in much the same 384597883Sgibbs * way we handle our scatter gather lists. The driver implements 384697883Sgibbs * the later. 384797883Sgibbs */ 384897883Sgibbsconst AHD_SENSE_BUFSIZE 256 384997883Sgibbs 385097883Sgibbs/* Target mode command processing constants */ 385197883Sgibbsconst CMD_GROUP_CODE_SHIFT 0x05 385297883Sgibbs 385397883Sgibbsconst STATUS_BUSY 0x08 385497883Sgibbsconst STATUS_QUEUE_FULL 0x28 385597883Sgibbsconst STATUS_PKT_SENSE 0xFF 385697883Sgibbsconst TARGET_DATA_IN 1 385797883Sgibbs 3858102681Sgibbsconst SCB_TRANSFER_SIZE_FULL_LUN 56 3859102681Sgibbsconst SCB_TRANSFER_SIZE_1BYTE_LUN 48 386097883Sgibbs/* PKT_OVERRUN_BUFSIZE must be a multiple of 256 less than 64K */ 386197883Sgibbsconst PKT_OVERRUN_BUFSIZE 512 386297883Sgibbs 386397883Sgibbs/* 386497883Sgibbs * Downloaded (kernel inserted) constants 386597883Sgibbs */ 386697883Sgibbsconst SG_PREFETCH_CNT download 386797883Sgibbsconst SG_PREFETCH_CNT_LIMIT download 386897883Sgibbsconst SG_PREFETCH_ALIGN_MASK download 386997883Sgibbsconst SG_PREFETCH_ADDR_MASK download 387097883Sgibbsconst SG_SIZEOF download 387197883Sgibbsconst PKT_OVERRUN_BUFOFFSET download 3872102681Sgibbsconst SCB_TRANSFER_SIZE download 387397883Sgibbs 387497883Sgibbs/* 387597883Sgibbs * BIOS SCB offsets 387697883Sgibbs */ 387797883Sgibbsconst NVRAM_SCB_OFFSET 0x2C 3878