aic79xx.reg revision 107441
1/* 2 * Aic79xx register and scratch ram definitions. 3 * 4 * Copyright (c) 1994-2001 Justin T. Gibbs. 5 * Copyright (c) 2000-2002 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $FreeBSD: head/sys/dev/aic7xxx/aic79xx.reg 107441 2002-12-01 08:13:37Z scottl $ 41 */ 42VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#55 $" 43 44/* 45 * This file is processed by the aic7xxx_asm utility for use in assembling 46 * firmware for the aic79xx family of SCSI host adapters as well as to generate 47 * a C header file for use in the kernel portion of the Aic79xx driver. 48 */ 49 50/* Register window Modes */ 51#define M_DFF0 0 52#define M_DFF1 1 53#define M_CCHAN 2 54#define M_SCSI 3 55#define M_CFG 4 56#define M_DST_SHIFT 4 57 58#define MK_MODE(src, dst) ((src) | ((dst) << M_DST_SHIFT)) 59#define SET_MODE(src, dst) \ 60 SET_SRC_MODE src; \ 61 SET_DST_MODE dst; \ 62 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ 63 mvi MK_MODE(src, dst) call set_mode_work_around; \ 64 } else { \ 65 mvi MODE_PTR, MK_MODE(src, dst); \ 66 } 67 68#define TOGGLE_DFF_MODE \ 69 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ 70 call toggle_dff_mode_work_around; \ 71 } else { \ 72 xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1); \ 73 } 74 75#define RESTORE_MODE(mode) \ 76 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ 77 mov mode call set_mode_work_around; \ 78 } else { \ 79 mov MODE_PTR, mode; \ 80 } 81 82#define SET_SEQINTCODE(code) \ 83 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { \ 84 mvi code call set_seqint_work_around; \ 85 } else { \ 86 mvi SEQINTCODE, code; \ 87 } 88 89/* 90 * Mode Pointer 91 * Controls which of the 5, 512byte, address spaces should be used 92 * as the source and destination of any register accesses in our 93 * register window. 94 */ 95register MODE_PTR { 96 address 0x000 97 access_mode RW 98 field DST_MODE 0x70 99 field SRC_MODE 0x07 100 mode_pointer 101} 102 103const SRC_MODE_SHIFT 0 104const DST_MODE_SHIFT 4 105 106/* 107 * Host Interrupt Status 108 */ 109register INTSTAT { 110 address 0x001 111 access_mode RW 112 field HWERRINT 0x80 113 field BRKADRINT 0x40 114 field SWTMINT 0x20 115 field PCIINT 0x10 116 field SCSIINT 0x08 117 field SEQINT 0x04 118 field CMDCMPLT 0x02 119 field SPLTINT 0x01 120 mask INT_PEND 0xFF 121} 122 123/* 124 * Sequencer Interrupt Code 125 */ 126register SEQINTCODE { 127 address 0x002 128 access_mode RW 129 field { 130 NO_SEQINT, /* No seqint pending. */ 131 BAD_PHASE, /* unknown scsi bus phase */ 132 SEND_REJECT, /* sending a message reject */ 133 PROTO_VIOLATION, /* Protocol Violation */ 134 NO_MATCH, /* no cmd match for reconnect */ 135 IGN_WIDE_RES, /* Complex IGN Wide Res Msg */ 136 PDATA_REINIT, /* 137 * Returned to data phase 138 * that requires data 139 * transfer pointers to be 140 * recalculated from the 141 * transfer residual. 142 */ 143 HOST_MSG_LOOP, /* 144 * The bus is ready for the 145 * host to perform another 146 * message transaction. This 147 * mechanism is used for things 148 * like sync/wide negotiation 149 * that require a kernel based 150 * message state engine. 151 */ 152 BAD_STATUS, /* Bad status from target */ 153 DATA_OVERRUN, /* 154 * Target attempted to write 155 * beyond the bounds of its 156 * command. 157 */ 158 MKMSG_FAILED, /* 159 * Target completed command 160 * without honoring our ATN 161 * request to issue a message. 162 */ 163 MISSED_BUSFREE, /* 164 * The sequencer never saw 165 * the bus go free after 166 * either a command complete 167 * or disconnect message. 168 */ 169 DUMP_CARD_STATE, 170 ILLEGAL_PHASE, 171 INVALID_SEQINT, 172 CFG4ISTAT_INTR, 173 STATUS_OVERRUN, 174 CFG4OVERRUN, 175 ENTERING_NONPACK, 176 TRACEPOINT0, 177 TRACEPOINT1, 178 TRACEPOINT2, 179 TRACEPOINT3, 180 SAW_HWERR 181 } 182} 183 184/* 185 * Clear Host Interrupt 186 */ 187register CLRINT { 188 address 0x003 189 access_mode WO 190 field CLRHWERRINT 0x80 /* Rev B or greater */ 191 field CLRBRKADRINT 0x40 192 field CLRSWTMINT 0x20 193 field CLRSCSIINT 0x08 194 field CLRSEQINT 0x04 195 field CLRCMDINT 0x02 196 field CLRSPLTINT 0x01 197} 198 199/* 200 * Error Register 201 */ 202register ERROR { 203 address 0x004 204 access_mode RO 205 field CIOPARERR 0x80 206 field CIOACCESFAIL 0x40 /* Rev B or greater */ 207 field MPARERR 0x20 208 field DPARERR 0x10 209 field SQPARERR 0x08 210 field ILLOPCODE 0x04 211 field DSCTMOUT 0x02 212} 213 214/* 215 * Clear Error 216 */ 217register CLRERR { 218 address 0x004 219 access_mode WO 220 field CLRCIOPARERR 0x80 221 field CLRCIOACCESFAIL 0x40 /* Rev B or greater */ 222 field CLRMPARERR 0x20 223 field CLRDPARERR 0x10 224 field CLRSQPARERR 0x08 225 field CLRILLOPCODE 0x04 226 field CLRDSCTMOUT 0x02 227} 228 229/* 230 * Host Control Register 231 * Overall host control of the device. 232 */ 233register HCNTRL { 234 address 0x005 235 access_mode RW 236 field SEQ_RESET 0x80 /* Rev B or greater */ 237 field POWRDN 0x40 238 field SWINT 0x10 239 field SWTIMER_START_B 0x08 /* Rev B or greater */ 240 field PAUSE 0x04 241 field INTEN 0x02 242 field CHIPRST 0x01 243 field CHIPRSTACK 0x01 244} 245 246/* 247 * Host New SCB Queue Offset 248 */ 249register HNSCB_QOFF { 250 address 0x006 251 access_mode RW 252 size 2 253} 254 255/* 256 * Host Empty SCB Queue Offset 257 */ 258register HESCB_QOFF { 259 address 0x008 260 access_mode RW 261} 262 263/* 264 * Host Mailbox 265 */ 266register HS_MAILBOX { 267 address 0x0B 268 access_mode RW 269 mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */ 270} 271 272/* 273 * Sequencer Interupt Status 274 */ 275register SEQINTSTAT { 276 address 0x0C 277 access_mode RO 278 field SEQ_SWTMRTO 0x10 279 field SEQ_SEQINT 0x08 280 field SEQ_SCSIINT 0x04 281 field SEQ_PCIINT 0x02 282 field SEQ_SPLTINT 0x01 283} 284 285/* 286 * Clear SEQ Interrupt 287 */ 288register CLRSEQINTSTAT { 289 address 0x0C0 290 access_mode WO 291 field CLRSEQ_SWTMRTO 0x10 292 field CLRSEQ_SEQINT 0x08 293 field CLRSEQ_SCSIINT 0x04 294 field CLRSEQ_PCIINT 0x02 295 field CLRSEQ_SPLTINT 0x01 296} 297 298/* 299 * Software Timer 300 */ 301register SWTIMER { 302 address 0x0E0 303 access_mode RW 304 size 2 305} 306 307/* 308 * SEQ New SCB Queue Offset 309 */ 310register SNSCB_QOFF { 311 address 0x010 312 access_mode RW 313 size 2 314 modes M_CCHAN 315} 316 317/* 318 * SEQ Empty SCB Queue Offset 319 */ 320register SESCB_QOFF { 321 address 0x012 322 access_mode RW 323 modes M_CCHAN 324} 325 326/* 327 * SEQ Done SCB Queue Offset 328 */ 329register SDSCB_QOFF { 330 address 0x014 331 access_mode RW 332 modes M_CCHAN 333 size 2 334} 335 336/* 337 * Queue Offset Control & Status 338 */ 339register QOFF_CTLSTA { 340 address 0x016 341 access_mode RW 342 modes M_CCHAN 343 field EMPTY_SCB_AVAIL 0x80 344 field NEW_SCB_AVAIL 0x40 345 field SDSCB_ROLLOVR 0x20 346 field HS_MAILBOX_ACT 0x10 347 field SCB_QSIZE 0x0F { 348 SCB_QSIZE_4, 349 SCB_QSIZE_8, 350 SCB_QSIZE_16, 351 SCB_QSIZE_32, 352 SCB_QSIZE_64, 353 SCB_QSIZE_128, 354 SCB_QSIZE_256, 355 SCB_QSIZE_512, 356 SCB_QSIZE_1024, 357 SCB_QSIZE_2048, 358 SCB_QSIZE_4096, 359 SCB_QSIZE_8192, 360 SCB_QSIZE_16384 361 } 362} 363 364/* 365 * Interrupt Control 366 */ 367register INTCTL { 368 address 0x018 369 access_mode RW 370 field SWTMINTMASK 0x80 371 field SWTMINTEN 0x40 372 field SWTIMER_START 0x20 373 field AUTOCLRCMDINT 0x10 374 field PCIINTEN 0x08 375 field SCSIINTEN 0x04 376 field SEQINTEN 0x02 377 field SPLTINTEN 0x01 378} 379 380/* 381 * Data FIFO Control 382 */ 383register DFCNTRL { 384 address 0x019 385 access_mode RW 386 modes M_DFF0, M_DFF1 387 field PRELOADEN 0x80 388 field SCSIENWRDIS 0x40 /* Rev B only. */ 389 field SCSIEN 0x20 390 field SCSIENACK 0x20 391 field HDMAEN 0x08 392 field HDMAENACK 0x08 393 field DIRECTION 0x04 394 field DIRECTIONACK 0x04 395 field FIFOFLUSH 0x02 396 field FIFOFLUSHACK 0x02 397 field DIRECTIONEN 0x01 398} 399 400/* 401 * Device Space Command 0 402 */ 403register DSCOMMAND0 { 404 address 0x019 405 access_mode RW 406 modes M_CFG 407 field CACHETHEN 0x80 /* Cache Threshold enable */ 408 field DPARCKEN 0x40 /* Data Parity Check Enable */ 409 field MPARCKEN 0x20 /* Memory Parity Check Enable */ 410 field EXTREQLCK 0x10 /* External Request Lock */ 411 field DISABLE_TWATE 0x02 /* Rev B or greater */ 412 field CIOPARCKEN 0x01 /* Internal bus parity error enable */ 413} 414 415/* 416 * Data FIFO Status 417 */ 418register DFSTATUS { 419 address 0x01A 420 access_mode RO 421 modes M_DFF0, M_DFF1 422 field PRELOAD_AVAIL 0x80 423 field PKT_PRELOAD_AVAIL 0x40 424 field MREQPEND 0x10 425 field HDONE 0x08 426 field DFTHRESH 0x04 427 field FIFOFULL 0x02 428 field FIFOEMP 0x01 429} 430 431/* 432 * S/G Cache Pointer 433 */ 434register SG_CACHE_PRE { 435 address 0x01B 436 access_mode WO 437 modes M_DFF0, M_DFF1 438 field SG_ADDR_MASK 0xf8 439 field ODD_SEG 0x04 440 field LAST_SEG 0x02 441} 442 443register SG_CACHE_SHADOW { 444 address 0x01B 445 access_mode RO 446 modes M_DFF0, M_DFF1 447 field SG_ADDR_MASK 0xf8 448 field ODD_SEG 0x04 449 field LAST_SEG 0x02 450 field LAST_SEG_DONE 0x01 451} 452 453/* 454 * Arbiter Control 455 */ 456register ARBCTL { 457 address 0x01B 458 access_mode RW 459 modes M_CFG 460 field RESET_HARB 0x80 461 field RETRY_SWEN 0x08 462 field USE_TIME 0x07 463} 464 465/* 466 * Data Channel Host Address 467 */ 468register HADDR { 469 address 0x070 470 access_mode RW 471 size 8 472 modes M_DFF0, M_DFF1 473} 474 475/* 476 * Host Overlay DMA Address 477 */ 478register HODMAADR { 479 address 0x070 480 access_mode RW 481 size 8 482 modes M_SCSI 483} 484 485/* 486 * PCI PLL Delay. 487 */ 488register PLLDELAY { 489 address 0x070 490 access_mode RW 491 size 1 492 modes M_CFG 493 field SPLIT_DROP_REQ 0x80 494} 495 496/* 497 * Data Channel Host Count 498 */ 499register HCNT { 500 address 0x078 501 access_mode RW 502 size 3 503 modes M_DFF0, M_DFF1 504} 505 506/* 507 * Host Overlay DMA Count 508 */ 509register HODMACNT { 510 address 0x078 511 access_mode RW 512 size 2 513 modes M_SCSI 514} 515 516/* 517 * Host Overlay DMA Enable 518 */ 519register HODMAEN { 520 address 0x07A 521 access_mode RW 522 modes M_SCSI 523} 524 525/* 526 * Scatter/Gather Host Address 527 */ 528register SGHADDR { 529 address 0x07C 530 access_mode RW 531 size 8 532 modes M_DFF0, M_DFF1 533} 534 535/* 536 * SCB Host Address 537 */ 538register SCBHADDR { 539 address 0x07C 540 access_mode RW 541 size 8 542 modes M_CCHAN 543} 544 545/* 546 * Scatter/Gather Host Count 547 */ 548register SGHCNT { 549 address 0x084 550 access_mode RW 551 modes M_DFF0, M_DFF1 552} 553 554/* 555 * SCB Host Count 556 */ 557register SCBHCNT { 558 address 0x084 559 access_mode RW 560 modes M_CCHAN 561} 562 563/* 564 * Data FIFO Threshold 565 */ 566register DFF_THRSH { 567 address 0x088 568 access_mode RW 569 modes M_CFG 570 field WR_DFTHRSH 0x70 { 571 WR_DFTHRSH_MIN, 572 WR_DFTHRSH_25, 573 WR_DFTHRSH_50, 574 WR_DFTHRSH_63, 575 WR_DFTHRSH_75, 576 WR_DFTHRSH_85, 577 WR_DFTHRSH_90, 578 WR_DFTHRSH_MAX 579 } 580 field RD_DFTHRSH 0x07 { 581 RD_DFTHRSH_MIN, 582 RD_DFTHRSH_25, 583 RD_DFTHRSH_50, 584 RD_DFTHRSH_63, 585 RD_DFTHRSH_75, 586 RD_DFTHRSH_85, 587 RD_DFTHRSH_90, 588 RD_DFTHRSH_MAX 589 } 590} 591 592/* 593 * ROM Address 594 */ 595register ROMADDR { 596 address 0x08A 597 access_mode RW 598 size 3 599} 600 601/* 602 * ROM Control 603 */ 604register ROMCNTRL { 605 address 0x08D 606 access_mode RW 607 field ROMOP 0xE0 608 field ROMSPD 0x18 609 field REPEAT 0x02 610 field RDY 0x01 611} 612 613/* 614 * ROM Data 615 */ 616register ROMDATA { 617 address 0x08E 618 access_mode RW 619} 620 621/* 622 * Data Channel Receive Message 0 623 */ 624register DCHRXMSG0 { 625 address 0x090 626 access_mode RO 627 modes M_DFF0, M_DFF1 628 field CDNUM 0xF8 629 field CFNUM 0x07 630} 631 632/* 633 * CMC Recieve Message 0 634 */ 635register CMCRXMSG0 { 636 address 0x090 637 access_mode RO 638 modes M_CCHAN 639 field CDNUM 0xF8 640 field CFNUM 0x07 641} 642 643/* 644 * Overlay Recieve Message 0 645 */ 646register OVLYRXMSG0 { 647 address 0x090 648 access_mode RO 649 modes M_SCSI 650 field CDNUM 0xF8 651 field CFNUM 0x07 652} 653 654/* 655 * Relaxed Order Enable 656 */ 657register ROENABLE { 658 address 0x090 659 access_mode RW 660 modes M_CFG 661 field MSIROEN 0x20 662 field OVLYROEN 0x10 663 field CMCROEN 0x08 664 field SGROEN 0x04 665 field DCH1ROEN 0x02 666 field DCH0ROEN 0x01 667} 668 669/* 670 * Data Channel Receive Message 1 671 */ 672register DCHRXMSG1 { 673 address 0x091 674 access_mode RO 675 modes M_DFF0, M_DFF1 676 field CBNUM 0xFF 677} 678 679/* 680 * CMC Recieve Message 1 681 */ 682register CMCRXMSG1 { 683 address 0x091 684 access_mode RO 685 modes M_CCHAN 686 field CBNUM 0xFF 687} 688 689/* 690 * Overlay Recieve Message 1 691 */ 692register OVLYRXMSG1 { 693 address 0x091 694 access_mode RO 695 modes M_SCSI 696 field CBNUM 0xFF 697} 698 699/* 700 * No Snoop Enable 701 */ 702register NSENABLE { 703 address 0x091 704 access_mode RW 705 modes M_CFG 706 field MSINSEN 0x20 707 field OVLYNSEN 0x10 708 field CMCNSEN 0x08 709 field SGNSEN 0x04 710 field DCH1NSEN 0x02 711 field DCH0NSEN 0x01 712} 713 714/* 715 * Data Channel Receive Message 2 716 */ 717register DCHRXMSG2 { 718 address 0x092 719 access_mode RO 720 modes M_DFF0, M_DFF1 721 field MINDEX 0xFF 722} 723 724/* 725 * CMC Recieve Message 2 726 */ 727register CMCRXMSG2 { 728 address 0x092 729 access_mode RO 730 modes M_CCHAN 731 field MINDEX 0xFF 732} 733 734/* 735 * Overlay Recieve Message 2 736 */ 737register OVLYRXMSG2 { 738 address 0x092 739 access_mode RO 740 modes M_SCSI 741 field MINDEX 0xFF 742} 743 744/* 745 * Outstanding Split Transactions 746 */ 747register OST { 748 address 0x092 749 access_mode RW 750 modes M_CFG 751} 752 753/* 754 * Data Channel Receive Message 3 755 */ 756register DCHRXMSG3 { 757 address 0x093 758 access_mode RO 759 modes M_DFF0, M_DFF1 760 field MCLASS 0x0F 761} 762 763/* 764 * CMC Recieve Message 3 765 */ 766register CMCRXMSG3 { 767 address 0x093 768 access_mode RO 769 modes M_CCHAN 770 field MCLASS 0x0F 771} 772 773/* 774 * Overlay Recieve Message 3 775 */ 776register OVLYRXMSG3 { 777 address 0x093 778 access_mode RO 779 modes M_SCSI 780 field MCLASS 0x0F 781} 782 783/* 784 * PCI-X Control 785 */ 786register PCIXCTL { 787 address 0x093 788 access_mode RW 789 modes M_CFG 790 field SERRPULSE 0x80 791 field UNEXPSCIEN 0x20 792 field SPLTSMADIS 0x10 793 field SPLTSTADIS 0x08 794 field SRSPDPEEN 0x04 795 field TSCSERREN 0x02 796 field CMPABCDIS 0x01 797} 798 799/* 800 * CMC Sequencer Byte Count 801 */ 802register CMCSEQBCNT { 803 address 0x094 804 access_mode RO 805 modes M_CCHAN 806} 807 808/* 809 * Overlay Sequencer Byte Count 810 */ 811register OVLYSEQBCNT { 812 address 0x094 813 access_mode RO 814 modes M_SCSI 815} 816 817/* 818 * Data Channel Sequencer Byte Count 819 */ 820register DCHSEQBCNT { 821 address 0x094 822 access_mode RO 823 size 2 824 modes M_DFF0, M_DFF1 825} 826 827/* 828 * Data Channel Split Status 0 829 */ 830register DCHSPLTSTAT0 { 831 address 0x096 832 access_mode RW 833 modes M_DFF0, M_DFF1 834 field STAETERM 0x80 835 field SCBCERR 0x40 836 field SCADERR 0x20 837 field SCDATBUCKET 0x10 838 field CNTNOTCMPLT 0x08 839 field RXOVRUN 0x04 840 field RXSCEMSG 0x02 841 field RXSPLTRSP 0x01 842} 843 844/* 845 * CMC Split Status 0 846 */ 847register CMCSPLTSTAT0 { 848 address 0x096 849 access_mode RW 850 modes M_CCHAN 851 field STAETERM 0x80 852 field SCBCERR 0x40 853 field SCADERR 0x20 854 field SCDATBUCKET 0x10 855 field CNTNOTCMPLT 0x08 856 field RXOVRUN 0x04 857 field RXSCEMSG 0x02 858 field RXSPLTRSP 0x01 859} 860 861/* 862 * Overlay Split Status 0 863 */ 864register OVLYSPLTSTAT0 { 865 address 0x096 866 access_mode RW 867 modes M_SCSI 868 field STAETERM 0x80 869 field SCBCERR 0x40 870 field SCADERR 0x20 871 field SCDATBUCKET 0x10 872 field CNTNOTCMPLT 0x08 873 field RXOVRUN 0x04 874 field RXSCEMSG 0x02 875 field RXSPLTRSP 0x01 876} 877 878/* 879 * Data Channel Split Status 1 880 */ 881register DCHSPLTSTAT1 { 882 address 0x097 883 access_mode RW 884 modes M_DFF0, M_DFF1 885 field RXDATABUCKET 0x01 886} 887 888/* 889 * CMC Split Status 1 890 */ 891register CMCSPLTSTAT1 { 892 address 0x097 893 access_mode RW 894 modes M_CCHAN 895 field RXDATABUCKET 0x01 896} 897 898/* 899 * Overlay Split Status 1 900 */ 901register OVLYSPLTSTAT1 { 902 address 0x097 903 access_mode RW 904 modes M_SCSI 905 field RXDATABUCKET 0x01 906} 907 908/* 909 * S/G Receive Message 0 910 */ 911register SGRXMSG0 { 912 address 0x098 913 access_mode RO 914 modes M_DFF0, M_DFF1 915 field CDNUM 0xF8 916 field CFNUM 0x07 917} 918 919/* 920 * S/G Receive Message 1 921 */ 922register SGRXMSG1 { 923 address 0x099 924 access_mode RO 925 modes M_DFF0, M_DFF1 926 field CBNUM 0xFF 927} 928 929/* 930 * S/G Receive Message 2 931 */ 932register SGRXMSG2 { 933 address 0x09A 934 access_mode RO 935 modes M_DFF0, M_DFF1 936 field MINDEX 0xFF 937} 938 939/* 940 * S/G Receive Message 3 941 */ 942register SGRXMSG3 { 943 address 0x09B 944 access_mode RO 945 modes M_DFF0, M_DFF1 946 field MCLASS 0x0F 947} 948 949/* 950 * Slave Split Out Address 0 951 */ 952register SLVSPLTOUTADR0 { 953 address 0x098 954 access_mode RO 955 modes M_SCSI 956 field LOWER_ADDR 0x7F 957} 958 959/* 960 * Slave Split Out Address 1 961 */ 962register SLVSPLTOUTADR1 { 963 address 0x099 964 access_mode RO 965 modes M_SCSI 966 field REQ_DNUM 0xF8 967 field REQ_FNUM 0x07 968} 969 970/* 971 * Slave Split Out Address 2 972 */ 973register SLVSPLTOUTADR2 { 974 address 0x09A 975 access_mode RO 976 modes M_SCSI 977 field REQ_BNUM 0xFF 978} 979 980/* 981 * Slave Split Out Address 3 982 */ 983register SLVSPLTOUTADR3 { 984 address 0x09B 985 access_mode RO 986 modes M_SCSI 987 field RLXORD 020 988 field TAG_NUM 0x1F 989} 990 991/* 992 * SG Sequencer Byte Count 993 */ 994register SGSEQBCNT { 995 address 0x09C 996 access_mode RO 997 modes M_DFF0, M_DFF1 998} 999 1000/* 1001 * Slave Split Out Attribute 0 1002 */ 1003register SLVSPLTOUTATTR0 { 1004 address 0x09C 1005 access_mode RO 1006 modes M_SCSI 1007 field LOWER_BCNT 0xFF 1008} 1009 1010/* 1011 * Slave Split Out Attribute 1 1012 */ 1013register SLVSPLTOUTATTR1 { 1014 address 0x09D 1015 access_mode RO 1016 modes M_SCSI 1017 field CMPLT_DNUM 0xF8 1018 field CMPLT_FNUM 0x07 1019} 1020 1021/* 1022 * Slave Split Out Attribute 2 1023 */ 1024register SLVSPLTOUTATTR2 { 1025 address 0x09E 1026 access_mode RO 1027 size 2 1028 modes M_SCSI 1029 field CMPLT_BNUM 0xFF 1030} 1031/* 1032 * S/G Split Status 0 1033 */ 1034register SGSPLTSTAT0 { 1035 address 0x09E 1036 access_mode RW 1037 modes M_DFF0, M_DFF1 1038 field STAETERM 0x80 1039 field SCBCERR 0x40 1040 field SCADERR 0x20 1041 field SCDATBUCKET 0x10 1042 field CNTNOTCMPLT 0x08 1043 field RXOVRUN 0x04 1044 field RXSCEMSG 0x02 1045 field RXSPLTRSP 0x01 1046} 1047 1048/* 1049 * S/G Split Status 1 1050 */ 1051register SGSPLTSTAT1 { 1052 address 0x09F 1053 access_mode RW 1054 modes M_DFF0, M_DFF1 1055 field RXDATABUCKET 0x01 1056} 1057 1058/* 1059 * Special Function 1060 */ 1061register SFUNCT { 1062 address 0x09f 1063 access_mode RW 1064 modes M_CFG 1065 field TEST_GROUP 0xF0 1066 field TEST_NUM 0x0F 1067} 1068 1069/* 1070 * Data FIFO 0 PCI Status 1071 */ 1072register DF0PCISTAT { 1073 address 0x0A0 1074 access_mode RW 1075 modes M_CFG 1076 field DPE 0x80 1077 field SSE 0x40 1078 field RMA 0x20 1079 field RTA 0x10 1080 field SCAAPERR 0x08 1081 field RDPERR 0x04 1082 field TWATERR 0x02 1083 field DPR 0x01 1084} 1085 1086/* 1087 * Data FIFO 1 PCI Status 1088 */ 1089register DF1PCISTAT { 1090 address 0x0A1 1091 access_mode RW 1092 modes M_CFG 1093 field DPE 0x80 1094 field SSE 0x40 1095 field RMA 0x20 1096 field RTA 0x10 1097 field SCAAPERR 0x08 1098 field RDPERR 0x04 1099 field TWATERR 0x02 1100 field DPR 0x01 1101} 1102 1103/* 1104 * S/G PCI Status 1105 */ 1106register SGPCISTAT { 1107 address 0x0A2 1108 access_mode RW 1109 modes M_CFG 1110 field DPE 0x80 1111 field SSE 0x40 1112 field RMA 0x20 1113 field RTA 0x10 1114 field SCAAPERR 0x08 1115 field RDPERR 0x04 1116 field DPR 0x01 1117} 1118 1119/* 1120 * CMC PCI Status 1121 */ 1122register CMCPCISTAT { 1123 address 0x0A3 1124 access_mode RW 1125 modes M_CFG 1126 field DPE 0x80 1127 field SSE 0x40 1128 field RMA 0x20 1129 field RTA 0x10 1130 field SCAAPERR 0x08 1131 field RDPERR 0x04 1132 field TWATERR 0x02 1133 field DPR 0x01 1134} 1135 1136/* 1137 * Overlay PCI Status 1138 */ 1139register OVLYPCISTAT { 1140 address 0x0A4 1141 access_mode RW 1142 modes M_CFG 1143 field DPE 0x80 1144 field SSE 0x40 1145 field RMA 0x20 1146 field RTA 0x10 1147 field SCAAPERR 0x08 1148 field RDPERR 0x04 1149 field DPR 0x01 1150} 1151 1152/* 1153 * PCI Status for MSI Master DMA Transfer 1154 */ 1155register MSIPCISTAT { 1156 address 0x0A6 1157 access_mode RW 1158 modes M_CFG 1159 field SSE 0x40 1160 field RMA 0x20 1161 field RTA 0x10 1162 field CLRPENDMSI 0x08 1163 field TWATERR 0x02 1164 field DPR 0x01 1165} 1166 1167/* 1168 * PCI Status for Target 1169 */ 1170register TARGPCISTAT { 1171 address 0x0A6 1172 access_mode RW 1173 modes M_CFG 1174 field DPE 0x80 1175 field SSE 0x40 1176 field STA 0x08 1177 field TWATERR 0x02 1178} 1179 1180/* 1181 * LQ Packet In 1182 * The last LQ Packet recieved 1183 */ 1184register LQIN { 1185 address 0x020 1186 access_mode RW 1187 size 20 1188 modes M_DFF0, M_DFF1, M_SCSI 1189} 1190 1191/* 1192 * SCB Type Pointer 1193 * SCB offset for Target Mode SCB type information 1194 */ 1195register TYPEPTR { 1196 address 0x020 1197 access_mode RW 1198 modes M_CFG 1199} 1200 1201/* 1202 * Queue Tag Pointer 1203 * SCB offset to the Two Byte tag identifier used for target mode. 1204 */ 1205register TAGPTR { 1206 address 0x021 1207 access_mode RW 1208 modes M_CFG 1209} 1210 1211/* 1212 * Logical Unit Number Pointer 1213 * SCB offset to the LSB (little endian) of the lun field. 1214 */ 1215register LUNPTR { 1216 address 0x022 1217 access_mode RW 1218 modes M_CFG 1219} 1220 1221/* 1222 * Data Length Pointer 1223 * SCB offset for the 4 byte data length field in target mode. 1224 */ 1225register DATALENPTR { 1226 address 0x023 1227 access_mode RW 1228 modes M_CFG 1229} 1230 1231/* 1232 * Status Length Pointer 1233 * SCB offset to the two byte status field in target SCBs. 1234 */ 1235register STATLENPTR { 1236 address 0x024 1237 access_mode RW 1238 modes M_CFG 1239} 1240 1241/* 1242 * Command Length Pointer 1243 * Scb offset for the CDB length field in initiator SCBs. 1244 */ 1245register CMDLENPTR { 1246 address 0x025 1247 access_mode RW 1248 modes M_CFG 1249} 1250 1251/* 1252 * Task Attribute Pointer 1253 * Scb offset for the byte field specifying the attribute byte 1254 * to be used in command packets. 1255 */ 1256register ATTRPTR { 1257 address 0x026 1258 access_mode RW 1259 modes M_CFG 1260} 1261 1262/* 1263 * Task Management Flags Pointer 1264 * Scb offset for the byte field specifying the attribute flags 1265 * byte to be used in command packets. 1266 */ 1267register FLAGPTR { 1268 address 0x027 1269 access_mode RW 1270 modes M_CFG 1271} 1272 1273/* 1274 * Command Pointer 1275 * Scb offset for the first byte in the CDB for initiator SCBs. 1276 */ 1277register CMDPTR { 1278 address 0x028 1279 access_mode RW 1280 modes M_CFG 1281} 1282 1283/* 1284 * Queue Next Pointer 1285 * Scb offset for the 2 byte "next scb link". 1286 */ 1287register QNEXTPTR { 1288 address 0x029 1289 access_mode RW 1290 modes M_CFG 1291} 1292 1293/* 1294 * SCSI ID Pointer 1295 * Scb offset to the value to place in the SCSIID register 1296 * during target mode connections. 1297 */ 1298register IDPTR { 1299 address 0x02A 1300 access_mode RW 1301 modes M_CFG 1302} 1303 1304/* 1305 * Command Aborted Byte Pointer 1306 * Offset to the SCB flags field that includes the 1307 * "SCB aborted" status bit. 1308 */ 1309register ABRTBYTEPTR { 1310 address 0x02B 1311 access_mode RW 1312 modes M_CFG 1313} 1314 1315/* 1316 * Command Aborted Bit Pointer 1317 * Bit offset in the SCB flags field for "SCB aborted" status. 1318 */ 1319register ABRTBITPTR { 1320 address 0x02C 1321 access_mode RW 1322 modes M_CFG 1323} 1324 1325/* 1326 * Rev B or greater. 1327 */ 1328register MAXCMDBYTES { 1329 address 0x02D 1330 access_mode RW 1331 modes M_CFG 1332} 1333 1334/* 1335 * Rev B or greater. 1336 */ 1337register MAXCMD2RCV { 1338 address 0x02E 1339 access_mode RW 1340 modes M_CFG 1341} 1342 1343/* 1344 * Rev B or greater. 1345 */ 1346register SHORTTHRESH { 1347 address 0x02F 1348 access_mode RW 1349 modes M_CFG 1350} 1351 1352/* 1353 * Logical Unit Number Length 1354 * The length, in bytes, of the SCB lun field. 1355 */ 1356register LUNLEN { 1357 address 0x030 1358 access_mode RW 1359 modes M_CFG 1360} 1361 1362/* 1363 * CDB Limit 1364 * The size, in bytes, of the embedded CDB field in initator SCBs. 1365 */ 1366register CDBLIMIT { 1367 address 0x031 1368 access_mode RW 1369 modes M_CFG 1370} 1371 1372/* 1373 * Maximum Commands 1374 * The maximum number of commands to issue during a 1375 * single packetized connection. 1376 */ 1377register MAXCMD { 1378 address 0x032 1379 access_mode RW 1380 modes M_CFG 1381} 1382 1383/* 1384 * Maximum Command Counter 1385 * The number of commands already sent during this connection 1386 */ 1387register MAXCMDCNT { 1388 address 0x033 1389 access_mode RW 1390 modes M_CFG 1391} 1392 1393/* 1394 * LQ Packet Reserved Bytes 1395 * The bytes to be sent in the currently reserved fileds 1396 * of all LQ packets. 1397 */ 1398register LQRSVD01 { 1399 address 0x034 1400 access_mode RW 1401 modes M_SCSI 1402} 1403register LQRSVD16 { 1404 address 0x035 1405 access_mode RW 1406 modes M_SCSI 1407} 1408register LQRSVD17 { 1409 address 0x036 1410 access_mode RW 1411 modes M_SCSI 1412} 1413 1414/* 1415 * Command Reserved 0 1416 * The byte to be sent for the reserved byte 0 of 1417 * outgoing command packets. 1418 */ 1419register CMDRSVD0 { 1420 address 0x037 1421 access_mode RW 1422 modes M_CFG 1423} 1424 1425/* 1426 * LQ Manager Control 0 1427 */ 1428register LQCTL0 { 1429 address 0x038 1430 access_mode RW 1431 modes M_CFG 1432 field LQITARGCLT 0xC0 1433 field LQIINITGCLT 0x30 1434 field LQ0TARGCLT 0x0C 1435 field LQ0INITGCLT 0x03 1436} 1437 1438/* 1439 * LQ Manager Control 1 1440 */ 1441register LQCTL1 { 1442 address 0x038 1443 access_mode RW 1444 modes M_DFF0, M_DFF1, M_SCSI 1445 field PCI2PCI 0x04 1446 field SINGLECMD 0x02 1447 field ABORTPENDING 0x01 1448} 1449 1450/* 1451 * LQ Manager Control 2 1452 */ 1453register LQCTL2 { 1454 address 0x039 1455 access_mode RW 1456 modes M_DFF0, M_DFF1, M_SCSI 1457 field LQIRETRY 0x80 1458 field LQICONTINUE 0x40 1459 field LQITOIDLE 0x20 1460 field LQIPAUSE 0x10 1461 field LQORETRY 0x08 1462 field LQOCONTINUE 0x04 1463 field LQOTOIDLE 0x02 1464 field LQOPAUSE 0x01 1465} 1466 1467/* 1468 * SCSI RAM BIST0 1469 */ 1470register SCSBIST0 { 1471 address 0x039 1472 access_mode RW 1473 modes M_CFG 1474 field GSBISTERR 0x40 1475 field GSBISTDONE 0x20 1476 field GSBISTRUN 0x10 1477 field OSBISTERR 0x04 1478 field OSBISTDONE 0x02 1479 field OSBISTRUN 0x01 1480} 1481 1482/* 1483 * SCSI Sequence Control0 1484 */ 1485register SCSISEQ0 { 1486 address 0x03A 1487 access_mode RW 1488 modes M_DFF0, M_DFF1, M_SCSI 1489 field TEMODEO 0x80 1490 field ENSELO 0x40 1491 field ENARBO 0x20 1492 field FORCEBUSFREE 0x10 1493 field SCSIRSTO 0x01 1494} 1495 1496/* 1497 * SCSI RAM BIST 1 1498 */ 1499register SCSBIST1 { 1500 address 0x03A 1501 access_mode RW 1502 modes M_CFG 1503 field NTBISTERR 0x04 1504 field NTBISTDONE 0x02 1505 field NTBISTRUN 0x01 1506} 1507 1508/* 1509 * SCSI Sequence Control 1 1510 */ 1511register SCSISEQ1 { 1512 address 0x03B 1513 access_mode RW 1514 modes M_DFF0, M_DFF1, M_SCSI 1515 field MANUALCTL 0x40 1516 field ENSELI 0x20 1517 field ENRSELI 0x10 1518 field MANUALP 0x0C 1519 field ENAUTOATNP 0x02 1520 field ALTSTIM 0x01 1521} 1522 1523/* 1524 * SCSI Transfer Control 0 1525 */ 1526register SXFRCTL0 { 1527 address 0x03C 1528 access_mode RW 1529 modes M_SCSI 1530 field DFON 0x80 1531 field DFPEXP 0x40 1532 field BIOSCANCELEN 0x10 1533 field SPIOEN 0x08 1534} 1535 1536/* 1537 * SCSI Transfer Control 1 1538 */ 1539register SXFRCTL1 { 1540 address 0x03D 1541 access_mode RW 1542 modes M_SCSI 1543 field BITBUCKET 0x80 1544 field ENSACHK 0x40 1545 field ENSPCHK 0x20 1546 field STIMESEL 0x18 1547 field ENSTIMER 0x04 1548 field ACTNEGEN 0x02 1549 field STPWEN 0x01 1550} 1551 1552/* 1553 * SCSI Transfer Control 2 1554 */ 1555register SXFRCTL2 { 1556 address 0x03E 1557 access_mode RW 1558 modes M_SCSI 1559 field AUTORSTDIS 0x10 1560 field CMDDMAEN 0x08 1561 field ASU 0x07 1562} 1563 1564/* 1565 * SCSI Bus Initiator IDs 1566 * Bitmask of observed initiators on the bus. 1567 */ 1568register BUSINITID { 1569 address 0x03C 1570 access_mode RW 1571 modes M_CFG 1572 size 2 1573} 1574 1575/* 1576 * Data Length Counters 1577 * Packet byte counter. 1578 */ 1579register DLCOUNT { 1580 address 0x03C 1581 access_mode RW 1582 modes M_DFF0, M_DFF1 1583 size 3 1584} 1585 1586/* 1587 * Data FIFO Status 1588 */ 1589register DFFSTAT { 1590 address 0x03F 1591 access_mode RW 1592 modes M_SCSI 1593 field FIFO1FREE 0x20 1594 field FIFO0FREE 0x10 1595 /* 1596 * On the B, this enum only works 1597 * in the read direction. For writes, 1598 * you must use the B version of the 1599 * CURRFIFO_0 definition which is defined 1600 * as a constant outside of this register 1601 * definition to avoid confusing the 1602 * register pretty printing code. 1603 */ 1604 enum CURRFIFO 0x03 { 1605 CURRFIFO_0, 1606 CURRFIFO_1, 1607 CURRFIFO_NONE 0x3 1608 } 1609} 1610 1611const B_CURRFIFO_0 0x2 1612 1613/* 1614 * SCSI Bus Target IDs 1615 * Bitmask of observed targets on the bus. 1616 */ 1617register BUSTARGID { 1618 address 0x03E 1619 access_mode RW 1620 modes M_CFG 1621 size 2 1622} 1623 1624/* 1625 * SCSI Control Signal Out 1626 */ 1627register SCSISIGO { 1628 address 0x040 1629 access_mode RW 1630 modes M_DFF0, M_DFF1, M_SCSI 1631 field CDO 0x80 1632 field IOO 0x40 1633 field MSGO 0x20 1634 field ATNO 0x10 1635 field SELO 0x08 1636 field BSYO 0x04 1637 field REQO 0x02 1638 field ACKO 0x01 1639/* 1640 * Possible phases to write into SCSISIG0 1641 */ 1642 enum PHASE_MASK CDO|IOO|MSGO { 1643 P_DATAOUT 0x0, 1644 P_DATAIN IOO, 1645 P_DATAOUT_DT P_DATAOUT|MSGO, 1646 P_DATAIN_DT P_DATAIN|MSGO, 1647 P_COMMAND CDO, 1648 P_MESGOUT CDO|MSGO, 1649 P_STATUS CDO|IOO, 1650 P_MESGIN CDO|IOO|MSGO 1651 } 1652} 1653 1654register SCSISIGI { 1655 address 0x041 1656 access_mode RO 1657 modes M_DFF0, M_DFF1, M_SCSI 1658 field CDI 0x80 1659 field IOI 0x40 1660 field MSGI 0x20 1661 field ATNI 0x10 1662 field SELI 0x08 1663 field BSYI 0x04 1664 field REQI 0x02 1665 field ACKI 0x01 1666/* 1667 * Possible phases in SCSISIGI 1668 */ 1669 enum PHASE_MASK CDO|IOO|MSGO { 1670 P_DATAOUT 0x0, 1671 P_DATAIN IOO, 1672 P_DATAOUT_DT P_DATAOUT|MSGO, 1673 P_DATAIN_DT P_DATAIN|MSGO, 1674 P_COMMAND CDO, 1675 P_MESGOUT CDO|MSGO, 1676 P_STATUS CDO|IOO, 1677 P_MESGIN CDO|IOO|MSGO 1678 } 1679} 1680 1681/* 1682 * Multiple Target IDs 1683 * Bitmask of ids to respond as a target. 1684 */ 1685register MULTARGID { 1686 address 0x040 1687 access_mode RW 1688 modes M_CFG 1689 size 2 1690} 1691 1692/* 1693 * SCSI Phase 1694 */ 1695register SCSIPHASE { 1696 address 0x042 1697 access_mode RO 1698 modes M_DFF0, M_DFF1, M_SCSI 1699 field STATUS_PHASE 0x20 1700 field COMMAND_PHASE 0x10 1701 field MSG_IN_PHASE 0x08 1702 field MSG_OUT_PHASE 0x04 1703 field DATA_PHASE_MASK 0x03 { 1704 DATA_OUT_PHASE 0x01, 1705 DATA_IN_PHASE 0x02 1706 } 1707} 1708 1709/* 1710 * SCSI Data 0 Image 1711 */ 1712register SCSIDAT0_IMG { 1713 address 0x043 1714 access_mode RW 1715 modes M_DFF0, M_DFF1, M_SCSI 1716} 1717 1718/* 1719 * SCSI Latched Data 1720 */ 1721register SCSIDAT { 1722 address 0x044 1723 access_mode RW 1724 modes M_DFF0, M_DFF1, M_SCSI 1725 size 2 1726} 1727 1728/* 1729 * SCSI Data Bus 1730 */ 1731register SCSIBUS { 1732 address 0x046 1733 access_mode RW 1734 modes M_DFF0, M_DFF1, M_SCSI 1735 size 2 1736} 1737 1738/* 1739 * Target ID In 1740 */ 1741register TARGIDIN { 1742 address 0x048 1743 access_mode RO 1744 modes M_DFF0, M_DFF1, M_SCSI 1745 field CLKOUT 0x80 1746 field TARGID 0x0F 1747} 1748 1749/* 1750 * Selection/Reselection ID 1751 * Upper four bits are the device id. The ONEBIT is set when the re/selecting 1752 * device did not set its own ID. 1753 */ 1754register SELID { 1755 address 0x049 1756 access_mode RW 1757 modes M_DFF0, M_DFF1, M_SCSI 1758 field SELID_MASK 0xf0 1759 field ONEBIT 0x08 1760} 1761 1762/* 1763 * SCSI Block Control 1764 * Controls Bus type and channel selection. SELWIDE allows for the 1765 * coexistence of 8bit and 16bit devices on a wide bus. 1766 */ 1767register SBLKCTL { 1768 address 0x04A 1769 access_mode RW 1770 modes M_DFF0, M_DFF1, M_SCSI 1771 field DIAGLEDEN 0x80 1772 field DIAGLEDON 0x40 1773 field ENAB40 0x08 /* LVD transceiver active */ 1774 field ENAB20 0x04 /* SE/HVD transceiver active */ 1775 field SELWIDE 0x02 1776} 1777 1778/* 1779 * Option Mode 1780 */ 1781register OPTIONMODE { 1782 address 0x04A 1783 access_mode RW 1784 modes M_CFG 1785 field BIOSCANCTL 0x80 1786 field AUTOACKEN 0x40 1787 field BIASCANCTL 0x20 1788 field BUSFREEREV 0x10 1789 field ENDGFORMCHK 0x04 1790 field AUTO_MSGOUT_DE 0x02 1791 mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE 1792} 1793 1794/* 1795 * SCSI Status 0 1796 */ 1797register SSTAT0 { 1798 address 0x04B 1799 access_mode RO 1800 modes M_DFF0, M_DFF1, M_SCSI 1801 field TARGET 0x80 /* Board acting as target */ 1802 field SELDO 0x40 /* Selection Done */ 1803 field SELDI 0x20 /* Board has been selected */ 1804 field SELINGO 0x10 /* Selection In Progress */ 1805 field IOERR 0x08 /* LVD Tranceiver mode changed */ 1806 field OVERRUN 0x04 /* SCSI Offset overrun detected */ 1807 field SPIORDY 0x02 /* SCSI PIO Ready */ 1808 field ARBDO 0x01 /* Arbitration Done Out */ 1809} 1810 1811/* 1812 * Clear SCSI Interrupt 0 1813 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 1814 */ 1815register CLRSINT0 { 1816 address 0x04B 1817 access_mode WO 1818 modes M_DFF0, M_DFF1, M_SCSI 1819 field CLRSELDO 0x40 1820 field CLRSELDI 0x20 1821 field CLRSELINGO 0x10 1822 field CLRIOERR 0x08 1823 field CLROVERRUN 0x04 1824 field CLRSPIORDY 0x02 1825 field CLRARBDO 0x01 1826} 1827 1828/* 1829 * SCSI Interrupt Mode 0 1830 * Setting any bit will enable the corresponding function 1831 * in SIMODE0 to interrupt via the IRQ pin. 1832 */ 1833register SIMODE0 { 1834 address 0x04B 1835 access_mode RW 1836 modes M_CFG 1837 field ENSELDO 0x40 1838 field ENSELDI 0x20 1839 field ENSELINGO 0x10 1840 field ENIOERR 0x08 1841 field ENOVERRUN 0x04 1842 field ENSPIORDY 0x02 1843 field ENARBDO 0x01 1844} 1845 1846/* 1847 * SCSI Status 1 1848 */ 1849register SSTAT1 { 1850 address 0x04C 1851 access_mode RO 1852 modes M_DFF0, M_DFF1, M_SCSI 1853 field SELTO 0x80 1854 field ATNTARG 0x40 1855 field SCSIRSTI 0x20 1856 field PHASEMIS 0x10 1857 field BUSFREE 0x08 1858 field SCSIPERR 0x04 1859 field STRB2FAST 0x02 1860 field REQINIT 0x01 1861} 1862 1863/* 1864 * Clear SCSI Interrupt 1 1865 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 1866 */ 1867register CLRSINT1 { 1868 address 0x04C 1869 access_mode WO 1870 modes M_DFF0, M_DFF1, M_SCSI 1871 field CLRSELTIMEO 0x80 1872 field CLRATNO 0x40 1873 field CLRSCSIRSTI 0x20 1874 field CLRBUSFREE 0x08 1875 field CLRSCSIPERR 0x04 1876 field CLRSTRB2FAST 0x02 1877 field CLRREQINIT 0x01 1878} 1879 1880/* 1881 * SCSI Status 2 1882 */ 1883register SSTAT2 { 1884 address 0x04d 1885 access_mode RO 1886 modes M_DFF0, M_DFF1, M_SCSI 1887 field BUSFREETIME 0xc0 { 1888 BUSFREE_LQO 0x40, 1889 BUSFREE_DFF0 0x80, 1890 BUSFREE_DFF1 0xC0 1891 } 1892 field NONPACKREQ 0x20 1893 field EXP_ACTIVE 0x10 /* SCSI Expander Active */ 1894 field BSYX 0x08 /* Busy Expander */ 1895 field WIDE_RES 0x04 /* Modes 0 and 1 only */ 1896 field SDONE 0x02 /* Modes 0 and 1 only */ 1897 field DMADONE 0x01 /* Modes 0 and 1 only */ 1898} 1899 1900/* 1901 * Clear SCSI Interrupt 2 1902 */ 1903register CLRSINT2 { 1904 address 0x04D 1905 access_mode WO 1906 modes M_DFF0, M_DFF1, M_SCSI 1907 field CLRNONPACKREQ 0x20 1908 field CLRWIDE_RES 0x04 /* Modes 0 and 1 only */ 1909 field CLRSDONE 0x02 /* Modes 0 and 1 only */ 1910 field CLRDMADONE 0x01 /* Modes 0 and 1 only */ 1911} 1912 1913/* 1914 * SCSI Interrupt Mode 2 1915 */ 1916register SIMODE2 { 1917 address 0x04D 1918 access_mode RW 1919 modes M_CFG 1920 field ENWIDE_RES 0x04 1921 field ENSDONE 0x02 1922 field ENDMADONE 0x01 1923} 1924 1925/* 1926 * Physical Error Diagnosis 1927 */ 1928register PERRDIAG { 1929 address 0x04E 1930 access_mode RO 1931 modes M_DFF0, M_DFF1, M_SCSI 1932 field HIZERO 0x80 1933 field HIPERR 0x40 1934 field PREVPHASE 0x20 1935 field PARITYERR 0x10 1936 field AIPERR 0x08 1937 field CRCERR 0x04 1938 field DGFORMERR 0x02 1939 field DTERR 0x01 1940} 1941 1942/* 1943 * LQI Manager Current State 1944 */ 1945register LQISTATE { 1946 address 0x04E 1947 access_mode RO 1948 modes M_CFG 1949} 1950 1951/* 1952 * SCSI Offset Count 1953 */ 1954register SOFFCNT { 1955 address 0x04F 1956 access_mode RO 1957 modes M_DFF0, M_DFF1, M_SCSI 1958} 1959 1960/* 1961 * LQO Manager Current State 1962 */ 1963register LQOSTATE { 1964 address 0x04F 1965 access_mode RO 1966 modes M_CFG 1967} 1968 1969/* 1970 * LQI Manager Status 1971 */ 1972register LQISTAT0 { 1973 address 0x050 1974 access_mode RO 1975 modes M_DFF0, M_DFF1, M_SCSI 1976 field LQIATNQAS 0x20 1977 field LQICRCT1 0x10 1978 field LQICRCT2 0x08 1979 field LQIBADLQT 0x04 1980 field LQIATNLQ 0x02 1981 field LQIATNCMD 0x01 1982} 1983 1984/* 1985 * Clear LQI Interrupts 0 1986 */ 1987register CLRLQIINT0 { 1988 address 0x050 1989 access_mode WO 1990 modes M_DFF0, M_DFF1, M_SCSI 1991 field CLRLQIATNQAS 0x20 1992 field CLRLQICRCT1 0x10 1993 field CLRLQICRCT2 0x08 1994 field CLRLQIBADLQT 0x04 1995 field CLRLQIATNLQ 0x02 1996 field CLRLQIATNCMD 0x01 1997} 1998 1999/* 2000 * LQI Manager Interrupt Mode 0 2001 */ 2002register LQIMODE0 { 2003 address 0x050 2004 access_mode RW 2005 modes M_CFG 2006 field ENLQIATNQASK 0x20 2007 field ENLQICRCT1 0x10 2008 field ENLQICRCT2 0x08 2009 field ENLQIBADLQT 0x04 2010 field ENLQIATNLQ 0x02 2011 field ENLQIATNCMD 0x01 2012} 2013 2014/* 2015 * LQI Manager Status 1 2016 */ 2017register LQISTAT1 { 2018 address 0x051 2019 access_mode RO 2020 modes M_DFF0, M_DFF1, M_SCSI 2021 field LQIPHASE_LQ 0x80 2022 field LQIPHASE_NLQ 0x40 2023 field LQIABORT 0x20 2024 field LQICRCI_LQ 0x10 2025 field LQICRCI_NLQ 0x08 2026 field LQIBADLQI 0x04 2027 field LQIOVERI_LQ 0x02 2028 field LQIOVERI_NLQ 0x01 2029} 2030 2031/* 2032 * Clear LQI Manager Interrupts1 2033 */ 2034register CLRLQIINT1 { 2035 address 0x051 2036 access_mode WO 2037 modes M_DFF0, M_DFF1, M_SCSI 2038 field CLRLQIPHASE_LQ 0x80 2039 field CLRLQIPHASE_NLQ 0x40 2040 field CLRLIQABORT 0x20 2041 field CLRLQICRCI_LQ 0x10 2042 field CLRLQICRCI_NLQ 0x08 2043 field CLRLQIBADLQI 0x04 2044 field CLRLQIOVERI_LQ 0x02 2045 field CLRLQIOVERI_NLQ 0x01 2046} 2047 2048/* 2049 * LQI Manager Interrupt Mode 1 2050 */ 2051register LQIMODE1 { 2052 address 0x051 2053 access_mode RW 2054 modes M_CFG 2055 field ENLQIPHASE_LQ 0x80 2056 field ENLQIPHASE_NLQ 0x40 2057 field ENLIQABORT 0x20 2058 field ENLQICRCI_LQ 0x10 2059 field ENLQICRCI_NLQ 0x08 2060 field ENLQIBADLQI 0x04 2061 field ENLQIOVERI_LQ 0x02 2062 field ENLQIOVERI_NLQ 0x01 2063} 2064 2065/* 2066 * LQI Manager Status 2 2067 */ 2068register LQISTAT2 { 2069 address 0x052 2070 access_mode RO 2071 modes M_DFF0, M_DFF1, M_SCSI 2072 field PACKETIZED 0x80 2073 field LQIPHASE_OUTPKT 0x40 2074 field LQIWORKONLQ 0x20 2075 field LQIWAITFIFO 0x10 2076 field LQISTOPPKT 0x08 2077 field LQISTOPLQ 0x04 2078 field LQISTOPCMD 0x02 2079 field LQIGSAVAIL 0x01 2080} 2081 2082/* 2083 * SCSI Status 3 2084 */ 2085register SSTAT3 { 2086 address 0x053 2087 access_mode RO 2088 modes M_DFF0, M_DFF1, M_SCSI 2089 field NTRAMPERR 0x02 2090 field OSRAMPERR 0x01 2091} 2092 2093/* 2094 * Clear SCSI Status 3 2095 */ 2096register CLRSINT3 { 2097 address 0x053 2098 access_mode WO 2099 modes M_DFF0, M_DFF1, M_SCSI 2100 field CLRNTRAMPERR 0x02 2101 field CLROSRAMPERR 0x01 2102} 2103 2104/* 2105 * SCSI Interrupt Mode 3 2106 */ 2107register SIMODE3 { 2108 address 0x053 2109 access_mode RW 2110 modes M_CFG 2111 field ENNTRAMPERR 0x02 2112 field ENOSRAMPERR 0x01 2113} 2114 2115/* 2116 * LQO Manager Status 0 2117 */ 2118register LQOSTAT0 { 2119 address 0x054 2120 access_mode RO 2121 modes M_DFF0, M_DFF1, M_SCSI 2122 field LQOTARGSCBPERR 0x10 2123 field LQOSTOPT2 0x08 2124 field LQOATNLQ 0x04 2125 field LQOATNPKT 0x02 2126 field LQOTCRC 0x01 2127} 2128 2129/* 2130 * Clear LQO Manager interrupt 0 2131 */ 2132register CLRLQOINT0 { 2133 address 0x054 2134 access_mode WO 2135 modes M_DFF0, M_DFF1, M_SCSI 2136 field CLRLQOTARGSCBPERR 0x10 2137 field CLRLQOSTOPT2 0x08 2138 field CLRLQOATNLQ 0x04 2139 field CLRLQOATNPKT 0x02 2140 field CLRLQOTCRC 0x01 2141} 2142 2143/* 2144 * LQO Manager Interrupt Mode 0 2145 */ 2146register LQOMODE0 { 2147 address 0x054 2148 access_mode RW 2149 modes M_CFG 2150 field ENLQOTARGSCBPERR 0x10 2151 field ENLQOSTOPT2 0x08 2152 field ENLQOATNLQ 0x04 2153 field ENLQOATNPKT 0x02 2154 field ENLQOTCRC 0x01 2155} 2156 2157/* 2158 * LQO Manager Status 1 2159 */ 2160register LQOSTAT1 { 2161 address 0x055 2162 access_mode RO 2163 modes M_DFF0, M_DFF1, M_SCSI 2164 field LQOINITSCBPERR 0x10 2165 field LQOSTOPI2 0x08 2166 field LQOBADQAS 0x04 2167 field LQOBUSFREE 0x02 2168 field LQOPHACHGINPKT 0x01 2169} 2170 2171/* 2172 * Clear LOQ Interrupt 1 2173 */ 2174register CLRLQOINT1 { 2175 address 0x055 2176 access_mode WO 2177 modes M_DFF0, M_DFF1, M_SCSI 2178 field CLRLQOINITSCBPERR 0x10 2179 field CLRLQOSTOPI2 0x08 2180 field CLRLQOBADQAS 0x04 2181 field CLRLQOBUSFREE 0x02 2182 field CLRLQOPHACHGINPKT 0x01 2183} 2184 2185/* 2186 * LQO Manager Interrupt Mode 1 2187 */ 2188register LQOMODE1 { 2189 address 0x055 2190 access_mode RW 2191 modes M_CFG 2192 field ENLQOINITSCBPERR 0x10 2193 field ENLQOSTOPI2 0x08 2194 field ENLQOBADQAS 0x04 2195 field ENLQOBUSFREE 0x02 2196 field ENLQOPHACHGINPKT 0x01 2197} 2198 2199/* 2200 * LQO Manager Status 2 2201 */ 2202register LQOSTAT2 { 2203 address 0x056 2204 access_mode RO 2205 modes M_DFF0, M_DFF1, M_SCSI 2206 field LQOPKT 0xE0 2207 field LQOWAITFIFO 0x10 2208 field LQOPHACHGOUTPKT 0x02 /* outside of packet boundaries. */ 2209 field LQOSTOP0 0x01 /* Stopped after sending all packets */ 2210} 2211 2212/* 2213 * Output Synchronizer Space Count 2214 */ 2215register OS_SPACE_CNT { 2216 address 0x056 2217 access_mode RO 2218 modes M_CFG 2219} 2220 2221/* 2222 * SCSI Interrupt Mode 1 2223 * Setting any bit will enable the corresponding function 2224 * in SIMODE1 to interrupt via the IRQ pin. 2225 */ 2226register SIMODE1 { 2227 address 0x057 2228 access_mode RW 2229 modes M_DFF0, M_DFF1, M_SCSI 2230 field ENSELTIMO 0x80 2231 field ENATNTARG 0x40 2232 field ENSCSIRST 0x20 2233 field ENPHASEMIS 0x10 2234 field ENBUSFREE 0x08 2235 field ENSCSIPERR 0x04 2236 field ENSTRB2FAST 0x02 2237 field ENREQINIT 0x01 2238} 2239 2240/* 2241 * Good Status FIFO 2242 */ 2243register GSFIFO { 2244 address 0x058 2245 access_mode RO 2246 size 2 2247 modes M_DFF0, M_DFF1, M_SCSI 2248} 2249 2250/* 2251 * Data FIFO SCSI Transfer Control 2252 */ 2253register DFFSXFRCTL { 2254 address 0x05A 2255 access_mode RW 2256 modes M_DFF0, M_DFF1 2257 field DFFBITBUCKET 0x08 2258 field CLRSHCNT 0x04 2259 field CLRCHN 0x02 2260 field RSTCHN 0x01 2261} 2262 2263/* 2264 * Next SCSI Control Block 2265 */ 2266register NEXTSCB { 2267 address 0x05A 2268 access_mode RW 2269 size 2 2270 modes M_SCSI 2271} 2272 2273/* Rev B only. */ 2274register LQOSCSCTL { 2275 address 0x05A 2276 access_mode RW 2277 size 1 2278 modes M_CFG 2279 field LQOH2A_VERSION 0x80 2280 field LQONOCHKOVER 0x01 2281} 2282 2283/* 2284 * SEQ Interrupts 2285 */ 2286register SEQINTSRC { 2287 address 0x05B 2288 access_mode RO 2289 modes M_DFF0, M_DFF1 2290 field CTXTDONE 0x40 2291 field SAVEPTRS 0x20 2292 field CFG4DATA 0x10 2293 field CFG4ISTAT 0x08 2294 field CFG4TSTAT 0x04 2295 field CFG4ICMD 0x02 2296 field CFG4TCMD 0x01 2297} 2298 2299/* 2300 * Clear Arp Interrupts 2301 */ 2302register CLRSEQINTSRC { 2303 address 0x05B 2304 access_mode WO 2305 modes M_DFF0, M_DFF1 2306 field CLRCTXTDONE 0x40 2307 field CLRSAVEPTRS 0x20 2308 field CLRCFG4DATA 0x10 2309 field CLRCFG4ISTAT 0x08 2310 field CLRCFG4TSTAT 0x04 2311 field CLRCFG4ICMD 0x02 2312 field CLRCFG4TCMD 0x01 2313} 2314 2315/* 2316 * SEQ Interrupt Enabled (Shared) 2317 */ 2318register SEQIMODE { 2319 address 0x05C 2320 access_mode RW 2321 modes M_DFF0, M_DFF1 2322 field ENCTXTDONE 0x40 2323 field ENSAVEPTRS 0x20 2324 field ENCFG4DATA 0x10 2325 field ENCFG4ISTAT 0x08 2326 field ENCFG4TSTAT 0x04 2327 field ENCFG4ICMD 0x02 2328 field ENCFG4TCMD 0x01 2329} 2330 2331/* 2332 * Current SCSI Control Block 2333 */ 2334register CURRSCB { 2335 address 0x05C 2336 access_mode RW 2337 size 2 2338 modes M_SCSI 2339} 2340 2341/* 2342 * Data FIFO Status 2343 */ 2344register MDFFSTAT { 2345 address 0x05D 2346 access_mode RO 2347 modes M_DFF0, M_DFF1 2348 field SHCNTNEGATIVE 0x40 /* Rev B or higher */ 2349 field SHCNTMINUS1 0x20 /* Rev B or higher */ 2350 field LASTSDONE 0x10 2351 field SHVALID 0x08 2352 field DLZERO 0x04 /* FIFO data ends on packet boundary. */ 2353 field DATAINFIFO 0x02 2354 field FIFOFREE 0x01 2355} 2356 2357/* 2358 * CRC Control 2359 */ 2360register CRCCONTROL { 2361 address 0x05d 2362 access_mode RW 2363 modes M_CFG 2364 field CRCVALCHKEN 0x40 2365} 2366 2367/* 2368 * SCSI Test Control 2369 */ 2370register SCSITEST { 2371 address 0x05E 2372 access_mode RW 2373 modes M_CFG 2374 field CNTRTEST 0x08 2375 field SEL_TXPLL_DEBUG 0x04 2376} 2377 2378/* 2379 * Data FIFO Queue Tag 2380 */ 2381register DFFTAG { 2382 address 0x05E 2383 access_mode RW 2384 size 2 2385 modes M_DFF0, M_DFF1 2386} 2387 2388/* 2389 * Last SCSI Control Block 2390 */ 2391register LASTSCB { 2392 address 0x05E 2393 access_mode RW 2394 size 2 2395 modes M_SCSI 2396} 2397 2398/* 2399 * SCSI I/O Cell Power-down Control 2400 */ 2401register IOPDNCTL { 2402 address 0x05F 2403 access_mode RW 2404 modes M_CFG 2405 field DISABLE_OE 0x80 2406 field PDN_IDIST 0x04 2407 field PDN_DIFFSENSE 0x01 2408} 2409 2410/* 2411 * Shaddow Host Address. 2412 */ 2413register SHADDR { 2414 address 0x060 2415 access_mode RO 2416 size 8 2417 modes M_DFF0, M_DFF1 2418} 2419 2420/* 2421 * Data Group CRC Interval. 2422 */ 2423register DGRPCRCI { 2424 address 0x060 2425 access_mode RW 2426 size 2 2427 modes M_CFG 2428} 2429 2430/* 2431 * Data Transfer Negotiation Address 2432 */ 2433register NEGOADDR { 2434 address 0x060 2435 access_mode RW 2436 modes M_SCSI 2437} 2438 2439/* 2440 * Data Transfer Negotiation Data - Period Byte 2441 */ 2442register NEGPERIOD { 2443 address 0x061 2444 access_mode RW 2445 modes M_SCSI 2446} 2447 2448/* 2449 * Packetized CRC Interval 2450 */ 2451register PACKCRCI { 2452 address 0x062 2453 access_mode RW 2454 size 2 2455 modes M_CFG 2456} 2457 2458/* 2459 * Data Transfer Negotiation Data - Offset Byte 2460 */ 2461register NEGOFFSET { 2462 address 0x062 2463 access_mode RW 2464 modes M_SCSI 2465} 2466 2467/* 2468 * Data Transfer Negotiation Data - PPR Options 2469 */ 2470register NEGPPROPTS { 2471 address 0x063 2472 access_mode RW 2473 modes M_SCSI 2474 field PPROPT_PACE 0x08 2475 field PPROPT_QAS 0x04 2476 field PPROPT_DT 0x02 2477 field PPROPT_IUT 0x01 2478} 2479 2480/* 2481 * Data Transfer Negotiation Data - Connection Options 2482 */ 2483register NEGCONOPTS { 2484 address 0x064 2485 access_mode RW 2486 modes M_SCSI 2487 field ENSNAPSHOT 0x40 2488 field RTI_WRTDIS 0x20 2489 field RTI_OVRDTRN 0x10 2490 field ENSLOWCRC 0x08 2491 field ENAUTOATNI 0x04 2492 field ENAUTOATNO 0x02 2493 field WIDEXFER 0x01 2494} 2495 2496/* 2497 * Negotiation Table Annex Column Index. 2498 */ 2499register ANNEXCOL { 2500 address 0x065 2501 access_mode RW 2502 modes M_SCSI 2503} 2504 2505register SCSCHKN { 2506 address 0x066 2507 access_mode RW 2508 modes M_CFG 2509 field STSELSKIDDIS 0x40 2510 field CURRFIFODEF 0x20 2511 field WIDERESEN 0x10 2512 field SDONEMSKDIS 0x08 2513 field DFFACTCLR 0x04 2514 field SHVALIDSTDIS 0x02 2515 field LSTSGCLRDIS 0x01 2516} 2517 2518const AHD_ANNEXCOL_PER_DEV0 4 2519const AHD_NUM_PER_DEV_ANNEXCOLS 4 2520const AHD_ANNEXCOL_PRECOMP_SLEW 4 2521const AHD_PRECOMP_MASK 0x07 2522const AHD_PRECOMP_SHIFT 0 2523const AHD_PRECOMP_CUTBACK_17 0x04 2524const AHD_PRECOMP_CUTBACK_29 0x06 2525const AHD_PRECOMP_CUTBACK_37 0x07 2526const AHD_SLEWRATE_MASK 0x78 2527const AHD_SLEWRATE_SHIFT 3 2528/* 2529 * Rev A has only a single bit of slew adjustment. 2530 * Rev B has 4 bits. 2531 */ 2532const AHD_SLEWRATE_DEF_REVA 0x01 2533const AHD_SLEWRATE_DEF_REVB 0x08 2534 2535/* Rev A does not have any amplitude setting. */ 2536const AHD_ANNEXCOL_AMPLITUDE 6 2537const AHD_AMPLITUDE_MASK 0x7 2538const AHD_AMPLITUDE_SHIFT 0 2539const AHD_AMPLITUDE_DEF 0x7 2540 2541/* 2542 * Negotiation Table Annex Data Port. 2543 */ 2544register ANNEXDAT { 2545 address 0x066 2546 access_mode RW 2547 modes M_SCSI 2548} 2549 2550/* 2551 * Initiator's Own Id. 2552 * The SCSI ID to use for Selection Out and seen during a reselection.. 2553 */ 2554register IOWNID { 2555 address 0x067 2556 access_mode RW 2557 modes M_SCSI 2558} 2559 2560/* 2561 * 960MHz Phase-Locked Loop Control 0 2562 */ 2563register PLL960CTL0 { 2564 address 0x068 2565 access_mode RW 2566 modes M_CFG 2567 field PLL_VCOSEL 0x80 2568 field PLL_PWDN 0x40 2569 field PLL_NS 0x30 2570 field PLL_ENLUD 0x08 2571 field PLL_ENLPF 0x04 2572 field PLL_DLPF 0x02 2573 field PLL_ENFBM 0x01 2574} 2575 2576/* 2577 * Target Own Id 2578 */ 2579register TOWNID { 2580 address 0x069 2581 access_mode RW 2582 modes M_SCSI 2583} 2584 2585/* 2586 * 960MHz Phase-Locked Loop Control 1 2587 */ 2588register PLL960CTL1 { 2589 address 0x069 2590 access_mode RW 2591 modes M_CFG 2592 field PLL_CNTEN 0x80 2593 field PLL_CNTCLR 0x40 2594 field PLL_RST 0x01 2595} 2596 2597/* 2598 * Expander Signature 2599 */ 2600register XSIG { 2601 address 0x06A 2602 access_mode RW 2603 modes M_SCSI 2604} 2605 2606/* 2607 * Shadow Byte Count 2608 */ 2609register SHCNT { 2610 address 0x068 2611 access_mode RW 2612 size 3 2613 modes M_DFF0, M_DFF1 2614} 2615 2616/* 2617 * Selection Out ID 2618 */ 2619register SELOID { 2620 address 0x06B 2621 access_mode RW 2622 modes M_SCSI 2623} 2624 2625/* 2626 * 960-MHz Phase-Locked Loop Test Count 2627 */ 2628register PLL960CNT0 { 2629 address 0x06A 2630 access_mode RO 2631 size 2 2632 modes M_CFG 2633} 2634 2635/* 2636 * 400-MHz Phase-Locked Loop Control 0 2637 */ 2638register PLL400CTL0 { 2639 address 0x06C 2640 access_mode RW 2641 modes M_CFG 2642 field PLL_VCOSEL 0x80 2643 field PLL_PWDN 0x40 2644 field PLL_NS 0x30 2645 field PLL_ENLUD 0x08 2646 field PLL_ENLPF 0x04 2647 field PLL_DLPF 0x02 2648 field PLL_ENFBM 0x01 2649} 2650 2651/* 2652 * Arbitration Fairness 2653 */ 2654register FAIRNESS { 2655 address 0x06C 2656 access_mode RW 2657 size 2 2658 modes M_SCSI 2659} 2660 2661/* 2662 * 400-MHz Phase-Locked Loop Control 1 2663 */ 2664register PLL400CTL1 { 2665 address 0x06D 2666 access_mode RW 2667 modes M_CFG 2668 field PLL_CNTEN 0x80 2669 field PLL_CNTCLR 0x40 2670 field PLL_RST 0x01 2671} 2672 2673/* 2674 * Arbitration Unfairness 2675 */ 2676register UNFAIRNESS { 2677 address 0x06E 2678 access_mode RW 2679 size 2 2680 modes M_SCSI 2681} 2682 2683/* 2684 * 400-MHz Phase-Locked Loop Test Count 2685 */ 2686register PLL400CNT0 { 2687 address 0x06E 2688 access_mode RO 2689 size 2 2690 modes M_CFG 2691} 2692 2693/* 2694 * SCB Page Pointer 2695 */ 2696register SCBPTR { 2697 address 0x0A8 2698 access_mode RW 2699 size 2 2700 modes M_DFF0, M_DFF1, M_CCHAN, M_SCSI 2701} 2702 2703/* 2704 * CMC SCB Array Count 2705 * Number of bytes to transfer between CMC SCB memory and SCBRAM. 2706 * Transfers must be 8byte aligned and sized. 2707 */ 2708register CCSCBACNT { 2709 address 0x0AB 2710 access_mode RW 2711 modes M_CCHAN 2712} 2713 2714/* 2715 * SCB Autopointer 2716 * SCB-Next Address Snooping logic. When an SCB is transferred to 2717 * the card, the next SCB address to be used by the CMC array can 2718 * be autoloaded from that transfer. 2719 */ 2720register SCBAUTOPTR { 2721 address 0x0AB 2722 access_mode RW 2723 modes M_CFG 2724 field AUSCBPTR_EN 0x80 2725 field SCBPTR_ADDR 0x38 2726 field SCBPTR_OFF 0x07 2727} 2728 2729/* 2730 * CMC SG Ram Address Pointer 2731 */ 2732register CCSGADDR { 2733 address 0x0AC 2734 access_mode RW 2735 modes M_DFF0, M_DFF1 2736} 2737 2738/* 2739 * CMC SCB RAM Address Pointer 2740 */ 2741register CCSCBADDR { 2742 address 0x0AC 2743 access_mode RW 2744 modes M_CCHAN 2745} 2746 2747/* 2748 * CMC SCB Ram Back-up Address Pointer 2749 * Indicates the true stop location of transfers halted prior 2750 * to SCBHCNT going to 0. 2751 */ 2752register CCSCBADR_BK { 2753 address 0x0AC 2754 access_mode RO 2755 modes M_CFG 2756} 2757 2758/* 2759 * CMC SG Control 2760 */ 2761register CCSGCTL { 2762 address 0x0AD 2763 access_mode RW 2764 modes M_DFF0, M_DFF1 2765 field CCSGDONE 0x80 2766 field SG_CACHE_AVAIL 0x10 2767 field CCSGENACK 0x08 2768 mask CCSGEN 0x0C 2769 field SG_FETCH_REQ 0x02 2770 field CCSGRESET 0x01 2771} 2772 2773/* 2774 * CMD SCB Control 2775 */ 2776register CCSCBCTL { 2777 address 0x0AD 2778 access_mode RW 2779 modes M_CCHAN 2780 field CCSCBDONE 0x80 2781 field ARRDONE 0x40 2782 field CCARREN 0x10 2783 field CCSCBEN 0x08 2784 field CCSCBDIR 0x04 2785 field CCSCBRESET 0x01 2786} 2787 2788/* 2789 * CMC Ram BIST 2790 */ 2791register CMC_RAMBIST { 2792 address 0x0AD 2793 access_mode RW 2794 modes M_CFG 2795 field SG_ELEMENT_SIZE 0x80 2796 field SCBRAMBIST_FAIL 0x40 2797 field SG_BIST_FAIL 0x20 2798 field SG_BIST_EN 0x10 2799 field CMC_BUFFER_BIST_FAIL 0x02 2800 field CMC_BUFFER_BIST_EN 0x01 2801} 2802 2803/* 2804 * CMC SG RAM Data Port 2805 */ 2806register CCSGRAM { 2807 address 0x0B0 2808 access_mode RW 2809 modes M_DFF0, M_DFF1 2810} 2811 2812/* 2813 * CMC SCB RAM Data Port 2814 */ 2815register CCSCBRAM { 2816 address 0x0B0 2817 access_mode RW 2818 modes M_CCHAN 2819} 2820 2821/* 2822 * Flex DMA Address. 2823 */ 2824register FLEXADR { 2825 address 0x0B0 2826 access_mode RW 2827 size 3 2828 modes M_SCSI 2829} 2830 2831/* 2832 * Flex DMA Byte Count 2833 */ 2834register FLEXCNT { 2835 address 0x0B3 2836 access_mode RW 2837 size 2 2838 modes M_SCSI 2839} 2840 2841/* 2842 * Flex DMA Status 2843 */ 2844register FLEXDMASTAT { 2845 address 0x0B5 2846 access_mode RW 2847 modes M_SCSI 2848 field FLEXDMAERR 0x02 2849 field FLEXDMADONE 0x01 2850} 2851 2852/* 2853 * Flex DMA Data Port 2854 */ 2855register FLEXDATA { 2856 address 0x0B6 2857 access_mode RW 2858 modes M_SCSI 2859} 2860 2861/* 2862 * Board Data 2863 */ 2864register BRDDAT { 2865 address 0x0B8 2866 access_mode RW 2867 modes M_SCSI 2868} 2869 2870/* 2871 * Board Control 2872 */ 2873register BRDCTL { 2874 address 0x0B9 2875 access_mode RW 2876 modes M_SCSI 2877 field FLXARBACK 0x80 2878 field FLXARBREQ 0x40 2879 field BRDADDR 0x38 2880 field BRDEN 0x04 2881 field BRDRW 0x02 2882 field BRDSTB 0x01 2883} 2884 2885/* 2886 * Serial EEPROM Address 2887 */ 2888register SEEADR { 2889 address 0x0BA 2890 access_mode RW 2891 modes M_SCSI 2892} 2893 2894/* 2895 * Serial EEPROM Data 2896 */ 2897register SEEDAT { 2898 address 0x0BC 2899 access_mode RW 2900 size 2 2901 modes M_SCSI 2902} 2903 2904/* 2905 * Serial EEPROM Status 2906 */ 2907register SEESTAT { 2908 address 0x0BE 2909 access_mode RO 2910 modes M_SCSI 2911 field INIT_DONE 0x80 2912 field SEEOPCODE 0x70 2913 field LDALTID_L 0x08 2914 field SEEARBACK 0x04 2915 field SEEBUSY 0x02 2916 field SEESTART 0x01 2917} 2918 2919/* 2920 * Serial EEPROM Control 2921 */ 2922register SEECTL { 2923 address 0x0BE 2924 access_mode RW 2925 modes M_SCSI 2926 field SEEOPCODE 0x70 { 2927 SEEOP_ERASE 0x70, 2928 SEEOP_READ 0x60, 2929 SEEOP_WRITE 0x50, 2930 /* 2931 * The following four commands use special 2932 * addresses for differentiation. 2933 */ 2934 SEEOP_ERAL 0x40 2935 } 2936 mask SEEOP_EWEN 0x40 2937 mask SEEOP_WALL 0x40 2938 mask SEEOP_EWDS 0x40 2939 field SEERST 0x02 2940 field SEESTART 0x01 2941} 2942 2943const SEEOP_ERAL_ADDR 0x80 2944const SEEOP_EWEN_ADDR 0xC0 2945const SEEOP_WRAL_ADDR 0x40 2946const SEEOP_EWDS_ADDR 0x00 2947 2948/* 2949 * SCB Counter 2950 */ 2951register SCBCNT { 2952 address 0x0BF 2953 access_mode RW 2954 modes M_SCSI 2955} 2956 2957/* 2958 * Data FIFO Write Address 2959 * Pointer to the next QWD location to be written to the data FIFO. 2960 */ 2961register DFWADDR { 2962 address 0x0C0 2963 access_mode RW 2964 size 2 2965 modes M_DFF0, M_DFF1 2966} 2967 2968/* 2969 * DSP Filter Control 2970 */ 2971register DSPFLTRCTL { 2972 address 0x0C0 2973 access_mode RW 2974 modes M_CFG 2975 field FLTRDISABLE 0x20 2976 field EDGESENSE 0x10 2977 field DSPFCNTSEL 0x0F 2978} 2979 2980/* 2981 * DSP Data Channel Control 2982 */ 2983register DSPDATACTL { 2984 address 0x0C1 2985 access_mode RW 2986 modes M_CFG 2987 field BYPASSENAB 0x80 2988 field DESQDIS 0x10 2989 field RCVROFFSTDIS 0x04 2990 field XMITOFFSTDIS 0x02 2991} 2992 2993/* 2994 * Data FIFO Read Address 2995 * Pointer to the next QWD location to be read from the data FIFO. 2996 */ 2997register DFRADDR { 2998 address 0x0C2 2999 access_mode RW 3000 size 2 3001 modes M_DFF0, M_DFF1 3002} 3003 3004/* 3005 * DSP REQ Control 3006 */ 3007register DSPREQCTL { 3008 address 0x0C2 3009 access_mode RW 3010 modes M_CFG 3011 field MANREQCTL 0xC0 3012 field MANREQDLY 0x3F 3013} 3014 3015/* 3016 * DSP ACK Control 3017 */ 3018register DSPACKCTL { 3019 address 0x0C3 3020 access_mode RW 3021 modes M_CFG 3022 field MANACKCTL 0xC0 3023 field MANACKDLY 0x3F 3024} 3025 3026/* 3027 * Data FIFO Data 3028 * Read/Write byte port into the data FIFO. The read and write 3029 * FIFO pointers increment with each read and write respectively 3030 * to this port. 3031 */ 3032register DFDAT { 3033 address 0x0C4 3034 access_mode RW 3035 modes M_DFF0, M_DFF1 3036} 3037 3038/* 3039 * DSP Channel Select 3040 */ 3041register DSPSELECT { 3042 address 0x0C4 3043 access_mode RW 3044 modes M_CFG 3045 field AUTOINCEN 0x80 3046 field DSPSEL 0x1F 3047} 3048 3049const NUMDSPS 0x14 3050 3051/* 3052 * Write Bias Control 3053 */ 3054register WRTBIASCTL { 3055 address 0x0C5 3056 access_mode WO 3057 modes M_CFG 3058 field AUTOXBCDIS 0x80 3059 field XMITMANVAL 0x3F 3060} 3061 3062/* 3063 * Currently the WRTBIASCTL is the same as the default. 3064 */ 3065const WRTBIASCTL_HP_DEFAULT 0x0 3066 3067/* 3068 * Receiver Bias Control 3069 */ 3070register RCVRBIOSCTL { 3071 address 0x0C6 3072 access_mode WO 3073 modes M_CFG 3074 field AUTORBCDIS 0x80 3075 field RCVRMANVAL 0x3F 3076} 3077 3078/* 3079 * Write Bias Calculator 3080 */ 3081register WRTBIASCALC { 3082 address 0x0C7 3083 access_mode RO 3084 modes M_CFG 3085} 3086 3087/* 3088 * Data FIFO Pointers 3089 * Contains the byte offset from DFWADDR and DWRADDR to the current 3090 * FIFO write/read locations. 3091 */ 3092register DFPTRS { 3093 address 0x0C8 3094 access_mode RW 3095 modes M_DFF0, M_DFF1 3096} 3097 3098/* 3099 * Receiver Bias Calculator 3100 */ 3101register RCVRBIASCALC { 3102 address 0x0C8 3103 access_mode RO 3104 modes M_CFG 3105} 3106 3107/* 3108 * Data FIFO Debug Control 3109 */ 3110register DFDBCTL { 3111 address 0x0C8 3112 access_mode RW 3113 modes M_DFF0, M_DFF1 3114 field DFF_CIO_WR_RDY 0x20 3115 field DFF_CIO_RD_RDY 0x10 3116 field DFF_DIR_ERR 0x08 3117 field DFF_RAMBIST_FAIL 0x04 3118 field DFF_RAMBIST_DONE 0x02 3119 field DFF_RAMBIST_EN 0x01 3120} 3121 3122/* 3123 * Data FIFO Backup Read Pointer 3124 * Contains the data FIFO address to be restored if the last 3125 * data accessed from the data FIFO was not transferred successfully. 3126 */ 3127register DFBKPTR { 3128 address 0x0C9 3129 access_mode RW 3130 size 2 3131 modes M_DFF0, M_DFF1 3132} 3133 3134/* 3135 * Skew Calculator 3136 */ 3137register SKEWCALC { 3138 address 0x0C9 3139 access_mode RO 3140 modes M_CFG 3141} 3142 3143/* 3144 * Data FIFO Space Count 3145 * Number of FIFO locations that are free. 3146 */ 3147register DFSCNT { 3148 address 0x0CC 3149 access_mode RO 3150 size 2 3151 modes M_DFF0, M_DFF1 3152} 3153 3154/* 3155 * Data FIFO Byte Count 3156 * Number of filled FIFO locations. 3157 */ 3158register DFBCNT { 3159 address 0x0CE 3160 access_mode RO 3161 size 2 3162 modes M_DFF0, M_DFF1 3163} 3164 3165/* 3166 * Sequencer Program Overlay Address. 3167 * Low address must be written prior to high address. 3168 */ 3169register OVLYADDR { 3170 address 0x0D4 3171 modes M_SCSI 3172 size 2 3173 access_mode RW 3174} 3175 3176/* 3177 * Sequencer Control 0 3178 * Error detection mode, speed configuration, 3179 * single step, breakpoints and program load. 3180 */ 3181register SEQCTL0 { 3182 address 0x0D6 3183 access_mode RW 3184 field PERRORDIS 0x80 3185 field PAUSEDIS 0x40 3186 field FAILDIS 0x20 3187 field FASTMODE 0x10 3188 field BRKADRINTEN 0x08 3189 field STEP 0x04 3190 field SEQRESET 0x02 3191 field LOADRAM 0x01 3192} 3193 3194/* 3195 * Sequencer Control 1 3196 * Instruction RAM Diagnostics 3197 */ 3198register SEQCTL1 { 3199 address 0x0D7 3200 access_mode RW 3201 field OVRLAY_DATA_CHK 0x08 3202 field RAMBIST_DONE 0x04 3203 field RAMBIST_FAIL 0x02 3204 field RAMBIST_EN 0x01 3205} 3206 3207/* 3208 * Sequencer Flags 3209 * Zero and Carry state of the ALU. 3210 */ 3211register FLAGS { 3212 address 0x0D8 3213 access_mode RO 3214 field ZERO 0x02 3215 field CARRY 0x01 3216} 3217 3218/* 3219 * Sequencer Interrupt Control 3220 */ 3221register SEQINTCTL { 3222 address 0x0D9 3223 access_mode RW 3224 field INTVEC1DSL 0x80 3225 field INT1_CONTEXT 0x20 3226 field SCS_SEQ_INT1M1 0x10 3227 field SCS_SEQ_INT1M0 0x08 3228 field INTMASK 0x06 3229 field IRET 0x01 3230} 3231 3232/* 3233 * Sequencer RAM Data Port 3234 * Single byte window into the Sequencer Instruction Ram area starting 3235 * at the address specified by OVLYADDR. To write a full instruction word, 3236 * simply write four bytes in succession. OVLYADDR will increment after the 3237 * most significant instrution byte (the byte with the parity bit) is written. 3238 */ 3239register SEQRAM { 3240 address 0x0DA 3241 access_mode RW 3242} 3243 3244/* 3245 * Sequencer Program Counter 3246 * Low byte must be written prior to high byte. 3247 */ 3248register PRGMCNT { 3249 address 0x0DE 3250 access_mode RW 3251 size 2 3252} 3253 3254/* 3255 * Accumulator 3256 */ 3257register ACCUM { 3258 address 0x0E0 3259 access_mode RW 3260 accumulator 3261} 3262 3263/* 3264 * Source Index Register 3265 * Incrementing index for reads of SINDIR and the destination (low byte only) 3266 * for any immediate operands passed in jmp, jc, jnc, call instructions. 3267 * Example: 3268 * mvi 0xFF call some_routine; 3269 * 3270 * Will set SINDEX[0] to 0xFF and call the routine "some_routine. 3271 */ 3272register SINDEX { 3273 address 0x0E2 3274 access_mode RW 3275 size 2 3276 sindex 3277} 3278 3279/* 3280 * Destination Index Register 3281 * Incrementing index for writes to DINDIR. Can be used as a scratch register. 3282 */ 3283register DINDEX { 3284 address 0x0E4 3285 access_mode RW 3286 size 2 3287} 3288 3289/* 3290 * Break Address 3291 * Sequencer instruction breakpoint address address. 3292 */ 3293register BRKADDR0 { 3294 address 0x0E6 3295 access_mode RW 3296} 3297 3298register BRKADDR1 { 3299 address 0x0E6 3300 access_mode RW 3301 field BRKDIS 0x80 /* Disable Breakpoint */ 3302} 3303 3304/* 3305 * All Ones 3306 * All reads to this register return the value 0xFF. 3307 */ 3308register ALLONES { 3309 address 0x0E8 3310 access_mode RO 3311 allones 3312} 3313 3314/* 3315 * All Zeros 3316 * All reads to this register return the value 0. 3317 */ 3318register ALLZEROS { 3319 address 0x0EA 3320 access_mode RO 3321 allzeros 3322} 3323 3324/* 3325 * No Destination 3326 * Writes to this register have no effect. 3327 */ 3328register NONE { 3329 address 0x0EA 3330 access_mode WO 3331 none 3332} 3333 3334/* 3335 * Source Index Indirect 3336 * Reading this register is equivalent to reading (register_base + SINDEX) and 3337 * incrementing SINDEX by 1. 3338 */ 3339register SINDIR { 3340 address 0x0EC 3341 access_mode RO 3342} 3343 3344/* 3345 * Destination Index Indirect 3346 * Writing this register is equivalent to writing to (register_base + DINDEX) 3347 * and incrementing DINDEX by 1. 3348 */ 3349register DINDIR { 3350 address 0x0ED 3351 access_mode WO 3352} 3353 3354/* 3355 * Function One 3356 * 2's complement to bit value conversion. Write the 2's complement value 3357 * (0-7 only) to the top nibble and retrieve the bit indexed by that value 3358 * on the next read of this register. 3359 * Example: 3360 * Write 0x60 3361 * Read 0x40 3362 */ 3363register FUNCTION1 { 3364 address 0x0F0 3365 access_mode RW 3366} 3367 3368/* 3369 * Stack 3370 * Window into the stack. Each stack location is 10 bits wide reported 3371 * low byte followed by high byte. There are 8 stack locations. 3372 */ 3373register STACK { 3374 address 0x0F2 3375 access_mode RW 3376} 3377 3378/* 3379 * Interrupt Vector 1 Address 3380 * Interrupt branch address for SCS SEQ_INT1 mode 0 and 1 interrupts. 3381 */ 3382register INTVEC1_ADDR { 3383 address 0x0F4 3384 access_mode RW 3385 size 2 3386 modes M_CFG 3387} 3388 3389/* 3390 * Current Address 3391 * Address of the SEQRAM instruction currently executing instruction. 3392 */ 3393register CURADDR { 3394 address 0x0F4 3395 access_mode RW 3396 size 2 3397 modes M_SCSI 3398} 3399 3400/* 3401 * Interrupt Vector 2 Address 3402 * Interrupt branch address for HST_SEQ_INT2 interrupts. 3403 */ 3404register INTVEC2_ADDR { 3405 address 0x0F6 3406 access_mode RW 3407 size 2 3408 modes M_CFG 3409} 3410 3411/* 3412 * Last Address 3413 * Address of the SEQRAM instruction executed prior to the current instruction. 3414 */ 3415register LASTADDR { 3416 address 0x0F6 3417 access_mode RW 3418 size 2 3419 modes M_SCSI 3420} 3421 3422register AHD_PCI_CONFIG_BASE { 3423 address 0x100 3424 access_mode RW 3425 size 256 3426 modes M_CFG 3427} 3428 3429/* ---------------------- Scratch RAM Offsets ------------------------- */ 3430scratch_ram { 3431 /* Mode Specific */ 3432 address 0x0A0 3433 size 8 3434 modes 0, 1, 2, 3 3435 REG0 { 3436 size 2 3437 } 3438 REG1 { 3439 size 2 3440 } 3441 REG_ISR { 3442 size 2 3443 } 3444 SG_STATE { 3445 size 1 3446 field SEGS_AVAIL 0x01 3447 field LOADING_NEEDED 0x02 3448 field FETCH_INPROG 0x04 3449 } 3450 /* 3451 * Track whether the transfer byte count for 3452 * the current data phase is odd. 3453 */ 3454 DATA_COUNT_ODD { 3455 size 1 3456 } 3457} 3458 3459scratch_ram { 3460 /* Mode Specific */ 3461 address 0x0F8 3462 size 8 3463 modes 0, 1, 2, 3 3464 LONGJMP_ADDR { 3465 size 2 3466 } 3467 LONGJMP_SCB { 3468 size 2 3469 } 3470 ACCUM_SAVE { 3471 size 1 3472 } 3473} 3474 3475 3476scratch_ram { 3477 address 0x100 3478 size 128 3479 modes 0, 1, 2, 3 3480 /* 3481 * Per "other-id" execution queues. We use an array of 3482 * tail pointers into lists of SCBs sorted by "other-id". 3483 * The execution head pointer threads the head SCBs for 3484 * each list. 3485 */ 3486 WAITING_SCB_TAILS { 3487 size 32 3488 } 3489 WAITING_TID_HEAD { 3490 size 2 3491 } 3492 WAITING_TID_TAIL { 3493 size 2 3494 } 3495 /* 3496 * SCBID of the next SCB in the new SCB queue. 3497 */ 3498 NEXT_QUEUED_SCB_ADDR { 3499 size 4 3500 } 3501 /* 3502 * head of list of SCBs that have 3503 * completed but have not been 3504 * put into the qoutfifo. 3505 */ 3506 COMPLETE_SCB_HEAD { 3507 size 2 3508 } 3509 /* 3510 * The list of completed SCBs in 3511 * the active DMA. 3512 */ 3513 COMPLETE_SCB_DMAINPROG_HEAD { 3514 size 2 3515 } 3516 /* 3517 * head of list of SCBs that have 3518 * completed but need to be uploaded 3519 * to the host prior to being completed. 3520 */ 3521 COMPLETE_DMA_SCB_HEAD { 3522 size 2 3523 } 3524 /* Counting semaphore to prevent new select-outs */ 3525 QFREEZE_COUNT { 3526 size 2 3527 } 3528 /* 3529 * Mode to restore on legacy idle loop exit. 3530 */ 3531 SAVED_MODE { 3532 size 1 3533 } 3534 /* 3535 * Single byte buffer used to designate the type or message 3536 * to send to a target. 3537 */ 3538 MSG_OUT { 3539 size 1 3540 } 3541 /* Parameters for DMA Logic */ 3542 DMAPARAMS { 3543 size 1 3544 field PRELOADEN 0x80 3545 field WIDEODD 0x40 3546 field SCSIEN 0x20 3547 field SDMAEN 0x10 3548 field SDMAENACK 0x10 3549 field HDMAEN 0x08 3550 field HDMAENACK 0x08 3551 field DIRECTION 0x04 /* Set indicates PCI->SCSI */ 3552 field FIFOFLUSH 0x02 3553 field FIFORESET 0x01 3554 } 3555 SEQ_FLAGS { 3556 size 1 3557 field NOT_IDENTIFIED 0x80 3558 field NO_CDB_SENT 0x40 3559 field TARGET_CMD_IS_TAGGED 0x40 3560 field DPHASE 0x20 3561 /* Target flags */ 3562 field TARG_CMD_PENDING 0x10 3563 field CMDPHASE_PENDING 0x08 3564 field DPHASE_PENDING 0x04 3565 field SPHASE_PENDING 0x02 3566 field NO_DISCONNECT 0x01 3567 } 3568 /* 3569 * Temporary storage for the 3570 * target/channel/lun of a 3571 * reconnecting target 3572 */ 3573 SAVED_SCSIID { 3574 size 1 3575 } 3576 SAVED_LUN { 3577 size 1 3578 } 3579 /* 3580 * The last bus phase as seen by the sequencer. 3581 */ 3582 LASTPHASE { 3583 size 1 3584 field CDI 0x80 3585 field IOI 0x40 3586 field MSGI 0x20 3587 field P_BUSFREE 0x01 3588 enum PHASE_MASK CDO|IOO|MSGO { 3589 P_DATAOUT 0x0, 3590 P_DATAIN IOO, 3591 P_DATAOUT_DT P_DATAOUT|MSGO, 3592 P_DATAIN_DT P_DATAIN|MSGO, 3593 P_COMMAND CDO, 3594 P_MESGOUT CDO|MSGO, 3595 P_STATUS CDO|IOO, 3596 P_MESGIN CDO|IOO|MSGO 3597 } 3598 } 3599 /* 3600 * Value to "or" into the SCBPTR[1] value to 3601 * indicate that an entry in the QINFIFO is valid. 3602 */ 3603 QOUTFIFO_ENTRY_VALID_TAG { 3604 size 1 3605 } 3606 /* 3607 * Base address of our shared data with the kernel driver in host 3608 * memory. This includes the qoutfifo and target mode 3609 * incoming command queue. 3610 */ 3611 SHARED_DATA_ADDR { 3612 size 4 3613 } 3614 /* 3615 * Pointer to location in host memory for next 3616 * position in the qoutfifo. 3617 */ 3618 QOUTFIFO_NEXT_ADDR { 3619 size 4 3620 } 3621 /* 3622 * Kernel and sequencer offsets into the queue of 3623 * incoming target mode command descriptors. The 3624 * queue is full when the KERNEL_TQINPOS == TQINPOS. 3625 */ 3626 KERNEL_TQINPOS { 3627 size 1 3628 } 3629 TQINPOS { 3630 size 1 3631 } 3632 ARG_1 { 3633 size 1 3634 mask SEND_MSG 0x80 3635 mask SEND_SENSE 0x40 3636 mask SEND_REJ 0x20 3637 mask MSGOUT_PHASEMIS 0x10 3638 mask EXIT_MSG_LOOP 0x08 3639 mask CONT_MSG_LOOP_WRITE 0x04 3640 mask CONT_MSG_LOOP_READ 0x03 3641 mask CONT_MSG_LOOP_TARG 0x02 3642 alias RETURN_1 3643 } 3644 ARG_2 { 3645 size 1 3646 alias RETURN_2 3647 } 3648 3649 /* 3650 * Snapshot of MSG_OUT taken after each message is sent. 3651 */ 3652 LAST_MSG { 3653 size 1 3654 } 3655 3656 /* 3657 * Sequences the kernel driver has okayed for us. This allows 3658 * the driver to do things like prevent initiator or target 3659 * operations. 3660 */ 3661 SCSISEQ_TEMPLATE { 3662 size 1 3663 field MANUALCTL 0x40 3664 field ENSELI 0x20 3665 field ENRSELI 0x10 3666 field MANUALP 0x0C 3667 field ENAUTOATNP 0x02 3668 field ALTSTIM 0x01 3669 } 3670 3671 /* 3672 * The initiator specified tag for this target mode transaction. 3673 */ 3674 INITIATOR_TAG { 3675 size 1 3676 } 3677 3678 SEQ_FLAGS2 { 3679 size 1 3680 field TARGET_MSG_PENDING 0x02 3681 field SELECTOUT_QFROZEN 0x04 3682 } 3683 3684 ALLOCFIFO_SCBPTR { 3685 size 2 3686 } 3687 3688 /* 3689 * Target-mode CDB type to CDB length table used 3690 * in non-packetized operation. 3691 */ 3692 CMDSIZE_TABLE { 3693 size 8 3694 } 3695} 3696 3697/************************* Hardware SCB Definition ****************************/ 3698scb { 3699 address 0x180 3700 size 64 3701 modes 0, 1, 2, 3 3702 SCB_RESIDUAL_DATACNT { 3703 size 4 3704 alias SCB_CDB_STORE 3705 } 3706 SCB_RESIDUAL_SGPTR { 3707 size 4 3708 alias SCB_CDB_PTR 3709 field SG_ADDR_MASK 0xf8 /* In the last byte */ 3710 field SG_OVERRUN_RESID 0x02 /* In the first byte */ 3711 field SG_LIST_NULL 0x01 /* In the first byte */ 3712 } 3713 SCB_SCSI_STATUS { 3714 size 1 3715 } 3716 SCB_TARGET_PHASES { 3717 size 1 3718 } 3719 SCB_TARGET_DATA_DIR { 3720 size 1 3721 } 3722 SCB_TARGET_ITAG { 3723 size 1 3724 } 3725 SCB_SENSE_BUSADDR { 3726 /* 3727 * Only valid if CDB length is less than 13 bytes or 3728 * we are using a CDB pointer. Otherwise contains 3729 * the last 4 bytes of embedded cdb information. 3730 */ 3731 size 4 3732 alias SCB_NEXT_COMPLETE 3733 } 3734 SCB_TAG { 3735 size 2 3736 } 3737 SCB_CDB_LEN { 3738 size 1 3739 field SCB_CDB_LEN_PTR 0x80 /* CDB in host memory */ 3740 } 3741 SCB_TASK_MANAGEMENT { 3742 size 1 3743 } 3744 SCB_NEXT { 3745 alias SCB_NEXT_SCB_BUSADDR 3746 size 2 3747 } 3748 SCB_NEXT2 { 3749 size 2 3750 } 3751 SCB_DATAPTR { 3752 size 8 3753 } 3754 SCB_DATACNT { 3755 /* 3756 * The last byte is really the high address bits for 3757 * the data address. 3758 */ 3759 size 4 3760 field SG_LAST_SEG 0x80 /* In the fourth byte */ 3761 field SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */ 3762 } 3763 SCB_SGPTR { 3764 size 4 3765 field SG_STATUS_VALID 0x04 /* In the first byte */ 3766 field SG_FULL_RESID 0x02 /* In the first byte */ 3767 field SG_LIST_NULL 0x01 /* In the first byte */ 3768 } 3769 SCB_CONTROL { 3770 size 1 3771 field TARGET_SCB 0x80 3772 field DISCENB 0x40 3773 field TAG_ENB 0x20 3774 field MK_MESSAGE 0x10 3775 field STATUS_RCVD 0x08 3776 field DISCONNECTED 0x04 3777 field SCB_TAG_TYPE 0x03 3778 } 3779 SCB_SCSIID { 3780 size 1 3781 field TID 0xF0 3782 field OID 0x0F 3783 } 3784 SCB_LUN { 3785 size 1 3786 field LID 0xff 3787 } 3788 SCB_TASK_ATTRIBUTE { 3789 size 1 3790 } 3791 SCB_BUSADDR { 3792 size 4 3793 } 3794 SCB_SPARE { 3795 size 8 3796 alias SCB_PKT_LUN 3797 } 3798 SCB_DISCONNECTED_LISTS { 3799 size 8 3800 } 3801} 3802 3803/*********************************** Constants ********************************/ 3804const MK_MESSAGE_BIT_OFFSET 4 3805const TID_SHIFT 4 3806const TARGET_CMD_CMPLT 0xfe 3807const INVALID_ADDR 0x80 3808#define SCB_LIST_NULL 0xff 3809#define QOUTFIFO_ENTRY_VALID_TOGGLE 0x80 3810 3811const CCSGADDR_MAX 0x80 3812const CCSCBADDR_MAX 0x80 3813const CCSGRAM_MAXSEGS 16 3814 3815/* Selection Timeout Timer Constants */ 3816const STIMESEL_SHIFT 3 3817const STIMESEL_MIN 0x18 3818const STIMESEL_BUG_ADJ 0x8 3819 3820/* WDTR Message values */ 3821const BUS_8_BIT 0x00 3822const BUS_16_BIT 0x01 3823const BUS_32_BIT 0x02 3824 3825/* Offset maximums */ 3826const MAX_OFFSET 0xfe 3827const MAX_OFFSET_PACED 0xfe 3828const MAX_OFFSET_PACED_BUG 0x7f 3829/* 3830 * Some 160 devices incorrectly accept 0xfe as a 3831 * sync offset, but will overrun this value. Limit 3832 * to 0x7f for speed lower than U320 which will 3833 * avoid the persistent sync offset overruns. 3834 */ 3835const MAX_OFFSET_NON_PACED 0x7f 3836const HOST_MSG 0xff 3837 3838/* 3839 * The size of our sense buffers. 3840 * Sense buffer mapping can be handled in either of two ways. 3841 * The first is to allocate a dmamap for each transaction. 3842 * Depending on the architecture, dmamaps can be costly. The 3843 * alternative is to statically map the buffers in much the same 3844 * way we handle our scatter gather lists. The driver implements 3845 * the later. 3846 */ 3847const AHD_SENSE_BUFSIZE 256 3848 3849/* Target mode command processing constants */ 3850const CMD_GROUP_CODE_SHIFT 0x05 3851 3852const STATUS_BUSY 0x08 3853const STATUS_QUEUE_FULL 0x28 3854const STATUS_PKT_SENSE 0xFF 3855const TARGET_DATA_IN 1 3856 3857const SCB_TRANSFER_SIZE_FULL_LUN 56 3858const SCB_TRANSFER_SIZE_1BYTE_LUN 48 3859/* PKT_OVERRUN_BUFSIZE must be a multiple of 256 less than 64K */ 3860const PKT_OVERRUN_BUFSIZE 512 3861 3862/* 3863 * Downloaded (kernel inserted) constants 3864 */ 3865const SG_PREFETCH_CNT download 3866const SG_PREFETCH_CNT_LIMIT download 3867const SG_PREFETCH_ALIGN_MASK download 3868const SG_PREFETCH_ADDR_MASK download 3869const SG_SIZEOF download 3870const PKT_OVERRUN_BUFOFFSET download 3871const SCB_TRANSFER_SIZE download 3872 3873/* 3874 * BIOS SCB offsets 3875 */ 3876const NVRAM_SCB_OFFSET 0x2C 3877