aic79xx.reg revision 104023
1206917Smarius/* 2206917Smarius * Aic79xx register and scratch ram definitions. 3206917Smarius * 4206917Smarius * Copyright (c) 1994-2001 Justin T. Gibbs. 5206917Smarius * Copyright (c) 2000-2002 Adaptec Inc. 6206917Smarius * All rights reserved. 7206917Smarius * 8206917Smarius * Redistribution and use in source and binary forms, with or without 9206917Smarius * modification, are permitted provided that the following conditions 10206917Smarius * are met: 11206917Smarius * 1. Redistributions of source code must retain the above copyright 12206917Smarius * notice, this list of conditions, and the following disclaimer, 13206917Smarius * without modification. 14206917Smarius * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15206917Smarius * substantially similar to the "NO WARRANTY" disclaimer below 16206917Smarius * ("Disclaimer") and any redistribution must be conditioned upon 17206917Smarius * including a substantially similar Disclaimer requirement for further 18206917Smarius * binary redistribution. 19206917Smarius * 3. Neither the names of the above-listed copyright holders nor the names 20206917Smarius * of any contributors may be used to endorse or promote products derived 21206917Smarius * from this software without specific prior written permission. 22206917Smarius * 23206917Smarius * Alternatively, this software may be distributed under the terms of the 24206917Smarius * GNU General Public License ("GPL") version 2 as published by the Free 25206917Smarius * Software Foundation. 26206917Smarius * 27206917Smarius * NO WARRANTY 28206917Smarius * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29206917Smarius * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30228975Suqs * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31206917Smarius * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32206917Smarius * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33206917Smarius * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34206917Smarius * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35206917Smarius * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36206917Smarius * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37206917Smarius * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38206917Smarius * POSSIBILITY OF SUCH DAMAGES. 39206917Smarius * 40206917Smarius * $FreeBSD: head/sys/dev/aic7xxx/aic79xx.reg 104023 2002-09-26 22:54:00Z gibbs $ 41206917Smarius */ 42206917SmariusVERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#45 $" 43206917Smarius 44206917Smarius/* 45206917Smarius * This file is processed by the aic7xxx_asm utility for use in assembling 46206917Smarius * firmware for the aic79xx family of SCSI host adapters as well as to generate 47206917Smarius * a C header file for use in the kernel portion of the Aic79xx driver. 48206917Smarius */ 49206917Smarius 50206917Smarius/* Register window Modes */ 51206917Smarius#define M_DFF0 0 52206917Smarius#define M_DFF1 1 53206917Smarius#define M_CCHAN 2 54206917Smarius#define M_SCSI 3 55206917Smarius#define M_CFG 4 56206917Smarius#define M_DST_SHIFT 4 57206917Smarius 58206917Smarius#define MK_MODE(src, dst) ((src) | ((dst) << M_DST_SHIFT)) 59206917Smarius#define SET_MODE(src, dst) \ 60206917Smarius SET_SRC_MODE src; \ 61206917Smarius SET_DST_MODE dst; \ 62206917Smarius if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ 63206917Smarius mvi MK_MODE(src, dst) call set_mode_work_around; \ 64206917Smarius } else { \ 65206917Smarius mvi MODE_PTR, MK_MODE(src, dst); \ 66206917Smarius } 67206917Smarius 68206917Smarius#define TOGGLE_DFF_MODE \ 69206917Smarius if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ 70206917Smarius call toggle_dff_mode_work_around; \ 71206917Smarius } else { \ 72206917Smarius xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1); \ 73206917Smarius } 74206917Smarius 75206917Smarius 76206917Smarius/* 77206917Smarius * Mode Pointer 78206917Smarius * Controls which of the 5, 512byte, address spaces should be used 79206917Smarius * as the source and destination of any register accesses in our 80206917Smarius * register window. 81206917Smarius */ 82206917Smariusregister MODE_PTR { 83206917Smarius address 0x000 84206917Smarius access_mode RW 85206917Smarius field DST_MODE 0x70 86206917Smarius field SRC_MODE 0x07 87206917Smarius mode_pointer 88206917Smarius} 89206917Smarius 90206917Smariusconst SRC_MODE_SHIFT 0 91206917Smariusconst DST_MODE_SHIFT 4 92206917Smarius 93206917Smarius/* 94206917Smarius * Host Interrupt Status 95206917Smarius */ 96206917Smariusregister INTSTAT { 97206917Smarius address 0x001 98206917Smarius access_mode RW 99206917Smarius field HWERRINT 0x80 100206917Smarius field BRKADRINT 0x40 101206917Smarius field SWTMINT 0x20 102206917Smarius field PCIINT 0x10 103206917Smarius field SCSIINT 0x08 104206917Smarius field SEQINT 0x04 105206917Smarius field CMDCMPLT 0x02 106206917Smarius field SPLTINT 0x01 107206917Smarius mask INT_PEND 0xFF 108206917Smarius} 109206917Smarius 110206917Smarius/* 111206917Smarius * Sequencer Interrupt Code 112206917Smarius */ 113206917Smariusregister SEQINTCODE { 114206917Smarius address 0x002 115206917Smarius access_mode RW 116206917Smarius field { 117206917Smarius BAD_PHASE 1, /* unknown scsi bus phase */ 118206917Smarius SEND_REJECT, /* sending a message reject */ 119206917Smarius PROTO_VIOLATION, /* Protocol Violation */ 120206917Smarius NO_MATCH, /* no cmd match for reconnect */ 121206917Smarius IGN_WIDE_RES, /* Complex IGN Wide Res Msg */ 122206917Smarius PDATA_REINIT, /* 123206917Smarius * Returned to data phase 124206917Smarius * that requires data 125206917Smarius * transfer pointers to be 126206917Smarius * recalculated from the 127206917Smarius * transfer residual. 128206917Smarius */ 129206917Smarius HOST_MSG_LOOP, /* 130206917Smarius * The bus is ready for the 131206917Smarius * host to perform another 132206917Smarius * message transaction. This 133206917Smarius * mechanism is used for things 134206917Smarius * like sync/wide negotiation 135206917Smarius * that require a kernel based 136206917Smarius * message state engine. 137206917Smarius */ 138206917Smarius BAD_STATUS, /* Bad status from target */ 139206917Smarius DATA_OVERRUN, /* 140206917Smarius * Target attempted to write 141206917Smarius * beyond the bounds of its 142206917Smarius * command. 143206917Smarius */ 144206917Smarius MKMSG_FAILED, /* 145206917Smarius * Target completed command 146206917Smarius * without honoring our ATN 147206917Smarius * request to issue a message. 148206917Smarius */ 149206917Smarius MISSED_BUSFREE, /* 150206917Smarius * The sequencer never saw 151206917Smarius * the bus go free after 152206917Smarius * either a command complete 153206917Smarius * or disconnect message. 154206917Smarius */ 155206917Smarius DUMP_CARD_STATE, 156206917Smarius ILLEGAL_PHASE, 157206917Smarius INVALID_SEQINT, 158206917Smarius CFG4ISTAT_INTR, 159206917Smarius STATUS_OVERRUN, 160206917Smarius CFG4OVERRUN, 161206917Smarius ENTERING_NONPACK 162206917Smarius } 163206917Smarius} 164206917Smarius 165206917Smarius/* 166206917Smarius * Clear Host Interrupt 167206917Smarius */ 168206917Smariusregister CLRINT { 169206917Smarius address 0x003 170206917Smarius access_mode WO 171206917Smarius field CLRHWERRINT 0x80 /* Rev B or greater */ 172206917Smarius field CLRBRKADRINT 0x40 173206917Smarius field CLRSWTMINT 0x20 174206917Smarius field CLRSCSIINT 0x08 175206917Smarius field CLRSEQINT 0x04 176206917Smarius field CLRCMDINT 0x02 177206917Smarius field CLRSPLTINT 0x01 178206917Smarius} 179206917Smarius 180206917Smarius/* 181206917Smarius * Error Register 182206917Smarius */ 183206917Smariusregister ERROR { 184206917Smarius address 0x004 185206917Smarius access_mode RO 186206917Smarius field CIOPARERR 0x80 187206917Smarius field CIOACCESFAIL 0x40 /* Rev B or greater */ 188206917Smarius field MPARERR 0x20 189206917Smarius field DPARERR 0x10 190206917Smarius field SQPARERR 0x08 191206917Smarius field ILLOPCODE 0x04 192206917Smarius field DSCTMOUT 0x02 193206917Smarius} 194206917Smarius 195206917Smarius/* 196206917Smarius * Clear Error 197206917Smarius */ 198206917Smariusregister CLRERR { 199206917Smarius address 0x004 200206917Smarius access_mode WO 201206917Smarius field CLRCIOPARERR 0x80 202206917Smarius field CLRCIOACCESFAIL 0x40 /* Rev B or greater */ 203206917Smarius field CLRMPARERR 0x20 204206917Smarius field CLRDPARERR 0x10 205206917Smarius field CLRSQPARERR 0x08 206206917Smarius field CLRILLOPCODE 0x04 207206917Smarius field CLRDSCTMOUT 0x02 208206917Smarius} 209206917Smarius 210206917Smarius/* 211206917Smarius * Host Control Register 212206917Smarius * Overall host control of the device. 213206917Smarius */ 214206917Smariusregister HCNTRL { 215206917Smarius address 0x005 216206917Smarius access_mode RW 217206917Smarius field SEQ_RESET 0x80 /* Rev B or greater */ 218206917Smarius field POWRDN 0x40 219206917Smarius field SWINT 0x10 220206917Smarius field SWTIMER_START_B 0x08 /* Rev B or greater */ 221206917Smarius field PAUSE 0x04 222206917Smarius field INTEN 0x02 223206917Smarius field CHIPRST 0x01 224206917Smarius field CHIPRSTACK 0x01 225206917Smarius} 226206917Smarius 227206917Smarius/* 228206917Smarius * Host New SCB Queue Offset 229206917Smarius */ 230206917Smariusregister HNSCB_QOFF { 231206917Smarius address 0x006 232206917Smarius access_mode RW 233206917Smarius size 2 234206917Smarius} 235206917Smarius 236206917Smarius/* 237206917Smarius * Host Empty SCB Queue Offset 238206917Smarius */ 239206917Smariusregister HESCB_QOFF { 240206917Smarius address 0x008 241206917Smarius access_mode RW 242206917Smarius} 243206917Smarius 244206917Smarius/* 245206917Smarius * Host Mailbox 246206917Smarius */ 247206917Smariusregister HS_MAILBOX { 248206917Smarius address 0x0B 249206917Smarius access_mode RW 250206917Smarius mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */ 251206917Smarius} 252206917Smarius 253206917Smarius/* 254206917Smarius * Sequencer Interupt Status 255206917Smarius */ 256206917Smariusregister SEQINTSTAT { 257206917Smarius address 0x0C 258206917Smarius access_mode RO 259206917Smarius field SEQ_SWTMRTO 0x10 260206917Smarius field SEQ_SEQINT 0x08 261206917Smarius field SEQ_SCSIINT 0x04 262206917Smarius field SEQ_PCIINT 0x02 263206917Smarius field SEQ_SPLTINT 0x01 264206917Smarius} 265206917Smarius 266206917Smarius/* 267206917Smarius * Clear SEQ Interrupt 268206917Smarius */ 269206917Smariusregister CLRSEQINTSTAT { 270206917Smarius address 0x0C0 271206917Smarius access_mode WO 272206917Smarius field CLRSEQ_SWTMRTO 0x10 273206917Smarius field CLRSEQ_SEQINT 0x08 274206917Smarius field CLRSEQ_SCSIINT 0x04 275206917Smarius field CLRSEQ_PCIINT 0x02 276206917Smarius field CLRSEQ_SPLTINT 0x01 277206917Smarius} 278206917Smarius 279206917Smarius/* 280206917Smarius * Software Timer 281206917Smarius */ 282206917Smariusregister SWTIMER { 283206917Smarius address 0x0E0 284206917Smarius access_mode RW 285206917Smarius size 2 286206917Smarius} 287206917Smarius 288206917Smarius/* 289206917Smarius * SEQ New SCB Queue Offset 290206917Smarius */ 291206917Smariusregister SNSCB_QOFF { 292206917Smarius address 0x010 293206917Smarius access_mode RW 294206917Smarius size 2 295206917Smarius modes M_CCHAN 296206917Smarius} 297206917Smarius 298206917Smarius/* 299206917Smarius * SEQ Empty SCB Queue Offset 300206917Smarius */ 301206917Smariusregister SESCB_QOFF { 302206917Smarius address 0x012 303206917Smarius access_mode RW 304206917Smarius modes M_CCHAN 305206917Smarius} 306206917Smarius 307206917Smarius/* 308206917Smarius * SEQ Done SCB Queue Offset 309206917Smarius */ 310206917Smariusregister SDSCB_QOFF { 311206917Smarius address 0x014 312206917Smarius access_mode RW 313206917Smarius modes M_CCHAN 314206917Smarius size 2 315206917Smarius} 316206917Smarius 317206917Smarius/* 318206917Smarius * Queue Offset Control & Status 319206917Smarius */ 320206917Smariusregister QOFF_CTLSTA { 321206917Smarius address 0x016 322206917Smarius access_mode RW 323206917Smarius modes M_CCHAN 324 field EMPTY_SCB_AVAIL 0x80 325 field NEW_SCB_AVAIL 0x40 326 field SDSCB_ROLLOVR 0x20 327 field HS_MAILBOX_ACT 0x10 328 field SCB_QSIZE 0x0F { 329 SCB_QSIZE_4, 330 SCB_QSIZE_8, 331 SCB_QSIZE_16, 332 SCB_QSIZE_32, 333 SCB_QSIZE_64, 334 SCB_QSIZE_128, 335 SCB_QSIZE_256, 336 SCB_QSIZE_512, 337 SCB_QSIZE_1024, 338 SCB_QSIZE_2048, 339 SCB_QSIZE_4096, 340 SCB_QSIZE_8192, 341 SCB_QSIZE_16384 342 } 343} 344 345/* 346 * Interrupt Control 347 */ 348register INTCTL { 349 address 0x018 350 access_mode RW 351 field SWTMINTMASK 0x80 352 field SWTMINTEN 0x40 353 field SWTIMER_START 0x20 354 field AUTOCLRCMDINT 0x10 355 field PCIINTEN 0x08 356 field SCSIINTEN 0x04 357 field SEQINTEN 0x02 358 field SPLTINTEN 0x01 359} 360 361/* 362 * Data FIFO Control 363 */ 364register DFCNTRL { 365 address 0x019 366 access_mode RW 367 modes M_DFF0, M_DFF1 368 field PRELOADEN 0x80 369 field SCSIEN 0x20 370 field SCSIENACK 0x20 371 field HDMAEN 0x08 372 field HDMAENACK 0x08 373 field DIRECTION 0x04 374 field DIRECTIONACK 0x04 375 field FIFOFLUSH 0x02 376 field FIFOFLUSHACK 0x02 377 field DIRECTIONEN 0x01 378} 379 380/* 381 * Device Space Command 0 382 */ 383register DSCOMMAND0 { 384 address 0x019 385 access_mode RW 386 modes M_CFG 387 field CACHETHEN 0x80 /* Cache Threshold enable */ 388 field DPARCKEN 0x40 /* Data Parity Check Enable */ 389 field MPARCKEN 0x20 /* Memory Parity Check Enable */ 390 field EXTREQLCK 0x10 /* External Request Lock */ 391 field DISABLE_TWATE 0x02 /* Rev B or greater */ 392 field CIOPARCKEN 0x01 /* Internal bus parity error enable */ 393} 394 395/* 396 * Data FIFO Status 397 */ 398register DFSTATUS { 399 address 0x01A 400 access_mode RO 401 modes M_DFF0, M_DFF1 402 field PRELOAD_AVAIL 0x80 403 field PKT_PRELOAD_AVAIL 0x40 404 field MREQPEND 0x10 405 field HDONE 0x08 406 field DFTHRESH 0x04 407 field FIFOFULL 0x02 408 field FIFOEMP 0x01 409} 410 411/* 412 * S/G Cache Pointer 413 */ 414register SG_CACHE_PRE { 415 address 0x01B 416 access_mode WO 417 modes M_DFF0, M_DFF1 418 field SG_ADDR_MASK 0xf8 419 field ODD_SEG 0x04 420 field LAST_SEG 0x02 421} 422 423register SG_CACHE_SHADOW { 424 address 0x01B 425 access_mode RO 426 modes M_DFF0, M_DFF1 427 field SG_ADDR_MASK 0xf8 428 field ODD_SEG 0x04 429 field LAST_SEG 0x02 430 field LAST_SEG_DONE 0x01 431} 432 433/* 434 * Arbiter Control 435 */ 436register ARBCTL { 437 address 0x01B 438 access_mode RW 439 modes M_CFG 440 field RESET_HARB 0x80 441 field RETRY_SWEN 0x08 442 field USE_TIME 0x07 443} 444 445/* 446 * Data Channel Host Address 447 */ 448register HADDR { 449 address 0x070 450 access_mode RW 451 size 8 452 modes M_DFF0, M_DFF1 453} 454 455/* 456 * Host Overlay DMA Address 457 */ 458register HODMAADR { 459 address 0x070 460 access_mode RW 461 size 8 462 modes M_SCSI 463} 464 465/* 466 * Data Channel Host Count 467 */ 468register HCNT { 469 address 0x078 470 access_mode RW 471 size 3 472 modes M_DFF0, M_DFF1 473} 474 475/* 476 * Host Overlay DMA Count 477 */ 478register HODMACNT { 479 address 0x078 480 access_mode RW 481 size 2 482 modes M_SCSI 483} 484 485/* 486 * Host Overlay DMA Enable 487 */ 488register HODMAEN { 489 address 0x07A 490 access_mode RW 491 modes M_SCSI 492} 493 494/* 495 * Scatter/Gather Host Address 496 */ 497register SGHADDR { 498 address 0x07C 499 access_mode RW 500 size 8 501 modes M_DFF0, M_DFF1 502} 503 504/* 505 * SCB Host Address 506 */ 507register SCBHADDR { 508 address 0x07C 509 access_mode RW 510 size 8 511 modes M_CCHAN 512} 513 514/* 515 * Scatter/Gather Host Count 516 */ 517register SGHCNT { 518 address 0x084 519 access_mode RW 520 modes M_DFF0, M_DFF1 521} 522 523/* 524 * SCB Host Count 525 */ 526register SCBHCNT { 527 address 0x084 528 access_mode RW 529 modes M_CCHAN 530} 531 532/* 533 * Data FIFO Threshold 534 */ 535register DFF_THRSH { 536 address 0x088 537 access_mode RW 538 modes M_CFG 539 field WR_DFTHRSH 0x70 { 540 WR_DFTHRSH_MIN, 541 WR_DFTHRSH_25, 542 WR_DFTHRSH_50, 543 WR_DFTHRSH_63, 544 WR_DFTHRSH_75, 545 WR_DFTHRSH_85, 546 WR_DFTHRSH_90, 547 WR_DFTHRSH_MAX 548 } 549 field RD_DFTHRSH 0x07 { 550 RD_DFTHRSH_MIN, 551 RD_DFTHRSH_25, 552 RD_DFTHRSH_50, 553 RD_DFTHRSH_63, 554 RD_DFTHRSH_75, 555 RD_DFTHRSH_85, 556 RD_DFTHRSH_90, 557 RD_DFTHRSH_MAX 558 } 559} 560 561/* 562 * ROM Address 563 */ 564register ROMADDR { 565 address 0x08A 566 access_mode RW 567 size 3 568} 569 570/* 571 * ROM Control 572 */ 573register ROMCNTRL { 574 address 0x08D 575 access_mode RW 576 field ROMOP 0xE0 577 field ROMSPD 0x18 578 field REPEAT 0x02 579 field RDY 0x01 580} 581 582/* 583 * ROM Data 584 */ 585register ROMDATA { 586 address 0x08E 587 access_mode RW 588} 589 590/* 591 * Data Channel Receive Message 0 592 */ 593register DCHRXMSG0 { 594 address 0x090 595 access_mode RO 596 modes M_DFF0, M_DFF1 597 field CDNUM 0xF8 598 field CFNUM 0x07 599} 600 601/* 602 * CMC Recieve Message 0 603 */ 604register CMCRXMSG0 { 605 address 0x090 606 access_mode RO 607 modes M_CCHAN 608 field CDNUM 0xF8 609 field CFNUM 0x07 610} 611 612/* 613 * Overlay Recieve Message 0 614 */ 615register OVLYRXMSG0 { 616 address 0x090 617 access_mode RO 618 modes M_SCSI 619 field CDNUM 0xF8 620 field CFNUM 0x07 621} 622 623/* 624 * Relaxed Order Enable 625 */ 626register ROENABLE { 627 address 0x090 628 access_mode RW 629 modes M_CFG 630 field MSIROEN 0x20 631 field OVLYROEN 0x10 632 field CMCROEN 0x08 633 field SGROEN 0x04 634 field DCH1ROEN 0x02 635 field DCH0ROEN 0x01 636} 637 638/* 639 * Data Channel Receive Message 1 640 */ 641register DCHRXMSG1 { 642 address 0x091 643 access_mode RO 644 modes M_DFF0, M_DFF1 645 field CBNUM 0xFF 646} 647 648/* 649 * CMC Recieve Message 1 650 */ 651register CMCRXMSG1 { 652 address 0x091 653 access_mode RO 654 modes M_CCHAN 655 field CBNUM 0xFF 656} 657 658/* 659 * Overlay Recieve Message 1 660 */ 661register OVLYRXMSG1 { 662 address 0x091 663 access_mode RO 664 modes M_SCSI 665 field CBNUM 0xFF 666} 667 668/* 669 * No Snoop Enable 670 */ 671register NSENABLE { 672 address 0x091 673 access_mode RW 674 modes M_CFG 675 field MSINSEN 0x20 676 field OVLYNSEN 0x10 677 field CMCNSEN 0x08 678 field SGNSEN 0x04 679 field DCH1NSEN 0x02 680 field DCH0NSEN 0x01 681} 682 683/* 684 * Data Channel Receive Message 2 685 */ 686register DCHRXMSG2 { 687 address 0x092 688 access_mode RO 689 modes M_DFF0, M_DFF1 690 field MINDEX 0xFF 691} 692 693/* 694 * CMC Recieve Message 2 695 */ 696register CMCRXMSG2 { 697 address 0x092 698 access_mode RO 699 modes M_CCHAN 700 field MINDEX 0xFF 701} 702 703/* 704 * Overlay Recieve Message 2 705 */ 706register OVLYRXMSG2 { 707 address 0x092 708 access_mode RO 709 modes M_SCSI 710 field MINDEX 0xFF 711} 712 713/* 714 * Outstanding Split Transactions 715 */ 716register OST { 717 address 0x092 718 access_mode RW 719 modes M_CFG 720} 721 722/* 723 * Data Channel Receive Message 3 724 */ 725register DCHRXMSG3 { 726 address 0x093 727 access_mode RO 728 modes M_DFF0, M_DFF1 729 field MCLASS 0x0F 730} 731 732/* 733 * CMC Recieve Message 3 734 */ 735register CMCRXMSG3 { 736 address 0x093 737 access_mode RO 738 modes M_CCHAN 739 field MCLASS 0x0F 740} 741 742/* 743 * Overlay Recieve Message 3 744 */ 745register OVLYRXMSG3 { 746 address 0x093 747 access_mode RO 748 modes M_SCSI 749 field MCLASS 0x0F 750} 751 752/* 753 * PCI-X Control 754 */ 755register PCIXCTL { 756 address 0x093 757 access_mode RW 758 modes M_CFG 759 field SERRPULSE 0x80 760 field UNEXPSCIEN 0x20 761 field SPLTSMADIS 0x10 762 field SPLTSTADIS 0x08 763 field SRSPDPEEN 0x04 764 field TSCSERREN 0x02 765 field CMPABCDIS 0x01 766} 767 768/* 769 * CMC Sequencer Byte Count 770 */ 771register CMCSEQBCNT { 772 address 0x094 773 access_mode RO 774 modes M_CCHAN 775} 776 777/* 778 * Overlay Sequencer Byte Count 779 */ 780register OVLYSEQBCNT { 781 address 0x094 782 access_mode RO 783 modes M_SCSI 784} 785 786/* 787 * Data Channel Sequencer Byte Count 788 */ 789register DCHSEQBCNT { 790 address 0x094 791 access_mode RO 792 size 2 793 modes M_DFF0, M_DFF1 794} 795 796/* 797 * Data Channel Split Status 0 798 */ 799register DCHSPLTSTAT0 { 800 address 0x096 801 access_mode RW 802 modes M_DFF0, M_DFF1 803 field STAETERM 0x80 804 field SCBCERR 0x40 805 field SCADERR 0x20 806 field SCDATBUCKET 0x10 807 field CNTNOTCMPLT 0x08 808 field RXOVRUN 0x04 809 field RXSCEMSG 0x02 810 field RXSPLTRSP 0x01 811} 812 813/* 814 * CMC Split Status 0 815 */ 816register CMCSPLTSTAT0 { 817 address 0x096 818 access_mode RW 819 modes M_CCHAN 820 field STAETERM 0x80 821 field SCBCERR 0x40 822 field SCADERR 0x20 823 field SCDATBUCKET 0x10 824 field CNTNOTCMPLT 0x08 825 field RXOVRUN 0x04 826 field RXSCEMSG 0x02 827 field RXSPLTRSP 0x01 828} 829 830/* 831 * Overlay Split Status 0 832 */ 833register OVLYSPLTSTAT0 { 834 address 0x096 835 access_mode RW 836 modes M_SCSI 837 field STAETERM 0x80 838 field SCBCERR 0x40 839 field SCADERR 0x20 840 field SCDATBUCKET 0x10 841 field CNTNOTCMPLT 0x08 842 field RXOVRUN 0x04 843 field RXSCEMSG 0x02 844 field RXSPLTRSP 0x01 845} 846 847/* 848 * Data Channel Split Status 1 849 */ 850register DCHSPLTSTAT1 { 851 address 0x097 852 access_mode RW 853 modes M_DFF0, M_DFF1 854 field RXDATABUCKET 0x01 855} 856 857/* 858 * CMC Split Status 1 859 */ 860register CMCSPLTSTAT1 { 861 address 0x097 862 access_mode RW 863 modes M_CCHAN 864 field RXDATABUCKET 0x01 865} 866 867/* 868 * Overlay Split Status 1 869 */ 870register OVLYSPLTSTAT1 { 871 address 0x097 872 access_mode RW 873 modes M_SCSI 874 field RXDATABUCKET 0x01 875} 876 877/* 878 * S/G Receive Message 0 879 */ 880register SGRXMSG0 { 881 address 0x098 882 access_mode RO 883 modes M_DFF0, M_DFF1 884 field CDNUM 0xF8 885 field CFNUM 0x07 886} 887 888/* 889 * S/G Receive Message 1 890 */ 891register SGRXMSG1 { 892 address 0x099 893 access_mode RO 894 modes M_DFF0, M_DFF1 895 field CBNUM 0xFF 896} 897 898/* 899 * S/G Receive Message 2 900 */ 901register SGRXMSG2 { 902 address 0x09A 903 access_mode RO 904 modes M_DFF0, M_DFF1 905 field MINDEX 0xFF 906} 907 908/* 909 * S/G Receive Message 3 910 */ 911register SGRXMSG3 { 912 address 0x09B 913 access_mode RO 914 modes M_DFF0, M_DFF1 915 field MCLASS 0x0F 916} 917 918/* 919 * Slave Split Out Address 0 920 */ 921register SLVSPLTOUTADR0 { 922 address 0x098 923 access_mode RO 924 modes M_SCSI 925 field LOWER_ADDR 0x7F 926} 927 928/* 929 * Slave Split Out Address 1 930 */ 931register SLVSPLTOUTADR1 { 932 address 0x099 933 access_mode RO 934 modes M_SCSI 935 field REQ_DNUM 0xF8 936 field REQ_FNUM 0x07 937} 938 939/* 940 * Slave Split Out Address 2 941 */ 942register SLVSPLTOUTADR2 { 943 address 0x09A 944 access_mode RO 945 modes M_SCSI 946 field REQ_BNUM 0xFF 947} 948 949/* 950 * Slave Split Out Address 3 951 */ 952register SLVSPLTOUTADR3 { 953 address 0x09B 954 access_mode RO 955 modes M_SCSI 956 field RLXORD 020 957 field TAG_NUM 0x1F 958} 959 960/* 961 * SG Sequencer Byte Count 962 */ 963register SGSEQBCNT { 964 address 0x09C 965 access_mode RO 966 modes M_DFF0, M_DFF1 967} 968 969/* 970 * Slave Split Out Attribute 0 971 */ 972register SLVSPLTOUTATTR0 { 973 address 0x09C 974 access_mode RO 975 modes M_SCSI 976 field LOWER_BCNT 0xFF 977} 978 979/* 980 * Slave Split Out Attribute 1 981 */ 982register SLVSPLTOUTATTR1 { 983 address 0x09D 984 access_mode RO 985 modes M_SCSI 986 field CMPLT_DNUM 0xF8 987 field CMPLT_FNUM 0x07 988} 989 990/* 991 * Slave Split Out Attribute 2 992 */ 993register SLVSPLTOUTATTR2 { 994 address 0x09E 995 access_mode RO 996 size 2 997 modes M_SCSI 998 field CMPLT_BNUM 0xFF 999} 1000/* 1001 * S/G Split Status 0 1002 */ 1003register SGSPLTSTAT0 { 1004 address 0x09E 1005 access_mode RW 1006 modes M_DFF0, M_DFF1 1007 field STAETERM 0x80 1008 field SCBCERR 0x40 1009 field SCADERR 0x20 1010 field SCDATBUCKET 0x10 1011 field CNTNOTCMPLT 0x08 1012 field RXOVRUN 0x04 1013 field RXSCEMSG 0x02 1014 field RXSPLTRSP 0x01 1015} 1016 1017/* 1018 * S/G Split Status 1 1019 */ 1020register SGSPLTSTAT1 { 1021 address 0x09F 1022 access_mode RW 1023 modes M_DFF0, M_DFF1 1024 field RXDATABUCKET 0x01 1025} 1026 1027/* 1028 * Special Function 1029 */ 1030register SFUNCT { 1031 address 0x09f 1032 access_mode RW 1033 modes M_CFG 1034 field TEST_GROUP 0xF0 1035 field TEST_NUM 0x0F 1036} 1037 1038/* 1039 * Data FIFO 0 PCI Status 1040 */ 1041register DF0PCISTAT { 1042 address 0x0A0 1043 access_mode RW 1044 modes M_CFG 1045 field DPE 0x80 1046 field SSE 0x40 1047 field RMA 0x20 1048 field RTA 0x10 1049 field SCAAPERR 0x08 1050 field RDPERR 0x04 1051 field TWATERR 0x02 1052 field DPR 0x01 1053} 1054 1055/* 1056 * Data FIFO 1 PCI Status 1057 */ 1058register DF1PCISTAT { 1059 address 0x0A1 1060 access_mode RW 1061 modes M_CFG 1062 field DPE 0x80 1063 field SSE 0x40 1064 field RMA 0x20 1065 field RTA 0x10 1066 field SCAAPERR 0x08 1067 field RDPERR 0x04 1068 field TWATERR 0x02 1069 field DPR 0x01 1070} 1071 1072/* 1073 * S/G PCI Status 1074 */ 1075register SGPCISTAT { 1076 address 0x0A2 1077 access_mode RW 1078 modes M_CFG 1079 field DPE 0x80 1080 field SSE 0x40 1081 field RMA 0x20 1082 field RTA 0x10 1083 field SCAAPERR 0x08 1084 field RDPERR 0x04 1085 field DPR 0x01 1086} 1087 1088/* 1089 * CMC PCI Status 1090 */ 1091register CMCPCISTAT { 1092 address 0x0A3 1093 access_mode RW 1094 modes M_CFG 1095 field DPE 0x80 1096 field SSE 0x40 1097 field RMA 0x20 1098 field RTA 0x10 1099 field SCAAPERR 0x08 1100 field RDPERR 0x04 1101 field TWATERR 0x02 1102 field DPR 0x01 1103} 1104 1105/* 1106 * Overlay PCI Status 1107 */ 1108register OVLYPCISTAT { 1109 address 0x0A4 1110 access_mode RW 1111 modes M_CFG 1112 field DPE 0x80 1113 field SSE 0x40 1114 field RMA 0x20 1115 field RTA 0x10 1116 field SCAAPERR 0x08 1117 field RDPERR 0x04 1118 field DPR 0x01 1119} 1120 1121/* 1122 * PCI Status for MSI Master DMA Transfer 1123 */ 1124register MSIPCISTAT { 1125 address 0x0A6 1126 access_mode RW 1127 modes M_CFG 1128 field SSE 0x40 1129 field RMA 0x20 1130 field RTA 0x10 1131 field CLRPENDMSI 0x08 1132 field TWATERR 0x02 1133 field DPR 0x01 1134} 1135 1136/* 1137 * PCI Status for Target 1138 */ 1139register TARGPCISTAT { 1140 address 0x0A6 1141 access_mode RW 1142 modes M_CFG 1143 field DPE 0x80 1144 field SSE 0x40 1145 field STA 0x08 1146 field TWATERR 0x02 1147} 1148 1149/* 1150 * LQ Packet In 1151 * The last LQ Packet recieved 1152 */ 1153register LQIN { 1154 address 0x020 1155 access_mode RW 1156 size 20 1157 modes M_DFF0, M_DFF1, M_SCSI 1158} 1159 1160/* 1161 * SCB Type Pointer 1162 * SCB offset for Target Mode SCB type information 1163 */ 1164register TYPEPTR { 1165 address 0x020 1166 access_mode RW 1167 modes M_CFG 1168} 1169 1170/* 1171 * Queue Tag Pointer 1172 * SCB offset to the Two Byte tag identifier used for target mode. 1173 */ 1174register TAGPTR { 1175 address 0x021 1176 access_mode RW 1177 modes M_CFG 1178} 1179 1180/* 1181 * Logical Unit Number Pointer 1182 * SCB offset to the LSB (little endian) of the lun field. 1183 */ 1184register LUNPTR { 1185 address 0x022 1186 access_mode RW 1187 modes M_CFG 1188} 1189 1190/* 1191 * Data Length Pointer 1192 * SCB offset for the 4 byte data length field in target mode. 1193 */ 1194register DATALENPTR { 1195 address 0x023 1196 access_mode RW 1197 modes M_CFG 1198} 1199 1200/* 1201 * Status Length Pointer 1202 * SCB offset to the two byte status field in target SCBs. 1203 */ 1204register STATLENPTR { 1205 address 0x024 1206 access_mode RW 1207 modes M_CFG 1208} 1209 1210/* 1211 * Command Length Pointer 1212 * Scb offset for the CDB length field in initiator SCBs. 1213 */ 1214register CMDLENPTR { 1215 address 0x025 1216 access_mode RW 1217 modes M_CFG 1218} 1219 1220/* 1221 * Task Attribute Pointer 1222 * Scb offset for the byte field specifying the attribute byte 1223 * to be used in command packets. 1224 */ 1225register ATTRPTR { 1226 address 0x026 1227 access_mode RW 1228 modes M_CFG 1229} 1230 1231/* 1232 * Task Management Flags Pointer 1233 * Scb offset for the byte field specifying the attribute flags 1234 * byte to be used in command packets. 1235 */ 1236register FLAGPTR { 1237 address 0x027 1238 access_mode RW 1239 modes M_CFG 1240} 1241 1242/* 1243 * Command Pointer 1244 * Scb offset for the first byte in the CDB for initiator SCBs. 1245 */ 1246register CMDPTR { 1247 address 0x028 1248 access_mode RW 1249 modes M_CFG 1250} 1251 1252/* 1253 * Queue Next Pointer 1254 * Scb offset for the 2 byte "next scb link". 1255 */ 1256register QNEXTPTR { 1257 address 0x029 1258 access_mode RW 1259 modes M_CFG 1260} 1261 1262/* 1263 * SCSI ID Pointer 1264 * Scb offset to the value to place in the SCSIID register 1265 * during target mode connections. 1266 */ 1267register IDPTR { 1268 address 0x02A 1269 access_mode RW 1270 modes M_CFG 1271} 1272 1273/* 1274 * Command Aborted Byte Pointer 1275 * Offset to the SCB flags field that includes the 1276 * "SCB aborted" status bit. 1277 */ 1278register ABRTBYTEPTR { 1279 address 0x02B 1280 access_mode RW 1281 modes M_CFG 1282} 1283 1284/* 1285 * Command Aborted Bit Pointer 1286 * Bit offset in the SCB flags field for "SCB aborted" status. 1287 */ 1288register ABRTBITPTR { 1289 address 0x02C 1290 access_mode RW 1291 modes M_CFG 1292} 1293 1294/* 1295 * Rev B or greater. 1296 */ 1297register MAXCMDBYTES { 1298 address 0x02D 1299 access_mode RW 1300 modes M_CFG 1301} 1302 1303/* 1304 * Rev B or greater. 1305 */ 1306register MAXCMD2RCV { 1307 address 0x02E 1308 access_mode RW 1309 modes M_CFG 1310} 1311 1312/* 1313 * Rev B or greater. 1314 */ 1315register SHORTTHRESH { 1316 address 0x02F 1317 access_mode RW 1318 modes M_CFG 1319} 1320 1321/* 1322 * Logical Unit Number Length 1323 * The length, in bytes, of the SCB lun field. 1324 */ 1325register LUNLEN { 1326 address 0x030 1327 access_mode RW 1328 modes M_CFG 1329} 1330 1331/* 1332 * CDB Limit 1333 * The size, in bytes, of the embedded CDB field in initator SCBs. 1334 */ 1335register CDBLIMIT { 1336 address 0x031 1337 access_mode RW 1338 modes M_CFG 1339} 1340 1341/* 1342 * Maximum Commands 1343 * The maximum number of commands to issue during a 1344 * single packetized connection. 1345 */ 1346register MAXCMD { 1347 address 0x032 1348 access_mode RW 1349 modes M_CFG 1350} 1351 1352/* 1353 * Maximum Command Counter 1354 * The number of commands already sent during this connection 1355 */ 1356register MAXCMDCNT { 1357 address 0x033 1358 access_mode RW 1359 modes M_CFG 1360} 1361 1362/* 1363 * LQ Packet Reserved Bytes 1364 * The bytes to be sent in the currently reserved fileds 1365 * of all LQ packets. 1366 */ 1367register LQRSVD01 { 1368 address 0x034 1369 access_mode RW 1370 modes M_SCSI 1371} 1372register LQRSVD16 { 1373 address 0x035 1374 access_mode RW 1375 modes M_SCSI 1376} 1377register LQRSVD17 { 1378 address 0x036 1379 access_mode RW 1380 modes M_SCSI 1381} 1382 1383/* 1384 * Command Reserved 0 1385 * The byte to be sent for the reserved byte 0 of 1386 * outgoing command packets. 1387 */ 1388register CMDRSVD0 { 1389 address 0x037 1390 access_mode RW 1391 modes M_CFG 1392} 1393 1394/* 1395 * LQ Manager Control 0 1396 */ 1397register LQCTL0 { 1398 address 0x038 1399 access_mode RW 1400 modes M_CFG 1401 field LQITARGCLT 0xC0 1402 field LQIINITGCLT 0x30 1403 field LQ0TARGCLT 0x0C 1404 field LQ0INITGCLT 0x03 1405} 1406 1407/* 1408 * LQ Manager Control 1 1409 */ 1410register LQCTL1 { 1411 address 0x038 1412 access_mode RW 1413 modes M_DFF0, M_DFF1, M_SCSI 1414 field PCI2PCI 0x04 1415 field SINGLECMD 0x02 1416 field ABORTPENDING 0x01 1417} 1418 1419/* 1420 * LQ Manager Control 2 1421 */ 1422register LQCTL2 { 1423 address 0x039 1424 access_mode RW 1425 modes M_DFF0, M_DFF1, M_SCSI 1426 field LQIRETRY 0x80 1427 field LQICONTINUE 0x40 1428 field LQITOIDLE 0x20 1429 field LQIPAUSE 0x10 1430 field LQORETRY 0x08 1431 field LQOCONTINUE 0x04 1432 field LQOTOIDLE 0x02 1433 field LQOPAUSE 0x01 1434} 1435 1436/* 1437 * SCSI RAM BIST0 1438 */ 1439register SCSBIST0 { 1440 address 0x039 1441 access_mode RW 1442 modes M_CFG 1443 field GSBISTERR 0x40 1444 field GSBISTDONE 0x20 1445 field GSBISTRUN 0x10 1446 field OSBISTERR 0x04 1447 field OSBISTDONE 0x02 1448 field OSBISTRUN 0x01 1449} 1450 1451/* 1452 * SCSI Sequence Control0 1453 */ 1454register SCSISEQ0 { 1455 address 0x03A 1456 access_mode RW 1457 modes M_DFF0, M_DFF1, M_SCSI 1458 field TEMODEO 0x80 1459 field ENSELO 0x40 1460 field ENARBO 0x20 1461 field FORCEBUSFREE 0x10 1462 field SCSIRSTO 0x01 1463} 1464 1465/* 1466 * SCSI RAM BIST 1 1467 */ 1468register SCSBIST1 { 1469 address 0x03A 1470 access_mode RW 1471 modes M_CFG 1472 field NTBISTERR 0x04 1473 field NTBISTDONE 0x02 1474 field NTBISTRUN 0x01 1475} 1476 1477/* 1478 * SCSI Sequence Control 1 1479 */ 1480register SCSISEQ1 { 1481 address 0x03B 1482 access_mode RW 1483 modes M_DFF0, M_DFF1, M_SCSI 1484 field MANUALCTL 0x40 1485 field ENSELI 0x20 1486 field ENRSELI 0x10 1487 field MANUALP 0x0C 1488 field ENAUTOATNP 0x02 1489 field ALTSTIM 0x01 1490} 1491 1492/* 1493 * SCSI Transfer Control 0 1494 */ 1495register SXFRCTL0 { 1496 address 0x03C 1497 access_mode RW 1498 modes M_SCSI 1499 field DFON 0x80 1500 field DFPEXP 0x40 1501 field BIOSCANCELEN 0x10 1502 field SPIOEN 0x08 1503} 1504 1505/* 1506 * SCSI Transfer Control 1 1507 */ 1508register SXFRCTL1 { 1509 address 0x03D 1510 access_mode RW 1511 modes M_SCSI 1512 field BITBUCKET 0x80 1513 field ENSACHK 0x40 1514 field ENSPCHK 0x20 1515 field STIMESEL 0x18 1516 field ENSTIMER 0x04 1517 field ACTNEGEN 0x02 1518 field STPWEN 0x01 1519} 1520 1521/* 1522 * SCSI Transfer Control 2 1523 */ 1524register SXFRCTL2 { 1525 address 0x03E 1526 access_mode RW 1527 modes M_SCSI 1528 field AUTORSTDIS 0x10 1529 field CMDDMAEN 0x08 1530 field ASU 0x07 1531} 1532 1533/* 1534 * SCSI Bus Initiator IDs 1535 * Bitmask of observed initiators on the bus. 1536 */ 1537register BUSINITID { 1538 address 0x03C 1539 access_mode RW 1540 modes M_CFG 1541 size 2 1542} 1543 1544/* 1545 * Data Length Counters 1546 * Packet byte counter. 1547 */ 1548register DLCOUNT { 1549 address 0x03C 1550 access_mode RW 1551 modes M_DFF0, M_DFF1 1552 size 3 1553} 1554 1555/* 1556 * Data FIFO Status 1557 */ 1558register DFFSTAT { 1559 address 0x03F 1560 access_mode RW 1561 modes M_SCSI 1562 field FIFO1FREE 0x20 1563 field FIFO0FREE 0x10 1564 field CURRFIFO 0x01 1565} 1566 1567/* 1568 * SCSI Bus Target IDs 1569 * Bitmask of observed targets on the bus. 1570 */ 1571register BUSTARGID { 1572 address 0x03E 1573 access_mode RW 1574 modes M_CFG 1575 size 2 1576} 1577 1578/* 1579 * SCSI Control Signal Out 1580 */ 1581register SCSISIGO { 1582 address 0x040 1583 access_mode RW 1584 modes M_DFF0, M_DFF1, M_SCSI 1585 field CDO 0x80 1586 field IOO 0x40 1587 field MSGO 0x20 1588 field ATNO 0x10 1589 field SELO 0x08 1590 field BSYO 0x04 1591 field REQO 0x02 1592 field ACKO 0x01 1593/* 1594 * Possible phases to write into SCSISIG0 1595 */ 1596 enum PHASE_MASK CDO|IOO|MSGO { 1597 P_DATAOUT 0x0, 1598 P_DATAIN IOO, 1599 P_DATAOUT_DT P_DATAOUT|MSGO, 1600 P_DATAIN_DT P_DATAIN|MSGO, 1601 P_COMMAND CDO, 1602 P_MESGOUT CDO|MSGO, 1603 P_STATUS CDO|IOO, 1604 P_MESGIN CDO|IOO|MSGO 1605 } 1606} 1607 1608register SCSISIGI { 1609 address 0x041 1610 access_mode RO 1611 modes M_DFF0, M_DFF1, M_SCSI 1612 field CDI 0x80 1613 field IOI 0x40 1614 field MSGI 0x20 1615 field ATNI 0x10 1616 field SELI 0x08 1617 field BSYI 0x04 1618 field REQI 0x02 1619 field ACKI 0x01 1620/* 1621 * Possible phases in SCSISIGI 1622 */ 1623 enum PHASE_MASK CDO|IOO|MSGO { 1624 P_DATAOUT 0x0, 1625 P_DATAIN IOO, 1626 P_DATAOUT_DT P_DATAOUT|MSGO, 1627 P_DATAIN_DT P_DATAIN|MSGO, 1628 P_COMMAND CDO, 1629 P_MESGOUT CDO|MSGO, 1630 P_STATUS CDO|IOO, 1631 P_MESGIN CDO|IOO|MSGO 1632 } 1633} 1634 1635/* 1636 * Multiple Target IDs 1637 * Bitmask of ids to respond as a target. 1638 */ 1639register MULTARGID { 1640 address 0x040 1641 access_mode RW 1642 modes M_CFG 1643 size 2 1644} 1645 1646/* 1647 * SCSI Phase 1648 */ 1649register SCSIPHASE { 1650 address 0x042 1651 access_mode RO 1652 modes M_DFF0, M_DFF1, M_SCSI 1653 field STATUS_PHASE 0x20 1654 field COMMAND_PHASE 0x10 1655 field MSG_IN_PHASE 0x08 1656 field MSG_OUT_PHASE 0x04 1657 field DATA_PHASE_MASK 0x03 { 1658 DATA_OUT_PHASE 0x01, 1659 DATA_IN_PHASE 0x02 1660 } 1661} 1662 1663/* 1664 * SCSI Data 0 Image 1665 */ 1666register SCSIDAT0_IMG { 1667 address 0x043 1668 access_mode RW 1669 modes M_DFF0, M_DFF1, M_SCSI 1670} 1671 1672/* 1673 * SCSI Latched Data 1674 */ 1675register SCSIDAT { 1676 address 0x044 1677 access_mode RW 1678 modes M_DFF0, M_DFF1, M_SCSI 1679 size 2 1680} 1681 1682/* 1683 * SCSI Data Bus 1684 */ 1685register SCSIBUS { 1686 address 0x046 1687 access_mode RW 1688 modes M_DFF0, M_DFF1, M_SCSI 1689 size 2 1690} 1691 1692/* 1693 * Target ID In 1694 */ 1695register TARGIDIN { 1696 address 0x048 1697 access_mode RO 1698 modes M_DFF0, M_DFF1, M_SCSI 1699 field CLKOUT 0x80 1700 field TARGID 0x0F 1701} 1702 1703/* 1704 * Selection/Reselection ID 1705 * Upper four bits are the device id. The ONEBIT is set when the re/selecting 1706 * device did not set its own ID. 1707 */ 1708register SELID { 1709 address 0x049 1710 access_mode RW 1711 modes M_DFF0, M_DFF1, M_SCSI 1712 field SELID_MASK 0xf0 1713 field ONEBIT 0x08 1714} 1715 1716/* 1717 * SCSI Block Control 1718 * Controls Bus type and channel selection. SELWIDE allows for the 1719 * coexistence of 8bit and 16bit devices on a wide bus. 1720 */ 1721register SBLKCTL { 1722 address 0x04A 1723 access_mode RW 1724 modes M_DFF0, M_DFF1, M_SCSI 1725 field DIAGLEDEN 0x80 1726 field DIAGLEDON 0x40 1727 field ENAB40 0x08 /* LVD transceiver active */ 1728 field ENAB20 0x04 /* SE/HVD transceiver active */ 1729 field SELWIDE 0x02 1730} 1731 1732/* 1733 * Option Mode 1734 */ 1735register OPTIONMODE { 1736 address 0x04A 1737 access_mode RW 1738 modes M_CFG 1739 field BIOSCANCTL 0x80 1740 field AUTOACKEN 0x40 1741 field BIASCANCTL 0x20 1742 field BUSFREEREV 0x10 1743 field ENDGFORMCHK 0x04 1744 field AUTO_MSGOUT_DE 0x02 1745 mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE 1746} 1747 1748/* 1749 * SCSI Status 0 1750 */ 1751register SSTAT0 { 1752 address 0x04B 1753 access_mode RO 1754 modes M_DFF0, M_DFF1, M_SCSI 1755 field TARGET 0x80 /* Board acting as target */ 1756 field SELDO 0x40 /* Selection Done */ 1757 field SELDI 0x20 /* Board has been selected */ 1758 field SELINGO 0x10 /* Selection In Progress */ 1759 field IOERR 0x08 /* LVD Tranceiver mode changed */ 1760 field OVERRUN 0x04 /* SCSI Offset overrun detected */ 1761 field SPIORDY 0x02 /* SCSI PIO Ready */ 1762 field ARBDO 0x01 /* Arbitration Done Out */ 1763} 1764 1765/* 1766 * Clear SCSI Interrupt 0 1767 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 1768 */ 1769register CLRSINT0 { 1770 address 0x04B 1771 access_mode WO 1772 modes M_DFF0, M_DFF1, M_SCSI 1773 field CLRSELDO 0x40 1774 field CLRSELDI 0x20 1775 field CLRSELINGO 0x10 1776 field CLRIOERR 0x08 1777 field CLROVERRUN 0x04 1778 field CLRSPIORDY 0x02 1779 field CLRARBDO 0x01 1780} 1781 1782/* 1783 * SCSI Interrupt Mode 0 1784 * Setting any bit will enable the corresponding function 1785 * in SIMODE0 to interrupt via the IRQ pin. 1786 */ 1787register SIMODE0 { 1788 address 0x04B 1789 access_mode RW 1790 modes M_CFG 1791 field ENSELDO 0x40 1792 field ENSELDI 0x20 1793 field ENSELINGO 0x10 1794 field ENIOERR 0x08 1795 field ENOVERRUN 0x04 1796 field ENSPIORDY 0x02 1797 field ENARBDO 0x01 1798} 1799 1800/* 1801 * SCSI Status 1 1802 */ 1803register SSTAT1 { 1804 address 0x04C 1805 access_mode RO 1806 modes M_DFF0, M_DFF1, M_SCSI 1807 field SELTO 0x80 1808 field ATNTARG 0x40 1809 field SCSIRSTI 0x20 1810 field PHASEMIS 0x10 1811 field BUSFREE 0x08 1812 field SCSIPERR 0x04 1813 field STRB2FAST 0x02 1814 field REQINIT 0x01 1815} 1816 1817/* 1818 * Clear SCSI Interrupt 1 1819 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 1820 */ 1821register CLRSINT1 { 1822 address 0x04C 1823 access_mode WO 1824 modes M_DFF0, M_DFF1, M_SCSI 1825 field CLRSELTIMEO 0x80 1826 field CLRATNO 0x40 1827 field CLRSCSIRSTI 0x20 1828 field CLRBUSFREE 0x08 1829 field CLRSCSIPERR 0x04 1830 field CLRSTRB2FAST 0x02 1831 field CLRREQINIT 0x01 1832} 1833 1834/* 1835 * SCSI Status 2 1836 */ 1837register SSTAT2 { 1838 address 0x04d 1839 access_mode RO 1840 modes M_DFF0, M_DFF1, M_SCSI 1841 field BUSFREETIME 0xc0 { 1842 BUSFREE_LQO 0x40, 1843 BUSFREE_DFF0 0x80, 1844 BUSFREE_DFF1 0xC0 1845 } 1846 field NONPACKREQ 0x20 1847 field EXP_ACTIVE 0x10 /* SCSI Expander Active */ 1848 field BSYX 0x08 /* Busy Expander */ 1849 field WIDE_RES 0x04 /* Modes 0 and 1 only */ 1850 field SDONE 0x02 /* Modes 0 and 1 only */ 1851 field DMADONE 0x01 /* Modes 0 and 1 only */ 1852} 1853 1854/* 1855 * Clear SCSI Interrupt 2 1856 */ 1857register CLRSINT2 { 1858 address 0x04D 1859 access_mode WO 1860 modes M_DFF0, M_DFF1, M_SCSI 1861 field CLRNONPACKREQ 0x20 1862 field CLRWIDE_RES 0x04 /* Modes 0 and 1 only */ 1863 field CLRSDONE 0x02 /* Modes 0 and 1 only */ 1864 field CLRDMADONE 0x01 /* Modes 0 and 1 only */ 1865} 1866 1867/* 1868 * SCSI Interrupt Mode 2 1869 */ 1870register SIMODE2 { 1871 address 0x04D 1872 access_mode RW 1873 modes M_CFG 1874 field ENWIDE_RES 0x04 1875 field ENSDONE 0x02 1876 field ENDMADONE 0x01 1877} 1878 1879/* 1880 * Physical Error Diagnosis 1881 */ 1882register PERRDIAG { 1883 address 0x04E 1884 access_mode RO 1885 modes M_DFF0, M_DFF1, M_SCSI 1886 field HIZERO 0x80 1887 field HIPERR 0x40 1888 field PREVPHASE 0x20 1889 field PARITYERR 0x10 1890 field AIPERR 0x08 1891 field CRCERR 0x04 1892 field DGFORMERR 0x02 1893 field DTERR 0x01 1894} 1895 1896/* 1897 * LQI Manager Current State 1898 */ 1899register LQISTATE { 1900 address 0x04E 1901 access_mode RO 1902 modes M_CFG 1903} 1904 1905/* 1906 * SCSI Offset Count 1907 */ 1908register SOFFCNT { 1909 address 0x04F 1910 access_mode RO 1911 modes M_DFF0, M_DFF1, M_SCSI 1912} 1913 1914/* 1915 * LQO Manager Current State 1916 */ 1917register LQOSTATE { 1918 address 0x04F 1919 access_mode RO 1920 modes M_CFG 1921} 1922 1923/* 1924 * LQI Manager Status 1925 */ 1926register LQISTAT0 { 1927 address 0x050 1928 access_mode RO 1929 modes M_DFF0, M_DFF1, M_SCSI 1930 field LQIATNQAS 0x20 1931 field LQICRCT1 0x10 1932 field LQICRCT2 0x08 1933 field LQIBADLQT 0x04 1934 field LQIATNLQ 0x02 1935 field LQIATNCMD 0x01 1936} 1937 1938/* 1939 * Clear LQI Interrupts 0 1940 */ 1941register CLRLQIINT0 { 1942 address 0x050 1943 access_mode WO 1944 modes M_DFF0, M_DFF1, M_SCSI 1945 field CLRLQIATNQAS 0x20 1946 field CLRLQICRCT1 0x10 1947 field CLRLQICRCT2 0x08 1948 field CLRLQIBADLQT 0x04 1949 field CLRLQIATNLQ 0x02 1950 field CLRLQIATNCMD 0x01 1951} 1952 1953/* 1954 * LQI Manager Interrupt Mode 0 1955 */ 1956register LQIMODE0 { 1957 address 0x050 1958 access_mode RW 1959 modes M_CFG 1960 field ENLQIATNQASK 0x20 1961 field ENLQICRCT1 0x10 1962 field ENLQICRCT2 0x08 1963 field ENLQIBADLQT 0x04 1964 field ENLQIATNLQ 0x02 1965 field ENLQIATNCMD 0x01 1966} 1967 1968/* 1969 * LQI Manager Status 1 1970 */ 1971register LQISTAT1 { 1972 address 0x051 1973 access_mode RO 1974 modes M_DFF0, M_DFF1, M_SCSI 1975 field LQIPHASE_LQ 0x80 1976 field LQIPHASE_NLQ 0x40 1977 field LQIABORT 0x20 1978 field LQICRCI_LQ 0x10 1979 field LQICRCI_NLQ 0x08 1980 field LQIBADLQI 0x04 1981 field LQIOVERI_LQ 0x02 1982 field LQIOVERI_NLQ 0x01 1983} 1984 1985/* 1986 * Clear LQI Manager Interrupts1 1987 */ 1988register CLRLQIINT1 { 1989 address 0x051 1990 access_mode WO 1991 modes M_DFF0, M_DFF1, M_SCSI 1992 field CLRLQIPHASE_LQ 0x80 1993 field CLRLQIPHASE_NLQ 0x40 1994 field CLRLIQABORT 0x20 1995 field CLRLQICRCI_LQ 0x10 1996 field CLRLQICRCI_NLQ 0x08 1997 field CLRLQIBADLQI 0x04 1998 field CLRLQIOVERI_LQ 0x02 1999 field CLRLQIOVERI_NLQ 0x01 2000} 2001 2002/* 2003 * LQI Manager Interrupt Mode 1 2004 */ 2005register LQIMODE1 { 2006 address 0x051 2007 access_mode RW 2008 modes M_CFG 2009 field ENLQIPHASE_LQ 0x80 2010 field ENLQIPHASE_NLQ 0x40 2011 field ENLIQABORT 0x20 2012 field ENLQICRCI_LQ 0x10 2013 field ENLQICRCI_NLQ 0x08 2014 field ENLQIBADLQI 0x04 2015 field ENLQIOVERI_LQ 0x02 2016 field ENLQIOVERI_NLQ 0x01 2017} 2018 2019/* 2020 * LQI Manager Status 2 2021 */ 2022register LQISTAT2 { 2023 address 0x052 2024 access_mode RO 2025 modes M_DFF0, M_DFF1, M_SCSI 2026 field PACKETIZED 0x80 2027 field LQIPHASE_OUTPKT 0x40 2028 field LQIWORKONLQ 0x20 2029 field LQIWAITFIFO 0x10 2030 field LQISTOPPKT 0x08 2031 field LQISTOPLQ 0x04 2032 field LQISTOPCMD 0x02 2033 field LQIGSAVAIL 0x01 2034} 2035 2036/* 2037 * SCSI Status 3 2038 */ 2039register SSTAT3 { 2040 address 0x053 2041 access_mode RO 2042 modes M_DFF0, M_DFF1, M_SCSI 2043 field NTRAMPERR 0x02 2044 field OSRAMPERR 0x01 2045} 2046 2047/* 2048 * Clear SCSI Status 3 2049 */ 2050register CLRSINT3 { 2051 address 0x053 2052 access_mode WO 2053 modes M_DFF0, M_DFF1, M_SCSI 2054 field CLRNTRAMPERR 0x02 2055 field CLROSRAMPERR 0x01 2056} 2057 2058/* 2059 * SCSI Interrupt Mode 3 2060 */ 2061register SIMODE3 { 2062 address 0x053 2063 access_mode RW 2064 modes M_CFG 2065 field ENNTRAMPERR 0x02 2066 field ENOSRAMPERR 0x01 2067} 2068 2069/* 2070 * LQO Manager Status 0 2071 */ 2072register LQOSTAT0 { 2073 address 0x054 2074 access_mode RO 2075 modes M_DFF0, M_DFF1, M_SCSI 2076 field LQOTARGSCBPERR 0x10 2077 field LQOSTOPT2 0x08 2078 field LQOATNLQ 0x04 2079 field LQOATNPKT 0x02 2080 field LQOTCRC 0x01 2081} 2082 2083/* 2084 * Clear LQO Manager interrupt 0 2085 */ 2086register CLRLQOINT0 { 2087 address 0x054 2088 access_mode WO 2089 modes M_DFF0, M_DFF1, M_SCSI 2090 field CLRLQOTARGSCBPERR 0x10 2091 field CLRLQOSTOPT2 0x08 2092 field CLRLQOATNLQ 0x04 2093 field CLRLQOATNPKT 0x02 2094 field CLRLQOTCRC 0x01 2095} 2096 2097/* 2098 * LQO Manager Interrupt Mode 0 2099 */ 2100register LQOMODE0 { 2101 address 0x054 2102 access_mode RW 2103 modes M_CFG 2104 field ENLQOTARGSCBPERR 0x10 2105 field ENLQOSTOPT2 0x08 2106 field ENLQOATNLQ 0x04 2107 field ENLQOATNPKT 0x02 2108 field ENLQOTCRC 0x01 2109} 2110 2111/* 2112 * LQO Manager Status 1 2113 */ 2114register LQOSTAT1 { 2115 address 0x055 2116 access_mode RO 2117 modes M_DFF0, M_DFF1, M_SCSI 2118 field LQOINITSCBPERR 0x10 2119 field LQOSTOPI2 0x08 2120 field LQOBADQAS 0x04 2121 field LQOBUSFREE 0x02 2122 field LQOPHACHGINPKT 0x01 2123} 2124 2125/* 2126 * Clear LOQ Interrupt 1 2127 */ 2128register CLRLQOINT1 { 2129 address 0x055 2130 access_mode WO 2131 modes M_DFF0, M_DFF1, M_SCSI 2132 field CLRLQOINITSCBPERR 0x10 2133 field CLRLQOSTOPI2 0x08 2134 field CLRLQOBADQAS 0x04 2135 field CLRLQOBUSFREE 0x02 2136 field CLRLQOPHACHGINPKT 0x01 2137} 2138 2139/* 2140 * LQO Manager Interrupt Mode 1 2141 */ 2142register LQOMODE1 { 2143 address 0x055 2144 access_mode RW 2145 modes M_CFG 2146 field ENLQOINITSCBPERR 0x10 2147 field ENLQOSTOPI2 0x08 2148 field ENLQOBADQAS 0x04 2149 field ENLQOBUSFREE 0x02 2150 field ENLQOPHACHGINPKT 0x01 2151} 2152 2153/* 2154 * LQO Manager Status 2 2155 */ 2156register LQOSTAT2 { 2157 address 0x056 2158 access_mode RO 2159 modes M_DFF0, M_DFF1, M_SCSI 2160 field LQOPKT 0xE0 2161 field LQOWAITFIFO 0x10 2162 field LQOPHACHGOUTPKT 0x02 /* outside of packet boundaries. */ 2163 field LQOSTOP0 0x01 /* Stopped after sending all packets */ 2164} 2165 2166/* 2167 * Output Synchronizer Space Count 2168 */ 2169register OS_SPACE_CNT { 2170 address 0x056 2171 access_mode RO 2172 modes M_CFG 2173} 2174 2175/* 2176 * SCSI Interrupt Mode 1 2177 * Setting any bit will enable the corresponding function 2178 * in SIMODE1 to interrupt via the IRQ pin. 2179 */ 2180register SIMODE1 { 2181 address 0x057 2182 access_mode RW 2183 modes M_DFF0, M_DFF1, M_SCSI 2184 field ENSELTIMO 0x80 2185 field ENATNTARG 0x40 2186 field ENSCSIRST 0x20 2187 field ENPHASEMIS 0x10 2188 field ENBUSFREE 0x08 2189 field ENSCSIPERR 0x04 2190 field ENSTRB2FAST 0x02 2191 field ENREQINIT 0x01 2192} 2193 2194/* 2195 * Good Status FIFO 2196 */ 2197register GSFIFO { 2198 address 0x058 2199 access_mode RO 2200 size 2 2201 modes M_DFF0, M_DFF1, M_SCSI 2202} 2203 2204/* 2205 * Data FIFO SCSI Transfer Control 2206 */ 2207register DFFSXFRCTL { 2208 address 0x05A 2209 access_mode RW 2210 modes M_DFF0, M_DFF1 2211 field CLRSHCNT 0x04 2212 field CLRCHN 0x02 2213 field RSTCHN 0x01 2214} 2215 2216/* 2217 * Next SCSI Control Block 2218 */ 2219register NEXTSCB { 2220 address 0x05A 2221 access_mode RW 2222 size 2 2223 modes M_SCSI 2224} 2225 2226/* 2227 * SEQ Interrupts 2228 */ 2229register SEQINTSRC { 2230 address 0x05B 2231 access_mode RO 2232 modes M_DFF0, M_DFF1 2233 field CTXTDONE 0x40 2234 field SAVEPTRS 0x20 2235 field CFG4DATA 0x10 2236 field CFG4ISTAT 0x08 2237 field CFG4TSTAT 0x04 2238 field CFG4ICMD 0x02 2239 field CFG4TCMD 0x01 2240} 2241 2242/* 2243 * Clear Arp Interrupts 2244 */ 2245register CLRSEQINTSRC { 2246 address 0x05B 2247 access_mode WO 2248 modes M_DFF0, M_DFF1 2249 field CLRCTXTDONE 0x40 2250 field CLRSAVEPTRS 0x20 2251 field CLRCFG4DATA 0x10 2252 field CLRCFG4ISTAT 0x08 2253 field CLRCFG4TSTAT 0x04 2254 field CLRCFG4ICMD 0x02 2255 field CLRCFG4TCMD 0x01 2256} 2257 2258/* 2259 * SEQ Interrupt Enabled (Shared) 2260 */ 2261register SEQIMODE { 2262 address 0x05C 2263 access_mode RW 2264 modes M_DFF0, M_DFF1 2265 field ENCTXTDONE 0x40 2266 field ENSAVEPTRS 0x20 2267 field ENCFG4DATA 0x10 2268 field ENCFG4ISTAT 0x08 2269 field ENCFG4TSTAT 0x04 2270 field ENCFG4ICMD 0x02 2271 field ENCFG4TCMD 0x01 2272} 2273 2274/* 2275 * Current SCSI Control Block 2276 */ 2277register CURRSCB { 2278 address 0x05C 2279 access_mode RW 2280 size 2 2281 modes M_SCSI 2282} 2283 2284/* 2285 * Data FIFO Status 2286 */ 2287register MDFFSTAT { 2288 address 0x05D 2289 access_mode RO 2290 modes M_DFF0, M_DFF1 2291 field SHCNTNEGATIVE 0x40 /* Rev B or higher */ 2292 field SHCNTMINUS1 0x20 /* Rev B or higher */ 2293 field LASTSDONE 0x10 2294 field SHVALID 0x08 2295 field DLZERO 0x04 /* FIFO data ends on packet boundary. */ 2296 field DATAINFIFO 0x02 2297 field FIFOFREE 0x01 2298} 2299 2300/* 2301 * CRC Control 2302 */ 2303register CRCCONTROL { 2304 address 0x05d 2305 access_mode RW 2306 modes M_CFG 2307 field CRCVALCHKEN 0x40 2308} 2309 2310/* 2311 * SCSI Test Control 2312 */ 2313register SCSITEST { 2314 address 0x05E 2315 access_mode RW 2316 modes M_CFG 2317 field CNTRTEST 0x08 2318 field SEL_TXPLL_DEBUG 0x04 2319} 2320 2321/* 2322 * Data FIFO Queue Tag 2323 */ 2324register DFFTAG { 2325 address 0x05E 2326 access_mode RW 2327 size 2 2328 modes M_DFF0, M_DFF1 2329} 2330 2331/* 2332 * Last SCSI Control Block 2333 */ 2334register LASTSCB { 2335 address 0x05E 2336 access_mode RW 2337 size 2 2338 modes M_SCSI 2339} 2340 2341/* 2342 * SCSI I/O Cell Power-down Control 2343 */ 2344register IOPDNCTL { 2345 address 0x05F 2346 access_mode RW 2347 modes M_CFG 2348 field DISABLE_OE 0x80 2349 field PDN_IDIST 0x04 2350 field PDN_DIFFSENSE 0x01 2351} 2352 2353/* 2354 * Shaddow Host Address. 2355 */ 2356register SHADDR { 2357 address 0x060 2358 access_mode RO 2359 size 8 2360 modes M_DFF0, M_DFF1 2361} 2362 2363/* 2364 * Data Group CRC Interval. 2365 */ 2366register DGRPCRCI { 2367 address 0x060 2368 access_mode RW 2369 size 2 2370 modes M_CFG 2371} 2372 2373/* 2374 * Data Transfer Negotiation Address 2375 */ 2376register NEGOADDR { 2377 address 0x060 2378 access_mode RW 2379 modes M_SCSI 2380} 2381 2382/* 2383 * Data Transfer Negotiation Data - Period Byte 2384 */ 2385register NEGPERIOD { 2386 address 0x061 2387 access_mode RW 2388 modes M_SCSI 2389} 2390 2391/* 2392 * Packetized CRC Interval 2393 */ 2394register PACKCRCI { 2395 address 0x062 2396 access_mode RW 2397 size 2 2398 modes M_CFG 2399} 2400 2401/* 2402 * Data Transfer Negotiation Data - Offset Byte 2403 */ 2404register NEGOFFSET { 2405 address 0x062 2406 access_mode RW 2407 modes M_SCSI 2408} 2409 2410/* 2411 * Data Transfer Negotiation Data - PPR Options 2412 */ 2413register NEGPPROPTS { 2414 address 0x063 2415 access_mode RW 2416 modes M_SCSI 2417 field PPROPT_PACE 0x08 2418 field PPROPT_QAS 0x04 2419 field PPROPT_DT 0x02 2420 field PPROPT_IUT 0x01 2421} 2422 2423/* 2424 * Data Transfer Negotiation Data - Connection Options 2425 */ 2426register NEGCONOPTS { 2427 address 0x064 2428 access_mode RW 2429 modes M_SCSI 2430 field ENAIP 0x08 2431 field ENAUTOATNI 0x04 2432 field ENAUTOATNO 0x02 2433 field WIDEXFER 0x01 2434} 2435 2436/* 2437 * Negotiation Table Annex Column Index. 2438 */ 2439register ANNEXCOL { 2440 address 0x065 2441 access_mode RW 2442 modes M_SCSI 2443} 2444 2445register SCSCHKN { 2446 address 0x066 2447 access_mode RW 2448 modes M_CFG 2449 field STSELSKIDDIS 0x40 2450 field CURFIFODEF 0x20 2451 field WIDERESEN 0x10 2452 field SDONEMSKDIS 0x08 2453 field DFFACTCLR 0x04 2454 field SHVALIDSTDIS 0x02 2455 field LSTSGCLRDIS 0x01 2456} 2457 2458const AHD_ANNEXCOL_PRECOMP 4 2459const AHD_PRECOMP_MASK 0x07 2460const AHD_PRECOMP_CUTBACK_17 0x04 2461const AHD_PRECOMP_CUTBACK_29 0x06 2462const AHD_PRECOMP_CUTBACK_37 0x07 2463const AHD_PRECOMP_FASTSLEW 0x40 2464const AHD_NUM_ANNEXCOLS 4 2465 2466/* 2467 * Negotiation Table Annex Data Port. 2468 */ 2469register ANNEXDAT { 2470 address 0x066 2471 access_mode RW 2472 modes M_SCSI 2473} 2474 2475/* 2476 * Initiator's Own Id. 2477 * The SCSI ID to use for Selection Out and seen during a reselection.. 2478 */ 2479register IOWNID { 2480 address 0x067 2481 access_mode RW 2482 modes M_SCSI 2483} 2484 2485/* 2486 * 960MHz Phase-Locked Loop Control 0 2487 */ 2488register PLL960CTL0 { 2489 address 0x068 2490 access_mode RW 2491 modes M_CFG 2492 field PLL_VCOSEL 0x80 2493 field PLL_PWDN 0x40 2494 field PLL_NS 0x30 2495 field PLL_ENLUD 0x08 2496 field PLL_ENLPF 0x04 2497 field PLL_DLPF 0x02 2498 field PLL_ENFBM 0x01 2499} 2500 2501/* 2502 * Target Own Id 2503 */ 2504register TOWNID { 2505 address 0x069 2506 access_mode RW 2507 modes M_SCSI 2508} 2509 2510/* 2511 * 960MHz Phase-Locked Loop Control 1 2512 */ 2513register PLL960CTL1 { 2514 address 0x069 2515 access_mode RW 2516 modes M_CFG 2517 field PLL_CNTEN 0x80 2518 field PLL_CNTCLR 0x40 2519 field PLL_RST 0x01 2520} 2521 2522/* 2523 * Expander Signature 2524 */ 2525register XSIG { 2526 address 0x06A 2527 access_mode RW 2528 modes M_SCSI 2529} 2530 2531/* 2532 * Shadow Byte Count 2533 */ 2534register SHCNT { 2535 address 0x068 2536 access_mode RW 2537 size 3 2538 modes M_DFF0, M_DFF1 2539} 2540 2541/* 2542 * Selection Out ID 2543 */ 2544register SELOID { 2545 address 0x06B 2546 access_mode RW 2547 modes M_SCSI 2548} 2549 2550/* 2551 * 960-MHz Phase-Locked Loop Test Count 2552 */ 2553register PLL960CNT0 { 2554 address 0x06A 2555 access_mode RO 2556 size 2 2557 modes M_CFG 2558} 2559 2560/* 2561 * 400-MHz Phase-Locked Loop Control 0 2562 */ 2563register PLL400CTL0 { 2564 address 0x06C 2565 access_mode RW 2566 modes M_CFG 2567 field PLL_VCOSEL 0x80 2568 field PLL_PWDN 0x40 2569 field PLL_NS 0x30 2570 field PLL_ENLUD 0x08 2571 field PLL_ENLPF 0x04 2572 field PLL_DLPF 0x02 2573 field PLL_ENFBM 0x01 2574} 2575 2576/* 2577 * Arbitration Fairness 2578 */ 2579register FAIRNESS { 2580 address 0x06C 2581 access_mode RW 2582 size 2 2583 modes M_SCSI 2584} 2585 2586/* 2587 * 400-MHz Phase-Locked Loop Control 1 2588 */ 2589register PLL400CTL1 { 2590 address 0x06D 2591 access_mode RW 2592 modes M_CFG 2593 field PLL_CNTEN 0x80 2594 field PLL_CNTCLR 0x40 2595 field PLL_RST 0x01 2596} 2597 2598/* 2599 * Arbitration Unfairness 2600 */ 2601register UNFAIRNESS { 2602 address 0x06E 2603 access_mode RW 2604 size 2 2605 modes M_SCSI 2606} 2607 2608/* 2609 * 400-MHz Phase-Locked Loop Test Count 2610 */ 2611register PLL400CNT0 { 2612 address 0x06E 2613 access_mode RO 2614 size 2 2615 modes M_CFG 2616} 2617 2618/* 2619 * SCB Page Pointer 2620 */ 2621register SCBPTR { 2622 address 0x0A8 2623 access_mode RW 2624 size 2 2625 modes M_DFF0, M_DFF1, M_CCHAN, M_SCSI 2626} 2627 2628/* 2629 * CMC SCB Array Count 2630 * Number of bytes to transfer between CMC SCB memory and SCBRAM. 2631 * Transfers must be 8byte aligned and sized. 2632 */ 2633register CCSCBACNT { 2634 address 0x0AB 2635 access_mode RW 2636 modes M_CCHAN 2637} 2638 2639/* 2640 * SCB Autopointer 2641 * SCB-Next Address Snooping logic. When an SCB is transferred to 2642 * the card, the next SCB address to be used by the CMC array can 2643 * be autoloaded from that transfer. 2644 */ 2645register SCBAUTOPTR { 2646 address 0x0AB 2647 access_mode RW 2648 modes M_CFG 2649 field AUSCBPTR_EN 0x80 2650 field SCBPTR_ADDR 0x38 2651 field SCBPTR_OFF 0x07 2652} 2653 2654/* 2655 * CMC SG Ram Address Pointer 2656 */ 2657register CCSGADDR { 2658 address 0x0AC 2659 access_mode RW 2660 modes M_DFF0, M_DFF1 2661} 2662 2663/* 2664 * CMC SCB RAM Address Pointer 2665 */ 2666register CCSCBADDR { 2667 address 0x0AC 2668 access_mode RW 2669 modes M_CCHAN 2670} 2671 2672/* 2673 * CMC SCB Ram Back-up Address Pointer 2674 * Indicates the true stop location of transfers halted prior 2675 * to SCBHCNT going to 0. 2676 */ 2677register CCSCBADR_BK { 2678 address 0x0AC 2679 access_mode RO 2680 modes M_CFG 2681} 2682 2683/* 2684 * CMC SG Control 2685 */ 2686register CCSGCTL { 2687 address 0x0AD 2688 access_mode RW 2689 modes M_DFF0, M_DFF1 2690 field CCSGDONE 0x80 2691 field SG_CACHE_AVAIL 0x10 2692 field CCSGEN 0x08 2693 field SG_FETCH_REQ 0x02 2694 field CCSGRESET 0x01 2695} 2696 2697/* 2698 * CMD SCB Control 2699 */ 2700register CCSCBCTL { 2701 address 0x0AD 2702 access_mode RW 2703 modes M_CCHAN 2704 field CCSCBDONE 0x80 2705 field ARRDONE 0x40 2706 field CCARREN 0x10 2707 field CCSCBEN 0x08 2708 field CCSCBDIR 0x04 2709 field CCSCBRESET 0x01 2710} 2711 2712/* 2713 * CMC Ram BIST 2714 */ 2715register CMC_RAMBIST { 2716 address 0x0AD 2717 access_mode RW 2718 modes M_CFG 2719 field SG_ELEMENT_SIZE 0x80 2720 field SCBRAMBIST_FAIL 0x40 2721 field SG_BIST_FAIL 0x20 2722 field SG_BIST_EN 0x10 2723 field CMC_BUFFER_BIST_FAIL 0x02 2724 field CMC_BUFFER_BIST_EN 0x01 2725} 2726 2727/* 2728 * CMC SG RAM Data Port 2729 */ 2730register CCSGRAM { 2731 address 0x0B0 2732 access_mode RW 2733 modes M_DFF0, M_DFF1 2734} 2735 2736/* 2737 * CMC SCB RAM Data Port 2738 */ 2739register CCSCBRAM { 2740 address 0x0B0 2741 access_mode RW 2742 modes M_CCHAN 2743} 2744 2745/* 2746 * Flex DMA Address. 2747 */ 2748register FLEXADR { 2749 address 0x0B0 2750 access_mode RW 2751 size 3 2752 modes M_SCSI 2753} 2754 2755/* 2756 * Flex DMA Byte Count 2757 */ 2758register FLEXCNT { 2759 address 0x0B3 2760 access_mode RW 2761 size 2 2762 modes M_SCSI 2763} 2764 2765/* 2766 * Flex DMA Status 2767 */ 2768register FLEXDMASTAT { 2769 address 0x0B5 2770 access_mode RW 2771 modes M_SCSI 2772 field FLEXDMAERR 0x02 2773 field FLEXDMADONE 0x01 2774} 2775 2776/* 2777 * Flex DMA Data Port 2778 */ 2779register FLEXDATA { 2780 address 0x0B6 2781 access_mode RW 2782 modes M_SCSI 2783} 2784 2785/* 2786 * Board Data 2787 */ 2788register BRDDAT { 2789 address 0x0B8 2790 access_mode RW 2791 modes M_SCSI 2792} 2793 2794/* 2795 * Board Control 2796 */ 2797register BRDCTL { 2798 address 0x0B9 2799 access_mode RW 2800 modes M_SCSI 2801 field FLXARBACK 0x80 2802 field FLXARBREQ 0x40 2803 field BRDADDR 0x38 2804 field BRDEN 0x04 2805 field BRDRW 0x02 2806 field BRDSTB 0x01 2807} 2808 2809/* 2810 * Serial EEPROM Address 2811 */ 2812register SEEADR { 2813 address 0x0BA 2814 access_mode RW 2815 modes M_SCSI 2816} 2817 2818/* 2819 * Serial EEPROM Data 2820 */ 2821register SEEDAT { 2822 address 0x0BC 2823 access_mode RW 2824 size 2 2825 modes M_SCSI 2826} 2827 2828/* 2829 * Serial EEPROM Status 2830 */ 2831register SEESTAT { 2832 address 0x0BE 2833 access_mode RO 2834 modes M_SCSI 2835 field INIT_DONE 0x80 2836 field SEEOPCODE 0x70 2837 field LDALTID_L 0x08 2838 field SEEARBACK 0x04 2839 field SEEBUSY 0x02 2840 field SEESTART 0x01 2841} 2842 2843/* 2844 * Serial EEPROM Control 2845 */ 2846register SEECTL { 2847 address 0x0BE 2848 access_mode RW 2849 modes M_SCSI 2850 field SEEOPCODE 0x70 { 2851 SEEOP_ERASE 0x70, 2852 SEEOP_READ 0x60, 2853 SEEOP_WRITE 0x50, 2854 /* 2855 * The following four commands use special 2856 * addresses for differentiation. 2857 */ 2858 SEEOP_ERAL 0x40 2859 } 2860 mask SEEOP_EWEN 0x40 2861 mask SEEOP_WALL 0x40 2862 mask SEEOP_EWDS 0x40 2863 field SEERST 0x02 2864 field SEESTART 0x01 2865} 2866 2867const SEEOP_ERAL_ADDR 0x80 2868const SEEOP_EWEN_ADDR 0xC0 2869const SEEOP_WRAL_ADDR 0x40 2870const SEEOP_EWDS_ADDR 0x00 2871 2872/* 2873 * SCB Counter 2874 */ 2875register SCBCNT { 2876 address 0x0BF 2877 access_mode RW 2878 modes M_SCSI 2879} 2880 2881/* 2882 * Data FIFO Write Address 2883 * Pointer to the next QWD location to be written to the data FIFO. 2884 */ 2885register DFWADDR { 2886 address 0x0C0 2887 access_mode RW 2888 size 2 2889 modes M_DFF0, M_DFF1 2890} 2891 2892/* 2893 * DSP Filter Control 2894 */ 2895register DSPFLTRCTL { 2896 address 0x0C0 2897 access_mode RW 2898 modes M_CFG 2899 field FLTRDISABLE 0x20 2900 field EDGESENSE 0x10 2901 field DSPFCNTSEL 0x0F 2902} 2903 2904/* 2905 * DSP Data Channel Control 2906 */ 2907register DSPDATACTL { 2908 address 0x0C1 2909 access_mode RW 2910 modes M_CFG 2911 field BYPASSENAB 0x80 2912 field DESQDIS 0x10 2913 field RCVROFFSTDIS 0x04 2914 field XMITOFFSTDIS 0x02 2915} 2916 2917/* 2918 * Data FIFO Read Address 2919 * Pointer to the next QWD location to be read from the data FIFO. 2920 */ 2921register DFRADDR { 2922 address 0x0C2 2923 access_mode RW 2924 size 2 2925 modes M_DFF0, M_DFF1 2926} 2927 2928/* 2929 * DSP REQ Control 2930 */ 2931register DSPREQCTL { 2932 address 0x0C2 2933 access_mode RW 2934 modes M_CFG 2935 field MANREQCTL 0xC0 2936 field MANREQDLY 0x3F 2937} 2938 2939/* 2940 * DSP ACK Control 2941 */ 2942register DSPACKCTL { 2943 address 0x0C3 2944 access_mode RW 2945 modes M_CFG 2946 field MANACKCTL 0xC0 2947 field MANACKDLY 0x3F 2948} 2949 2950/* 2951 * Data FIFO Data 2952 * Read/Write byte port into the data FIFO. The read and write 2953 * FIFO pointers increment with each read and write respectively 2954 * to this port. 2955 */ 2956register DFDAT { 2957 address 0x0C4 2958 access_mode RW 2959 modes M_DFF0, M_DFF1 2960} 2961 2962/* 2963 * DSP Channel Select 2964 */ 2965register DSPSELECT { 2966 address 0x0C4 2967 access_mode RW 2968 modes M_CFG 2969 field AUTOINCEN 0x80 2970 field DSPSEL 0x1F 2971} 2972 2973const NUMDSPS 0x14 2974 2975/* 2976 * Write Bias Control 2977 */ 2978register WRTBIASCTL { 2979 address 0x0C5 2980 access_mode WO 2981 modes M_CFG 2982 field AUTOXBCDIS 0x80 2983 field XMITMANVAL 0x3F 2984} 2985 2986const WRTBIASCTL_CPQ_DEFAULT 0x97 2987 2988/* 2989 * Receiver Bias Control 2990 */ 2991register RCVRBIOSCTL { 2992 address 0x0C6 2993 access_mode WO 2994 modes M_CFG 2995 field AUTORBCDIS 0x80 2996 field RCVRMANVAL 0x3F 2997} 2998 2999/* 3000 * Write Bias Calculator 3001 */ 3002register WRTBIASCALC { 3003 address 0x0C7 3004 access_mode RO 3005 modes M_CFG 3006} 3007 3008/* 3009 * Data FIFO Pointers 3010 * Contains the byte offset from DFWADDR and DWRADDR to the current 3011 * FIFO write/read locations. 3012 */ 3013register DFPTRS { 3014 address 0x0C8 3015 access_mode RW 3016 modes M_DFF0, M_DFF1 3017} 3018 3019/* 3020 * Receiver Bias Calculator 3021 */ 3022register RCVRBIASCALC { 3023 address 0x0C8 3024 access_mode RO 3025 modes M_CFG 3026} 3027 3028/* 3029 * Data FIFO Debug Control 3030 */ 3031register DFDBCTL { 3032 address 0x0C8 3033 access_mode RW 3034 modes M_DFF0, M_DFF1 3035 field DFF_CIO_WR_RDY 0x20 3036 field DFF_CIO_RD_RDY 0x10 3037 field DFF_DIR_ERR 0x08 3038 field DFF_RAMBIST_FAIL 0x04 3039 field DFF_RAMBIST_DONE 0x02 3040 field DFF_RAMBIST_EN 0x01 3041} 3042 3043/* 3044 * Data FIFO Backup Read Pointer 3045 * Contains the data FIFO address to be restored if the last 3046 * data accessed from the data FIFO was not transferred successfully. 3047 */ 3048register DFBKPTR { 3049 address 0x0C9 3050 access_mode RW 3051 size 2 3052 modes M_DFF0, M_DFF1 3053} 3054 3055/* 3056 * Skew Calculator 3057 */ 3058register SKEWCALC { 3059 address 0x0C9 3060 access_mode RO 3061 modes M_CFG 3062} 3063 3064/* 3065 * Data FIFO Space Count 3066 * Number of FIFO locations that are free. 3067 */ 3068register DFSCNT { 3069 address 0x0CC 3070 access_mode RO 3071 size 2 3072 modes M_DFF0, M_DFF1 3073} 3074 3075/* 3076 * Data FIFO Byte Count 3077 * Number of filled FIFO locations. 3078 */ 3079register DFBCNT { 3080 address 0x0CE 3081 access_mode RO 3082 size 2 3083 modes M_DFF0, M_DFF1 3084} 3085 3086/* 3087 * Sequencer Program Overlay Address. 3088 * Low address must be written prior to high address. 3089 */ 3090register OVLYADDR { 3091 address 0x0D4 3092 modes M_SCSI 3093 size 2 3094 access_mode RW 3095} 3096 3097/* 3098 * Sequencer Control 0 3099 * Error detection mode, speed configuration, 3100 * single step, breakpoints and program load. 3101 */ 3102register SEQCTL0 { 3103 address 0x0D6 3104 access_mode RW 3105 field PERRORDIS 0x80 3106 field PAUSEDIS 0x40 3107 field FAILDIS 0x20 3108 field FASTMODE 0x10 3109 field BRKADRINTEN 0x08 3110 field STEP 0x04 3111 field SEQRESET 0x02 3112 field LOADRAM 0x01 3113} 3114 3115/* 3116 * Sequencer Control 1 3117 * Instruction RAM Diagnostics 3118 */ 3119register SEQCTL1 { 3120 address 0x0D7 3121 access_mode RW 3122 field OVRLAY_DATA_CHK 0x08 3123 field RAMBIST_DONE 0x04 3124 field RAMBIST_FAIL 0x02 3125 field RAMBIST_EN 0x01 3126} 3127 3128/* 3129 * Sequencer Flags 3130 * Zero and Carry state of the ALU. 3131 */ 3132register FLAGS { 3133 address 0x0D8 3134 access_mode RO 3135 field ZERO 0x02 3136 field CARRY 0x01 3137} 3138 3139/* 3140 * Sequencer Interrupt Control 3141 */ 3142register SEQINTCTL { 3143 address 0x0D9 3144 access_mode RW 3145 field INTVEC1DSL 0x80 3146 field INT1_CONTEXT 0x20 3147 field SCS_SEQ_INT1M1 0x10 3148 field SCS_SEQ_INT1M0 0x08 3149 field INTMASK 0x06 3150 field IRET 0x01 3151} 3152 3153/* 3154 * Sequencer RAM Data Port 3155 * Single byte window into the Sequencer Instruction Ram area starting 3156 * at the address specified by OVLYADDR. To write a full instruction word, 3157 * simply write four bytes in succession. OVLYADDR will increment after the 3158 * most significant instrution byte (the byte with the parity bit) is written. 3159 */ 3160register SEQRAM { 3161 address 0x0DA 3162 access_mode RW 3163} 3164 3165/* 3166 * Sequencer Program Counter 3167 * Low byte must be written prior to high byte. 3168 */ 3169register PRGMCNT { 3170 address 0x0DE 3171 access_mode RW 3172 size 2 3173} 3174 3175/* 3176 * Accumulator 3177 */ 3178register ACCUM { 3179 address 0x0E0 3180 access_mode RW 3181 accumulator 3182} 3183 3184/* 3185 * Source Index Register 3186 * Incrementing index for reads of SINDIR and the destination (low byte only) 3187 * for any immediate operands passed in jmp, jc, jnc, call instructions. 3188 * Example: 3189 * mvi 0xFF call some_routine; 3190 * 3191 * Will set SINDEX[0] to 0xFF and call the routine "some_routine. 3192 */ 3193register SINDEX { 3194 address 0x0E2 3195 access_mode RW 3196 size 2 3197 sindex 3198} 3199 3200/* 3201 * Destination Index Register 3202 * Incrementing index for writes to DINDIR. Can be used as a scratch register. 3203 */ 3204register DINDEX { 3205 address 0x0E4 3206 access_mode RW 3207 size 2 3208} 3209 3210/* 3211 * Break Address 3212 * Sequencer instruction breakpoint address address. 3213 */ 3214register BRKADDR0 { 3215 address 0x0E6 3216 access_mode RW 3217} 3218 3219register BRKADDR1 { 3220 address 0x0E6 3221 access_mode RW 3222 field BRKDIS 0x80 /* Disable Breakpoint */ 3223} 3224 3225/* 3226 * All Ones 3227 * All reads to this register return the value 0xFF. 3228 */ 3229register ALLONES { 3230 address 0x0E8 3231 access_mode RO 3232 allones 3233} 3234 3235/* 3236 * All Zeros 3237 * All reads to this register return the value 0. 3238 */ 3239register ALLZEROS { 3240 address 0x0EA 3241 access_mode RO 3242 allzeros 3243} 3244 3245/* 3246 * No Destination 3247 * Writes to this register have no effect. 3248 */ 3249register NONE { 3250 address 0x0EA 3251 access_mode WO 3252 none 3253} 3254 3255/* 3256 * Source Index Indirect 3257 * Reading this register is equivalent to reading (register_base + SINDEX) and 3258 * incrementing SINDEX by 1. 3259 */ 3260register SINDIR { 3261 address 0x0EC 3262 access_mode RO 3263} 3264 3265/* 3266 * Destination Index Indirect 3267 * Writing this register is equivalent to writing to (register_base + DINDEX) 3268 * and incrementing DINDEX by 1. 3269 */ 3270register DINDIR { 3271 address 0x0ED 3272 access_mode WO 3273} 3274 3275/* 3276 * Function One 3277 * 2's complement to bit value conversion. Write the 2's complement value 3278 * (0-7 only) to the top nibble and retrieve the bit indexed by that value 3279 * on the next read of this register. 3280 * Example: 3281 * Write 0x60 3282 * Read 0x40 3283 */ 3284register FUNCTION1 { 3285 address 0x0F0 3286 access_mode RW 3287} 3288 3289/* 3290 * Stack 3291 * Window into the stack. Each stack location is 10 bits wide reported 3292 * low byte followed by high byte. There are 8 stack locations. 3293 */ 3294register STACK { 3295 address 0x0F2 3296 access_mode RW 3297} 3298 3299/* 3300 * Interrupt Vector 1 Address 3301 * Interrupt branch address for SCS SEQ_INT1 mode 0 and 1 interrupts. 3302 */ 3303register INTVEC1_ADDR { 3304 address 0x0F4 3305 access_mode RW 3306 size 2 3307 modes M_CFG 3308} 3309 3310/* 3311 * Current Address 3312 * Address of the SEQRAM instruction currently executing instruction. 3313 */ 3314register CURADDR { 3315 address 0x0F4 3316 access_mode RW 3317 size 2 3318 modes M_SCSI 3319} 3320 3321/* 3322 * Interrupt Vector 2 Address 3323 * Interrupt branch address for HST_SEQ_INT2 interrupts. 3324 */ 3325register INTVEC2_ADDR { 3326 address 0x0F6 3327 access_mode RW 3328 size 2 3329 modes M_CFG 3330} 3331 3332/* 3333 * Last Address 3334 * Address of the SEQRAM instruction executed prior to the current instruction. 3335 */ 3336register LASTADDR { 3337 address 0x0F6 3338 access_mode RW 3339 size 2 3340 modes M_SCSI 3341} 3342 3343register AHD_PCI_CONFIG_BASE { 3344 address 0x100 3345 access_mode RW 3346 size 256 3347 modes M_CFG 3348} 3349 3350/* ---------------------- Scratch RAM Offsets ------------------------- */ 3351scratch_ram { 3352 /* Mode Specific */ 3353 address 0x0A0 3354 size 8 3355 modes 0, 1, 2, 3 3356 REG0 { 3357 size 2 3358 } 3359 REG1 { 3360 size 2 3361 } 3362 REG_ISR { 3363 size 2 3364 } 3365 SG_STATE { 3366 size 1 3367 field SEGS_AVAIL 0x01 3368 field LOADING_NEEDED 0x02 3369 field FETCH_INPROG 0x04 3370 } 3371 /* 3372 * Track whether the transfer byte count for 3373 * the current data phase is odd. 3374 */ 3375 DATA_COUNT_ODD { 3376 size 1 3377 } 3378} 3379 3380scratch_ram { 3381 /* Mode Specific */ 3382 address 0x0F8 3383 size 8 3384 modes 0, 1, 2, 3 3385 LONGJMP_ADDR { 3386 size 2 3387 } 3388 LONGJMP_SCB { 3389 size 2 3390 } 3391 ACCUM_SAVE { 3392 size 1 3393 } 3394} 3395 3396 3397scratch_ram { 3398 address 0x100 3399 size 128 3400 modes 0, 1, 2, 3 3401 /* 3402 * Per "other-id" execution queues. We use an array of 3403 * tail pointers into lists of SCBs sorted by "other-id". 3404 * The execution head pointer threads the head SCBs for 3405 * each list. 3406 */ 3407 WAITING_SCB_TAILS { 3408 size 32 3409 } 3410 WAITING_TID_HEAD { 3411 size 2 3412 } 3413 WAITING_TID_TAIL { 3414 size 2 3415 } 3416 /* 3417 * SCBID of the next SCB in the new SCB queue. 3418 */ 3419 NEXT_QUEUED_SCB_ADDR { 3420 size 4 3421 } 3422 /* 3423 * head of list of SCBs that have 3424 * completed but have not been 3425 * put into the qoutfifo. 3426 */ 3427 COMPLETE_SCB_HEAD { 3428 size 2 3429 } 3430 /* 3431 * The list of completed SCBs in 3432 * the active DMA. 3433 */ 3434 COMPLETE_SCB_DMAINPROG_HEAD { 3435 size 2 3436 } 3437 /* 3438 * head of list of SCBs that have 3439 * completed but need to be uploaded 3440 * to the host prior to being completed. 3441 */ 3442 COMPLETE_DMA_SCB_HEAD { 3443 size 2 3444 } 3445 /* Counting semaphore to prevent new select-outs */ 3446 QFREEZE_COUNT { 3447 size 2 3448 } 3449 /* 3450 * Mode to restore on idle_loop exit. 3451 */ 3452 SAVED_MODE { 3453 size 1 3454 } 3455 /* 3456 * Single byte buffer used to designate the type or message 3457 * to send to a target. 3458 */ 3459 MSG_OUT { 3460 size 1 3461 } 3462 /* Parameters for DMA Logic */ 3463 DMAPARAMS { 3464 size 1 3465 field PRELOADEN 0x80 3466 field WIDEODD 0x40 3467 field SCSIEN 0x20 3468 field SDMAEN 0x10 3469 field SDMAENACK 0x10 3470 field HDMAEN 0x08 3471 field HDMAENACK 0x08 3472 field DIRECTION 0x04 /* Set indicates PCI->SCSI */ 3473 field FIFOFLUSH 0x02 3474 field FIFORESET 0x01 3475 } 3476 SEQ_FLAGS { 3477 size 1 3478 field NOT_IDENTIFIED 0x80 3479 field NO_CDB_SENT 0x40 3480 field TARGET_CMD_IS_TAGGED 0x40 3481 field DPHASE 0x20 3482 /* Target flags */ 3483 field TARG_CMD_PENDING 0x10 3484 field CMDPHASE_PENDING 0x08 3485 field DPHASE_PENDING 0x04 3486 field SPHASE_PENDING 0x02 3487 field NO_DISCONNECT 0x01 3488 } 3489 /* 3490 * Temporary storage for the 3491 * target/channel/lun of a 3492 * reconnecting target 3493 */ 3494 SAVED_SCSIID { 3495 size 1 3496 } 3497 SAVED_LUN { 3498 size 1 3499 } 3500 /* 3501 * The last bus phase as seen by the sequencer. 3502 */ 3503 LASTPHASE { 3504 size 1 3505 field CDI 0x80 3506 field IOI 0x40 3507 field MSGI 0x20 3508 field P_BUSFREE 0x01 3509 enum PHASE_MASK CDO|IOO|MSGO { 3510 P_DATAOUT 0x0, 3511 P_DATAIN IOO, 3512 P_DATAOUT_DT P_DATAOUT|MSGO, 3513 P_DATAIN_DT P_DATAIN|MSGO, 3514 P_COMMAND CDO, 3515 P_MESGOUT CDO|MSGO, 3516 P_STATUS CDO|IOO, 3517 P_MESGIN CDO|IOO|MSGO 3518 } 3519 } 3520 /* 3521 * Base address of our shared data with the kernel driver in host 3522 * memory. This includes the qoutfifo and target mode 3523 * incoming command queue. 3524 */ 3525 SHARED_DATA_ADDR { 3526 size 4 3527 } 3528 /* 3529 * Pointer to location in host memory for next 3530 * position in the qoutfifo. 3531 */ 3532 QOUTFIFO_NEXT_ADDR { 3533 size 4 3534 } 3535 /* 3536 * Value to "or" into the SCBPTR[1] value to 3537 * indicate that an entry in the QINFIFO is valid. 3538 */ 3539 QOUTFIFO_ENTRY_VALID_TAG { 3540 size 1 3541 } 3542 /* 3543 * Kernel and sequencer offsets into the queue of 3544 * incoming target mode command descriptors. The 3545 * queue is full when the KERNEL_TQINPOS == TQINPOS. 3546 */ 3547 KERNEL_TQINPOS { 3548 size 1 3549 } 3550 TQINPOS { 3551 size 1 3552 } 3553 ARG_1 { 3554 size 1 3555 mask SEND_MSG 0x80 3556 mask SEND_SENSE 0x40 3557 mask SEND_REJ 0x20 3558 mask MSGOUT_PHASEMIS 0x10 3559 mask EXIT_MSG_LOOP 0x08 3560 mask CONT_MSG_LOOP_WRITE 0x04 3561 mask CONT_MSG_LOOP_READ 0x03 3562 mask CONT_MSG_LOOP_TARG 0x02 3563 alias RETURN_1 3564 } 3565 ARG_2 { 3566 size 1 3567 alias RETURN_2 3568 } 3569 3570 /* 3571 * Snapshot of MSG_OUT taken after each message is sent. 3572 */ 3573 LAST_MSG { 3574 size 1 3575 } 3576 3577 /* 3578 * Sequences the kernel driver has okayed for us. This allows 3579 * the driver to do things like prevent initiator or target 3580 * operations. 3581 */ 3582 SCSISEQ_TEMPLATE { 3583 size 1 3584 field MANUALCTL 0x40 3585 field ENSELI 0x20 3586 field ENRSELI 0x10 3587 field MANUALP 0x0C 3588 field ENAUTOATNP 0x02 3589 field ALTSTIM 0x01 3590 } 3591 3592 /* 3593 * The initiator specified tag for this target mode transaction. 3594 */ 3595 INITIATOR_TAG { 3596 size 1 3597 } 3598 3599 SEQ_FLAGS2 { 3600 size 1 3601 field TARGET_MSG_PENDING 0x02 3602 field SELECTOUT_QFROZEN 0x04 3603 } 3604 3605 ALLOCFIFO_SCBPTR { 3606 size 2 3607 } 3608 3609 /* 3610 * Target-mode CDB type to CDB length table used 3611 * in non-packetized operation. 3612 */ 3613 CMDSIZE_TABLE { 3614 size 8 3615 } 3616} 3617 3618/************************* Hardware SCB Definition ****************************/ 3619scb { 3620 address 0x180 3621 size 64 3622 modes 0, 1, 2, 3 3623 SCB_RESIDUAL_DATACNT { 3624 size 4 3625 alias SCB_CDB_STORE 3626 } 3627 SCB_RESIDUAL_SGPTR { 3628 size 4 3629 alias SCB_CDB_PTR 3630 field SG_ADDR_MASK 0xf8 /* In the last byte */ 3631 field SG_OVERRUN_RESID 0x02 /* In the first byte */ 3632 field SG_LIST_NULL 0x01 /* In the first byte */ 3633 } 3634 SCB_SCSI_STATUS { 3635 size 1 3636 } 3637 SCB_TARGET_PHASES { 3638 size 1 3639 } 3640 SCB_TARGET_DATA_DIR { 3641 size 1 3642 } 3643 SCB_TARGET_ITAG { 3644 size 1 3645 } 3646 SCB_SENSE_BUSADDR { 3647 /* 3648 * Only valid if CDB length is less than 13 bytes or 3649 * we are using a CDB pointer. Otherwise contains 3650 * the last 4 bytes of embedded cdb information. 3651 */ 3652 size 4 3653 alias SCB_NEXT_COMPLETE 3654 } 3655 SCB_TAG { 3656 size 2 3657 } 3658 SCB_CDB_LEN { 3659 size 1 3660 field SCB_CDB_LEN_PTR 0x80 /* CDB in host memory */ 3661 } 3662 SCB_TASK_MANAGEMENT { 3663 size 1 3664 } 3665 SCB_NEXT { 3666 alias SCB_NEXT_SCB_BUSADDR 3667 size 2 3668 } 3669 SCB_NEXT2 { 3670 size 2 3671 } 3672 SCB_DATAPTR { 3673 size 8 3674 } 3675 SCB_DATACNT { 3676 /* 3677 * The last byte is really the high address bits for 3678 * the data address. 3679 */ 3680 size 4 3681 field SG_LAST_SEG 0x80 /* In the fourth byte */ 3682 field SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */ 3683 } 3684 SCB_SGPTR { 3685 size 4 3686 field SG_STATUS_VALID 0x04 /* In the first byte */ 3687 field SG_FULL_RESID 0x02 /* In the first byte */ 3688 field SG_LIST_NULL 0x01 /* In the first byte */ 3689 } 3690 SCB_CONTROL { 3691 size 1 3692 field TARGET_SCB 0x80 3693 field DISCENB 0x40 3694 field TAG_ENB 0x20 3695 field MK_MESSAGE 0x10 3696 field STATUS_RCVD 0x08 3697 field DISCONNECTED 0x04 3698 field SCB_TAG_TYPE 0x03 3699 } 3700 SCB_SCSIID { 3701 size 1 3702 field TID 0xF0 3703 field OID 0x0F 3704 } 3705 SCB_LUN { 3706 size 1 3707 field LID 0xff 3708 } 3709 SCB_TASK_ATTRIBUTE { 3710 size 1 3711 } 3712 SCB_BUSADDR { 3713 size 4 3714 } 3715 SCB_SPARE { 3716 size 8 3717 alias SCB_PKT_LUN 3718 } 3719 SCB_DISCONNECTED_LISTS { 3720 size 8 3721 } 3722} 3723 3724/*********************************** Constants ********************************/ 3725const SEQ_STACK_SIZE 8 3726const MK_MESSAGE_BIT_OFFSET 4 3727const TID_SHIFT 4 3728const TARGET_CMD_CMPLT 0xfe 3729const INVALID_ADDR 0x80 3730#define SCB_LIST_NULL 0xff 3731#define QOUTFIFO_ENTRY_VALID_TOGGLE 0x80 3732 3733const CCSGADDR_MAX 0x80 3734const CCSCBADDR_MAX 0x80 3735const CCSGRAM_MAXSEGS 16 3736 3737/* Selection Timeout Timer Constants */ 3738const STIMESEL_SHIFT 3 3739const STIMESEL_MIN 0x18 3740const STIMESEL_BUG_ADJ 0x8 3741 3742/* WDTR Message values */ 3743const BUS_8_BIT 0x00 3744const BUS_16_BIT 0x01 3745const BUS_32_BIT 0x02 3746 3747/* Offset maximums */ 3748const MAX_OFFSET 0xfe 3749const MAX_OFFSET_PACED 0x7f 3750const HOST_MSG 0xff 3751 3752/* 3753 * The size of our sense buffers. 3754 * Sense buffer mapping can be handled in either of two ways. 3755 * The first is to allocate a dmamap for each transaction. 3756 * Depending on the architecture, dmamaps can be costly. The 3757 * alternative is to statically map the buffers in much the same 3758 * way we handle our scatter gather lists. The driver implements 3759 * the later. 3760 */ 3761const AHD_SENSE_BUFSIZE 256 3762 3763/* Target mode command processing constants */ 3764const CMD_GROUP_CODE_SHIFT 0x05 3765 3766const STATUS_BUSY 0x08 3767const STATUS_QUEUE_FULL 0x28 3768const STATUS_PKT_SENSE 0xFF 3769const TARGET_DATA_IN 1 3770 3771const SCB_TRANSFER_SIZE_FULL_LUN 56 3772const SCB_TRANSFER_SIZE_1BYTE_LUN 48 3773/* PKT_OVERRUN_BUFSIZE must be a multiple of 256 less than 64K */ 3774const PKT_OVERRUN_BUFSIZE 512 3775 3776/* 3777 * Downloaded (kernel inserted) constants 3778 */ 3779const SG_PREFETCH_CNT download 3780const SG_PREFETCH_CNT_LIMIT download 3781const SG_PREFETCH_ALIGN_MASK download 3782const SG_PREFETCH_ADDR_MASK download 3783const SG_SIZEOF download 3784const PKT_OVERRUN_BUFOFFSET download 3785const SCB_TRANSFER_SIZE download 3786 3787/* 3788 * BIOS SCB offsets 3789 */ 3790const NVRAM_SCB_OFFSET 0x2C 3791