aic79xx.reg revision 102681
1/* 2 * Aic79xx register and scratch ram definitions. 3 * 4 * Copyright (c) 1994-2001 Justin T. Gibbs. 5 * Copyright (c) 2000-2002 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $FreeBSD: head/sys/dev/aic7xxx/aic79xx.reg 102681 2002-08-31 06:49:11Z gibbs $ 41 */ 42VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#39 $" 43 44/* 45 * This file is processed by the aic7xxx_asm utility for use in assembling 46 * firmware for the aic79xx family of SCSI host adapters as well as to generate 47 * a C header file for use in the kernel portion of the Aic79xx driver. 48 */ 49 50/* Register window Modes */ 51#define M_DFF0 0 52#define M_DFF1 1 53#define M_CCHAN 2 54#define M_SCSI 3 55#define M_CFG 4 56#define M_DST_SHIFT 4 57 58#define MK_MODE(src, dst) ((src) | ((dst) << M_DST_SHIFT)) 59#define SET_MODE(src, dst) \ 60 SET_SRC_MODE src; \ 61 SET_DST_MODE dst; \ 62 mvi MK_MODE(src, dst) call set_mode_work_around 63 64/* 65 * Mode Pointer 66 * Controls which of the 5, 512byte, address spaces should be used 67 * as the source and destination of any register accesses in our 68 * register window. 69 */ 70register MODE_PTR { 71 address 0x000 72 access_mode RW 73 field DST_MODE 0x70 74 field SRC_MODE 0x07 75 mode_pointer 76} 77 78const SRC_MODE_SHIFT 0 79const DST_MODE_SHIFT 4 80 81/* 82 * Host Interrupt Status 83 */ 84register INTSTAT { 85 address 0x001 86 access_mode RW 87 field HWERRINT 0x80 88 field BRKADRINT 0x40 89 field SWTMINT 0x20 90 field PCIINT 0x10 91 field SCSIINT 0x08 92 field SEQINT 0x04 93 field CMDCMPLT 0x02 94 field SPLTINT 0x01 95 mask INT_PEND 0xFF 96} 97 98/* 99 * Sequencer Interrupt Code 100 */ 101register SEQINTCODE { 102 address 0x002 103 access_mode RW 104 field { 105 BAD_PHASE 1, /* unknown scsi bus phase */ 106 SEND_REJECT, /* sending a message reject */ 107 PROTO_VIOLATION, /* Protocol Violation */ 108 NO_MATCH, /* no cmd match for reconnect */ 109 IGN_WIDE_RES, /* Complex IGN Wide Res Msg */ 110 PDATA_REINIT, /* 111 * Returned to data phase 112 * that requires data 113 * transfer pointers to be 114 * recalculated from the 115 * transfer residual. 116 */ 117 HOST_MSG_LOOP, /* 118 * The bus is ready for the 119 * host to perform another 120 * message transaction. This 121 * mechanism is used for things 122 * like sync/wide negotiation 123 * that require a kernel based 124 * message state engine. 125 */ 126 BAD_STATUS, /* Bad status from target */ 127 DATA_OVERRUN, /* 128 * Target attempted to write 129 * beyond the bounds of its 130 * command. 131 */ 132 MKMSG_FAILED, /* 133 * Target completed command 134 * without honoring our ATN 135 * request to issue a message. 136 */ 137 MISSED_BUSFREE, /* 138 * The sequencer never saw 139 * the bus go free after 140 * either a command complete 141 * or disconnect message. 142 */ 143 DUMP_CARD_STATE, 144 ILLEGAL_PHASE, 145 INVALID_SEQINT, 146 CFG4ISTAT_INTR, 147 STATUS_OVERRUN, 148 CFG4OVERRUN, 149 ENTERING_NONPACK 150 } 151} 152 153/* 154 * Clear Host Interrupt 155 */ 156register CLRINT { 157 address 0x003 158 access_mode WO 159 field CLRHWERRINT 0x80 /* Rev B or greater */ 160 field CLRBRKADRINT 0x40 161 field CLRSWTMINT 0x20 162 field CLRSCSIINT 0x08 163 field CLRSEQINT 0x04 164 field CLRCMDINT 0x02 165 field CLRSPLTINT 0x01 166} 167 168/* 169 * Error Register 170 */ 171register ERROR { 172 address 0x004 173 access_mode RO 174 field CIOPARERR 0x80 175 field CIOACCESFAIL 0x40 /* Rev B or greater */ 176 field MPARERR 0x20 177 field DPARERR 0x10 178 field SQPARERR 0x08 179 field ILLOPCODE 0x04 180 field DSCTMOUT 0x02 181} 182 183/* 184 * Clear Error 185 */ 186register CLRERR { 187 address 0x004 188 access_mode WO 189 field CLRCIOPARERR 0x80 190 field CLRCIOACCESFAIL 0x40 /* Rev B or greater */ 191 field CLRMPARERR 0x20 192 field CLRDPARERR 0x10 193 field CLRSQPARERR 0x08 194 field CLRILLOPCODE 0x04 195 field CLRDSCTMOUT 0x02 196} 197 198/* 199 * Host Control Register 200 * Overall host control of the device. 201 */ 202register HCNTRL { 203 address 0x005 204 access_mode RW 205 field SEQ_RESET 0x80 /* Rev B or greater */ 206 field POWRDN 0x40 207 field SWINT 0x10 208 field SWTIMER_START_B 0x08 /* Rev B or greater */ 209 field PAUSE 0x04 210 field INTEN 0x02 211 field CHIPRST 0x01 212 field CHIPRSTACK 0x01 213} 214 215/* 216 * Host New SCB Queue Offset 217 */ 218register HNSCB_QOFF { 219 address 0x006 220 access_mode RW 221 size 2 222} 223 224/* 225 * Host Empty SCB Queue Offset 226 */ 227register HESCB_QOFF { 228 address 0x008 229 access_mode RW 230} 231 232/* 233 * Host Mailbox 234 */ 235register HS_MAILBOX { 236 address 0x0B 237 access_mode RW 238 mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */ 239} 240 241/* 242 * Sequencer Interupt Status 243 */ 244register SEQINTSTAT { 245 address 0x0C 246 access_mode RO 247 field SEQ_SWTMRTO 0x10 248 field SEQ_SEQINT 0x08 249 field SEQ_SCSIINT 0x04 250 field SEQ_PCIINT 0x02 251 field SEQ_SPLTINT 0x01 252} 253 254/* 255 * Clear SEQ Interrupt 256 */ 257register CLRSEQINTSTAT { 258 address 0x0C0 259 access_mode WO 260 field CLRSEQ_SWTMRTO 0x10 261 field CLRSEQ_SEQINT 0x08 262 field CLRSEQ_SCSIINT 0x04 263 field CLRSEQ_PCIINT 0x02 264 field CLRSEQ_SPLTINT 0x01 265} 266 267/* 268 * Software Timer 269 */ 270register SWTIMER { 271 address 0x0E0 272 access_mode RW 273 size 2 274} 275 276/* 277 * SEQ New SCB Queue Offset 278 */ 279register SNSCB_QOFF { 280 address 0x010 281 access_mode RW 282 size 2 283 modes M_CCHAN 284} 285 286/* 287 * SEQ Empty SCB Queue Offset 288 */ 289register SESCB_QOFF { 290 address 0x012 291 access_mode RW 292 modes M_CCHAN 293} 294 295/* 296 * SEQ Done SCB Queue Offset 297 */ 298register SDSCB_QOFF { 299 address 0x014 300 access_mode RW 301 modes M_CCHAN 302 size 2 303} 304 305/* 306 * Queue Offset Control & Status 307 */ 308register QOFF_CTLSTA { 309 address 0x016 310 access_mode RW 311 modes M_CCHAN 312 field EMPTY_SCB_AVAIL 0x80 313 field NEW_SCB_AVAIL 0x40 314 field SDSCB_ROLLOVR 0x20 315 field HS_MAILBOX_ACT 0x10 316 field SCB_QSIZE 0x0F { 317 SCB_QSIZE_4, 318 SCB_QSIZE_8, 319 SCB_QSIZE_16, 320 SCB_QSIZE_32, 321 SCB_QSIZE_64, 322 SCB_QSIZE_128, 323 SCB_QSIZE_256, 324 SCB_QSIZE_512, 325 SCB_QSIZE_1024, 326 SCB_QSIZE_2048, 327 SCB_QSIZE_4096, 328 SCB_QSIZE_8192, 329 SCB_QSIZE_16384 330 } 331} 332 333/* 334 * Interrupt Control 335 */ 336register INTCTL { 337 address 0x018 338 access_mode RW 339 field SWTMINTMASK 0x80 340 field SWTMINTEN 0x40 341 field SWTIMER_START 0x20 342 field AUTOCLRCMDINT 0x10 343 field PCIINTEN 0x08 344 field SCSIINTEN 0x04 345 field SEQINTEN 0x02 346 field SPLTINTEN 0x01 347} 348 349/* 350 * Data FIFO Control 351 */ 352register DFCNTRL { 353 address 0x019 354 access_mode RW 355 modes M_DFF0, M_DFF1 356 field PRELOADEN 0x80 357 field SCSIEN 0x20 358 field SCSIENACK 0x20 359 field HDMAEN 0x08 360 field HDMAENACK 0x08 361 field DIRECTION 0x04 362 field DIRECTIONACK 0x04 363 field FIFOFLUSH 0x02 364 field FIFOFLUSHACK 0x02 365 field DIRECTIONEN 0x01 366} 367 368/* 369 * Device Space Command 0 370 */ 371register DSCOMMAND0 { 372 address 0x019 373 access_mode RW 374 modes M_CFG 375 field CACHETHEN 0x80 /* Cache Threshold enable */ 376 field DPARCKEN 0x40 /* Data Parity Check Enable */ 377 field MPARCKEN 0x20 /* Memory Parity Check Enable */ 378 field EXTREQLCK 0x10 /* External Request Lock */ 379 field DISABLE_TWATE 0x02 /* Rev B or greater */ 380 field CIOPARCKEN 0x01 /* Internal bus parity error enable */ 381} 382 383/* 384 * Data FIFO Status 385 */ 386register DFSTATUS { 387 address 0x01A 388 access_mode RO 389 modes M_DFF0, M_DFF1 390 field PRELOAD_AVAIL 0x80 391 field PKT_PRELOAD_AVAIL 0x40 392 field MREQPEND 0x10 393 field HDONE 0x08 394 field DFTHRESH 0x04 395 field FIFOFULL 0x02 396 field FIFOEMP 0x01 397} 398 399/* 400 * S/G Cache Pointer 401 */ 402register SG_CACHE_PRE { 403 address 0x01B 404 access_mode WO 405 modes M_DFF0, M_DFF1 406 field SG_ADDR_MASK 0xf8 407 field ODD_SEG 0x04 408 field LAST_SEG 0x02 409} 410 411register SG_CACHE_SHADOW { 412 address 0x01B 413 access_mode RO 414 modes M_DFF0, M_DFF1 415 field SG_ADDR_MASK 0xf8 416 field ODD_SEG 0x04 417 field LAST_SEG 0x02 418 field LAST_SEG_DONE 0x01 419} 420 421/* 422 * Arbiter Control 423 */ 424register ARBCTL { 425 address 0x01B 426 access_mode RW 427 modes M_CFG 428 field RESET_HARB 0x80 429 field RETRY_SWEN 0x08 430 field USE_TIME 0x07 431} 432 433/* 434 * Data Channel Host Address 435 */ 436register HADDR { 437 address 0x070 438 access_mode RW 439 size 8 440 modes M_DFF0, M_DFF1 441} 442 443/* 444 * Host Overlay DMA Address 445 */ 446register HODMAADR { 447 address 0x070 448 access_mode RW 449 size 8 450 modes M_SCSI 451} 452 453/* 454 * Data Channel Host Count 455 */ 456register HCNT { 457 address 0x078 458 access_mode RW 459 size 3 460 modes M_DFF0, M_DFF1 461} 462 463/* 464 * Host Overlay DMA Count 465 */ 466register HODMACNT { 467 address 0x078 468 access_mode RW 469 size 2 470 modes M_SCSI 471} 472 473/* 474 * Host Overlay DMA Enable 475 */ 476register HODMAEN { 477 address 0x07A 478 access_mode RW 479 modes M_SCSI 480} 481 482/* 483 * Scatter/Gather Host Address 484 */ 485register SGHADDR { 486 address 0x07C 487 access_mode RW 488 size 8 489 modes M_DFF0, M_DFF1 490} 491 492/* 493 * SCB Host Address 494 */ 495register SCBHADDR { 496 address 0x07C 497 access_mode RW 498 size 8 499 modes M_CCHAN 500} 501 502/* 503 * Scatter/Gather Host Count 504 */ 505register SGHCNT { 506 address 0x084 507 access_mode RW 508 modes M_DFF0, M_DFF1 509} 510 511/* 512 * SCB Host Count 513 */ 514register SCBHCNT { 515 address 0x084 516 access_mode RW 517 modes M_CCHAN 518} 519 520/* 521 * Data FIFO Threshold 522 */ 523register DFF_THRSH { 524 address 0x088 525 access_mode RW 526 modes M_CFG 527 field WR_DFTHRSH 0x70 { 528 WR_DFTHRSH_MIN, 529 WR_DFTHRSH_25, 530 WR_DFTHRSH_50, 531 WR_DFTHRSH_63, 532 WR_DFTHRSH_75, 533 WR_DFTHRSH_85, 534 WR_DFTHRSH_90, 535 WR_DFTHRSH_MAX 536 } 537 field RD_DFTHRSH 0x07 { 538 RD_DFTHRSH_MIN, 539 RD_DFTHRSH_25, 540 RD_DFTHRSH_50, 541 RD_DFTHRSH_63, 542 RD_DFTHRSH_75, 543 RD_DFTHRSH_85, 544 RD_DFTHRSH_90, 545 RD_DFTHRSH_MAX 546 } 547} 548 549/* 550 * ROM Address 551 */ 552register ROMADDR { 553 address 0x08A 554 access_mode RW 555 size 3 556} 557 558/* 559 * ROM Control 560 */ 561register ROMCNTRL { 562 address 0x08D 563 access_mode RW 564 field ROMOP 0xE0 565 field ROMSPD 0x18 566 field REPEAT 0x02 567 field RDY 0x01 568} 569 570/* 571 * ROM Data 572 */ 573register ROMDATA { 574 address 0x08E 575 access_mode RW 576} 577 578/* 579 * Data Channel Receive Message 0 580 */ 581register DCHRXMSG0 { 582 address 0x090 583 access_mode RO 584 modes M_DFF0, M_DFF1 585 field CDNUM 0xF8 586 field CFNUM 0x07 587} 588 589/* 590 * CMC Recieve Message 0 591 */ 592register CMCRXMSG0 { 593 address 0x090 594 access_mode RO 595 modes M_CCHAN 596 field CDNUM 0xF8 597 field CFNUM 0x07 598} 599 600/* 601 * Overlay Recieve Message 0 602 */ 603register OVLYRXMSG0 { 604 address 0x090 605 access_mode RO 606 modes M_SCSI 607 field CDNUM 0xF8 608 field CFNUM 0x07 609} 610 611/* 612 * Relaxed Order Enable 613 */ 614register ROENABLE { 615 address 0x090 616 access_mode RW 617 modes M_CFG 618 field MSIROEN 0x20 619 field OVLYROEN 0x10 620 field CMCROEN 0x08 621 field SGROEN 0x04 622 field DCH1ROEN 0x02 623 field DCH0ROEN 0x01 624} 625 626/* 627 * Data Channel Receive Message 1 628 */ 629register DCHRXMSG1 { 630 address 0x091 631 access_mode RO 632 modes M_DFF0, M_DFF1 633 field CBNUM 0xFF 634} 635 636/* 637 * CMC Recieve Message 1 638 */ 639register CMCRXMSG1 { 640 address 0x091 641 access_mode RO 642 modes M_CCHAN 643 field CBNUM 0xFF 644} 645 646/* 647 * Overlay Recieve Message 1 648 */ 649register OVLYRXMSG1 { 650 address 0x091 651 access_mode RO 652 modes M_SCSI 653 field CBNUM 0xFF 654} 655 656/* 657 * No Snoop Enable 658 */ 659register NSENABLE { 660 address 0x091 661 access_mode RW 662 modes M_CFG 663 field MSINSEN 0x20 664 field OVLYNSEN 0x10 665 field CMCNSEN 0x08 666 field SGNSEN 0x04 667 field DCH1NSEN 0x02 668 field DCH0NSEN 0x01 669} 670 671/* 672 * Data Channel Receive Message 2 673 */ 674register DCHRXMSG2 { 675 address 0x092 676 access_mode RO 677 modes M_DFF0, M_DFF1 678 field MINDEX 0xFF 679} 680 681/* 682 * CMC Recieve Message 2 683 */ 684register CMCRXMSG2 { 685 address 0x092 686 access_mode RO 687 modes M_CCHAN 688 field MINDEX 0xFF 689} 690 691/* 692 * Overlay Recieve Message 2 693 */ 694register OVLYRXMSG2 { 695 address 0x092 696 access_mode RO 697 modes M_SCSI 698 field MINDEX 0xFF 699} 700 701/* 702 * Outstanding Split Transactions 703 */ 704register OST { 705 address 0x092 706 access_mode RW 707 modes M_CFG 708} 709 710/* 711 * Data Channel Receive Message 3 712 */ 713register DCHRXMSG3 { 714 address 0x093 715 access_mode RO 716 modes M_DFF0, M_DFF1 717 field MCLASS 0x0F 718} 719 720/* 721 * CMC Recieve Message 3 722 */ 723register CMCRXMSG3 { 724 address 0x093 725 access_mode RO 726 modes M_CCHAN 727 field MCLASS 0x0F 728} 729 730/* 731 * Overlay Recieve Message 3 732 */ 733register OVLYRXMSG3 { 734 address 0x093 735 access_mode RO 736 modes M_SCSI 737 field MCLASS 0x0F 738} 739 740/* 741 * PCI-X Control 742 */ 743register PCIXCTL { 744 address 0x093 745 access_mode RW 746 modes M_CFG 747 field SERRPULSE 0x80 748 field UNEXPSCIEN 0x20 749 field SPLTSMADIS 0x10 750 field SPLTSTADIS 0x08 751 field SRSPDPEEN 0x04 752 field TSCSERREN 0x02 753 field CMPABCDIS 0x01 754} 755 756/* 757 * CMC Sequencer Byte Count 758 */ 759register CMCSEQBCNT { 760 address 0x094 761 access_mode RO 762 modes M_CCHAN 763} 764 765/* 766 * Overlay Sequencer Byte Count 767 */ 768register OVLYSEQBCNT { 769 address 0x094 770 access_mode RO 771 modes M_SCSI 772} 773 774/* 775 * Data Channel Sequencer Byte Count 776 */ 777register DCHSEQBCNT { 778 address 0x094 779 access_mode RO 780 size 2 781 modes M_DFF0, M_DFF1 782} 783 784/* 785 * Data Channel Split Status 0 786 */ 787register DCHSPLTSTAT0 { 788 address 0x096 789 access_mode RW 790 modes M_DFF0, M_DFF1 791 field STAETERM 0x80 792 field SCBCERR 0x40 793 field SCADERR 0x20 794 field SCDATBUCKET 0x10 795 field CNTNOTCMPLT 0x08 796 field RXOVRUN 0x04 797 field RXSCEMSG 0x02 798 field RXSPLTRSP 0x01 799} 800 801/* 802 * CMC Split Status 0 803 */ 804register CMCSPLTSTAT0 { 805 address 0x096 806 access_mode RW 807 modes M_CCHAN 808 field STAETERM 0x80 809 field SCBCERR 0x40 810 field SCADERR 0x20 811 field SCDATBUCKET 0x10 812 field CNTNOTCMPLT 0x08 813 field RXOVRUN 0x04 814 field RXSCEMSG 0x02 815 field RXSPLTRSP 0x01 816} 817 818/* 819 * Overlay Split Status 0 820 */ 821register OVLYSPLTSTAT0 { 822 address 0x096 823 access_mode RW 824 modes M_SCSI 825 field STAETERM 0x80 826 field SCBCERR 0x40 827 field SCADERR 0x20 828 field SCDATBUCKET 0x10 829 field CNTNOTCMPLT 0x08 830 field RXOVRUN 0x04 831 field RXSCEMSG 0x02 832 field RXSPLTRSP 0x01 833} 834 835/* 836 * Data Channel Split Status 1 837 */ 838register DCHSPLTSTAT1 { 839 address 0x097 840 access_mode RW 841 modes M_DFF0, M_DFF1 842 field RXDATABUCKET 0x01 843} 844 845/* 846 * CMC Split Status 1 847 */ 848register CMCSPLTSTAT1 { 849 address 0x097 850 access_mode RW 851 modes M_CCHAN 852 field RXDATABUCKET 0x01 853} 854 855/* 856 * Overlay Split Status 1 857 */ 858register OVLYSPLTSTAT1 { 859 address 0x097 860 access_mode RW 861 modes M_SCSI 862 field RXDATABUCKET 0x01 863} 864 865/* 866 * S/G Receive Message 0 867 */ 868register SGRXMSG0 { 869 address 0x098 870 access_mode RO 871 modes M_DFF0, M_DFF1 872 field CDNUM 0xF8 873 field CFNUM 0x07 874} 875 876/* 877 * S/G Receive Message 1 878 */ 879register SGRXMSG1 { 880 address 0x099 881 access_mode RO 882 modes M_DFF0, M_DFF1 883 field CBNUM 0xFF 884} 885 886/* 887 * S/G Receive Message 2 888 */ 889register SGRXMSG2 { 890 address 0x09A 891 access_mode RO 892 modes M_DFF0, M_DFF1 893 field MINDEX 0xFF 894} 895 896/* 897 * S/G Receive Message 3 898 */ 899register SGRXMSG3 { 900 address 0x09B 901 access_mode RO 902 modes M_DFF0, M_DFF1 903 field MCLASS 0x0F 904} 905 906/* 907 * Slave Split Out Address 0 908 */ 909register SLVSPLTOUTADR0 { 910 address 0x098 911 access_mode RO 912 modes M_SCSI 913 field LOWER_ADDR 0x7F 914} 915 916/* 917 * Slave Split Out Address 1 918 */ 919register SLVSPLTOUTADR1 { 920 address 0x099 921 access_mode RO 922 modes M_SCSI 923 field REQ_DNUM 0xF8 924 field REQ_FNUM 0x07 925} 926 927/* 928 * Slave Split Out Address 2 929 */ 930register SLVSPLTOUTADR2 { 931 address 0x09A 932 access_mode RO 933 modes M_SCSI 934 field REQ_BNUM 0xFF 935} 936 937/* 938 * Slave Split Out Address 3 939 */ 940register SLVSPLTOUTADR3 { 941 address 0x09B 942 access_mode RO 943 modes M_SCSI 944 field RLXORD 020 945 field TAG_NUM 0x1F 946} 947 948/* 949 * SG Sequencer Byte Count 950 */ 951register SGSEQBCNT { 952 address 0x09C 953 access_mode RO 954 modes M_DFF0, M_DFF1 955} 956 957/* 958 * Slave Split Out Attribute 0 959 */ 960register SLVSPLTOUTATTR0 { 961 address 0x09C 962 access_mode RO 963 modes M_SCSI 964 field LOWER_BCNT 0xFF 965} 966 967/* 968 * Slave Split Out Attribute 1 969 */ 970register SLVSPLTOUTATTR1 { 971 address 0x09D 972 access_mode RO 973 modes M_SCSI 974 field CMPLT_DNUM 0xF8 975 field CMPLT_FNUM 0x07 976} 977 978/* 979 * Slave Split Out Attribute 2 980 */ 981register SLVSPLTOUTATTR2 { 982 address 0x09E 983 access_mode RO 984 size 2 985 modes M_SCSI 986 field CMPLT_BNUM 0xFF 987} 988/* 989 * S/G Split Status 0 990 */ 991register SGSPLTSTAT0 { 992 address 0x09E 993 access_mode RW 994 modes M_DFF0, M_DFF1 995 field STAETERM 0x80 996 field SCBCERR 0x40 997 field SCADERR 0x20 998 field SCDATBUCKET 0x10 999 field CNTNOTCMPLT 0x08 1000 field RXOVRUN 0x04 1001 field RXSCEMSG 0x02 1002 field RXSPLTRSP 0x01 1003} 1004 1005/* 1006 * S/G Split Status 1 1007 */ 1008register SGSPLTSTAT1 { 1009 address 0x09F 1010 access_mode RW 1011 modes M_DFF0, M_DFF1 1012 field RXDATABUCKET 0x01 1013} 1014 1015/* 1016 * Special Function 1017 */ 1018register SFUNCT { 1019 address 0x09f 1020 access_mode RW 1021 modes M_CFG 1022 field TEST_GROUP 0xF0 1023 field TEST_NUM 0x0F 1024} 1025 1026/* 1027 * Data FIFO 0 PCI Status 1028 */ 1029register DF0PCISTAT { 1030 address 0x0A0 1031 access_mode RW 1032 modes M_CFG 1033 field DPE 0x80 1034 field SSE 0x40 1035 field RMA 0x20 1036 field RTA 0x10 1037 field SCAAPERR 0x08 1038 field RDPERR 0x04 1039 field TWATERR 0x02 1040 field DPR 0x01 1041} 1042 1043/* 1044 * Data FIFO 1 PCI Status 1045 */ 1046register DF1PCISTAT { 1047 address 0x0A1 1048 access_mode RW 1049 modes M_CFG 1050 field DPE 0x80 1051 field SSE 0x40 1052 field RMA 0x20 1053 field RTA 0x10 1054 field SCAAPERR 0x08 1055 field RDPERR 0x04 1056 field TWATERR 0x02 1057 field DPR 0x01 1058} 1059 1060/* 1061 * S/G PCI Status 1062 */ 1063register SGPCISTAT { 1064 address 0x0A2 1065 access_mode RW 1066 modes M_CFG 1067 field DPE 0x80 1068 field SSE 0x40 1069 field RMA 0x20 1070 field RTA 0x10 1071 field SCAAPERR 0x08 1072 field RDPERR 0x04 1073 field DPR 0x01 1074} 1075 1076/* 1077 * CMC PCI Status 1078 */ 1079register CMCPCISTAT { 1080 address 0x0A3 1081 access_mode RW 1082 modes M_CFG 1083 field DPE 0x80 1084 field SSE 0x40 1085 field RMA 0x20 1086 field RTA 0x10 1087 field SCAAPERR 0x08 1088 field RDPERR 0x04 1089 field TWATERR 0x02 1090 field DPR 0x01 1091} 1092 1093/* 1094 * Overlay PCI Status 1095 */ 1096register OVLYPCISTAT { 1097 address 0x0A4 1098 access_mode RW 1099 modes M_CFG 1100 field DPE 0x80 1101 field SSE 0x40 1102 field RMA 0x20 1103 field RTA 0x10 1104 field SCAAPERR 0x08 1105 field RDPERR 0x04 1106 field DPR 0x01 1107} 1108 1109/* 1110 * PCI Status for MSI Master DMA Transfer 1111 */ 1112register MSIPCISTAT { 1113 address 0x0A6 1114 access_mode RW 1115 modes M_CFG 1116 field SSE 0x40 1117 field RMA 0x20 1118 field RTA 0x10 1119 field CLRPENDMSI 0x08 1120 field TWATERR 0x02 1121 field DPR 0x01 1122} 1123 1124/* 1125 * PCI Status for Target 1126 */ 1127register TARGPCISTAT { 1128 address 0x0A6 1129 access_mode RW 1130 modes M_CFG 1131 field DPE 0x80 1132 field SSE 0x40 1133 field STA 0x08 1134 field TWATERR 0x02 1135} 1136 1137/* 1138 * LQ Packet In 1139 * The last LQ Packet recieved 1140 */ 1141register LQIN { 1142 address 0x020 1143 access_mode RW 1144 size 20 1145 modes M_DFF0, M_DFF1, M_SCSI 1146} 1147 1148/* 1149 * SCB Type Pointer 1150 * SCB offset for Target Mode SCB type information 1151 */ 1152register TYPEPTR { 1153 address 0x020 1154 access_mode RW 1155 modes M_CFG 1156} 1157 1158/* 1159 * Queue Tag Pointer 1160 * SCB offset to the Two Byte tag identifier used for target mode. 1161 */ 1162register TAGPTR { 1163 address 0x021 1164 access_mode RW 1165 modes M_CFG 1166} 1167 1168/* 1169 * Logical Unit Number Pointer 1170 * SCB offset to the LSB (little endian) of the lun field. 1171 */ 1172register LUNPTR { 1173 address 0x022 1174 access_mode RW 1175 modes M_CFG 1176} 1177 1178/* 1179 * Data Length Pointer 1180 * SCB offset for the 4 byte data length field in target mode. 1181 */ 1182register DATALENPTR { 1183 address 0x023 1184 access_mode RW 1185 modes M_CFG 1186} 1187 1188/* 1189 * Status Length Pointer 1190 * SCB offset to the two byte status field in target SCBs. 1191 */ 1192register STATLENPTR { 1193 address 0x024 1194 access_mode RW 1195 modes M_CFG 1196} 1197 1198/* 1199 * Command Length Pointer 1200 * Scb offset for the CDB length field in initiator SCBs. 1201 */ 1202register CMDLENPTR { 1203 address 0x025 1204 access_mode RW 1205 modes M_CFG 1206} 1207 1208/* 1209 * Task Attribute Pointer 1210 * Scb offset for the byte field specifying the attribute byte 1211 * to be used in command packets. 1212 */ 1213register ATTRPTR { 1214 address 0x026 1215 access_mode RW 1216 modes M_CFG 1217} 1218 1219/* 1220 * Task Management Flags Pointer 1221 * Scb offset for the byte field specifying the attribute flags 1222 * byte to be used in command packets. 1223 */ 1224register FLAGPTR { 1225 address 0x027 1226 access_mode RW 1227 modes M_CFG 1228} 1229 1230/* 1231 * Command Pointer 1232 * Scb offset for the first byte in the CDB for initiator SCBs. 1233 */ 1234register CMDPTR { 1235 address 0x028 1236 access_mode RW 1237 modes M_CFG 1238} 1239 1240/* 1241 * Queue Next Pointer 1242 * Scb offset for the 2 byte "next scb link". 1243 */ 1244register QNEXTPTR { 1245 address 0x029 1246 access_mode RW 1247 modes M_CFG 1248} 1249 1250/* 1251 * SCSI ID Pointer 1252 * Scb offset to the value to place in the SCSIID register 1253 * during target mode connections. 1254 */ 1255register IDPTR { 1256 address 0x02A 1257 access_mode RW 1258 modes M_CFG 1259} 1260 1261/* 1262 * Command Aborted Byte Pointer 1263 * Offset to the SCB flags field that includes the 1264 * "SCB aborted" status bit. 1265 */ 1266register ABRTBYTEPTR { 1267 address 0x02B 1268 access_mode RW 1269 modes M_CFG 1270} 1271 1272/* 1273 * Command Aborted Bit Pointer 1274 * Bit offset in the SCB flags field for "SCB aborted" status. 1275 */ 1276register ABRTBITPTR { 1277 address 0x02C 1278 access_mode RW 1279 modes M_CFG 1280} 1281 1282/* 1283 * Rev B or greater. 1284 */ 1285register MAXCMDBYTES { 1286 address 0x02D 1287 access_mode RW 1288 modes M_CFG 1289} 1290 1291/* 1292 * Rev B or greater. 1293 */ 1294register MAXCMD2RCV { 1295 address 0x02E 1296 access_mode RW 1297 modes M_CFG 1298} 1299 1300/* 1301 * Rev B or greater. 1302 */ 1303register SHORTTHRESH { 1304 address 0x02F 1305 access_mode RW 1306 modes M_CFG 1307} 1308 1309/* 1310 * Logical Unit Number Length 1311 * The length, in bytes, of the SCB lun field. 1312 */ 1313register LUNLEN { 1314 address 0x030 1315 access_mode RW 1316 modes M_CFG 1317} 1318 1319/* 1320 * CDB Limit 1321 * The size, in bytes, of the embedded CDB field in initator SCBs. 1322 */ 1323register CDBLIMIT { 1324 address 0x031 1325 access_mode RW 1326 modes M_CFG 1327} 1328 1329/* 1330 * Maximum Commands 1331 * The maximum number of commands to issue during a 1332 * single packetized connection. 1333 */ 1334register MAXCMD { 1335 address 0x032 1336 access_mode RW 1337 modes M_CFG 1338} 1339 1340/* 1341 * Maximum Command Counter 1342 * The number of commands already sent during this connection 1343 */ 1344register MAXCMDCNT { 1345 address 0x033 1346 access_mode RW 1347 modes M_CFG 1348} 1349 1350/* 1351 * LQ Packet Reserved Bytes 1352 * The bytes to be sent in the currently reserved fileds 1353 * of all LQ packets. 1354 */ 1355register LQRSVD01 { 1356 address 0x034 1357 access_mode RW 1358 modes M_SCSI 1359} 1360register LQRSVD16 { 1361 address 0x035 1362 access_mode RW 1363 modes M_SCSI 1364} 1365register LQRSVD17 { 1366 address 0x036 1367 access_mode RW 1368 modes M_SCSI 1369} 1370 1371/* 1372 * Command Reserved 0 1373 * The byte to be sent for the reserved byte 0 of 1374 * outgoing command packets. 1375 */ 1376register CMDRSVD0 { 1377 address 0x037 1378 access_mode RW 1379 modes M_CFG 1380} 1381 1382/* 1383 * LQ Manager Control 0 1384 */ 1385register LQCTL0 { 1386 address 0x038 1387 access_mode RW 1388 modes M_CFG 1389 field LQITARGCLT 0xC0 1390 field LQIINITGCLT 0x30 1391 field LQ0TARGCLT 0x0C 1392 field LQ0INITGCLT 0x03 1393} 1394 1395/* 1396 * LQ Manager Control 1 1397 */ 1398register LQCTL1 { 1399 address 0x038 1400 access_mode RW 1401 modes M_DFF0, M_DFF1, M_SCSI 1402 field PCI2PCI 0x04 1403 field SINGLECMD 0x02 1404 field ABORTPENDING 0x01 1405} 1406 1407/* 1408 * LQ Manager Control 2 1409 */ 1410register LQCTL2 { 1411 address 0x039 1412 access_mode RW 1413 modes M_DFF0, M_DFF1, M_SCSI 1414 field LQIRETRY 0x80 1415 field LQICONTINUE 0x40 1416 field LQITOIDLE 0x20 1417 field LQIPAUSE 0x10 1418 field LQORETRY 0x08 1419 field LQOCONTINUE 0x04 1420 field LQOTOIDLE 0x02 1421 field LQOPAUSE 0x01 1422} 1423 1424/* 1425 * SCSI RAM BIST0 1426 */ 1427register SCSBIST0 { 1428 address 0x039 1429 access_mode RW 1430 modes M_CFG 1431 field GSBISTERR 0x40 1432 field GSBISTDONE 0x20 1433 field GSBISTRUN 0x10 1434 field OSBISTERR 0x04 1435 field OSBISTDONE 0x02 1436 field OSBISTRUN 0x01 1437} 1438 1439/* 1440 * SCSI Sequence Control0 1441 */ 1442register SCSISEQ0 { 1443 address 0x03A 1444 access_mode RW 1445 modes M_DFF0, M_DFF1, M_SCSI 1446 field TEMODEO 0x80 1447 field ENSELO 0x40 1448 field ENARBO 0x20 1449 field FORCEBUSFREE 0x10 1450 field SCSIRSTO 0x01 1451} 1452 1453/* 1454 * SCSI RAM BIST 1 1455 */ 1456register SCSBIST1 { 1457 address 0x03A 1458 access_mode RW 1459 modes M_CFG 1460 field NTBISTERR 0x04 1461 field NTBISTDONE 0x02 1462 field NTBISTRUN 0x01 1463} 1464 1465/* 1466 * SCSI Sequence Control 1 1467 */ 1468register SCSISEQ1 { 1469 address 0x03B 1470 access_mode RW 1471 modes M_DFF0, M_DFF1, M_SCSI 1472 field MANUALCTL 0x40 1473 field ENSELI 0x20 1474 field ENRSELI 0x10 1475 field MANUALP 0x0C 1476 field ENAUTOATNP 0x02 1477 field ALTSTIM 0x01 1478} 1479 1480/* 1481 * SCSI Transfer Control 0 1482 */ 1483register SXFRCTL0 { 1484 address 0x03C 1485 access_mode RW 1486 modes M_SCSI 1487 field DFON 0x80 1488 field DFPEXP 0x40 1489 field BIOSCANCELEN 0x10 1490 field SPIOEN 0x08 1491} 1492 1493/* 1494 * SCSI Transfer Control 1 1495 */ 1496register SXFRCTL1 { 1497 address 0x03D 1498 access_mode RW 1499 modes M_SCSI 1500 field BITBUCKET 0x80 1501 field ENSACHK 0x40 1502 field ENSPCHK 0x20 1503 field STIMESEL 0x18 1504 field ENSTIMER 0x04 1505 field ACTNEGEN 0x02 1506 field STPWEN 0x01 1507} 1508 1509/* 1510 * SCSI Transfer Control 2 1511 */ 1512register SXFRCTL2 { 1513 address 0x03E 1514 access_mode RW 1515 modes M_SCSI 1516 field AUTORSTDIS 0x10 1517 field CMDDMAEN 0x08 1518 field ASU 0x07 1519} 1520 1521/* 1522 * SCSI Bus Initiator IDs 1523 * Bitmask of observed initiators on the bus. 1524 */ 1525register BUSINITID { 1526 address 0x03C 1527 access_mode RW 1528 modes M_CFG 1529 size 2 1530} 1531 1532/* 1533 * Data Length Counters 1534 * Packet byte counter. 1535 */ 1536register DLCOUNT { 1537 address 0x03C 1538 access_mode RW 1539 modes M_DFF0, M_DFF1 1540 size 3 1541} 1542 1543/* 1544 * Data FIFO Status 1545 */ 1546register DFFSTAT { 1547 address 0x03F 1548 access_mode RW 1549 modes M_SCSI 1550 field FIFO1FREE 0x20 1551 field FIFO0FREE 0x10 1552 field CURRFIFO 0x01 1553} 1554 1555/* 1556 * SCSI Bus Target IDs 1557 * Bitmask of observed targets on the bus. 1558 */ 1559register BUSTARGID { 1560 address 0x03E 1561 access_mode RW 1562 modes M_CFG 1563 size 2 1564} 1565 1566/* 1567 * SCSI Control Signal Out 1568 */ 1569register SCSISIGO { 1570 address 0x040 1571 access_mode RW 1572 modes M_DFF0, M_DFF1, M_SCSI 1573 field CDO 0x80 1574 field IOO 0x40 1575 field MSGO 0x20 1576 field ATNO 0x10 1577 field SELO 0x08 1578 field BSYO 0x04 1579 field REQO 0x02 1580 field ACKO 0x01 1581/* 1582 * Possible phases to write into SCSISIG0 1583 */ 1584 enum PHASE_MASK CDO|IOO|MSGO { 1585 P_DATAOUT 0x0, 1586 P_DATAIN IOO, 1587 P_DATAOUT_DT P_DATAOUT|MSGO, 1588 P_DATAIN_DT P_DATAIN|MSGO, 1589 P_COMMAND CDO, 1590 P_MESGOUT CDO|MSGO, 1591 P_STATUS CDO|IOO, 1592 P_MESGIN CDO|IOO|MSGO 1593 } 1594} 1595 1596register SCSISIGI { 1597 address 0x041 1598 access_mode RO 1599 modes M_DFF0, M_DFF1, M_SCSI 1600 field CDI 0x80 1601 field IOI 0x40 1602 field MSGI 0x20 1603 field ATNI 0x10 1604 field SELI 0x08 1605 field BSYI 0x04 1606 field REQI 0x02 1607 field ACKI 0x01 1608/* 1609 * Possible phases in SCSISIGI 1610 */ 1611 enum PHASE_MASK CDO|IOO|MSGO { 1612 P_DATAOUT 0x0, 1613 P_DATAIN IOO, 1614 P_DATAOUT_DT P_DATAOUT|MSGO, 1615 P_DATAIN_DT P_DATAIN|MSGO, 1616 P_COMMAND CDO, 1617 P_MESGOUT CDO|MSGO, 1618 P_STATUS CDO|IOO, 1619 P_MESGIN CDO|IOO|MSGO 1620 } 1621} 1622 1623/* 1624 * Multiple Target IDs 1625 * Bitmask of ids to respond as a target. 1626 */ 1627register MULTARGID { 1628 address 0x040 1629 access_mode RW 1630 modes M_CFG 1631 size 2 1632} 1633 1634/* 1635 * SCSI Phase 1636 */ 1637register SCSIPHASE { 1638 address 0x042 1639 access_mode RO 1640 modes M_DFF0, M_DFF1, M_SCSI 1641 field STATUS_PHASE 0x20 1642 field COMMAND_PHASE 0x10 1643 field MSG_IN_PHASE 0x08 1644 field MSG_OUT_PHASE 0x04 1645 field DATA_PHASE_MASK 0x03 { 1646 DATA_OUT_PHASE 0x01, 1647 DATA_IN_PHASE 0x02 1648 } 1649} 1650 1651/* 1652 * SCSI Data 0 Image 1653 */ 1654register SCSIDAT0_IMG { 1655 address 0x043 1656 access_mode RW 1657 modes M_DFF0, M_DFF1, M_SCSI 1658} 1659 1660/* 1661 * SCSI Latched Data 1662 */ 1663register SCSIDAT { 1664 address 0x044 1665 access_mode RW 1666 modes M_DFF0, M_DFF1, M_SCSI 1667 size 2 1668} 1669 1670/* 1671 * SCSI Data Bus 1672 */ 1673register SCSIBUS { 1674 address 0x046 1675 access_mode RW 1676 modes M_DFF0, M_DFF1, M_SCSI 1677 size 2 1678} 1679 1680/* 1681 * Target ID In 1682 */ 1683register TARGIDIN { 1684 address 0x048 1685 access_mode RO 1686 modes M_DFF0, M_DFF1, M_SCSI 1687 field CLKOUT 0x80 1688 field TARGID 0x0F 1689} 1690 1691/* 1692 * Selection/Reselection ID 1693 * Upper four bits are the device id. The ONEBIT is set when the re/selecting 1694 * device did not set its own ID. 1695 */ 1696register SELID { 1697 address 0x049 1698 access_mode RW 1699 modes M_DFF0, M_DFF1, M_SCSI 1700 field SELID_MASK 0xf0 1701 field ONEBIT 0x08 1702} 1703 1704/* 1705 * SCSI Block Control 1706 * Controls Bus type and channel selection. SELWIDE allows for the 1707 * coexistence of 8bit and 16bit devices on a wide bus. 1708 */ 1709register SBLKCTL { 1710 address 0x04A 1711 access_mode RW 1712 modes M_DFF0, M_DFF1, M_SCSI 1713 field DIAGLEDEN 0x80 1714 field DIAGLEDON 0x40 1715 field ENAB40 0x08 /* LVD transceiver active */ 1716 field ENAB20 0x04 /* SE/HVD transceiver active */ 1717 field SELWIDE 0x02 1718} 1719 1720/* 1721 * Option Mode 1722 */ 1723register OPTIONMODE { 1724 address 0x04A 1725 access_mode RW 1726 modes M_CFG 1727 field BIOSCANCTL 0x80 1728 field AUTOACKEN 0x40 1729 field BIASCANCTL 0x20 1730 field BUSFREEREV 0x10 1731 field ENDGFORMCHK 0x04 1732 field AUTO_MSGOUT_DE 0x02 1733 mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE 1734} 1735 1736/* 1737 * SCSI Status 0 1738 */ 1739register SSTAT0 { 1740 address 0x04B 1741 access_mode RO 1742 modes M_DFF0, M_DFF1, M_SCSI 1743 field TARGET 0x80 /* Board acting as target */ 1744 field SELDO 0x40 /* Selection Done */ 1745 field SELDI 0x20 /* Board has been selected */ 1746 field SELINGO 0x10 /* Selection In Progress */ 1747 field IOERR 0x08 /* LVD Tranceiver mode changed */ 1748 field OVERRUN 0x04 /* SCSI Offset overrun detected */ 1749 field SPIORDY 0x02 /* SCSI PIO Ready */ 1750 field ARBDO 0x01 /* Arbitration Done Out */ 1751} 1752 1753/* 1754 * Clear SCSI Interrupt 0 1755 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 1756 */ 1757register CLRSINT0 { 1758 address 0x04B 1759 access_mode WO 1760 modes M_DFF0, M_DFF1, M_SCSI 1761 field CLRSELDO 0x40 1762 field CLRSELDI 0x20 1763 field CLRSELINGO 0x10 1764 field CLRIOERR 0x08 1765 field CLROVERRUN 0x04 1766 field CLRSPIORDY 0x02 1767 field CLRARBDO 0x01 1768} 1769 1770/* 1771 * SCSI Interrupt Mode 0 1772 * Setting any bit will enable the corresponding function 1773 * in SIMODE0 to interrupt via the IRQ pin. 1774 */ 1775register SIMODE0 { 1776 address 0x04B 1777 access_mode RW 1778 modes M_CFG 1779 field ENSELDO 0x40 1780 field ENSELDI 0x20 1781 field ENSELINGO 0x10 1782 field ENIOERR 0x08 1783 field ENOVERRUN 0x04 1784 field ENSPIORDY 0x02 1785 field ENARBDO 0x01 1786} 1787 1788/* 1789 * SCSI Status 1 1790 */ 1791register SSTAT1 { 1792 address 0x04C 1793 access_mode RO 1794 modes M_DFF0, M_DFF1, M_SCSI 1795 field SELTO 0x80 1796 field ATNTARG 0x40 1797 field SCSIRSTI 0x20 1798 field PHASEMIS 0x10 1799 field BUSFREE 0x08 1800 field SCSIPERR 0x04 1801 field STRB2FAST 0x02 1802 field REQINIT 0x01 1803} 1804 1805/* 1806 * Clear SCSI Interrupt 1 1807 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 1808 */ 1809register CLRSINT1 { 1810 address 0x04c 1811 access_mode WO 1812 modes M_DFF0, M_DFF1, M_SCSI 1813 field CLRSELTIMEO 0x80 1814 field CLRATNO 0x40 1815 field CLRSCSIRSTI 0x20 1816 field CLRBUSFREE 0x08 1817 field CLRSCSIPERR 0x04 1818 field CLRSTRB2FAST 0x02 1819 field CLRREQINIT 0x01 1820} 1821 1822/* 1823 * SCSI Status 2 1824 */ 1825register SSTAT2 { 1826 address 0x04d 1827 access_mode RO 1828 modes M_DFF0, M_DFF1, M_SCSI 1829 field BUSFREETIME 0xc0 { 1830 BUSFREE_LQO 0x40, 1831 BUSFREE_DFF0 0x80, 1832 BUSFREE_DFF1 0xC0 1833 } 1834 field NONPACKREQ 0x20 1835 field EXP_ACTIVE 0x10 /* SCSI Expander Active */ 1836 field BSYX 0x08 /* Busy Expander */ 1837 field WIDE_RES 0x04 /* Modes 0 and 1 only */ 1838 field SDONE 0x02 /* Modes 0 and 1 only */ 1839 field DMADONE 0x01 /* Modes 0 and 1 only */ 1840} 1841 1842/* 1843 * Clear SCSI Interrupt 2 1844 */ 1845register CLRSINT2 { 1846 address 0x04D 1847 access_mode WO 1848 modes M_DFF0, M_DFF1, M_SCSI 1849 field CLRNONPACKREQ 0x20 1850 field CLRWIDE_RES 0x04 /* Modes 0 and 1 only */ 1851 field CLRSDONE 0x02 /* Modes 0 and 1 only */ 1852 field CLRDMADONE 0x01 /* Modes 0 and 1 only */ 1853} 1854 1855/* 1856 * SCSI Interrupt Mode 2 1857 */ 1858register SIMODE2 { 1859 address 0x04D 1860 access_mode RW 1861 modes M_CFG 1862 field ENWIDE_RES 0x04 1863 field ENSDONE 0x02 1864 field ENDMADONE 0x01 1865} 1866 1867/* 1868 * Physical Error Diagnosis 1869 */ 1870register PERRDIAG { 1871 address 0x04E 1872 access_mode RO 1873 modes M_DFF0, M_DFF1, M_SCSI 1874 field HIZERO 0x80 1875 field HIPERR 0x40 1876 field PREVPHASE 0x20 1877 field PARITYERR 0x10 1878 field AIPERR 0x08 1879 field CRCERR 0x04 1880 field DGFORMERR 0x02 1881 field DTERR 0x01 1882} 1883 1884/* 1885 * LQI Manager Current State 1886 */ 1887register LQISTATE { 1888 address 0x04E 1889 access_mode RO 1890 modes M_CFG 1891} 1892 1893/* 1894 * SCSI Offset Count 1895 */ 1896register SOFFCNT { 1897 address 0x04F 1898 access_mode RO 1899 modes M_DFF0, M_DFF1, M_SCSI 1900} 1901 1902/* 1903 * LQO Manager Current State 1904 */ 1905register LQOSTATE { 1906 address 0x04F 1907 access_mode RO 1908 modes M_CFG 1909} 1910 1911/* 1912 * LQI Manager Status 1913 */ 1914register LQISTAT0 { 1915 address 0x050 1916 access_mode RO 1917 modes M_DFF0, M_DFF1, M_SCSI 1918 field LQIATNQAS 0x20 1919 field LQICRCT1 0x10 1920 field LQICRCT2 0x08 1921 field LQIBADLQT 0x04 1922 field LQIATNLQ 0x02 1923 field LQIATNCMD 0x01 1924} 1925 1926/* 1927 * Clear LQI Interrupts 0 1928 */ 1929register CLRLQIINT0 { 1930 address 0x050 1931 access_mode WO 1932 modes M_DFF0, M_DFF1, M_SCSI 1933 field CLRLQIATNQAS 0x20 1934 field CLRLQICRCT1 0x10 1935 field CLRLQICRCT2 0x08 1936 field CLRLQIBADLQT 0x04 1937 field CLRLQIATNLQ 0x02 1938 field CLRLQIATNCMD 0x01 1939} 1940 1941/* 1942 * LQI Manager Interrupt Mode 0 1943 */ 1944register LQIMODE0 { 1945 address 0x050 1946 access_mode RW 1947 modes M_CFG 1948 field ENLQIATNQASK 0x20 1949 field ENLQICRCT1 0x10 1950 field ENLQICRCT2 0x08 1951 field ENLQIBADLQT 0x04 1952 field ENLQIATNLQ 0x02 1953 field ENLQIATNCMD 0x01 1954} 1955 1956/* 1957 * LQI Manager Status 1 1958 */ 1959register LQISTAT1 { 1960 address 0x051 1961 access_mode RO 1962 modes M_DFF0, M_DFF1, M_SCSI 1963 field LQIPHASE_LQ 0x80 1964 field LQIPHASE_NLQ 0x40 1965 field LQIABORT 0x20 1966 field LQICRCI_LQ 0x10 1967 field LQICRCI_NLQ 0x08 1968 field LQIBADLQI 0x04 1969 field LQIOVERI_LQ 0x02 1970 field LQIOVERI_NLQ 0x01 1971} 1972 1973/* 1974 * Clear LQI Manager Interrupts1 1975 */ 1976register CLRLQIINT1 { 1977 address 0x051 1978 access_mode WO 1979 modes M_DFF0, M_DFF1, M_SCSI 1980 field CLRLQIPHASE_LQ 0x80 1981 field CLRLQIPHASE_NLQ 0x40 1982 field CLRLIQABORT 0x20 1983 field CLRLQICRCI_LQ 0x10 1984 field CLRLQICRCI_NLQ 0x08 1985 field CLRLQIBADLQI 0x04 1986 field CLRLQIOVERI_LQ 0x02 1987 field CLRLQIOVERI_NLQ 0x01 1988} 1989 1990/* 1991 * LQI Manager Interrupt Mode 1 1992 */ 1993register LQIMODE1 { 1994 address 0x051 1995 access_mode RW 1996 modes M_CFG 1997 field ENLQIPHASE_LQ 0x80 1998 field ENLQIPHASE_NLQ 0x40 1999 field ENLIQABORT 0x20 2000 field ENLQICRCI_LQ 0x10 2001 field ENLQICRCI_NLQ 0x08 2002 field ENLQIBADLQI 0x04 2003 field ENLQIOVERI_LQ 0x02 2004 field ENLQIOVERI_NLQ 0x01 2005} 2006 2007/* 2008 * LQI Manager Status 2 2009 */ 2010register LQISTAT2 { 2011 address 0x052 2012 access_mode RO 2013 modes M_DFF0, M_DFF1, M_SCSI 2014 field PACKETIZED 0x80 2015 field LQIPHASE_OUTPKT 0x40 2016 field LQIWORKONLQ 0x20 2017 field LQIWAITFIFO 0x10 2018 field LQISTOPPKT 0x08 2019 field LQISTOPLQ 0x04 2020 field LQISTOPCMD 0x02 2021 field LQIGSAVAIL 0x01 2022} 2023 2024/* 2025 * SCSI Status 3 2026 */ 2027register SSTAT3 { 2028 address 0x053 2029 access_mode RO 2030 modes M_DFF0, M_DFF1, M_SCSI 2031 field NTRAMPERR 0x02 2032 field OSRAMPERR 0x01 2033} 2034 2035/* 2036 * Clear SCSI Status 3 2037 */ 2038register CLRSINT3 { 2039 address 0x053 2040 access_mode WO 2041 modes M_DFF0, M_DFF1, M_SCSI 2042 field CLRNTRAMPERR 0x02 2043 field CLROSRAMPERR 0x01 2044} 2045 2046/* 2047 * SCSI Interrupt Mode 3 2048 */ 2049register SIMODE3 { 2050 address 0x053 2051 access_mode RW 2052 modes M_CFG 2053 field ENNTRAMPERR 0x02 2054 field ENOSRAMPERR 0x01 2055} 2056 2057/* 2058 * LQO Manager Status 0 2059 */ 2060register LQOSTAT0 { 2061 address 0x054 2062 access_mode RO 2063 modes M_DFF0, M_DFF1, M_SCSI 2064 field LQOTARGSCBPERR 0x10 2065 field LQOSTOPT2 0x08 2066 field LQOATNLQ 0x04 2067 field LQOATNPKT 0x02 2068 field LQOTCRC 0x01 2069} 2070 2071/* 2072 * Clear LQO Manager interrupt 0 2073 */ 2074register CLRLQOINT0 { 2075 address 0x054 2076 access_mode WO 2077 modes M_DFF0, M_DFF1, M_SCSI 2078 field CLRLQOTARGSCBPERR 0x10 2079 field CLRLQOSTOPT2 0x08 2080 field CLRLQOATNLQ 0x04 2081 field CLRLQOATNPKT 0x02 2082 field CLRLQOTCRC 0x01 2083} 2084 2085/* 2086 * LQO Manager Interrupt Mode 0 2087 */ 2088register LQOMODE0 { 2089 address 0x054 2090 access_mode RW 2091 modes M_CFG 2092 field ENLQOTARGSCBPERR 0x10 2093 field ENLQOSTOPT2 0x08 2094 field ENLQOATNLQ 0x04 2095 field ENLQOATNPKT 0x02 2096 field ENLQOTCRC 0x01 2097} 2098 2099/* 2100 * LQO Manager Status 1 2101 */ 2102register LQOSTAT1 { 2103 address 0x055 2104 access_mode RO 2105 modes M_DFF0, M_DFF1, M_SCSI 2106 field LQOINITSCBPERR 0x10 2107 field LQOSTOPI2 0x08 2108 field LQOBADQAS 0x04 2109 field LQOBUSFREE 0x02 2110 field LQOPHACHGINPKT 0x01 2111} 2112 2113/* 2114 * Clear LOQ Interrupt 1 2115 */ 2116register CLRLQOINT1 { 2117 address 0x055 2118 access_mode WO 2119 modes M_DFF0, M_DFF1, M_SCSI 2120 field CLRLQOINITSCBPERR 0x10 2121 field CLRLQOSTOPI2 0x08 2122 field CLRLQOBADQAS 0x04 2123 field CLRLQOBUSFREE 0x02 2124 field CLRLQOPHACHGINPKT 0x01 2125} 2126 2127/* 2128 * LQO Manager Interrupt Mode 1 2129 */ 2130register LQOMODE1 { 2131 address 0x055 2132 access_mode RW 2133 modes M_CFG 2134 field ENLQOINITSCBPERR 0x10 2135 field ENLQOSTOPI2 0x08 2136 field ENLQOBADQAS 0x04 2137 field ENLQOBUSFREE 0x02 2138 field ENLQOPHACHGINPKT 0x01 2139} 2140 2141/* 2142 * LQO Manager Status 2 2143 */ 2144register LQOSTAT2 { 2145 address 0x056 2146 access_mode RO 2147 modes M_DFF0, M_DFF1, M_SCSI 2148 field LQOPKT 0xE0 2149 field LQOWAITFIFO 0x10 2150 field LQOPHACHGOUTPKT 0x02 /* outside of packet boundaries. */ 2151 field LQOSTOP0 0x01 /* Stopped after sending all packets */ 2152} 2153 2154/* 2155 * Output Synchronizer Space Count 2156 */ 2157register OS_SPACE_CNT { 2158 address 0x056 2159 access_mode RO 2160 modes M_CFG 2161} 2162 2163/* 2164 * SCSI Interrupt Mode 1 2165 * Setting any bit will enable the corresponding function 2166 * in SIMODE1 to interrupt via the IRQ pin. 2167 */ 2168register SIMODE1 { 2169 address 0x057 2170 access_mode RW 2171 modes M_DFF0, M_DFF1, M_SCSI 2172 field ENSELTIMO 0x80 2173 field ENATNTARG 0x40 2174 field ENSCSIRST 0x20 2175 field ENPHASEMIS 0x10 2176 field ENBUSFREE 0x08 2177 field ENSCSIPERR 0x04 2178 field ENSTRB2FAST 0x02 2179 field ENREQINIT 0x01 2180} 2181 2182/* 2183 * Good Status FIFO 2184 */ 2185register GSFIFO { 2186 address 0x058 2187 access_mode RO 2188 size 2 2189 modes M_DFF0, M_DFF1, M_SCSI 2190} 2191 2192/* 2193 * Data FIFO SCSI Transfer Control 2194 */ 2195register DFFSXFRCTL { 2196 address 0x05A 2197 access_mode RW 2198 modes M_DFF0, M_DFF1 2199 field CLRSHCNT 0x04 2200 field CLRCHN 0x02 2201 field RSTCHN 0x01 2202} 2203 2204/* 2205 * Next SCSI Control Block 2206 */ 2207register NEXTSCB { 2208 address 0x05A 2209 access_mode RW 2210 size 2 2211 modes M_SCSI 2212} 2213 2214/* 2215 * SEQ Interrupts 2216 */ 2217register SEQINTSRC { 2218 address 0x05B 2219 access_mode RO 2220 modes M_DFF0, M_DFF1 2221 field CTXTDONE 0x40 2222 field SAVEPTRS 0x20 2223 field CFG4DATA 0x10 2224 field CFG4ISTAT 0x08 2225 field CFG4TSTAT 0x04 2226 field CFG4ICMD 0x02 2227 field CFG4TCMD 0x01 2228} 2229 2230/* 2231 * Clear Arp Interrupts 2232 */ 2233register CLRSEQINTSRC { 2234 address 0x05B 2235 access_mode WO 2236 modes M_DFF0, M_DFF1 2237 field CLRCTXTDONE 0x40 2238 field CLRSAVEPTRS 0x20 2239 field CLRCFG4DATA 0x10 2240 field CLRCFG4ISTAT 0x08 2241 field CLRCFG4TSTAT 0x04 2242 field CLRCFG4ICMD 0x02 2243 field CLRCFG4TCMD 0x01 2244} 2245 2246/* 2247 * SEQ Interrupt Enabled (Shared) 2248 */ 2249register SEQIMODE { 2250 address 0x05C 2251 access_mode RW 2252 modes M_DFF0, M_DFF1 2253 field ENCTXTDONE 0x40 2254 field ENSAVEPTRS 0x20 2255 field ENCFG4DATA 0x10 2256 field ENCFG4ISTAT 0x08 2257 field ENCFG4TSTAT 0x04 2258 field ENCFG4ICMD 0x02 2259 field ENCFG4TCMD 0x01 2260} 2261 2262/* 2263 * Current SCSI Control Block 2264 */ 2265register CURRSCB { 2266 address 0x05C 2267 access_mode RW 2268 size 2 2269 modes M_SCSI 2270} 2271 2272/* 2273 * Data FIFO Status 2274 */ 2275register MDFFSTAT { 2276 address 0x05D 2277 access_mode RO 2278 modes M_DFF0, M_DFF1 2279 field SHCNTNEGATIVE 0x40 /* Rev B or higher */ 2280 field SHCNTMINUS1 0x20 /* Rev B or higher */ 2281 field LASTSDONE 0x10 2282 field SHVALID 0x08 2283 field DLZERO 0x04 /* FIFO data ends on packet boundary. */ 2284 field DATAINFIFO 0x02 2285 field FIFOFREE 0x01 2286} 2287 2288/* 2289 * CRC Control 2290 */ 2291register CRCCONTROL { 2292 address 0x05d 2293 access_mode RW 2294 modes M_CFG 2295 field CRCVALCHKEN 0x40 2296} 2297 2298/* 2299 * SCSI Test Control 2300 */ 2301register SCSITEST { 2302 address 0x05E 2303 access_mode RW 2304 modes M_CFG 2305 field CNTRTEST 0x08 2306 field SEL_TXPLL_DEBUG 0x04 2307} 2308 2309/* 2310 * Data FIFO Queue Tag 2311 */ 2312register DFFTAG { 2313 address 0x05E 2314 access_mode RW 2315 size 2 2316 modes M_DFF0, M_DFF1 2317} 2318 2319/* 2320 * Last SCSI Control Block 2321 */ 2322register LASTSCB { 2323 address 0x05E 2324 access_mode RW 2325 size 2 2326 modes M_SCSI 2327} 2328 2329/* 2330 * SCSI I/O Cell Power-down Control 2331 */ 2332register IOPDNCTL { 2333 address 0x05F 2334 access_mode RW 2335 modes M_CFG 2336 field DISABLE_OE 0x80 2337 field PDN_IDIST 0x04 2338 field PDN_DIFFSENSE 0x01 2339} 2340 2341/* 2342 * Shaddow Host Address. 2343 */ 2344register SHADDR { 2345 address 0x060 2346 access_mode RO 2347 size 8 2348 modes M_DFF0, M_DFF1 2349} 2350 2351/* 2352 * Data Group CRC Interval. 2353 */ 2354register DGRPCRCI { 2355 address 0x060 2356 access_mode RW 2357 size 2 2358 modes M_CFG 2359} 2360 2361/* 2362 * Data Transfer Negotiation Address 2363 */ 2364register NEGOADDR { 2365 address 0x060 2366 access_mode RW 2367 modes M_SCSI 2368} 2369 2370/* 2371 * Data Transfer Negotiation Data - Period Byte 2372 */ 2373register NEGPERIOD { 2374 address 0x061 2375 access_mode RW 2376 modes M_SCSI 2377} 2378 2379/* 2380 * Packetized CRC Interval 2381 */ 2382register PACKCRCI { 2383 address 0x062 2384 access_mode RW 2385 size 2 2386 modes M_CFG 2387} 2388 2389/* 2390 * Data Transfer Negotiation Data - Offset Byte 2391 */ 2392register NEGOFFSET { 2393 address 0x062 2394 access_mode RW 2395 modes M_SCSI 2396} 2397 2398/* 2399 * Data Transfer Negotiation Data - PPR Options 2400 */ 2401register NEGPPROPTS { 2402 address 0x063 2403 access_mode RW 2404 modes M_SCSI 2405 field PPROPT_PACE 0x08 2406 field PPROPT_QAS 0x04 2407 field PPROPT_DT 0x02 2408 field PPROPT_IUT 0x01 2409} 2410 2411/* 2412 * Data Transfer Negotiation Data - Connection Options 2413 */ 2414register NEGCONOPTS { 2415 address 0x064 2416 access_mode RW 2417 modes M_SCSI 2418 field ENAIP 0x08 2419 field ENAUTOATNI 0x04 2420 field ENAUTOATNO 0x02 2421 field WIDEXFER 0x01 2422} 2423 2424/* 2425 * Negotiation Table Annex Column Index. 2426 */ 2427register ANNEXCOL { 2428 address 0x065 2429 access_mode RW 2430 modes M_SCSI 2431} 2432 2433register SCSCHKN { 2434 address 0x066 2435 access_mode RW 2436 modes M_CFG 2437 field STSELSKIDDIS 0x40 2438 field CURFIFODEF 0x20 2439 field WIDERESEN 0x10 2440 field SDONEMSKDIS 0x08 2441 field DFFACTCLR 0x04 2442 field SHVALIDSTDIS 0x02 2443 field LSTSGCLRDIS 0x01 2444} 2445 2446const AHD_ANNEXCOL_PRECOMP 4 2447const AHD_PRECOMP_MASK 0x07 2448const AHD_PRECOMP_CUTBACK_17 0x04 2449const AHD_PRECOMP_CUTBACK_29 0x06 2450const AHD_PRECOMP_CUTBACK_37 0x07 2451const AHD_PRECOMP_FASTSLEW 0x40 2452const AHD_NUM_ANNEXCOLS 4 2453 2454/* 2455 * Negotiation Table Annex Data Port. 2456 */ 2457register ANNEXDAT { 2458 address 0x066 2459 access_mode RW 2460 modes M_SCSI 2461} 2462 2463/* 2464 * Initiator's Own Id. 2465 * The SCSI ID to use for Selection Out and seen during a reselection.. 2466 */ 2467register IOWNID { 2468 address 0x067 2469 access_mode RW 2470 modes M_SCSI 2471} 2472 2473/* 2474 * 960MHz Phase-Locked Loop Control 0 2475 */ 2476register PLL960CTL0 { 2477 address 0x068 2478 access_mode RW 2479 modes M_CFG 2480 field PLL_VCOSEL 0x80 2481 field PLL_PWDN 0x40 2482 field PLL_NS 0x30 2483 field PLL_ENLUD 0x08 2484 field PLL_ENLPF 0x04 2485 field PLL_DLPF 0x02 2486 field PLL_ENFBM 0x01 2487} 2488 2489/* 2490 * Target Own Id 2491 */ 2492register TOWNID { 2493 address 0x069 2494 access_mode RW 2495 modes M_SCSI 2496} 2497 2498/* 2499 * 960MHz Phase-Locked Loop Control 1 2500 */ 2501register PLL960CTL1 { 2502 address 0x069 2503 access_mode RW 2504 modes M_CFG 2505 field PLL_CNTEN 0x80 2506 field PLL_CNTCLR 0x40 2507 field PLL_RST 0x01 2508} 2509 2510/* 2511 * Expander Signature 2512 */ 2513register XSIG { 2514 address 0x06A 2515 access_mode RW 2516 modes M_SCSI 2517} 2518 2519/* 2520 * Shadow Byte Count 2521 */ 2522register SHCNT { 2523 address 0x068 2524 access_mode RW 2525 size 3 2526 modes M_DFF0, M_DFF1 2527} 2528 2529/* 2530 * Selection Out ID 2531 */ 2532register SELOID { 2533 address 0x06B 2534 access_mode RW 2535 modes M_SCSI 2536} 2537 2538/* 2539 * 960-MHz Phase-Locked Loop Test Count 2540 */ 2541register PLL960CNT0 { 2542 address 0x06A 2543 access_mode RO 2544 size 2 2545 modes M_CFG 2546} 2547 2548/* 2549 * 400-MHz Phase-Locked Loop Control 0 2550 */ 2551register PLL400CTL0 { 2552 address 0x06C 2553 access_mode RW 2554 modes M_CFG 2555 field PLL_VCOSEL 0x80 2556 field PLL_PWDN 0x40 2557 field PLL_NS 0x30 2558 field PLL_ENLUD 0x08 2559 field PLL_ENLPF 0x04 2560 field PLL_DLPF 0x02 2561 field PLL_ENFBM 0x01 2562} 2563 2564/* 2565 * Arbitration Fairness 2566 */ 2567register FAIRNESS { 2568 address 0x06C 2569 access_mode RW 2570 size 2 2571 modes M_SCSI 2572} 2573 2574/* 2575 * 400-MHz Phase-Locked Loop Control 1 2576 */ 2577register PLL400CTL1 { 2578 address 0x06D 2579 access_mode RW 2580 modes M_CFG 2581 field PLL_CNTEN 0x80 2582 field PLL_CNTCLR 0x40 2583 field PLL_RST 0x01 2584} 2585 2586/* 2587 * Arbitration Unfairness 2588 */ 2589register UNFAIRNESS { 2590 address 0x06E 2591 access_mode RW 2592 size 2 2593 modes M_SCSI 2594} 2595 2596/* 2597 * 400-MHz Phase-Locked Loop Test Count 2598 */ 2599register PLL400CNT0 { 2600 address 0x06E 2601 access_mode RO 2602 size 2 2603 modes M_CFG 2604} 2605 2606/* 2607 * SCB Page Pointer 2608 */ 2609register SCBPTR { 2610 address 0x0A8 2611 access_mode RW 2612 size 2 2613 modes M_DFF0, M_DFF1, M_CCHAN, M_SCSI 2614} 2615 2616/* 2617 * CMC SCB Array Count 2618 * Number of bytes to transfer between CMC SCB memory and SCBRAM. 2619 * Transfers must be 8byte aligned and sized. 2620 */ 2621register CCSCBACNT { 2622 address 0x0AB 2623 access_mode RW 2624 modes M_CCHAN 2625} 2626 2627/* 2628 * SCB Autopointer 2629 * SCB-Next Address Snooping logic. When an SCB is transferred to 2630 * the card, the next SCB address to be used by the CMC array can 2631 * be autoloaded from that transfer. 2632 */ 2633register SCBAUTOPTR { 2634 address 0x0AB 2635 access_mode RW 2636 modes M_CFG 2637 field AUSCBPTR_EN 0x80 2638 field SCBPTR_ADDR 0x38 2639 field SCBPTR_OFF 0x07 2640} 2641 2642/* 2643 * CMC SG Ram Address Pointer 2644 */ 2645register CCSGADDR { 2646 address 0x0AC 2647 access_mode RW 2648 modes M_DFF0, M_DFF1 2649} 2650 2651/* 2652 * CMC SCB RAM Address Pointer 2653 */ 2654register CCSCBADDR { 2655 address 0x0AC 2656 access_mode RW 2657 modes M_CCHAN 2658} 2659 2660/* 2661 * CMC SCB Ram Back-up Address Pointer 2662 * Indicates the true stop location of transfers halted prior 2663 * to SCBHCNT going to 0. 2664 */ 2665register CCSCBADR_BK { 2666 address 0x0AC 2667 access_mode RO 2668 modes M_CFG 2669} 2670 2671/* 2672 * CMC SG Control 2673 */ 2674register CCSGCTL { 2675 address 0x0AD 2676 access_mode RW 2677 modes M_DFF0, M_DFF1 2678 field CCSGDONE 0x80 2679 field SG_CACHE_AVAIL 0x10 2680 field CCSGEN 0x08 2681 field SG_FETCH_REQ 0x02 2682 field CCSGRESET 0x01 2683} 2684 2685/* 2686 * CMD SCB Control 2687 */ 2688register CCSCBCTL { 2689 address 0x0AD 2690 access_mode RW 2691 modes M_CCHAN 2692 field CCSCBDONE 0x80 2693 field ARRDONE 0x40 2694 field CCARREN 0x10 2695 field CCSCBEN 0x08 2696 field CCSCBDIR 0x04 2697 field CCSCBRESET 0x01 2698} 2699 2700/* 2701 * CMC Ram BIST 2702 */ 2703register CMC_RAMBIST { 2704 address 0x0AD 2705 access_mode RW 2706 modes M_CFG 2707 field SG_ELEMENT_SIZE 0x80 2708 field SCBRAMBIST_FAIL 0x40 2709 field SG_BIST_FAIL 0x20 2710 field SG_BIST_EN 0x10 2711 field CMC_BUFFER_BIST_FAIL 0x02 2712 field CMC_BUFFER_BIST_EN 0x01 2713} 2714 2715/* 2716 * CMC SG RAM Data Port 2717 */ 2718register CCSGRAM { 2719 address 0x0B0 2720 access_mode RW 2721 modes M_DFF0, M_DFF1 2722} 2723 2724/* 2725 * CMC SCB RAM Data Port 2726 */ 2727register CCSCBRAM { 2728 address 0x0B0 2729 access_mode RW 2730 modes M_CCHAN 2731} 2732 2733/* 2734 * Flex DMA Address. 2735 */ 2736register FLEXADR { 2737 address 0x0B0 2738 access_mode RW 2739 size 3 2740 modes M_SCSI 2741} 2742 2743/* 2744 * Flex DMA Byte Count 2745 */ 2746register FLEXCNT { 2747 address 0x0B3 2748 access_mode RW 2749 size 2 2750 modes M_SCSI 2751} 2752 2753/* 2754 * Flex DMA Status 2755 */ 2756register FLEXDMASTAT { 2757 address 0x0B5 2758 access_mode RW 2759 modes M_SCSI 2760 field FLEXDMAERR 0x02 2761 field FLEXDMADONE 0x01 2762} 2763 2764/* 2765 * Flex DMA Data Port 2766 */ 2767register FLEXDATA { 2768 address 0x0B6 2769 access_mode RW 2770 modes M_SCSI 2771} 2772 2773/* 2774 * Board Data 2775 */ 2776register BRDDAT { 2777 address 0x0B8 2778 access_mode RW 2779 modes M_SCSI 2780} 2781 2782/* 2783 * Board Control 2784 */ 2785register BRDCTL { 2786 address 0x0B9 2787 access_mode RW 2788 modes M_SCSI 2789 field FLXARBACK 0x80 2790 field FLXARBREQ 0x40 2791 field BRDADDR 0x38 2792 field BRDEN 0x04 2793 field BRDRW 0x02 2794 field BRDSTB 0x01 2795} 2796 2797/* 2798 * Serial EEPROM Address 2799 */ 2800register SEEADR { 2801 address 0x0BA 2802 access_mode RW 2803 modes M_SCSI 2804} 2805 2806/* 2807 * Serial EEPROM Data 2808 */ 2809register SEEDAT { 2810 address 0x0BC 2811 access_mode RW 2812 size 2 2813 modes M_SCSI 2814} 2815 2816/* 2817 * Serial EEPROM Status 2818 */ 2819register SEESTAT { 2820 address 0x0BE 2821 access_mode RO 2822 modes M_SCSI 2823 field INIT_DONE 0x80 2824 field SEEOPCODE 0x70 2825 field LDALTID_L 0x08 2826 field SEEARBACK 0x04 2827 field SEEBUSY 0x02 2828 field SEESTART 0x01 2829} 2830 2831/* 2832 * Serial EEPROM Control 2833 */ 2834register SEECTL { 2835 address 0x0BE 2836 access_mode RW 2837 modes M_SCSI 2838 field SEEOPCODE 0x70 { 2839 SEEOP_ERASE 0x70, 2840 SEEOP_READ 0x60, 2841 SEEOP_WRITE 0x50, 2842 /* 2843 * The following four commands use special 2844 * addresses for differentiation. 2845 */ 2846 SEEOP_ERAL 0x40 2847 } 2848 mask SEEOP_EWEN 0x40 2849 mask SEEOP_WALL 0x40 2850 mask SEEOP_EWDS 0x40 2851 field SEERST 0x02 2852 field SEESTART 0x01 2853} 2854 2855const SEEOP_ERAL_ADDR 0x80 2856const SEEOP_EWEN_ADDR 0xC0 2857const SEEOP_WRAL_ADDR 0x40 2858const SEEOP_EWDS_ADDR 0x00 2859 2860/* 2861 * SCB Counter 2862 */ 2863register SCBCNT { 2864 address 0x0BF 2865 access_mode RW 2866 modes M_SCSI 2867} 2868 2869/* 2870 * Data FIFO Write Address 2871 * Pointer to the next QWD location to be written to the data FIFO. 2872 */ 2873register DFWADDR { 2874 address 0x0C0 2875 access_mode RW 2876 size 2 2877 modes M_DFF0, M_DFF1 2878} 2879 2880/* 2881 * DSP Filter Control 2882 */ 2883register DSPFLTRCTL { 2884 address 0x0C0 2885 access_mode RW 2886 modes M_CFG 2887 field FLTRDISABLE 0x20 2888 field EDGESENSE 0x10 2889 field DSPFCNTSEL 0x0F 2890} 2891 2892/* 2893 * DSP Data Channel Control 2894 */ 2895register DSPDATACTL { 2896 address 0x0C1 2897 access_mode RW 2898 modes M_CFG 2899 field BYPASSENAB 0x80 2900 field DESQDIS 0x10 2901 field RCVROFFSTDIS 0x04 2902 field XMITOFFSTDIS 0x02 2903} 2904 2905/* 2906 * Data FIFO Read Address 2907 * Pointer to the next QWD location to be read from the data FIFO. 2908 */ 2909register DFRADDR { 2910 address 0x0C2 2911 access_mode RW 2912 size 2 2913 modes M_DFF0, M_DFF1 2914} 2915 2916/* 2917 * DSP REQ Control 2918 */ 2919register DSPREQCTL { 2920 address 0x0C2 2921 access_mode RW 2922 modes M_CFG 2923 field MANREQCTL 0xC0 2924 field MANREQDLY 0x3F 2925} 2926 2927/* 2928 * DSP ACK Control 2929 */ 2930register DSPACKCTL { 2931 address 0x0C3 2932 access_mode RW 2933 modes M_CFG 2934 field MANACKCTL 0xC0 2935 field MANACKDLY 0x3F 2936} 2937 2938/* 2939 * Data FIFO Data 2940 * Read/Write byte port into the data FIFO. The read and write 2941 * FIFO pointers increment with each read and write respectively 2942 * to this port. 2943 */ 2944register DFDAT { 2945 address 0x0C4 2946 access_mode RW 2947 modes M_DFF0, M_DFF1 2948} 2949 2950/* 2951 * DSP Channel Select 2952 */ 2953register DSPSELECT { 2954 address 0x0C4 2955 access_mode RW 2956 modes M_CFG 2957 field AUTOINCEN 0x80 2958 field DSPSEL 0x1F 2959} 2960 2961const NUMDSPS 0x14 2962 2963/* 2964 * Write Bias Control 2965 */ 2966register WRTBIASCTL { 2967 address 0x0C5 2968 access_mode WO 2969 modes M_CFG 2970 field AUTOXBCDIS 0x80 2971 field XMITMANVAL 0x3F 2972} 2973 2974const WRTBIASCTL_CPQ_DEFAULT 0x97 2975 2976/* 2977 * Receiver Bias Control 2978 */ 2979register RCVRBIOSCTL { 2980 address 0x0C6 2981 access_mode WO 2982 modes M_CFG 2983 field AUTORBCDIS 0x80 2984 field RCVRMANVAL 0x3F 2985} 2986 2987/* 2988 * Write Bias Calculator 2989 */ 2990register WRTBIASCALC { 2991 address 0x0C7 2992 access_mode RO 2993 modes M_CFG 2994} 2995 2996/* 2997 * Data FIFO Pointers 2998 * Contains the byte offset from DFWADDR and DWRADDR to the current 2999 * FIFO write/read locations. 3000 */ 3001register DFPTRS { 3002 address 0x0C8 3003 access_mode RW 3004 modes M_DFF0, M_DFF1 3005} 3006 3007/* 3008 * Receiver Bias Calculator 3009 */ 3010register RCVRBIASCALC { 3011 address 0x0C8 3012 access_mode RO 3013 modes M_CFG 3014} 3015 3016/* 3017 * Data FIFO Debug Control 3018 */ 3019register DFDBCTL { 3020 address 0x0C8 3021 access_mode RW 3022 modes M_DFF0, M_DFF1 3023 field DFF_CIO_WR_RDY 0x20 3024 field DFF_CIO_RD_RDY 0x10 3025 field DFF_DIR_ERR 0x08 3026 field DFF_RAMBIST_FAIL 0x04 3027 field DFF_RAMBIST_DONE 0x02 3028 field DFF_RAMBIST_EN 0x01 3029} 3030 3031/* 3032 * Data FIFO Backup Read Pointer 3033 * Contains the data FIFO address to be restored if the last 3034 * data accessed from the data FIFO was not transferred successfully. 3035 */ 3036register DFBKPTR { 3037 address 0x0C9 3038 access_mode RW 3039 size 2 3040 modes M_DFF0, M_DFF1 3041} 3042 3043/* 3044 * Skew Calculator 3045 */ 3046register SKEWCALC { 3047 address 0x0C9 3048 access_mode RO 3049 modes M_CFG 3050} 3051 3052/* 3053 * Data FIFO Space Count 3054 * Number of FIFO locations that are free. 3055 */ 3056register DFSCNT { 3057 address 0x0CC 3058 access_mode RO 3059 size 2 3060 modes M_DFF0, M_DFF1 3061} 3062 3063/* 3064 * Data FIFO Byte Count 3065 * Number of filled FIFO locations. 3066 */ 3067register DFBCNT { 3068 address 0x0CE 3069 access_mode RO 3070 size 2 3071 modes M_DFF0, M_DFF1 3072} 3073 3074/* 3075 * Sequencer Program Overlay Address. 3076 * Low address must be written prior to high address. 3077 */ 3078register OVLYADDR { 3079 address 0x0D4 3080 modes M_SCSI 3081 size 2 3082 access_mode RW 3083} 3084 3085/* 3086 * Sequencer Control 0 3087 * Error detection mode, speed configuration, 3088 * single step, breakpoints and program load. 3089 */ 3090register SEQCTL0 { 3091 address 0x0D6 3092 access_mode RW 3093 field PERRORDIS 0x80 3094 field PAUSEDIS 0x40 3095 field FAILDIS 0x20 3096 field FASTMODE 0x10 3097 field BRKADRINTEN 0x08 3098 field STEP 0x04 3099 field SEQRESET 0x02 3100 field LOADRAM 0x01 3101} 3102 3103/* 3104 * Sequencer Control 1 3105 * Instruction RAM Diagnostics 3106 */ 3107register SEQCTL1 { 3108 address 0x0D7 3109 access_mode RW 3110 field OVRLAY_DATA_CHK 0x08 3111 field RAMBIST_DONE 0x04 3112 field RAMBIST_FAIL 0x02 3113 field RAMBIST_EN 0x01 3114} 3115 3116/* 3117 * Sequencer Flags 3118 * Zero and Carry state of the ALU. 3119 */ 3120register FLAGS { 3121 address 0x0D8 3122 access_mode RO 3123 field ZERO 0x02 3124 field CARRY 0x01 3125} 3126 3127/* 3128 * Sequencer Interrupt Control 3129 */ 3130register SEQINTCTL { 3131 address 0x0D9 3132 access_mode RW 3133 field INTVEC1DSL 0x80 3134 field INT1_CONTEXT 0x20 3135 field SCS_SEQ_INT1M1 0x10 3136 field SCS_SEQ_INT1M0 0x08 3137 field INTMASK 0x06 3138 field IRET 0x01 3139} 3140 3141/* 3142 * Sequencer RAM Data Port 3143 * Single byte window into the Sequencer Instruction Ram area starting 3144 * at the address specified by OVLYADDR. To write a full instruction word, 3145 * simply write four bytes in succession. OVLYADDR will increment after the 3146 * most significant instrution byte (the byte with the parity bit) is written. 3147 */ 3148register SEQRAM { 3149 address 0x0DA 3150 access_mode RW 3151} 3152 3153/* 3154 * Sequencer Program Counter 3155 * Low byte must be written prior to high byte. 3156 */ 3157register PRGMCNT { 3158 address 0x0DE 3159 access_mode RW 3160 size 2 3161} 3162 3163/* 3164 * Accumulator 3165 */ 3166register ACCUM { 3167 address 0x0E0 3168 access_mode RW 3169 accumulator 3170} 3171 3172/* 3173 * Source Index Register 3174 * Incrementing index for reads of SINDIR and the destination (low byte only) 3175 * for any immediate operands passed in jmp, jc, jnc, call instructions. 3176 * Example: 3177 * mvi 0xFF call some_routine; 3178 * 3179 * Will set SINDEX[0] to 0xFF and call the routine "some_routine. 3180 */ 3181register SINDEX { 3182 address 0x0E2 3183 access_mode RW 3184 size 2 3185 sindex 3186} 3187 3188/* 3189 * Destination Index Register 3190 * Incrementing index for writes to DINDIR. Can be used as a scratch register. 3191 */ 3192register DINDEX { 3193 address 0x0E4 3194 access_mode RW 3195 size 2 3196} 3197 3198/* 3199 * Break Address 3200 * Sequencer instruction breakpoint address address. 3201 */ 3202register BRKADDR0 { 3203 address 0x0E6 3204 access_mode RW 3205} 3206 3207register BRKADDR1 { 3208 address 0x0E6 3209 access_mode RW 3210 field BRKDIS 0x80 /* Disable Breakpoint */ 3211} 3212 3213/* 3214 * All Ones 3215 * All reads to this register return the value 0xFF. 3216 */ 3217register ALLONES { 3218 address 0x0E8 3219 access_mode RO 3220 allones 3221} 3222 3223/* 3224 * All Zeros 3225 * All reads to this register return the value 0. 3226 */ 3227register ALLZEROS { 3228 address 0x0EA 3229 access_mode RO 3230 allzeros 3231} 3232 3233/* 3234 * No Destination 3235 * Writes to this register have no effect. 3236 */ 3237register NONE { 3238 address 0x0EA 3239 access_mode WO 3240 none 3241} 3242 3243/* 3244 * Source Index Indirect 3245 * Reading this register is equivalent to reading (register_base + SINDEX) and 3246 * incrementing SINDEX by 1. 3247 */ 3248register SINDIR { 3249 address 0x0EC 3250 access_mode RO 3251} 3252 3253/* 3254 * Destination Index Indirect 3255 * Writing this register is equivalent to writing to (register_base + DINDEX) 3256 * and incrementing DINDEX by 1. 3257 */ 3258register DINDIR { 3259 address 0x0ED 3260 access_mode WO 3261} 3262 3263/* 3264 * Function One 3265 * 2's complement to bit value conversion. Write the 2's complement value 3266 * (0-7 only) to the top nibble and retrieve the bit indexed by that value 3267 * on the next read of this register. 3268 * Example: 3269 * Write 0x60 3270 * Read 0x40 3271 */ 3272register FUNCTION1 { 3273 address 0x0F0 3274 access_mode RW 3275} 3276 3277/* 3278 * Stack 3279 * Window into the stack. Each stack location is 10 bits wide reported 3280 * low byte followed by high byte. There are 8 stack locations. 3281 */ 3282register STACK { 3283 address 0x0F2 3284 access_mode RW 3285} 3286 3287/* 3288 * Interrupt Vector 1 Address 3289 * Interrupt branch address for SCS SEQ_INT1 mode 0 and 1 interrupts. 3290 */ 3291register INTVEC1_ADDR { 3292 address 0x0F4 3293 access_mode RW 3294 size 2 3295 modes M_CFG 3296} 3297 3298/* 3299 * Current Address 3300 * Address of the SEQRAM instruction currently executing instruction. 3301 */ 3302register CURADDR { 3303 address 0x0F4 3304 access_mode RW 3305 size 2 3306 modes M_SCSI 3307} 3308 3309/* 3310 * Interrupt Vector 2 Address 3311 * Interrupt branch address for HST_SEQ_INT2 interrupts. 3312 */ 3313register INTVEC2_ADDR { 3314 address 0x0F6 3315 access_mode RW 3316 size 2 3317 modes M_CFG 3318} 3319 3320/* 3321 * Last Address 3322 * Address of the SEQRAM instruction executed prior to the current instruction. 3323 */ 3324register LASTADDR { 3325 address 0x0F6 3326 access_mode RW 3327 size 2 3328 modes M_SCSI 3329} 3330 3331register AHD_PCI_CONFIG_BASE { 3332 address 0x100 3333 access_mode RW 3334 size 256 3335 modes M_CFG 3336} 3337 3338/* ---------------------- Scratch RAM Offsets ------------------------- */ 3339scratch_ram { 3340 /* Mode Specific */ 3341 address 0x0A0 3342 size 8 3343 modes 0, 1, 2, 3 3344 REG0 { 3345 size 2 3346 } 3347 REG1 { 3348 size 2 3349 } 3350 REG2 { 3351 size 2 3352 } 3353 SG_STATE { 3354 size 1 3355 field SEGS_AVAIL 0x01 3356 field LOADING_NEEDED 0x02 3357 field FETCH_INPROG 0x04 3358 } 3359 /* 3360 * Track whether the transfer byte count for 3361 * the current data phase is odd. 3362 */ 3363 DATA_COUNT_ODD { 3364 size 1 3365 } 3366} 3367 3368scratch_ram { 3369 /* Mode Specific */ 3370 address 0x0F8 3371 size 8 3372 modes 0, 1, 2, 3 3373 LONGJMP_ADDR { 3374 size 2 3375 } 3376 LONGJMP_SCB { 3377 size 2 3378 } 3379 ACCUM_SAVE { 3380 size 1 3381 } 3382} 3383 3384 3385scratch_ram { 3386 address 0x100 3387 size 128 3388 modes 0, 1, 2, 3 3389 /* 3390 * Per "other-id" execution queues. We use an array of 3391 * tail pointers into lists of SCBs sorted by "other-id". 3392 * The execution head pointer threads the head SCBs for 3393 * each list. 3394 */ 3395 WAITING_SCB_TAILS { 3396 size 32 3397 } 3398 WAITING_TID_HEAD { 3399 size 2 3400 } 3401 WAITING_TID_TAIL { 3402 size 2 3403 } 3404 /* 3405 * SCBID of the next SCB in the new SCB queue. 3406 */ 3407 NEXT_QUEUED_SCB_ADDR { 3408 size 4 3409 } 3410 /* 3411 * head of list of SCBs that have 3412 * completed but have not been 3413 * put into the qoutfifo. 3414 */ 3415 COMPLETE_SCB_HEAD { 3416 size 2 3417 } 3418 /* 3419 * The list of completed SCBs in 3420 * the active DMA. 3421 */ 3422 COMPLETE_SCB_DMAINPROG_HEAD { 3423 size 2 3424 } 3425 /* 3426 * head of list of SCBs that have 3427 * completed but need to be uploaded 3428 * to the host prior to being completed. 3429 */ 3430 COMPLETE_DMA_SCB_HEAD { 3431 size 2 3432 } 3433 /* Counting semaphore to prevent new select-outs */ 3434 QFREEZE_COUNT { 3435 size 2 3436 } 3437 /* 3438 * Mode to restore on idle_loop exit. 3439 */ 3440 SAVED_MODE { 3441 size 1 3442 } 3443 /* 3444 * Single byte buffer used to designate the type or message 3445 * to send to a target. 3446 */ 3447 MSG_OUT { 3448 size 1 3449 } 3450 /* Parameters for DMA Logic */ 3451 DMAPARAMS { 3452 size 1 3453 field PRELOADEN 0x80 3454 field WIDEODD 0x40 3455 field SCSIEN 0x20 3456 field SDMAEN 0x10 3457 field SDMAENACK 0x10 3458 field HDMAEN 0x08 3459 field HDMAENACK 0x08 3460 field DIRECTION 0x04 /* Set indicates PCI->SCSI */ 3461 field FIFOFLUSH 0x02 3462 field FIFORESET 0x01 3463 } 3464 SEQ_FLAGS { 3465 size 1 3466 field NOT_IDENTIFIED 0x80 3467 field TARGET_CMD_IS_TAGGED 0x40 3468 field NO_CDB_SENT 0x40 3469 field DPHASE 0x20 3470 /* Target flags */ 3471 field TARG_CMD_PENDING 0x10 3472 field CMDPHASE_PENDING 0x08 3473 field DPHASE_PENDING 0x04 3474 field SPHASE_PENDING 0x02 3475 field NO_DISCONNECT 0x01 3476 } 3477 /* 3478 * Temporary storage for the 3479 * target/channel/lun of a 3480 * reconnecting target 3481 */ 3482 SAVED_SCSIID { 3483 size 1 3484 } 3485 SAVED_LUN { 3486 size 1 3487 } 3488 /* 3489 * The last bus phase as seen by the sequencer. 3490 */ 3491 LASTPHASE { 3492 size 1 3493 field CDI 0x80 3494 field IOI 0x40 3495 field MSGI 0x20 3496 enum PHASE_MASK CDO|IOO|MSGO { 3497 P_DATAOUT 0x0, 3498 P_DATAIN IOO, 3499 P_DATAOUT_DT P_DATAOUT|MSGO, 3500 P_DATAIN_DT P_DATAIN|MSGO, 3501 P_COMMAND CDO, 3502 P_MESGOUT CDO|MSGO, 3503 P_STATUS CDO|IOO, 3504 P_MESGIN CDO|IOO|MSGO, 3505 P_BUSFREE 0x01 3506 } 3507 } 3508 /* 3509 * Base address of our shared data with the kernel driver in host 3510 * memory. This includes the qoutfifo and target mode 3511 * incoming command queue. 3512 */ 3513 SHARED_DATA_ADDR { 3514 size 4 3515 } 3516 /* 3517 * Pointer to location in host memory for next 3518 * position in the qoutfifo. 3519 */ 3520 QOUTFIFO_NEXT_ADDR { 3521 size 4 3522 } 3523 /* 3524 * Value to "or" into the SCBPTR[1] value to 3525 * indicate that an entry in the QINFIFO is valid. 3526 */ 3527 QOUTFIFO_ENTRY_VALID_TAG { 3528 size 1 3529 } 3530 /* 3531 * Kernel and sequencer offsets into the queue of 3532 * incoming target mode command descriptors. The 3533 * queue is full when the KERNEL_TQINPOS == TQINPOS. 3534 */ 3535 KERNEL_TQINPOS { 3536 size 1 3537 } 3538 TQINPOS { 3539 size 1 3540 } 3541 ARG_1 { 3542 size 1 3543 mask SEND_MSG 0x80 3544 mask SEND_SENSE 0x40 3545 mask SEND_REJ 0x20 3546 mask MSGOUT_PHASEMIS 0x10 3547 mask EXIT_MSG_LOOP 0x08 3548 mask CONT_MSG_LOOP_WRITE 0x04 3549 mask CONT_MSG_LOOP_READ 0x03 3550 mask CONT_MSG_LOOP_TARG 0x02 3551 alias RETURN_1 3552 } 3553 ARG_2 { 3554 size 1 3555 alias RETURN_2 3556 } 3557 3558 /* 3559 * Snapshot of MSG_OUT taken after each message is sent. 3560 */ 3561 LAST_MSG { 3562 size 1 3563 } 3564 3565 /* 3566 * Sequences the kernel driver has okayed for us. This allows 3567 * the driver to do things like prevent initiator or target 3568 * operations. 3569 */ 3570 SCSISEQ_TEMPLATE { 3571 size 1 3572 field MANUALCTL 0x40 3573 field ENSELI 0x20 3574 field ENRSELI 0x10 3575 field MANUALP 0x0C 3576 field ENAUTOATNP 0x02 3577 field ALTSTIM 0x01 3578 } 3579 3580 /* 3581 * The initiator specified tag for this target mode transaction. 3582 */ 3583 INITIATOR_TAG { 3584 size 1 3585 } 3586 3587 SEQ_FLAGS2 { 3588 size 1 3589 field SCB_DMA 0x01 3590 field TARGET_MSG_PENDING 0x02 3591 field SELECTOUT_QFROZEN 0x04 3592 } 3593 /* 3594 * Target-mode CDB type to CDB length table used 3595 * in non-packetized operation. 3596 */ 3597 CMDSIZE_TABLE { 3598 size 8 3599 } 3600} 3601 3602/************************* Hardware SCB Definition ****************************/ 3603scb { 3604 address 0x180 3605 size 64 3606 modes 0, 1, 2, 3 3607 SCB_RESIDUAL_DATACNT { 3608 size 4 3609 alias SCB_CDB_STORE 3610 } 3611 SCB_RESIDUAL_SGPTR { 3612 size 4 3613 alias SCB_CDB_PTR 3614 field SG_ADDR_MASK 0xf8 /* In the last byte */ 3615 field SG_OVERRUN_RESID 0x02 /* In the first byte */ 3616 field SG_LIST_NULL 0x01 /* In the first byte */ 3617 } 3618 SCB_SCSI_STATUS { 3619 size 1 3620 } 3621 SCB_TARGET_PHASES { 3622 size 1 3623 } 3624 SCB_TARGET_DATA_DIR { 3625 size 1 3626 } 3627 SCB_TARGET_ITAG { 3628 size 1 3629 } 3630 SCB_SENSE_BUSADDR { 3631 /* 3632 * Only valid if CDB length is less than 13 bytes or 3633 * we are using a CDB pointer. Otherwise contains 3634 * the last 4 bytes of embedded cdb information. 3635 */ 3636 size 4 3637 alias SCB_NEXT_COMPLETE 3638 } 3639 SCB_CDB_LEN { 3640 size 1 3641 field SCB_CDB_LEN_PTR 0x80 /* CDB in host memory */ 3642 } 3643 SCB_TASK_MANAGEMENT { 3644 size 1 3645 } 3646 SCB_TAG { 3647 size 2 3648 } 3649 SCB_NEXT { 3650 alias SCB_NEXT_SCB_BUSADDR 3651 size 2 3652 } 3653 SCB_NEXT2 { 3654 size 2 3655 } 3656 SCB_DATAPTR { 3657 size 8 3658 } 3659 SCB_DATACNT { 3660 /* 3661 * The last byte is really the high address bits for 3662 * the data address. 3663 */ 3664 size 4 3665 field SG_LAST_SEG 0x80 /* In the fourth byte */ 3666 field SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */ 3667 } 3668 SCB_SGPTR { 3669 size 4 3670 field SG_STATUS_VALID 0x04 /* In the first byte */ 3671 field SG_FULL_RESID 0x02 /* In the first byte */ 3672 field SG_LIST_NULL 0x01 /* In the first byte */ 3673 } 3674 SCB_CONTROL { 3675 size 1 3676 field TARGET_SCB 0x80 3677 field DISCENB 0x40 3678 field TAG_ENB 0x20 3679 field MK_MESSAGE 0x10 3680 field STATUS_RCVD 0x08 3681 field DISCONNECTED 0x04 3682 field SCB_TAG_TYPE 0x03 3683 } 3684 SCB_SCSIID { 3685 size 1 3686 field TID 0xF0 3687 field OID 0x0F 3688 } 3689 SCB_LUN { 3690 size 1 3691 field LID 0xff 3692 } 3693 SCB_TASK_ATTRIBUTE { 3694 size 1 3695 } 3696 SCB_BUSADDR { 3697 size 4 3698 } 3699 SCB_SPARE { 3700 size 8 3701 alias SCB_PKT_LUN 3702 } 3703 SCB_DISCONNECTED_LISTS { 3704 size 8 3705 } 3706} 3707 3708/*********************************** Constants ********************************/ 3709const SEQ_STACK_SIZE 8 3710const MK_MESSAGE_BIT_OFFSET 4 3711const TID_SHIFT 4 3712const TARGET_CMD_CMPLT 0xfe 3713const INVALID_ADDR 0x80 3714#define SCB_LIST_NULL 0xff 3715#define QOUTFIFO_ENTRY_VALID_TOGGLE 0x80 3716 3717const CCSGADDR_MAX 0x80 3718const CCSCBADDR_MAX 0x80 3719const CCSGRAM_MAXSEGS 16 3720 3721/* Selection Timeout Timer Constants */ 3722const STIMESEL_SHIFT 3 3723const STIMESEL_MIN 0x18 3724const STIMESEL_BUG_ADJ 0x8 3725 3726/* WDTR Message values */ 3727const BUS_8_BIT 0x00 3728const BUS_16_BIT 0x01 3729const BUS_32_BIT 0x02 3730 3731/* Offset maximums */ 3732const MAX_OFFSET 0xfe 3733const MAX_OFFSET_PACED 0x7f 3734const HOST_MSG 0xff 3735 3736/* 3737 * The size of our sense buffers. 3738 * Sense buffer mapping can be handled in either of two ways. 3739 * The first is to allocate a dmamap for each transaction. 3740 * Depending on the architecture, dmamaps can be costly. The 3741 * alternative is to statically map the buffers in much the same 3742 * way we handle our scatter gather lists. The driver implements 3743 * the later. 3744 */ 3745const AHD_SENSE_BUFSIZE 256 3746 3747/* Target mode command processing constants */ 3748const CMD_GROUP_CODE_SHIFT 0x05 3749 3750const STATUS_BUSY 0x08 3751const STATUS_QUEUE_FULL 0x28 3752const STATUS_PKT_SENSE 0xFF 3753const TARGET_DATA_IN 1 3754 3755const SCB_TRANSFER_SIZE_FULL_LUN 56 3756const SCB_TRANSFER_SIZE_1BYTE_LUN 48 3757/* PKT_OVERRUN_BUFSIZE must be a multiple of 256 less than 64K */ 3758const PKT_OVERRUN_BUFSIZE 512 3759 3760/* 3761 * Downloaded (kernel inserted) constants 3762 */ 3763const SG_PREFETCH_CNT download 3764const SG_PREFETCH_CNT_LIMIT download 3765const SG_PREFETCH_ALIGN_MASK download 3766const SG_PREFETCH_ADDR_MASK download 3767const SG_SIZEOF download 3768const PKT_OVERRUN_BUFOFFSET download 3769const SCB_TRANSFER_SIZE download 3770 3771/* 3772 * BIOS SCB offsets 3773 */ 3774const NVRAM_SCB_OFFSET 0x2C 3775