ahci_pci.c revision 256843
1/*- 2 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/ahci/ahci.c 256843 2013-10-21 12:00:26Z mav $"); 29 30#include <sys/param.h> 31#include <sys/module.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/bus.h> 35#include <sys/conf.h> 36#include <sys/endian.h> 37#include <sys/malloc.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40#include <machine/stdarg.h> 41#include <machine/resource.h> 42#include <machine/bus.h> 43#include <sys/rman.h> 44#include <dev/pci/pcivar.h> 45#include <dev/pci/pcireg.h> 46#include "ahci.h" 47 48#include <cam/cam.h> 49#include <cam/cam_ccb.h> 50#include <cam/cam_sim.h> 51#include <cam/cam_xpt_sim.h> 52#include <cam/cam_debug.h> 53 54/* local prototypes */ 55static int ahci_setup_interrupt(device_t dev); 56static void ahci_intr(void *data); 57static void ahci_intr_one(void *data); 58static void ahci_intr_one_edge(void *data); 59static int ahci_suspend(device_t dev); 60static int ahci_resume(device_t dev); 61static int ahci_ch_init(device_t dev); 62static int ahci_ch_deinit(device_t dev); 63static int ahci_ch_suspend(device_t dev); 64static int ahci_ch_resume(device_t dev); 65static void ahci_ch_pm(void *arg); 66static void ahci_ch_intr(void *arg); 67static void ahci_ch_intr_direct(void *arg); 68static void ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus); 69static int ahci_ctlr_reset(device_t dev); 70static int ahci_ctlr_setup(device_t dev); 71static void ahci_begin_transaction(device_t dev, union ccb *ccb); 72static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 73static void ahci_execute_transaction(struct ahci_slot *slot); 74static void ahci_timeout(struct ahci_slot *slot); 75static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 76static int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 77static void ahci_dmainit(device_t dev); 78static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 79static void ahci_dmafini(device_t dev); 80static void ahci_slotsalloc(device_t dev); 81static void ahci_slotsfree(device_t dev); 82static void ahci_reset(device_t dev); 83static void ahci_start(device_t dev, int fbs); 84static void ahci_stop(device_t dev); 85static void ahci_clo(device_t dev); 86static void ahci_start_fr(device_t dev); 87static void ahci_stop_fr(device_t dev); 88 89static int ahci_sata_connect(struct ahci_channel *ch); 90static int ahci_sata_phy_reset(device_t dev); 91static int ahci_wait_ready(device_t dev, int t, int t0); 92 93static void ahci_issue_recovery(device_t dev); 94static void ahci_process_read_log(device_t dev, union ccb *ccb); 95static void ahci_process_request_sense(device_t dev, union ccb *ccb); 96 97static void ahciaction(struct cam_sim *sim, union ccb *ccb); 98static void ahcipoll(struct cam_sim *sim); 99 100static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 101 102static struct { 103 uint32_t id; 104 uint8_t rev; 105 const char *name; 106 int quirks; 107#define AHCI_Q_NOFORCE 1 108#define AHCI_Q_NOPMP 2 109#define AHCI_Q_NONCQ 4 110#define AHCI_Q_1CH 8 111#define AHCI_Q_2CH 16 112#define AHCI_Q_4CH 32 113#define AHCI_Q_EDGEIS 64 114#define AHCI_Q_SATA2 128 115#define AHCI_Q_NOBSYRES 256 116#define AHCI_Q_NOAA 512 117#define AHCI_Q_NOCOUNT 1024 118#define AHCI_Q_ALTSIG 2048 119#define AHCI_Q_NOMSI 4096 120 121#define AHCI_Q_BIT_STRING \ 122 "\020" \ 123 "\001NOFORCE" \ 124 "\002NOPMP" \ 125 "\003NONCQ" \ 126 "\0041CH" \ 127 "\0052CH" \ 128 "\0064CH" \ 129 "\007EDGEIS" \ 130 "\010SATA2" \ 131 "\011NOBSYRES" \ 132 "\012NOAA" \ 133 "\013NOCOUNT" \ 134 "\014ALTSIG" \ 135 "\015NOMSI" 136} ahci_ids[] = { 137 {0x43801002, 0x00, "ATI IXP600", AHCI_Q_NOMSI}, 138 {0x43901002, 0x00, "ATI IXP700", 0}, 139 {0x43911002, 0x00, "ATI IXP700", 0}, 140 {0x43921002, 0x00, "ATI IXP700", 0}, 141 {0x43931002, 0x00, "ATI IXP700", 0}, 142 {0x43941002, 0x00, "ATI IXP800", 0}, 143 {0x43951002, 0x00, "ATI IXP800", 0}, 144 {0x78001022, 0x00, "AMD Hudson-2", 0}, 145 {0x78011022, 0x00, "AMD Hudson-2", 0}, 146 {0x78021022, 0x00, "AMD Hudson-2", 0}, 147 {0x78031022, 0x00, "AMD Hudson-2", 0}, 148 {0x78041022, 0x00, "AMD Hudson-2", 0}, 149 {0x06121b21, 0x00, "ASMedia ASM1061", 0}, 150 {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE}, 151 {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE}, 152 {0x26818086, 0x00, "Intel ESB2", 0}, 153 {0x26828086, 0x00, "Intel ESB2", 0}, 154 {0x26838086, 0x00, "Intel ESB2", 0}, 155 {0x27c18086, 0x00, "Intel ICH7", 0}, 156 {0x27c38086, 0x00, "Intel ICH7", 0}, 157 {0x27c58086, 0x00, "Intel ICH7M", 0}, 158 {0x27c68086, 0x00, "Intel ICH7M", 0}, 159 {0x28218086, 0x00, "Intel ICH8", 0}, 160 {0x28228086, 0x00, "Intel ICH8", 0}, 161 {0x28248086, 0x00, "Intel ICH8", 0}, 162 {0x28298086, 0x00, "Intel ICH8M", 0}, 163 {0x282a8086, 0x00, "Intel ICH8M", 0}, 164 {0x29228086, 0x00, "Intel ICH9", 0}, 165 {0x29238086, 0x00, "Intel ICH9", 0}, 166 {0x29248086, 0x00, "Intel ICH9", 0}, 167 {0x29258086, 0x00, "Intel ICH9", 0}, 168 {0x29278086, 0x00, "Intel ICH9", 0}, 169 {0x29298086, 0x00, "Intel ICH9M", 0}, 170 {0x292a8086, 0x00, "Intel ICH9M", 0}, 171 {0x292b8086, 0x00, "Intel ICH9M", 0}, 172 {0x292c8086, 0x00, "Intel ICH9M", 0}, 173 {0x292f8086, 0x00, "Intel ICH9M", 0}, 174 {0x294d8086, 0x00, "Intel ICH9", 0}, 175 {0x294e8086, 0x00, "Intel ICH9M", 0}, 176 {0x3a058086, 0x00, "Intel ICH10", 0}, 177 {0x3a228086, 0x00, "Intel ICH10", 0}, 178 {0x3a258086, 0x00, "Intel ICH10", 0}, 179 {0x3b228086, 0x00, "Intel 5 Series/3400 Series", 0}, 180 {0x3b238086, 0x00, "Intel 5 Series/3400 Series", 0}, 181 {0x3b258086, 0x00, "Intel 5 Series/3400 Series", 0}, 182 {0x3b298086, 0x00, "Intel 5 Series/3400 Series", 0}, 183 {0x3b2c8086, 0x00, "Intel 5 Series/3400 Series", 0}, 184 {0x3b2f8086, 0x00, "Intel 5 Series/3400 Series", 0}, 185 {0x1c028086, 0x00, "Intel Cougar Point", 0}, 186 {0x1c038086, 0x00, "Intel Cougar Point", 0}, 187 {0x1c048086, 0x00, "Intel Cougar Point", 0}, 188 {0x1c058086, 0x00, "Intel Cougar Point", 0}, 189 {0x1d028086, 0x00, "Intel Patsburg", 0}, 190 {0x1d048086, 0x00, "Intel Patsburg", 0}, 191 {0x1d068086, 0x00, "Intel Patsburg", 0}, 192 {0x28268086, 0x00, "Intel Patsburg (RAID)", 0}, 193 {0x1e028086, 0x00, "Intel Panther Point", 0}, 194 {0x1e038086, 0x00, "Intel Panther Point", 0}, 195 {0x1e048086, 0x00, "Intel Panther Point", 0}, 196 {0x1e058086, 0x00, "Intel Panther Point", 0}, 197 {0x1e068086, 0x00, "Intel Panther Point", 0}, 198 {0x1e078086, 0x00, "Intel Panther Point", 0}, 199 {0x1e0e8086, 0x00, "Intel Panther Point", 0}, 200 {0x1e0f8086, 0x00, "Intel Panther Point", 0}, 201 {0x23a38086, 0x00, "Intel Coleto Creek", 0}, 202 {0x8c028086, 0x00, "Intel Lynx Point", 0}, 203 {0x8c038086, 0x00, "Intel Lynx Point", 0}, 204 {0x8c048086, 0x00, "Intel Lynx Point", 0}, 205 {0x8c058086, 0x00, "Intel Lynx Point", 0}, 206 {0x8c068086, 0x00, "Intel Lynx Point", 0}, 207 {0x8c078086, 0x00, "Intel Lynx Point", 0}, 208 {0x8c0e8086, 0x00, "Intel Lynx Point", 0}, 209 {0x8c0f8086, 0x00, "Intel Lynx Point", 0}, 210 {0x23238086, 0x00, "Intel DH89xxCC", 0}, 211 {0x2360197b, 0x00, "JMicron JMB360", 0}, 212 {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE}, 213 {0x2362197b, 0x00, "JMicron JMB362", 0}, 214 {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE}, 215 {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE}, 216 {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE}, 217 {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE}, 218 {0x611111ab, 0x00, "Marvell 88SE6111", AHCI_Q_NOFORCE | AHCI_Q_1CH | 219 AHCI_Q_EDGEIS}, 220 {0x612111ab, 0x00, "Marvell 88SE6121", AHCI_Q_NOFORCE | AHCI_Q_2CH | 221 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 222 {0x614111ab, 0x00, "Marvell 88SE6141", AHCI_Q_NOFORCE | AHCI_Q_4CH | 223 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 224 {0x614511ab, 0x00, "Marvell 88SE6145", AHCI_Q_NOFORCE | AHCI_Q_4CH | 225 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 226 {0x91201b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_NOBSYRES}, 227 {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 228 {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2|AHCI_Q_NOBSYRES}, 229 {0x91251b4b, 0x00, "Marvell 88SE9125", AHCI_Q_NOBSYRES}, 230 {0x91281b4b, 0x00, "Marvell 88SE9128", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 231 {0x91301b4b, 0x00, "Marvell 88SE9130", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 232 {0x91721b4b, 0x00, "Marvell 88SE9172", AHCI_Q_NOBSYRES}, 233 {0x91821b4b, 0x00, "Marvell 88SE9182", AHCI_Q_NOBSYRES}, 234 {0x91831b4b, 0x00, "Marvell 88SS9183", AHCI_Q_NOBSYRES}, 235 {0x91a01b4b, 0x00, "Marvell 88SE91Ax", AHCI_Q_NOBSYRES}, 236 {0x92151b4b, 0x00, "Marvell 88SE9215", AHCI_Q_NOBSYRES}, 237 {0x92201b4b, 0x00, "Marvell 88SE9220", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 238 {0x92301b4b, 0x00, "Marvell 88SE9230", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 239 {0x92351b4b, 0x00, "Marvell 88SE9235", AHCI_Q_NOBSYRES}, 240 {0x06201103, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES}, 241 {0x06201b4b, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES}, 242 {0x06221103, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES}, 243 {0x06221b4b, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES}, 244 {0x06401103, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES}, 245 {0x06401b4b, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES}, 246 {0x06441103, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES}, 247 {0x06441b4b, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES}, 248 {0x06411103, 0x00, "HighPoint RocketRAID 640L", AHCI_Q_NOBSYRES}, 249 {0x06421103, 0x00, "HighPoint RocketRAID 642L", AHCI_Q_NOBSYRES}, 250 {0x06451103, 0x00, "HighPoint RocketRAID 644L", AHCI_Q_NOBSYRES}, 251 {0x044c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 252 {0x044d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 253 {0x044e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 254 {0x044f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 255 {0x045c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 256 {0x045d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 257 {0x045e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 258 {0x045f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 259 {0x055010de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 260 {0x055110de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 261 {0x055210de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 262 {0x055310de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 263 {0x055410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 264 {0x055510de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 265 {0x055610de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 266 {0x055710de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 267 {0x055810de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 268 {0x055910de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 269 {0x055A10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 270 {0x055B10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 271 {0x058410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 272 {0x07f010de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 273 {0x07f110de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 274 {0x07f210de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 275 {0x07f310de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 276 {0x07f410de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 277 {0x07f510de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 278 {0x07f610de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 279 {0x07f710de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 280 {0x07f810de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 281 {0x07f910de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 282 {0x07fa10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 283 {0x07fb10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 284 {0x0ad010de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 285 {0x0ad110de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 286 {0x0ad210de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 287 {0x0ad310de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 288 {0x0ad410de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 289 {0x0ad510de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 290 {0x0ad610de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 291 {0x0ad710de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 292 {0x0ad810de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 293 {0x0ad910de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 294 {0x0ada10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 295 {0x0adb10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 296 {0x0ab410de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 297 {0x0ab510de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 298 {0x0ab610de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 299 {0x0ab710de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 300 {0x0ab810de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 301 {0x0ab910de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 302 {0x0aba10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 303 {0x0abb10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 304 {0x0abc10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 305 {0x0abd10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 306 {0x0abe10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 307 {0x0abf10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 308 {0x0d8410de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 309 {0x0d8510de, 0x00, "NVIDIA MCP89", AHCI_Q_NOFORCE|AHCI_Q_NOAA}, 310 {0x0d8610de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 311 {0x0d8710de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 312 {0x0d8810de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 313 {0x0d8910de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 314 {0x0d8a10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 315 {0x0d8b10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 316 {0x0d8c10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 317 {0x0d8d10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 318 {0x0d8e10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 319 {0x0d8f10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 320 {0x33491106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 321 {0x62871106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 322 {0x11841039, 0x00, "SiS 966", 0}, 323 {0x11851039, 0x00, "SiS 968", 0}, 324 {0x01861039, 0x00, "SiS 968", 0}, 325 {0x00000000, 0x00, NULL, 0} 326}; 327 328#define recovery_type spriv_field0 329#define RECOVERY_NONE 0 330#define RECOVERY_READ_LOG 1 331#define RECOVERY_REQUEST_SENSE 2 332#define recovery_slot spriv_field1 333 334static int force_ahci = 1; 335TUNABLE_INT("hw.ahci.force", &force_ahci); 336 337static int 338ahci_probe(device_t dev) 339{ 340 char buf[64]; 341 int i, valid = 0; 342 uint32_t devid = pci_get_devid(dev); 343 uint8_t revid = pci_get_revid(dev); 344 345 /* Is this a possible AHCI candidate? */ 346 if (pci_get_class(dev) == PCIC_STORAGE && 347 pci_get_subclass(dev) == PCIS_STORAGE_SATA && 348 pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0) 349 valid = 1; 350 /* Is this a known AHCI chip? */ 351 for (i = 0; ahci_ids[i].id != 0; i++) { 352 if (ahci_ids[i].id == devid && 353 ahci_ids[i].rev <= revid && 354 (valid || (force_ahci == 1 && 355 !(ahci_ids[i].quirks & AHCI_Q_NOFORCE)))) { 356 /* Do not attach JMicrons with single PCI function. */ 357 if (pci_get_vendor(dev) == 0x197b && 358 (pci_read_config(dev, 0xdf, 1) & 0x40) == 0) 359 return (ENXIO); 360 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 361 ahci_ids[i].name); 362 device_set_desc_copy(dev, buf); 363 return (BUS_PROBE_VENDOR); 364 } 365 } 366 if (!valid) 367 return (ENXIO); 368 device_set_desc_copy(dev, "AHCI SATA controller"); 369 return (BUS_PROBE_VENDOR); 370} 371 372static int 373ahci_ata_probe(device_t dev) 374{ 375 char buf[64]; 376 int i; 377 uint32_t devid = pci_get_devid(dev); 378 uint8_t revid = pci_get_revid(dev); 379 380 if ((intptr_t)device_get_ivars(dev) >= 0) 381 return (ENXIO); 382 /* Is this a known AHCI chip? */ 383 for (i = 0; ahci_ids[i].id != 0; i++) { 384 if (ahci_ids[i].id == devid && 385 ahci_ids[i].rev <= revid) { 386 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 387 ahci_ids[i].name); 388 device_set_desc_copy(dev, buf); 389 return (BUS_PROBE_VENDOR); 390 } 391 } 392 device_set_desc_copy(dev, "AHCI SATA controller"); 393 return (BUS_PROBE_VENDOR); 394} 395 396static int 397ahci_attach(device_t dev) 398{ 399 struct ahci_controller *ctlr = device_get_softc(dev); 400 device_t child; 401 int error, unit, speed, i; 402 u_int u; 403 uint32_t devid = pci_get_devid(dev); 404 uint8_t revid = pci_get_revid(dev); 405 u_int32_t version; 406 407 ctlr->dev = dev; 408 i = 0; 409 while (ahci_ids[i].id != 0 && 410 (ahci_ids[i].id != devid || 411 ahci_ids[i].rev > revid)) 412 i++; 413 ctlr->quirks = ahci_ids[i].quirks; 414 resource_int_value(device_get_name(dev), 415 device_get_unit(dev), "ccc", &ctlr->ccc); 416 /* if we have a memory BAR(5) we are likely on an AHCI part */ 417 ctlr->r_rid = PCIR_BAR(5); 418 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 419 &ctlr->r_rid, RF_ACTIVE))) 420 return ENXIO; 421 /* Setup our own memory management for channels. */ 422 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 423 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 424 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 425 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 426 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 427 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 428 return (error); 429 } 430 if ((error = rman_manage_region(&ctlr->sc_iomem, 431 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 432 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 433 rman_fini(&ctlr->sc_iomem); 434 return (error); 435 } 436 pci_enable_busmaster(dev); 437 /* Reset controller */ 438 if ((error = ahci_ctlr_reset(dev)) != 0) { 439 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 440 rman_fini(&ctlr->sc_iomem); 441 return (error); 442 }; 443 /* Get the HW capabilities */ 444 version = ATA_INL(ctlr->r_mem, AHCI_VS); 445 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 446 if (version >= 0x00010200) 447 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 448 if (ctlr->caps & AHCI_CAP_EMS) 449 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL); 450 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 451 452 /* Identify and set separate quirks for HBA and RAID f/w Marvells. */ 453 if ((ctlr->quirks & AHCI_Q_NOBSYRES) && 454 (ctlr->quirks & AHCI_Q_ALTSIG) && 455 (ctlr->caps & AHCI_CAP_SPM) == 0) 456 ctlr->quirks &= ~AHCI_Q_NOBSYRES; 457 458 if (ctlr->quirks & AHCI_Q_1CH) { 459 ctlr->caps &= ~AHCI_CAP_NPMASK; 460 ctlr->ichannels &= 0x01; 461 } 462 if (ctlr->quirks & AHCI_Q_2CH) { 463 ctlr->caps &= ~AHCI_CAP_NPMASK; 464 ctlr->caps |= 1; 465 ctlr->ichannels &= 0x03; 466 } 467 if (ctlr->quirks & AHCI_Q_4CH) { 468 ctlr->caps &= ~AHCI_CAP_NPMASK; 469 ctlr->caps |= 3; 470 ctlr->ichannels &= 0x0f; 471 } 472 ctlr->channels = MAX(flsl(ctlr->ichannels), 473 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 474 if (ctlr->quirks & AHCI_Q_NOPMP) 475 ctlr->caps &= ~AHCI_CAP_SPM; 476 if (ctlr->quirks & AHCI_Q_NONCQ) 477 ctlr->caps &= ~AHCI_CAP_SNCQ; 478 if ((ctlr->caps & AHCI_CAP_CCCS) == 0) 479 ctlr->ccc = 0; 480 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC); 481 482 /* Create controller-wide DMA tag. */ 483 if (bus_dma_tag_create(bus_get_dma_tag(dev), 0, 0, 484 (ctlr->caps & AHCI_CAP_64BIT) ? BUS_SPACE_MAXADDR : 485 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 486 BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, 487 0, NULL, NULL, &ctlr->dma_tag)) { 488 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, 489 ctlr->r_mem); 490 rman_fini(&ctlr->sc_iomem); 491 return ENXIO; 492 } 493 494 ahci_ctlr_setup(dev); 495 /* Setup interrupts. */ 496 if (ahci_setup_interrupt(dev)) { 497 bus_dma_tag_destroy(ctlr->dma_tag); 498 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 499 rman_fini(&ctlr->sc_iomem); 500 return ENXIO; 501 } 502 i = 0; 503 for (u = ctlr->ichannels; u != 0; u >>= 1) 504 i += (u & 1); 505 ctlr->direct = (ctlr->msi && (ctlr->numirqs > 1 || i <= 3)); 506 resource_int_value(device_get_name(dev), device_get_unit(dev), 507 "direct", &ctlr->direct); 508 /* Announce HW capabilities. */ 509 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 510 device_printf(dev, 511 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n", 512 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 513 ((version >> 4) & 0xf0) + (version & 0x0f), 514 (ctlr->caps & AHCI_CAP_NPMASK) + 1, 515 ((speed == 1) ? "1.5":((speed == 2) ? "3": 516 ((speed == 3) ? "6":"?"))), 517 (ctlr->caps & AHCI_CAP_SPM) ? 518 "supported" : "not supported", 519 (ctlr->caps & AHCI_CAP_FBSS) ? 520 " with FBS" : ""); 521 if (ctlr->quirks != 0) { 522 device_printf(dev, "quirks=0x%b\n", ctlr->quirks, 523 AHCI_Q_BIT_STRING); 524 } 525 if (bootverbose) { 526 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 527 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 528 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 529 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 530 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 531 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 532 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 533 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 534 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 535 ((speed == 1) ? "1.5":((speed == 2) ? "3": 536 ((speed == 3) ? "6":"?")))); 537 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 538 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 539 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 540 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 541 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 542 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 543 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 544 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 545 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 546 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 547 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 548 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 549 } 550 if (bootverbose && version >= 0x00010200) { 551 device_printf(dev, "Caps2:%s%s%s%s%s%s\n", 552 (ctlr->caps2 & AHCI_CAP2_DESO) ? " DESO":"", 553 (ctlr->caps2 & AHCI_CAP2_SADM) ? " SADM":"", 554 (ctlr->caps2 & AHCI_CAP2_SDS) ? " SDS":"", 555 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 556 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 557 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 558 } 559 /* Attach all channels on this controller */ 560 for (unit = 0; unit < ctlr->channels; unit++) { 561 child = device_add_child(dev, "ahcich", -1); 562 if (child == NULL) { 563 device_printf(dev, "failed to add channel device\n"); 564 continue; 565 } 566 device_set_ivars(child, (void *)(intptr_t)unit); 567 if ((ctlr->ichannels & (1 << unit)) == 0) 568 device_disable(child); 569 } 570 if (ctlr->caps & AHCI_CAP_EMS) { 571 child = device_add_child(dev, "ahciem", -1); 572 if (child == NULL) 573 device_printf(dev, "failed to add enclosure device\n"); 574 else 575 device_set_ivars(child, (void *)(intptr_t)-1); 576 } 577 bus_generic_attach(dev); 578 return 0; 579} 580 581static int 582ahci_detach(device_t dev) 583{ 584 struct ahci_controller *ctlr = device_get_softc(dev); 585 int i; 586 587 /* Detach & delete all children */ 588 device_delete_children(dev); 589 590 /* Free interrupts. */ 591 for (i = 0; i < ctlr->numirqs; i++) { 592 if (ctlr->irqs[i].r_irq) { 593 bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 594 ctlr->irqs[i].handle); 595 bus_release_resource(dev, SYS_RES_IRQ, 596 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 597 } 598 } 599 pci_release_msi(dev); 600 bus_dma_tag_destroy(ctlr->dma_tag); 601 /* Free memory. */ 602 rman_fini(&ctlr->sc_iomem); 603 if (ctlr->r_mem) 604 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 605 return (0); 606} 607 608static int 609ahci_ctlr_reset(device_t dev) 610{ 611 struct ahci_controller *ctlr = device_get_softc(dev); 612 int timeout; 613 614 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == 0x28298086 && 615 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04) 616 pci_write_config(dev, 0x92, 0x01, 1); 617 /* Enable AHCI mode */ 618 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 619 /* Reset AHCI controller */ 620 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 621 for (timeout = 1000; timeout > 0; timeout--) { 622 DELAY(1000); 623 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 624 break; 625 } 626 if (timeout == 0) { 627 device_printf(dev, "AHCI controller reset failure\n"); 628 return ENXIO; 629 } 630 /* Reenable AHCI mode */ 631 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 632 return (0); 633} 634 635static int 636ahci_ctlr_setup(device_t dev) 637{ 638 struct ahci_controller *ctlr = device_get_softc(dev); 639 /* Clear interrupts */ 640 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 641 /* Configure CCC */ 642 if (ctlr->ccc) { 643 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 644 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 645 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 646 (4 << AHCI_CCCC_CC_SHIFT) | 647 AHCI_CCCC_EN); 648 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 649 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 650 if (bootverbose) { 651 device_printf(dev, 652 "CCC with %dms/4cmd enabled on vector %d\n", 653 ctlr->ccc, ctlr->cccv); 654 } 655 } 656 /* Enable AHCI interrupts */ 657 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 658 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 659 return (0); 660} 661 662static int 663ahci_suspend(device_t dev) 664{ 665 struct ahci_controller *ctlr = device_get_softc(dev); 666 667 bus_generic_suspend(dev); 668 /* Disable interupts, so the state change(s) doesn't trigger */ 669 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 670 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE)); 671 return 0; 672} 673 674static int 675ahci_resume(device_t dev) 676{ 677 int res; 678 679 if ((res = ahci_ctlr_reset(dev)) != 0) 680 return (res); 681 ahci_ctlr_setup(dev); 682 return (bus_generic_resume(dev)); 683} 684 685static int 686ahci_setup_interrupt(device_t dev) 687{ 688 struct ahci_controller *ctlr = device_get_softc(dev); 689 int i; 690 691 ctlr->msi = 2; 692 /* Process hints. */ 693 if (ctlr->quirks & AHCI_Q_NOMSI) 694 ctlr->msi = 0; 695 resource_int_value(device_get_name(dev), 696 device_get_unit(dev), "msi", &ctlr->msi); 697 ctlr->numirqs = 1; 698 if (ctlr->msi < 0) 699 ctlr->msi = 0; 700 else if (ctlr->msi == 1) 701 ctlr->msi = min(1, pci_msi_count(dev)); 702 else if (ctlr->msi > 1) { 703 ctlr->msi = 2; 704 ctlr->numirqs = pci_msi_count(dev); 705 } 706 /* Allocate MSI if needed/present. */ 707 if (ctlr->msi && pci_alloc_msi(dev, &ctlr->numirqs) != 0) { 708 ctlr->msi = 0; 709 ctlr->numirqs = 1; 710 } 711 /* Check for single MSI vector fallback. */ 712 if (ctlr->numirqs > 1 && 713 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 714 device_printf(dev, "Falling back to one MSI\n"); 715 ctlr->numirqs = 1; 716 } 717 /* Allocate all IRQs. */ 718 for (i = 0; i < ctlr->numirqs; i++) { 719 ctlr->irqs[i].ctlr = ctlr; 720 ctlr->irqs[i].r_irq_rid = i + (ctlr->msi ? 1 : 0); 721 if (ctlr->numirqs == 1 || i >= ctlr->channels || 722 (ctlr->ccc && i == ctlr->cccv)) 723 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 724 else if (i == ctlr->numirqs - 1) 725 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 726 else 727 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 728 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 729 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 730 device_printf(dev, "unable to map interrupt\n"); 731 return ENXIO; 732 } 733 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 734 (ctlr->irqs[i].mode != AHCI_IRQ_MODE_ONE) ? ahci_intr : 735 ((ctlr->quirks & AHCI_Q_EDGEIS) ? ahci_intr_one_edge : 736 ahci_intr_one), 737 &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 738 /* SOS XXX release r_irq */ 739 device_printf(dev, "unable to setup interrupt\n"); 740 return ENXIO; 741 } 742 if (ctlr->numirqs > 1) { 743 bus_describe_intr(dev, ctlr->irqs[i].r_irq, 744 ctlr->irqs[i].handle, 745 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ? 746 "ch%d" : "%d", i); 747 } 748 } 749 return (0); 750} 751 752/* 753 * Common case interrupt handler. 754 */ 755static void 756ahci_intr(void *data) 757{ 758 struct ahci_controller_irq *irq = data; 759 struct ahci_controller *ctlr = irq->ctlr; 760 u_int32_t is, ise = 0; 761 void *arg; 762 int unit; 763 764 if (irq->mode == AHCI_IRQ_MODE_ALL) { 765 unit = 0; 766 if (ctlr->ccc) 767 is = ctlr->ichannels; 768 else 769 is = ATA_INL(ctlr->r_mem, AHCI_IS); 770 } else { /* AHCI_IRQ_MODE_AFTER */ 771 unit = irq->r_irq_rid - 1; 772 is = ATA_INL(ctlr->r_mem, AHCI_IS); 773 } 774 /* CCC interrupt is edge triggered. */ 775 if (ctlr->ccc) 776 ise = 1 << ctlr->cccv; 777 /* Some controllers have edge triggered IS. */ 778 if (ctlr->quirks & AHCI_Q_EDGEIS) 779 ise |= is; 780 if (ise != 0) 781 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise); 782 for (; unit < ctlr->channels; unit++) { 783 if ((is & (1 << unit)) != 0 && 784 (arg = ctlr->interrupt[unit].argument)) { 785 ctlr->interrupt[unit].function(arg); 786 } 787 } 788 /* AHCI declares level triggered IS. */ 789 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 790 ATA_OUTL(ctlr->r_mem, AHCI_IS, is); 791} 792 793/* 794 * Simplified interrupt handler for multivector MSI mode. 795 */ 796static void 797ahci_intr_one(void *data) 798{ 799 struct ahci_controller_irq *irq = data; 800 struct ahci_controller *ctlr = irq->ctlr; 801 void *arg; 802 int unit; 803 804 unit = irq->r_irq_rid - 1; 805 if ((arg = ctlr->interrupt[unit].argument)) 806 ctlr->interrupt[unit].function(arg); 807 /* AHCI declares level triggered IS. */ 808 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 809} 810 811static void 812ahci_intr_one_edge(void *data) 813{ 814 struct ahci_controller_irq *irq = data; 815 struct ahci_controller *ctlr = irq->ctlr; 816 void *arg; 817 int unit; 818 819 unit = irq->r_irq_rid - 1; 820 /* Some controllers have edge triggered IS. */ 821 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 822 if ((arg = ctlr->interrupt[unit].argument)) 823 ctlr->interrupt[unit].function(arg); 824} 825 826static struct resource * 827ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 828 u_long start, u_long end, u_long count, u_int flags) 829{ 830 struct ahci_controller *ctlr = device_get_softc(dev); 831 struct resource *res; 832 long st; 833 int offset, size, unit; 834 835 unit = (intptr_t)device_get_ivars(child); 836 res = NULL; 837 switch (type) { 838 case SYS_RES_MEMORY: 839 if (unit >= 0) { 840 offset = AHCI_OFFSET + (unit << 7); 841 size = 128; 842 } else if (*rid == 0) { 843 offset = AHCI_EM_CTL; 844 size = 4; 845 } else { 846 offset = (ctlr->emloc & 0xffff0000) >> 14; 847 size = (ctlr->emloc & 0x0000ffff) << 2; 848 if (*rid != 1) { 849 if (*rid == 2 && (ctlr->capsem & 850 (AHCI_EM_XMT | AHCI_EM_SMB)) == 0) 851 offset += size; 852 else 853 break; 854 } 855 } 856 st = rman_get_start(ctlr->r_mem); 857 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 858 st + offset + size - 1, size, RF_ACTIVE, child); 859 if (res) { 860 bus_space_handle_t bsh; 861 bus_space_tag_t bst; 862 bsh = rman_get_bushandle(ctlr->r_mem); 863 bst = rman_get_bustag(ctlr->r_mem); 864 bus_space_subregion(bst, bsh, offset, 128, &bsh); 865 rman_set_bushandle(res, bsh); 866 rman_set_bustag(res, bst); 867 } 868 break; 869 case SYS_RES_IRQ: 870 if (*rid == ATA_IRQ_RID) 871 res = ctlr->irqs[0].r_irq; 872 break; 873 } 874 return (res); 875} 876 877static int 878ahci_release_resource(device_t dev, device_t child, int type, int rid, 879 struct resource *r) 880{ 881 882 switch (type) { 883 case SYS_RES_MEMORY: 884 rman_release_resource(r); 885 return (0); 886 case SYS_RES_IRQ: 887 if (rid != ATA_IRQ_RID) 888 return ENOENT; 889 return (0); 890 } 891 return (EINVAL); 892} 893 894static int 895ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 896 int flags, driver_filter_t *filter, driver_intr_t *function, 897 void *argument, void **cookiep) 898{ 899 struct ahci_controller *ctlr = device_get_softc(dev); 900 int unit = (intptr_t)device_get_ivars(child); 901 902 if (filter != NULL) { 903 printf("ahci.c: we cannot use a filter here\n"); 904 return (EINVAL); 905 } 906 ctlr->interrupt[unit].function = function; 907 ctlr->interrupt[unit].argument = argument; 908 return (0); 909} 910 911static int 912ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 913 void *cookie) 914{ 915 struct ahci_controller *ctlr = device_get_softc(dev); 916 int unit = (intptr_t)device_get_ivars(child); 917 918 ctlr->interrupt[unit].function = NULL; 919 ctlr->interrupt[unit].argument = NULL; 920 return (0); 921} 922 923static int 924ahci_print_child(device_t dev, device_t child) 925{ 926 int retval, channel; 927 928 retval = bus_print_child_header(dev, child); 929 channel = (int)(intptr_t)device_get_ivars(child); 930 if (channel >= 0) 931 retval += printf(" at channel %d", channel); 932 retval += bus_print_child_footer(dev, child); 933 return (retval); 934} 935 936static int 937ahci_child_location_str(device_t dev, device_t child, char *buf, 938 size_t buflen) 939{ 940 int channel; 941 942 channel = (int)(intptr_t)device_get_ivars(child); 943 if (channel >= 0) 944 snprintf(buf, buflen, "channel=%d", channel); 945 return (0); 946} 947 948static bus_dma_tag_t 949ahci_get_dma_tag(device_t dev, device_t child) 950{ 951 struct ahci_controller *ctlr = device_get_softc(dev); 952 953 return (ctlr->dma_tag); 954} 955 956devclass_t ahci_devclass; 957static device_method_t ahci_methods[] = { 958 DEVMETHOD(device_probe, ahci_probe), 959 DEVMETHOD(device_attach, ahci_attach), 960 DEVMETHOD(device_detach, ahci_detach), 961 DEVMETHOD(device_suspend, ahci_suspend), 962 DEVMETHOD(device_resume, ahci_resume), 963 DEVMETHOD(bus_print_child, ahci_print_child), 964 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 965 DEVMETHOD(bus_release_resource, ahci_release_resource), 966 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 967 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 968 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 969 DEVMETHOD(bus_get_dma_tag, ahci_get_dma_tag), 970 { 0, 0 } 971}; 972static driver_t ahci_driver = { 973 "ahci", 974 ahci_methods, 975 sizeof(struct ahci_controller) 976}; 977DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0); 978static device_method_t ahci_ata_methods[] = { 979 DEVMETHOD(device_probe, ahci_ata_probe), 980 DEVMETHOD(device_attach, ahci_attach), 981 DEVMETHOD(device_detach, ahci_detach), 982 DEVMETHOD(device_suspend, ahci_suspend), 983 DEVMETHOD(device_resume, ahci_resume), 984 DEVMETHOD(bus_print_child, ahci_print_child), 985 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 986 DEVMETHOD(bus_release_resource, ahci_release_resource), 987 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 988 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 989 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 990 { 0, 0 } 991}; 992static driver_t ahci_ata_driver = { 993 "ahci", 994 ahci_ata_methods, 995 sizeof(struct ahci_controller) 996}; 997DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, 0, 0); 998MODULE_VERSION(ahci, 1); 999MODULE_DEPEND(ahci, cam, 1, 1, 1); 1000 1001static int 1002ahci_ch_probe(device_t dev) 1003{ 1004 1005 device_set_desc_copy(dev, "AHCI channel"); 1006 return (0); 1007} 1008 1009static int 1010ahci_ch_attach(device_t dev) 1011{ 1012 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1013 struct ahci_channel *ch = device_get_softc(dev); 1014 struct cam_devq *devq; 1015 int rid, error, i, sata_rev = 0; 1016 u_int32_t version; 1017 1018 ch->dev = dev; 1019 ch->unit = (intptr_t)device_get_ivars(dev); 1020 ch->caps = ctlr->caps; 1021 ch->caps2 = ctlr->caps2; 1022 ch->quirks = ctlr->quirks; 1023 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1; 1024 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 1025 resource_int_value(device_get_name(dev), 1026 device_get_unit(dev), "pm_level", &ch->pm_level); 1027 STAILQ_INIT(&ch->doneq); 1028 if (ch->pm_level > 3) 1029 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 1030 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0); 1031 /* Limit speed for my onboard JMicron external port. 1032 * It is not eSATA really. */ 1033 if (pci_get_devid(ctlr->dev) == 0x2363197b && 1034 pci_get_subvendor(ctlr->dev) == 0x1043 && 1035 pci_get_subdevice(ctlr->dev) == 0x81e4 && 1036 ch->unit == 0) 1037 sata_rev = 1; 1038 if (ch->quirks & AHCI_Q_SATA2) 1039 sata_rev = 2; 1040 resource_int_value(device_get_name(dev), 1041 device_get_unit(dev), "sata_rev", &sata_rev); 1042 for (i = 0; i < 16; i++) { 1043 ch->user[i].revision = sata_rev; 1044 ch->user[i].mode = 0; 1045 ch->user[i].bytecount = 8192; 1046 ch->user[i].tags = ch->numslots; 1047 ch->user[i].caps = 0; 1048 ch->curr[i] = ch->user[i]; 1049 if (ch->pm_level) { 1050 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 1051 CTS_SATA_CAPS_H_APST | 1052 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST; 1053 } 1054 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA | 1055 CTS_SATA_CAPS_H_AN; 1056 } 1057 rid = 0; 1058 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1059 &rid, RF_ACTIVE))) 1060 return (ENXIO); 1061 ahci_dmainit(dev); 1062 ahci_slotsalloc(dev); 1063 ahci_ch_init(dev); 1064 mtx_lock(&ch->mtx); 1065 rid = ATA_IRQ_RID; 1066 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1067 &rid, RF_SHAREABLE | RF_ACTIVE))) { 1068 device_printf(dev, "Unable to map interrupt\n"); 1069 error = ENXIO; 1070 goto err0; 1071 } 1072 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 1073 ctlr->direct ? ahci_ch_intr_direct : ahci_ch_intr, 1074 dev, &ch->ih))) { 1075 device_printf(dev, "Unable to setup interrupt\n"); 1076 error = ENXIO; 1077 goto err1; 1078 } 1079 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD); 1080 version = ATA_INL(ctlr->r_mem, AHCI_VS); 1081 if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS)) 1082 ch->chcaps |= AHCI_P_CMD_FBSCP; 1083 if (bootverbose) { 1084 device_printf(dev, "Caps:%s%s%s%s%s\n", 1085 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"", 1086 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"", 1087 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"", 1088 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"", 1089 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":""); 1090 } 1091 /* Create the device queue for our SIM. */ 1092 devq = cam_simq_alloc(ch->numslots); 1093 if (devq == NULL) { 1094 device_printf(dev, "Unable to allocate simq\n"); 1095 error = ENOMEM; 1096 goto err1; 1097 } 1098 /* Construct SIM entry */ 1099 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 1100 device_get_unit(dev), &ch->mtx, 1101 min(2, ch->numslots), 1102 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0, 1103 devq); 1104 if (ch->sim == NULL) { 1105 cam_simq_free(devq); 1106 device_printf(dev, "unable to allocate sim\n"); 1107 error = ENOMEM; 1108 goto err1; 1109 } 1110 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 1111 device_printf(dev, "unable to register xpt bus\n"); 1112 error = ENXIO; 1113 goto err2; 1114 } 1115 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 1116 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1117 device_printf(dev, "unable to create path\n"); 1118 error = ENXIO; 1119 goto err3; 1120 } 1121 if (ch->pm_level > 3) { 1122 callout_reset(&ch->pm_timer, 1123 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 1124 ahci_ch_pm, dev); 1125 } 1126 mtx_unlock(&ch->mtx); 1127 return (0); 1128 1129err3: 1130 xpt_bus_deregister(cam_sim_path(ch->sim)); 1131err2: 1132 cam_sim_free(ch->sim, /*free_devq*/TRUE); 1133err1: 1134 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1135err0: 1136 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1137 mtx_unlock(&ch->mtx); 1138 mtx_destroy(&ch->mtx); 1139 return (error); 1140} 1141 1142static int 1143ahci_ch_detach(device_t dev) 1144{ 1145 struct ahci_channel *ch = device_get_softc(dev); 1146 1147 mtx_lock(&ch->mtx); 1148 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 1149 /* Forget about reset. */ 1150 if (ch->resetting) { 1151 ch->resetting = 0; 1152 xpt_release_simq(ch->sim, TRUE); 1153 } 1154 xpt_free_path(ch->path); 1155 xpt_bus_deregister(cam_sim_path(ch->sim)); 1156 cam_sim_free(ch->sim, /*free_devq*/TRUE); 1157 mtx_unlock(&ch->mtx); 1158 1159 if (ch->pm_level > 3) 1160 callout_drain(&ch->pm_timer); 1161 callout_drain(&ch->reset_timer); 1162 bus_teardown_intr(dev, ch->r_irq, ch->ih); 1163 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1164 1165 ahci_ch_deinit(dev); 1166 ahci_slotsfree(dev); 1167 ahci_dmafini(dev); 1168 1169 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1170 mtx_destroy(&ch->mtx); 1171 return (0); 1172} 1173 1174static int 1175ahci_ch_init(device_t dev) 1176{ 1177 struct ahci_channel *ch = device_get_softc(dev); 1178 uint64_t work; 1179 1180 /* Disable port interrupts */ 1181 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1182 /* Setup work areas */ 1183 work = ch->dma.work_bus + AHCI_CL_OFFSET; 1184 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 1185 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 1186 work = ch->dma.rfis_bus; 1187 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 1188 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 1189 /* Activate the channel and power/spin up device */ 1190 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 1191 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1192 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 1193 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 1194 ahci_start_fr(dev); 1195 ahci_start(dev, 1); 1196 return (0); 1197} 1198 1199static int 1200ahci_ch_deinit(device_t dev) 1201{ 1202 struct ahci_channel *ch = device_get_softc(dev); 1203 1204 /* Disable port interrupts. */ 1205 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1206 /* Reset command register. */ 1207 ahci_stop(dev); 1208 ahci_stop_fr(dev); 1209 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 1210 /* Allow everything, including partial and slumber modes. */ 1211 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 1212 /* Request slumber mode transition and give some time to get there. */ 1213 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 1214 DELAY(100); 1215 /* Disable PHY. */ 1216 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 1217 return (0); 1218} 1219 1220static int 1221ahci_ch_suspend(device_t dev) 1222{ 1223 struct ahci_channel *ch = device_get_softc(dev); 1224 1225 mtx_lock(&ch->mtx); 1226 xpt_freeze_simq(ch->sim, 1); 1227 /* Forget about reset. */ 1228 if (ch->resetting) { 1229 ch->resetting = 0; 1230 callout_stop(&ch->reset_timer); 1231 xpt_release_simq(ch->sim, TRUE); 1232 } 1233 while (ch->oslots) 1234 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100); 1235 ahci_ch_deinit(dev); 1236 mtx_unlock(&ch->mtx); 1237 return (0); 1238} 1239 1240static int 1241ahci_ch_resume(device_t dev) 1242{ 1243 struct ahci_channel *ch = device_get_softc(dev); 1244 1245 mtx_lock(&ch->mtx); 1246 ahci_ch_init(dev); 1247 ahci_reset(dev); 1248 xpt_release_simq(ch->sim, TRUE); 1249 mtx_unlock(&ch->mtx); 1250 return (0); 1251} 1252 1253devclass_t ahcich_devclass; 1254static device_method_t ahcich_methods[] = { 1255 DEVMETHOD(device_probe, ahci_ch_probe), 1256 DEVMETHOD(device_attach, ahci_ch_attach), 1257 DEVMETHOD(device_detach, ahci_ch_detach), 1258 DEVMETHOD(device_suspend, ahci_ch_suspend), 1259 DEVMETHOD(device_resume, ahci_ch_resume), 1260 { 0, 0 } 1261}; 1262static driver_t ahcich_driver = { 1263 "ahcich", 1264 ahcich_methods, 1265 sizeof(struct ahci_channel) 1266}; 1267DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, 0, 0); 1268 1269struct ahci_dc_cb_args { 1270 bus_addr_t maddr; 1271 int error; 1272}; 1273 1274static void 1275ahci_dmainit(device_t dev) 1276{ 1277 struct ahci_channel *ch = device_get_softc(dev); 1278 struct ahci_dc_cb_args dcba; 1279 size_t rfsize; 1280 1281 /* Command area. */ 1282 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 1283 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1284 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 1285 0, NULL, NULL, &ch->dma.work_tag)) 1286 goto error; 1287 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 1288 BUS_DMA_ZERO, &ch->dma.work_map)) 1289 goto error; 1290 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 1291 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1292 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1293 goto error; 1294 } 1295 ch->dma.work_bus = dcba.maddr; 1296 /* FIS receive area. */ 1297 if (ch->chcaps & AHCI_P_CMD_FBSCP) 1298 rfsize = 4096; 1299 else 1300 rfsize = 256; 1301 if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0, 1302 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1303 NULL, NULL, rfsize, 1, rfsize, 1304 0, NULL, NULL, &ch->dma.rfis_tag)) 1305 goto error; 1306 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 1307 &ch->dma.rfis_map)) 1308 goto error; 1309 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 1310 rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1311 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1312 goto error; 1313 } 1314 ch->dma.rfis_bus = dcba.maddr; 1315 /* Data area. */ 1316 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 1317 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1318 NULL, NULL, 1319 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 1320 AHCI_SG_ENTRIES, AHCI_PRD_MAX, 1321 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 1322 goto error; 1323 } 1324 return; 1325 1326error: 1327 device_printf(dev, "WARNING - DMA initialization failed\n"); 1328 ahci_dmafini(dev); 1329} 1330 1331static void 1332ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1333{ 1334 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 1335 1336 if (!(dcba->error = error)) 1337 dcba->maddr = segs[0].ds_addr; 1338} 1339 1340static void 1341ahci_dmafini(device_t dev) 1342{ 1343 struct ahci_channel *ch = device_get_softc(dev); 1344 1345 if (ch->dma.data_tag) { 1346 bus_dma_tag_destroy(ch->dma.data_tag); 1347 ch->dma.data_tag = NULL; 1348 } 1349 if (ch->dma.rfis_bus) { 1350 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 1351 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1352 ch->dma.rfis_bus = 0; 1353 ch->dma.rfis_map = NULL; 1354 ch->dma.rfis = NULL; 1355 } 1356 if (ch->dma.work_bus) { 1357 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 1358 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1359 ch->dma.work_bus = 0; 1360 ch->dma.work_map = NULL; 1361 ch->dma.work = NULL; 1362 } 1363 if (ch->dma.work_tag) { 1364 bus_dma_tag_destroy(ch->dma.work_tag); 1365 ch->dma.work_tag = NULL; 1366 } 1367} 1368 1369static void 1370ahci_slotsalloc(device_t dev) 1371{ 1372 struct ahci_channel *ch = device_get_softc(dev); 1373 int i; 1374 1375 /* Alloc and setup command/dma slots */ 1376 bzero(ch->slot, sizeof(ch->slot)); 1377 for (i = 0; i < ch->numslots; i++) { 1378 struct ahci_slot *slot = &ch->slot[i]; 1379 1380 slot->dev = dev; 1381 slot->slot = i; 1382 slot->state = AHCI_SLOT_EMPTY; 1383 slot->ccb = NULL; 1384 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 1385 1386 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 1387 device_printf(ch->dev, "FAILURE - create data_map\n"); 1388 } 1389} 1390 1391static void 1392ahci_slotsfree(device_t dev) 1393{ 1394 struct ahci_channel *ch = device_get_softc(dev); 1395 int i; 1396 1397 /* Free all dma slots */ 1398 for (i = 0; i < ch->numslots; i++) { 1399 struct ahci_slot *slot = &ch->slot[i]; 1400 1401 callout_drain(&slot->timeout); 1402 if (slot->dma.data_map) { 1403 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 1404 slot->dma.data_map = NULL; 1405 } 1406 } 1407} 1408 1409static int 1410ahci_phy_check_events(device_t dev, u_int32_t serr) 1411{ 1412 struct ahci_channel *ch = device_get_softc(dev); 1413 1414 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) || 1415 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) { 1416 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1417 union ccb *ccb; 1418 1419 if (bootverbose) { 1420 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 1421 device_printf(dev, "CONNECT requested\n"); 1422 else 1423 device_printf(dev, "DISCONNECT requested\n"); 1424 } 1425 ahci_reset(dev); 1426 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1427 return (0); 1428 if (xpt_create_path(&ccb->ccb_h.path, NULL, 1429 cam_sim_path(ch->sim), 1430 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1431 xpt_free_ccb(ccb); 1432 return (0); 1433 } 1434 xpt_rescan(ccb); 1435 return (1); 1436 } 1437 return (0); 1438} 1439 1440static void 1441ahci_cpd_check_events(device_t dev) 1442{ 1443 struct ahci_channel *ch = device_get_softc(dev); 1444 u_int32_t status; 1445 union ccb *ccb; 1446 1447 if (ch->pm_level == 0) 1448 return; 1449 1450 status = ATA_INL(ch->r_mem, AHCI_P_CMD); 1451 if ((status & AHCI_P_CMD_CPD) == 0) 1452 return; 1453 1454 if (bootverbose) { 1455 if (status & AHCI_P_CMD_CPS) { 1456 device_printf(dev, "COLD CONNECT requested\n"); 1457 } else 1458 device_printf(dev, "COLD DISCONNECT requested\n"); 1459 } 1460 ahci_reset(dev); 1461 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1462 return; 1463 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim), 1464 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1465 xpt_free_ccb(ccb); 1466 return; 1467 } 1468 xpt_rescan(ccb); 1469} 1470 1471static void 1472ahci_notify_events(device_t dev, u_int32_t status) 1473{ 1474 struct ahci_channel *ch = device_get_softc(dev); 1475 struct cam_path *dpath; 1476 int i; 1477 1478 if (ch->caps & AHCI_CAP_SSNTF) 1479 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 1480 if (bootverbose) 1481 device_printf(dev, "SNTF 0x%04x\n", status); 1482 for (i = 0; i < 16; i++) { 1483 if ((status & (1 << i)) == 0) 1484 continue; 1485 if (xpt_create_path(&dpath, NULL, 1486 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 1487 xpt_async(AC_SCSI_AEN, dpath, NULL); 1488 xpt_free_path(dpath); 1489 } 1490 } 1491} 1492 1493static void 1494ahci_done(struct ahci_channel *ch, union ccb *ccb) 1495{ 1496 1497 mtx_assert(&ch->mtx, MA_OWNED); 1498 if ((ccb->ccb_h.func_code & XPT_FC_QUEUED) == 0 || 1499 ch->batch == 0) { 1500 xpt_done(ccb); 1501 return; 1502 } 1503 1504 STAILQ_INSERT_TAIL(&ch->doneq, &ccb->ccb_h, sim_links.stqe); 1505} 1506 1507static void 1508ahci_ch_intr(void *arg) 1509{ 1510 device_t dev = (device_t)arg; 1511 struct ahci_channel *ch = device_get_softc(dev); 1512 uint32_t istatus; 1513 1514 /* Read interrupt statuses. */ 1515 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1516 if (istatus == 0) 1517 return; 1518 1519 mtx_lock(&ch->mtx); 1520 ahci_ch_intr_main(ch, istatus); 1521 mtx_unlock(&ch->mtx); 1522} 1523 1524static void 1525ahci_ch_intr_direct(void *arg) 1526{ 1527 device_t dev = (device_t)arg; 1528 struct ahci_channel *ch = device_get_softc(dev); 1529 struct ccb_hdr *ccb_h; 1530 uint32_t istatus; 1531 1532 /* Read interrupt statuses. */ 1533 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1534 if (istatus == 0) 1535 return; 1536 1537 mtx_lock(&ch->mtx); 1538 ch->batch = 1; 1539 ahci_ch_intr_main(ch, istatus); 1540 ch->batch = 0; 1541 mtx_unlock(&ch->mtx); 1542 while ((ccb_h = STAILQ_FIRST(&ch->doneq)) != NULL) { 1543 STAILQ_REMOVE_HEAD(&ch->doneq, sim_links.stqe); 1544 xpt_done_direct((union ccb *)ccb_h); 1545 } 1546} 1547 1548static void 1549ahci_ch_pm(void *arg) 1550{ 1551 device_t dev = (device_t)arg; 1552 struct ahci_channel *ch = device_get_softc(dev); 1553 uint32_t work; 1554 1555 if (ch->numrslots != 0) 1556 return; 1557 work = ATA_INL(ch->r_mem, AHCI_P_CMD); 1558 if (ch->pm_level == 4) 1559 work |= AHCI_P_CMD_PARTIAL; 1560 else 1561 work |= AHCI_P_CMD_SLUMBER; 1562 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 1563} 1564 1565static void 1566ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus) 1567{ 1568 device_t dev = ch->dev; 1569 uint32_t cstatus, serr = 0, sntf = 0, ok, err; 1570 enum ahci_err_type et; 1571 int i, ccs, port, reset = 0; 1572 1573 /* Clear interrupt statuses. */ 1574 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 1575 /* Read command statuses. */ 1576 if (ch->numtslots != 0) 1577 cstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1578 else 1579 cstatus = 0; 1580 if (ch->numrslots != ch->numtslots) 1581 cstatus |= ATA_INL(ch->r_mem, AHCI_P_CI); 1582 /* Read SNTF in one of possible ways. */ 1583 if ((istatus & AHCI_P_IX_SDB) && 1584 (ch->pm_present || ch->curr[0].atapi != 0)) { 1585 if (ch->caps & AHCI_CAP_SSNTF) 1586 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 1587 else if (ch->fbs_enabled) { 1588 u_int8_t *fis = ch->dma.rfis + 0x58; 1589 1590 for (i = 0; i < 16; i++) { 1591 if (fis[1] & 0x80) { 1592 fis[1] &= 0x7f; 1593 sntf |= 1 << i; 1594 } 1595 fis += 256; 1596 } 1597 } else { 1598 u_int8_t *fis = ch->dma.rfis + 0x58; 1599 1600 if (fis[1] & 0x80) 1601 sntf = (1 << (fis[1] & 0x0f)); 1602 } 1603 } 1604 /* Process PHY events */ 1605 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 1606 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1607 serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 1608 if (serr) { 1609 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 1610 reset = ahci_phy_check_events(dev, serr); 1611 } 1612 } 1613 /* Process cold presence detection events */ 1614 if ((istatus & AHCI_P_IX_CPD) && !reset) 1615 ahci_cpd_check_events(dev); 1616 /* Process command errors */ 1617 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 1618 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1619 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1620 >> AHCI_P_CMD_CCS_SHIFT; 1621//device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n", 1622// __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 1623// serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs); 1624 port = -1; 1625 if (ch->fbs_enabled) { 1626 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS); 1627 if (fbs & AHCI_P_FBS_SDE) { 1628 port = (fbs & AHCI_P_FBS_DWE) 1629 >> AHCI_P_FBS_DWE_SHIFT; 1630 } else { 1631 for (i = 0; i < 16; i++) { 1632 if (ch->numrslotspd[i] == 0) 1633 continue; 1634 if (port == -1) 1635 port = i; 1636 else if (port != i) { 1637 port = -2; 1638 break; 1639 } 1640 } 1641 } 1642 } 1643 err = ch->rslots & cstatus; 1644 } else { 1645 ccs = 0; 1646 err = 0; 1647 port = -1; 1648 } 1649 /* Complete all successfull commands. */ 1650 ok = ch->rslots & ~cstatus; 1651 for (i = 0; i < ch->numslots; i++) { 1652 if ((ok >> i) & 1) 1653 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 1654 } 1655 /* On error, complete the rest of commands with error statuses. */ 1656 if (err) { 1657 if (ch->frozen) { 1658 union ccb *fccb = ch->frozen; 1659 ch->frozen = NULL; 1660 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1661 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1662 xpt_freeze_devq(fccb->ccb_h.path, 1); 1663 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1664 } 1665 ahci_done(ch, fccb); 1666 } 1667 for (i = 0; i < ch->numslots; i++) { 1668 /* XXX: reqests in loading state. */ 1669 if (((err >> i) & 1) == 0) 1670 continue; 1671 if (port >= 0 && 1672 ch->slot[i].ccb->ccb_h.target_id != port) 1673 continue; 1674 if (istatus & AHCI_P_IX_TFE) { 1675 if (port != -2) { 1676 /* Task File Error */ 1677 if (ch->numtslotspd[ 1678 ch->slot[i].ccb->ccb_h.target_id] == 0) { 1679 /* Untagged operation. */ 1680 if (i == ccs) 1681 et = AHCI_ERR_TFE; 1682 else 1683 et = AHCI_ERR_INNOCENT; 1684 } else { 1685 /* Tagged operation. */ 1686 et = AHCI_ERR_NCQ; 1687 } 1688 } else { 1689 et = AHCI_ERR_TFE; 1690 ch->fatalerr = 1; 1691 } 1692 } else if (istatus & AHCI_P_IX_IF) { 1693 if (ch->numtslots == 0 && i != ccs && port != -2) 1694 et = AHCI_ERR_INNOCENT; 1695 else 1696 et = AHCI_ERR_SATA; 1697 } else 1698 et = AHCI_ERR_INVALID; 1699 ahci_end_transaction(&ch->slot[i], et); 1700 } 1701 /* 1702 * We can't reinit port if there are some other 1703 * commands active, use resume to complete them. 1704 */ 1705 if (ch->rslots != 0 && !ch->recoverycmd) 1706 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC); 1707 } 1708 /* Process NOTIFY events */ 1709 if (sntf) 1710 ahci_notify_events(dev, sntf); 1711} 1712 1713/* Must be called with channel locked. */ 1714static int 1715ahci_check_collision(device_t dev, union ccb *ccb) 1716{ 1717 struct ahci_channel *ch = device_get_softc(dev); 1718 int t = ccb->ccb_h.target_id; 1719 1720 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1721 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1722 /* Tagged command while we have no supported tag free. */ 1723 if (((~ch->oslots) & (0xffffffff >> (32 - 1724 ch->curr[t].tags))) == 0) 1725 return (1); 1726 /* If we have FBS */ 1727 if (ch->fbs_enabled) { 1728 /* Tagged command while untagged are active. */ 1729 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0) 1730 return (1); 1731 } else { 1732 /* Tagged command while untagged are active. */ 1733 if (ch->numrslots != 0 && ch->numtslots == 0) 1734 return (1); 1735 /* Tagged command while tagged to other target is active. */ 1736 if (ch->numtslots != 0 && 1737 ch->taggedtarget != ccb->ccb_h.target_id) 1738 return (1); 1739 } 1740 } else { 1741 /* If we have FBS */ 1742 if (ch->fbs_enabled) { 1743 /* Untagged command while tagged are active. */ 1744 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0) 1745 return (1); 1746 } else { 1747 /* Untagged command while tagged are active. */ 1748 if (ch->numrslots != 0 && ch->numtslots != 0) 1749 return (1); 1750 } 1751 } 1752 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1753 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1754 /* Atomic command while anything active. */ 1755 if (ch->numrslots != 0) 1756 return (1); 1757 } 1758 /* We have some atomic command running. */ 1759 if (ch->aslots != 0) 1760 return (1); 1761 return (0); 1762} 1763 1764/* Must be called with channel locked. */ 1765static void 1766ahci_begin_transaction(device_t dev, union ccb *ccb) 1767{ 1768 struct ahci_channel *ch = device_get_softc(dev); 1769 struct ahci_slot *slot; 1770 int tag, tags; 1771 1772 /* Choose empty slot. */ 1773 tags = ch->numslots; 1774 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1775 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) 1776 tags = ch->curr[ccb->ccb_h.target_id].tags; 1777 tag = ch->lastslot; 1778 while (1) { 1779 if (tag >= tags) 1780 tag = 0; 1781 if (ch->slot[tag].state == AHCI_SLOT_EMPTY) 1782 break; 1783 tag++; 1784 }; 1785 ch->lastslot = tag; 1786 /* Occupy chosen slot. */ 1787 slot = &ch->slot[tag]; 1788 slot->ccb = ccb; 1789 /* Stop PM timer. */ 1790 if (ch->numrslots == 0 && ch->pm_level > 3) 1791 callout_stop(&ch->pm_timer); 1792 /* Update channel stats. */ 1793 ch->oslots |= (1 << slot->slot); 1794 ch->numrslots++; 1795 ch->numrslotspd[ccb->ccb_h.target_id]++; 1796 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1797 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1798 ch->numtslots++; 1799 ch->numtslotspd[ccb->ccb_h.target_id]++; 1800 ch->taggedtarget = ccb->ccb_h.target_id; 1801 } 1802 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1803 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1804 ch->aslots |= (1 << slot->slot); 1805 slot->dma.nsegs = 0; 1806 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1807 slot->state = AHCI_SLOT_LOADING; 1808 bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map, ccb, 1809 ahci_dmasetprd, slot, 0); 1810 } else 1811 ahci_execute_transaction(slot); 1812} 1813 1814/* Locked by busdma engine. */ 1815static void 1816ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1817{ 1818 struct ahci_slot *slot = arg; 1819 struct ahci_channel *ch = device_get_softc(slot->dev); 1820 struct ahci_cmd_tab *ctp; 1821 struct ahci_dma_prd *prd; 1822 int i; 1823 1824 if (error) { 1825 device_printf(slot->dev, "DMA load error\n"); 1826 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1827 return; 1828 } 1829 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1830 /* Get a piece of the workspace for this request */ 1831 ctp = (struct ahci_cmd_tab *) 1832 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1833 /* Fill S/G table */ 1834 prd = &ctp->prd_tab[0]; 1835 for (i = 0; i < nsegs; i++) { 1836 prd[i].dba = htole64(segs[i].ds_addr); 1837 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1838 } 1839 slot->dma.nsegs = nsegs; 1840 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1841 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1842 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1843 ahci_execute_transaction(slot); 1844} 1845 1846/* Must be called with channel locked. */ 1847static void 1848ahci_execute_transaction(struct ahci_slot *slot) 1849{ 1850 device_t dev = slot->dev; 1851 struct ahci_channel *ch = device_get_softc(dev); 1852 struct ahci_cmd_tab *ctp; 1853 struct ahci_cmd_list *clp; 1854 union ccb *ccb = slot->ccb; 1855 int port = ccb->ccb_h.target_id & 0x0f; 1856 int fis_size, i, softreset; 1857 uint8_t *fis = ch->dma.rfis + 0x40; 1858 uint8_t val; 1859 1860 /* Get a piece of the workspace for this request */ 1861 ctp = (struct ahci_cmd_tab *) 1862 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1863 /* Setup the FIS for this request */ 1864 if (!(fis_size = ahci_setup_fis(dev, ctp, ccb, slot->slot))) { 1865 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1866 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1867 return; 1868 } 1869 /* Setup the command list entry */ 1870 clp = (struct ahci_cmd_list *) 1871 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1872 clp->cmd_flags = htole16( 1873 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1874 (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1875 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1876 (fis_size / sizeof(u_int32_t)) | 1877 (port << 12)); 1878 clp->prd_length = htole16(slot->dma.nsegs); 1879 /* Special handling for Soft Reset command. */ 1880 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1881 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1882 if (ccb->ataio.cmd.control & ATA_A_RESET) { 1883 softreset = 1; 1884 /* Kick controller into sane state */ 1885 ahci_stop(dev); 1886 ahci_clo(dev); 1887 ahci_start(dev, 0); 1888 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1889 } else { 1890 softreset = 2; 1891 /* Prepare FIS receive area for check. */ 1892 for (i = 0; i < 20; i++) 1893 fis[i] = 0xff; 1894 } 1895 } else 1896 softreset = 0; 1897 clp->bytecount = 0; 1898 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1899 (AHCI_CT_SIZE * slot->slot)); 1900 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1901 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1902 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1903 BUS_DMASYNC_PREREAD); 1904 /* Set ACTIVE bit for NCQ commands. */ 1905 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1906 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1907 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1908 } 1909 /* If FBS is enabled, set PMP port. */ 1910 if (ch->fbs_enabled) { 1911 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | 1912 (port << AHCI_P_FBS_DEV_SHIFT)); 1913 } 1914 /* Issue command to the controller. */ 1915 slot->state = AHCI_SLOT_RUNNING; 1916 ch->rslots |= (1 << slot->slot); 1917 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1918 /* Device reset commands doesn't interrupt. Poll them. */ 1919 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1920 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) { 1921 int count, timeout = ccb->ccb_h.timeout * 100; 1922 enum ahci_err_type et = AHCI_ERR_NONE; 1923 1924 for (count = 0; count < timeout; count++) { 1925 DELAY(10); 1926 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1927 break; 1928 if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) && 1929 softreset != 1) { 1930#if 0 1931 device_printf(ch->dev, 1932 "Poll error on slot %d, TFD: %04x\n", 1933 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1934#endif 1935 et = AHCI_ERR_TFE; 1936 break; 1937 } 1938 /* Workaround for ATI SB600/SB700 chipsets. */ 1939 if (ccb->ccb_h.target_id == 15 && 1940 pci_get_vendor(device_get_parent(dev)) == 0x1002 && 1941 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) { 1942 et = AHCI_ERR_TIMEOUT; 1943 break; 1944 } 1945 } 1946 1947 /* Marvell controllers do not wait for readyness. */ 1948 if ((ch->quirks & AHCI_Q_NOBSYRES) && softreset == 2 && 1949 et == AHCI_ERR_NONE) { 1950 while ((val = fis[2]) & ATA_S_BUSY) { 1951 DELAY(10); 1952 if (count++ >= timeout) 1953 break; 1954 } 1955 } 1956 1957 if (timeout && (count >= timeout)) { 1958 device_printf(dev, "Poll timeout on slot %d port %d\n", 1959 slot->slot, port); 1960 device_printf(dev, "is %08x cs %08x ss %08x " 1961 "rs %08x tfd %02x serr %08x cmd %08x\n", 1962 ATA_INL(ch->r_mem, AHCI_P_IS), 1963 ATA_INL(ch->r_mem, AHCI_P_CI), 1964 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1965 ATA_INL(ch->r_mem, AHCI_P_TFD), 1966 ATA_INL(ch->r_mem, AHCI_P_SERR), 1967 ATA_INL(ch->r_mem, AHCI_P_CMD)); 1968 et = AHCI_ERR_TIMEOUT; 1969 } 1970 1971 /* Kick controller into sane state and enable FBS. */ 1972 if (softreset == 2) 1973 ch->eslots |= (1 << slot->slot); 1974 ahci_end_transaction(slot, et); 1975 return; 1976 } 1977 /* Start command execution timeout */ 1978 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000, 1979 (timeout_t*)ahci_timeout, slot); 1980 return; 1981} 1982 1983/* Must be called with channel locked. */ 1984static void 1985ahci_process_timeout(device_t dev) 1986{ 1987 struct ahci_channel *ch = device_get_softc(dev); 1988 int i; 1989 1990 mtx_assert(&ch->mtx, MA_OWNED); 1991 /* Handle the rest of commands. */ 1992 for (i = 0; i < ch->numslots; i++) { 1993 /* Do we have a running request on slot? */ 1994 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1995 continue; 1996 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT); 1997 } 1998} 1999 2000/* Must be called with channel locked. */ 2001static void 2002ahci_rearm_timeout(device_t dev) 2003{ 2004 struct ahci_channel *ch = device_get_softc(dev); 2005 int i; 2006 2007 mtx_assert(&ch->mtx, MA_OWNED); 2008 for (i = 0; i < ch->numslots; i++) { 2009 struct ahci_slot *slot = &ch->slot[i]; 2010 2011 /* Do we have a running request on slot? */ 2012 if (slot->state < AHCI_SLOT_RUNNING) 2013 continue; 2014 if ((ch->toslots & (1 << i)) == 0) 2015 continue; 2016 callout_reset(&slot->timeout, 2017 (int)slot->ccb->ccb_h.timeout * hz / 2000, 2018 (timeout_t*)ahci_timeout, slot); 2019 } 2020} 2021 2022/* Locked by callout mechanism. */ 2023static void 2024ahci_timeout(struct ahci_slot *slot) 2025{ 2026 device_t dev = slot->dev; 2027 struct ahci_channel *ch = device_get_softc(dev); 2028 uint32_t sstatus; 2029 int ccs; 2030 int i; 2031 2032 /* Check for stale timeout. */ 2033 if (slot->state < AHCI_SLOT_RUNNING) 2034 return; 2035 2036 /* Check if slot was not being executed last time we checked. */ 2037 if (slot->state < AHCI_SLOT_EXECUTING) { 2038 /* Check if slot started executing. */ 2039 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 2040 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 2041 >> AHCI_P_CMD_CCS_SHIFT; 2042 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot || 2043 ch->fbs_enabled || ch->wrongccs) 2044 slot->state = AHCI_SLOT_EXECUTING; 2045 else if ((ch->rslots & (1 << ccs)) == 0) { 2046 ch->wrongccs = 1; 2047 slot->state = AHCI_SLOT_EXECUTING; 2048 } 2049 2050 callout_reset(&slot->timeout, 2051 (int)slot->ccb->ccb_h.timeout * hz / 2000, 2052 (timeout_t*)ahci_timeout, slot); 2053 return; 2054 } 2055 2056 device_printf(dev, "Timeout on slot %d port %d\n", 2057 slot->slot, slot->ccb->ccb_h.target_id & 0x0f); 2058 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x " 2059 "serr %08x cmd %08x\n", 2060 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 2061 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 2062 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR), 2063 ATA_INL(ch->r_mem, AHCI_P_CMD)); 2064 2065 /* Handle frozen command. */ 2066 if (ch->frozen) { 2067 union ccb *fccb = ch->frozen; 2068 ch->frozen = NULL; 2069 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2070 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2071 xpt_freeze_devq(fccb->ccb_h.path, 1); 2072 fccb->ccb_h.status |= CAM_DEV_QFRZN; 2073 } 2074 ahci_done(ch, fccb); 2075 } 2076 if (!ch->fbs_enabled && !ch->wrongccs) { 2077 /* Without FBS we know real timeout source. */ 2078 ch->fatalerr = 1; 2079 /* Handle command with timeout. */ 2080 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 2081 /* Handle the rest of commands. */ 2082 for (i = 0; i < ch->numslots; i++) { 2083 /* Do we have a running request on slot? */ 2084 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2085 continue; 2086 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2087 } 2088 } else { 2089 /* With FBS we wait for other commands timeout and pray. */ 2090 if (ch->toslots == 0) 2091 xpt_freeze_simq(ch->sim, 1); 2092 ch->toslots |= (1 << slot->slot); 2093 if ((ch->rslots & ~ch->toslots) == 0) 2094 ahci_process_timeout(dev); 2095 else 2096 device_printf(dev, " ... waiting for slots %08x\n", 2097 ch->rslots & ~ch->toslots); 2098 } 2099} 2100 2101/* Must be called with channel locked. */ 2102static void 2103ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 2104{ 2105 device_t dev = slot->dev; 2106 struct ahci_channel *ch = device_get_softc(dev); 2107 union ccb *ccb = slot->ccb; 2108 struct ahci_cmd_list *clp; 2109 int lastto; 2110 uint32_t sig; 2111 2112 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 2113 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2114 clp = (struct ahci_cmd_list *) 2115 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 2116 /* Read result registers to the result struct 2117 * May be incorrect if several commands finished same time, 2118 * so read only when sure or have to. 2119 */ 2120 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2121 struct ata_res *res = &ccb->ataio.res; 2122 2123 if ((et == AHCI_ERR_TFE) || 2124 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 2125 u_int8_t *fis = ch->dma.rfis + 0x40; 2126 2127 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 2128 BUS_DMASYNC_POSTREAD); 2129 if (ch->fbs_enabled) { 2130 fis += ccb->ccb_h.target_id * 256; 2131 res->status = fis[2]; 2132 res->error = fis[3]; 2133 } else { 2134 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 2135 2136 res->status = tfd; 2137 res->error = tfd >> 8; 2138 } 2139 res->lba_low = fis[4]; 2140 res->lba_mid = fis[5]; 2141 res->lba_high = fis[6]; 2142 res->device = fis[7]; 2143 res->lba_low_exp = fis[8]; 2144 res->lba_mid_exp = fis[9]; 2145 res->lba_high_exp = fis[10]; 2146 res->sector_count = fis[12]; 2147 res->sector_count_exp = fis[13]; 2148 2149 /* 2150 * Some weird controllers do not return signature in 2151 * FIS receive area. Read it from PxSIG register. 2152 */ 2153 if ((ch->quirks & AHCI_Q_ALTSIG) && 2154 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2155 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 2156 sig = ATA_INL(ch->r_mem, AHCI_P_SIG); 2157 res->lba_high = sig >> 24; 2158 res->lba_mid = sig >> 16; 2159 res->lba_low = sig >> 8; 2160 res->sector_count = sig; 2161 } 2162 } else 2163 bzero(res, sizeof(*res)); 2164 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 && 2165 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2166 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2167 ccb->ataio.resid = 2168 ccb->ataio.dxfer_len - le32toh(clp->bytecount); 2169 } 2170 } else { 2171 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2172 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2173 ccb->csio.resid = 2174 ccb->csio.dxfer_len - le32toh(clp->bytecount); 2175 } 2176 } 2177 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2178 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 2179 (ccb->ccb_h.flags & CAM_DIR_IN) ? 2180 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2181 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 2182 } 2183 if (et != AHCI_ERR_NONE) 2184 ch->eslots |= (1 << slot->slot); 2185 /* In case of error, freeze device for proper recovery. */ 2186 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) && 2187 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 2188 xpt_freeze_devq(ccb->ccb_h.path, 1); 2189 ccb->ccb_h.status |= CAM_DEV_QFRZN; 2190 } 2191 /* Set proper result status. */ 2192 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2193 switch (et) { 2194 case AHCI_ERR_NONE: 2195 ccb->ccb_h.status |= CAM_REQ_CMP; 2196 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 2197 ccb->csio.scsi_status = SCSI_STATUS_OK; 2198 break; 2199 case AHCI_ERR_INVALID: 2200 ch->fatalerr = 1; 2201 ccb->ccb_h.status |= CAM_REQ_INVALID; 2202 break; 2203 case AHCI_ERR_INNOCENT: 2204 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 2205 break; 2206 case AHCI_ERR_TFE: 2207 case AHCI_ERR_NCQ: 2208 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2209 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 2210 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 2211 } else { 2212 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 2213 } 2214 break; 2215 case AHCI_ERR_SATA: 2216 ch->fatalerr = 1; 2217 if (!ch->recoverycmd) { 2218 xpt_freeze_simq(ch->sim, 1); 2219 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2220 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2221 } 2222 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 2223 break; 2224 case AHCI_ERR_TIMEOUT: 2225 if (!ch->recoverycmd) { 2226 xpt_freeze_simq(ch->sim, 1); 2227 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2228 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2229 } 2230 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 2231 break; 2232 default: 2233 ch->fatalerr = 1; 2234 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 2235 } 2236 /* Free slot. */ 2237 ch->oslots &= ~(1 << slot->slot); 2238 ch->rslots &= ~(1 << slot->slot); 2239 ch->aslots &= ~(1 << slot->slot); 2240 slot->state = AHCI_SLOT_EMPTY; 2241 slot->ccb = NULL; 2242 /* Update channel stats. */ 2243 ch->numrslots--; 2244 ch->numrslotspd[ccb->ccb_h.target_id]--; 2245 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2246 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 2247 ch->numtslots--; 2248 ch->numtslotspd[ccb->ccb_h.target_id]--; 2249 } 2250 /* Cancel timeout state if request completed normally. */ 2251 if (et != AHCI_ERR_TIMEOUT) { 2252 lastto = (ch->toslots == (1 << slot->slot)); 2253 ch->toslots &= ~(1 << slot->slot); 2254 if (lastto) 2255 xpt_release_simq(ch->sim, TRUE); 2256 } 2257 /* If it was first request of reset sequence and there is no error, 2258 * proceed to second request. */ 2259 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2260 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2261 (ccb->ataio.cmd.control & ATA_A_RESET) && 2262 et == AHCI_ERR_NONE) { 2263 ccb->ataio.cmd.control &= ~ATA_A_RESET; 2264 ahci_begin_transaction(dev, ccb); 2265 return; 2266 } 2267 /* If it was our READ LOG command - process it. */ 2268 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) { 2269 ahci_process_read_log(dev, ccb); 2270 /* If it was our REQUEST SENSE command - process it. */ 2271 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) { 2272 ahci_process_request_sense(dev, ccb); 2273 /* If it was NCQ or ATAPI command error, put result on hold. */ 2274 } else if (et == AHCI_ERR_NCQ || 2275 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 2276 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) { 2277 ch->hold[slot->slot] = ccb; 2278 ch->numhslots++; 2279 } else 2280 ahci_done(ch, ccb); 2281 /* If we have no other active commands, ... */ 2282 if (ch->rslots == 0) { 2283 /* if there was fatal error - reset port. */ 2284 if (ch->toslots != 0 || ch->fatalerr) { 2285 ahci_reset(dev); 2286 } else { 2287 /* if we have slots in error, we can reinit port. */ 2288 if (ch->eslots != 0) { 2289 ahci_stop(dev); 2290 ahci_clo(dev); 2291 ahci_start(dev, 1); 2292 } 2293 /* if there commands on hold, we can do READ LOG. */ 2294 if (!ch->recoverycmd && ch->numhslots) 2295 ahci_issue_recovery(dev); 2296 } 2297 /* If all the rest of commands are in timeout - give them chance. */ 2298 } else if ((ch->rslots & ~ch->toslots) == 0 && 2299 et != AHCI_ERR_TIMEOUT) 2300 ahci_rearm_timeout(dev); 2301 /* Unfreeze frozen command. */ 2302 if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) { 2303 union ccb *fccb = ch->frozen; 2304 ch->frozen = NULL; 2305 ahci_begin_transaction(dev, fccb); 2306 xpt_release_simq(ch->sim, TRUE); 2307 } 2308 /* Start PM timer. */ 2309 if (ch->numrslots == 0 && ch->pm_level > 3 && 2310 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 2311 callout_schedule(&ch->pm_timer, 2312 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 2313 } 2314} 2315 2316static void 2317ahci_issue_recovery(device_t dev) 2318{ 2319 struct ahci_channel *ch = device_get_softc(dev); 2320 union ccb *ccb; 2321 struct ccb_ataio *ataio; 2322 struct ccb_scsiio *csio; 2323 int i; 2324 2325 /* Find some held command. */ 2326 for (i = 0; i < ch->numslots; i++) { 2327 if (ch->hold[i]) 2328 break; 2329 } 2330 ccb = xpt_alloc_ccb_nowait(); 2331 if (ccb == NULL) { 2332 device_printf(dev, "Unable to allocate recovery command\n"); 2333completeall: 2334 /* We can't do anything -- complete held commands. */ 2335 for (i = 0; i < ch->numslots; i++) { 2336 if (ch->hold[i] == NULL) 2337 continue; 2338 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2339 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL; 2340 ahci_done(ch, ch->hold[i]); 2341 ch->hold[i] = NULL; 2342 ch->numhslots--; 2343 } 2344 ahci_reset(dev); 2345 return; 2346 } 2347 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 2348 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2349 /* READ LOG */ 2350 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG; 2351 ccb->ccb_h.func_code = XPT_ATA_IO; 2352 ccb->ccb_h.flags = CAM_DIR_IN; 2353 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2354 ataio = &ccb->ataio; 2355 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 2356 if (ataio->data_ptr == NULL) { 2357 xpt_free_ccb(ccb); 2358 device_printf(dev, 2359 "Unable to allocate memory for READ LOG command\n"); 2360 goto completeall; 2361 } 2362 ataio->dxfer_len = 512; 2363 bzero(&ataio->cmd, sizeof(ataio->cmd)); 2364 ataio->cmd.flags = CAM_ATAIO_48BIT; 2365 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 2366 ataio->cmd.sector_count = 1; 2367 ataio->cmd.sector_count_exp = 0; 2368 ataio->cmd.lba_low = 0x10; 2369 ataio->cmd.lba_mid = 0; 2370 ataio->cmd.lba_mid_exp = 0; 2371 } else { 2372 /* REQUEST SENSE */ 2373 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE; 2374 ccb->ccb_h.recovery_slot = i; 2375 ccb->ccb_h.func_code = XPT_SCSI_IO; 2376 ccb->ccb_h.flags = CAM_DIR_IN; 2377 ccb->ccb_h.status = 0; 2378 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2379 csio = &ccb->csio; 2380 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data; 2381 csio->dxfer_len = ch->hold[i]->csio.sense_len; 2382 csio->cdb_len = 6; 2383 bzero(&csio->cdb_io, sizeof(csio->cdb_io)); 2384 csio->cdb_io.cdb_bytes[0] = 0x03; 2385 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len; 2386 } 2387 /* Freeze SIM while doing recovery. */ 2388 ch->recoverycmd = 1; 2389 xpt_freeze_simq(ch->sim, 1); 2390 ahci_begin_transaction(dev, ccb); 2391} 2392 2393static void 2394ahci_process_read_log(device_t dev, union ccb *ccb) 2395{ 2396 struct ahci_channel *ch = device_get_softc(dev); 2397 uint8_t *data; 2398 struct ata_res *res; 2399 int i; 2400 2401 ch->recoverycmd = 0; 2402 2403 data = ccb->ataio.data_ptr; 2404 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 2405 (data[0] & 0x80) == 0) { 2406 for (i = 0; i < ch->numslots; i++) { 2407 if (!ch->hold[i]) 2408 continue; 2409 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2410 continue; 2411 if ((data[0] & 0x1F) == i) { 2412 res = &ch->hold[i]->ataio.res; 2413 res->status = data[2]; 2414 res->error = data[3]; 2415 res->lba_low = data[4]; 2416 res->lba_mid = data[5]; 2417 res->lba_high = data[6]; 2418 res->device = data[7]; 2419 res->lba_low_exp = data[8]; 2420 res->lba_mid_exp = data[9]; 2421 res->lba_high_exp = data[10]; 2422 res->sector_count = data[12]; 2423 res->sector_count_exp = data[13]; 2424 } else { 2425 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2426 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 2427 } 2428 ahci_done(ch, ch->hold[i]); 2429 ch->hold[i] = NULL; 2430 ch->numhslots--; 2431 } 2432 } else { 2433 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 2434 device_printf(dev, "Error while READ LOG EXT\n"); 2435 else if ((data[0] & 0x80) == 0) { 2436 device_printf(dev, "Non-queued command error in READ LOG EXT\n"); 2437 } 2438 for (i = 0; i < ch->numslots; i++) { 2439 if (!ch->hold[i]) 2440 continue; 2441 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2442 continue; 2443 ahci_done(ch, ch->hold[i]); 2444 ch->hold[i] = NULL; 2445 ch->numhslots--; 2446 } 2447 } 2448 free(ccb->ataio.data_ptr, M_AHCI); 2449 xpt_free_ccb(ccb); 2450 xpt_release_simq(ch->sim, TRUE); 2451} 2452 2453static void 2454ahci_process_request_sense(device_t dev, union ccb *ccb) 2455{ 2456 struct ahci_channel *ch = device_get_softc(dev); 2457 int i; 2458 2459 ch->recoverycmd = 0; 2460 2461 i = ccb->ccb_h.recovery_slot; 2462 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) { 2463 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID; 2464 } else { 2465 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2466 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL; 2467 } 2468 ahci_done(ch, ch->hold[i]); 2469 ch->hold[i] = NULL; 2470 ch->numhslots--; 2471 xpt_free_ccb(ccb); 2472 xpt_release_simq(ch->sim, TRUE); 2473} 2474 2475static void 2476ahci_start(device_t dev, int fbs) 2477{ 2478 struct ahci_channel *ch = device_get_softc(dev); 2479 u_int32_t cmd; 2480 2481 /* Clear SATA error register */ 2482 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 2483 /* Clear any interrupts pending on this channel */ 2484 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 2485 /* Configure FIS-based switching if supported. */ 2486 if (ch->chcaps & AHCI_P_CMD_FBSCP) { 2487 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0; 2488 ATA_OUTL(ch->r_mem, AHCI_P_FBS, 2489 ch->fbs_enabled ? AHCI_P_FBS_EN : 0); 2490 } 2491 /* Start operations on this channel */ 2492 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2493 cmd &= ~AHCI_P_CMD_PMA; 2494 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 2495 (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 2496} 2497 2498static void 2499ahci_stop(device_t dev) 2500{ 2501 struct ahci_channel *ch = device_get_softc(dev); 2502 u_int32_t cmd; 2503 int timeout; 2504 2505 /* Kill all activity on this channel */ 2506 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2507 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 2508 /* Wait for activity stop. */ 2509 timeout = 0; 2510 do { 2511 DELAY(10); 2512 if (timeout++ > 50000) { 2513 device_printf(dev, "stopping AHCI engine failed\n"); 2514 break; 2515 } 2516 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 2517 ch->eslots = 0; 2518} 2519 2520static void 2521ahci_clo(device_t dev) 2522{ 2523 struct ahci_channel *ch = device_get_softc(dev); 2524 u_int32_t cmd; 2525 int timeout; 2526 2527 /* Issue Command List Override if supported */ 2528 if (ch->caps & AHCI_CAP_SCLO) { 2529 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2530 cmd |= AHCI_P_CMD_CLO; 2531 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 2532 timeout = 0; 2533 do { 2534 DELAY(10); 2535 if (timeout++ > 50000) { 2536 device_printf(dev, "executing CLO failed\n"); 2537 break; 2538 } 2539 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 2540 } 2541} 2542 2543static void 2544ahci_stop_fr(device_t dev) 2545{ 2546 struct ahci_channel *ch = device_get_softc(dev); 2547 u_int32_t cmd; 2548 int timeout; 2549 2550 /* Kill all FIS reception on this channel */ 2551 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2552 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 2553 /* Wait for FIS reception stop. */ 2554 timeout = 0; 2555 do { 2556 DELAY(10); 2557 if (timeout++ > 50000) { 2558 device_printf(dev, "stopping AHCI FR engine failed\n"); 2559 break; 2560 } 2561 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 2562} 2563 2564static void 2565ahci_start_fr(device_t dev) 2566{ 2567 struct ahci_channel *ch = device_get_softc(dev); 2568 u_int32_t cmd; 2569 2570 /* Start FIS reception on this channel */ 2571 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2572 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 2573} 2574 2575static int 2576ahci_wait_ready(device_t dev, int t, int t0) 2577{ 2578 struct ahci_channel *ch = device_get_softc(dev); 2579 int timeout = 0; 2580 uint32_t val; 2581 2582 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 2583 (ATA_S_BUSY | ATA_S_DRQ)) { 2584 if (timeout > t) { 2585 if (t != 0) { 2586 device_printf(dev, 2587 "AHCI reset: device not ready after %dms " 2588 "(tfd = %08x)\n", 2589 MAX(t, 0) + t0, val); 2590 } 2591 return (EBUSY); 2592 } 2593 DELAY(1000); 2594 timeout++; 2595 } 2596 if (bootverbose) 2597 device_printf(dev, "AHCI reset: device ready after %dms\n", 2598 timeout + t0); 2599 return (0); 2600} 2601 2602static void 2603ahci_reset_to(void *arg) 2604{ 2605 device_t dev = arg; 2606 struct ahci_channel *ch = device_get_softc(dev); 2607 2608 if (ch->resetting == 0) 2609 return; 2610 ch->resetting--; 2611 if (ahci_wait_ready(dev, ch->resetting == 0 ? -1 : 0, 2612 (310 - ch->resetting) * 100) == 0) { 2613 ch->resetting = 0; 2614 ahci_start(dev, 1); 2615 xpt_release_simq(ch->sim, TRUE); 2616 return; 2617 } 2618 if (ch->resetting == 0) { 2619 ahci_clo(dev); 2620 ahci_start(dev, 1); 2621 xpt_release_simq(ch->sim, TRUE); 2622 return; 2623 } 2624 callout_schedule(&ch->reset_timer, hz / 10); 2625} 2626 2627static void 2628ahci_reset(device_t dev) 2629{ 2630 struct ahci_channel *ch = device_get_softc(dev); 2631 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2632 int i; 2633 2634 xpt_freeze_simq(ch->sim, 1); 2635 if (bootverbose) 2636 device_printf(dev, "AHCI reset...\n"); 2637 /* Forget about previous reset. */ 2638 if (ch->resetting) { 2639 ch->resetting = 0; 2640 callout_stop(&ch->reset_timer); 2641 xpt_release_simq(ch->sim, TRUE); 2642 } 2643 /* Requeue freezed command. */ 2644 if (ch->frozen) { 2645 union ccb *fccb = ch->frozen; 2646 ch->frozen = NULL; 2647 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2648 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2649 xpt_freeze_devq(fccb->ccb_h.path, 1); 2650 fccb->ccb_h.status |= CAM_DEV_QFRZN; 2651 } 2652 ahci_done(ch, fccb); 2653 } 2654 /* Kill the engine and requeue all running commands. */ 2655 ahci_stop(dev); 2656 for (i = 0; i < ch->numslots; i++) { 2657 /* Do we have a running request on slot? */ 2658 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2659 continue; 2660 /* XXX; Commands in loading state. */ 2661 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2662 } 2663 for (i = 0; i < ch->numslots; i++) { 2664 if (!ch->hold[i]) 2665 continue; 2666 ahci_done(ch, ch->hold[i]); 2667 ch->hold[i] = NULL; 2668 ch->numhslots--; 2669 } 2670 if (ch->toslots != 0) 2671 xpt_release_simq(ch->sim, TRUE); 2672 ch->eslots = 0; 2673 ch->toslots = 0; 2674 ch->wrongccs = 0; 2675 ch->fatalerr = 0; 2676 /* Tell the XPT about the event */ 2677 xpt_async(AC_BUS_RESET, ch->path, NULL); 2678 /* Disable port interrupts */ 2679 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 2680 /* Reset and reconnect PHY, */ 2681 if (!ahci_sata_phy_reset(dev)) { 2682 if (bootverbose) 2683 device_printf(dev, 2684 "AHCI reset: device not found\n"); 2685 ch->devices = 0; 2686 /* Enable wanted port interrupts */ 2687 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2688 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2689 AHCI_P_IX_PRC | AHCI_P_IX_PC)); 2690 xpt_release_simq(ch->sim, TRUE); 2691 return; 2692 } 2693 if (bootverbose) 2694 device_printf(dev, "AHCI reset: device found\n"); 2695 /* Wait for clearing busy status. */ 2696 if (ahci_wait_ready(dev, dumping ? 31000 : 0, 0)) { 2697 if (dumping) 2698 ahci_clo(dev); 2699 else 2700 ch->resetting = 310; 2701 } 2702 ch->devices = 1; 2703 /* Enable wanted port interrupts */ 2704 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2705 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2706 AHCI_P_IX_TFE | AHCI_P_IX_HBF | 2707 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 2708 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC | 2709 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 2710 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 2711 if (ch->resetting) 2712 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, dev); 2713 else { 2714 ahci_start(dev, 1); 2715 xpt_release_simq(ch->sim, TRUE); 2716 } 2717} 2718 2719static int 2720ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 2721{ 2722 struct ahci_channel *ch = device_get_softc(dev); 2723 u_int8_t *fis = &ctp->cfis[0]; 2724 2725 bzero(ctp->cfis, 16); 2726 fis[0] = 0x27; /* host to device */ 2727 fis[1] = (ccb->ccb_h.target_id & 0x0f); 2728 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2729 fis[1] |= 0x80; 2730 fis[2] = ATA_PACKET_CMD; 2731 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2732 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 2733 fis[3] = ATA_F_DMA; 2734 else { 2735 fis[5] = ccb->csio.dxfer_len; 2736 fis[6] = ccb->csio.dxfer_len >> 8; 2737 } 2738 fis[7] = ATA_D_LBA; 2739 fis[15] = ATA_A_4BIT; 2740 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 2741 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 2742 ctp->acmd, ccb->csio.cdb_len); 2743 bzero(ctp->acmd + ccb->csio.cdb_len, 32 - ccb->csio.cdb_len); 2744 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 2745 fis[1] |= 0x80; 2746 fis[2] = ccb->ataio.cmd.command; 2747 fis[3] = ccb->ataio.cmd.features; 2748 fis[4] = ccb->ataio.cmd.lba_low; 2749 fis[5] = ccb->ataio.cmd.lba_mid; 2750 fis[6] = ccb->ataio.cmd.lba_high; 2751 fis[7] = ccb->ataio.cmd.device; 2752 fis[8] = ccb->ataio.cmd.lba_low_exp; 2753 fis[9] = ccb->ataio.cmd.lba_mid_exp; 2754 fis[10] = ccb->ataio.cmd.lba_high_exp; 2755 fis[11] = ccb->ataio.cmd.features_exp; 2756 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 2757 fis[12] = tag << 3; 2758 fis[13] = 0; 2759 } else { 2760 fis[12] = ccb->ataio.cmd.sector_count; 2761 fis[13] = ccb->ataio.cmd.sector_count_exp; 2762 } 2763 fis[15] = ATA_A_4BIT; 2764 } else { 2765 fis[15] = ccb->ataio.cmd.control; 2766 } 2767 return (20); 2768} 2769 2770static int 2771ahci_sata_connect(struct ahci_channel *ch) 2772{ 2773 u_int32_t status; 2774 int timeout, found = 0; 2775 2776 /* Wait up to 100ms for "connect well" */ 2777 for (timeout = 0; timeout < 1000 ; timeout++) { 2778 status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 2779 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 2780 found = 1; 2781 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 2782 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 2783 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 2784 break; 2785 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 2786 if (bootverbose) { 2787 device_printf(ch->dev, "SATA offline status=%08x\n", 2788 status); 2789 } 2790 return (0); 2791 } 2792 if (found == 0 && timeout >= 100) 2793 break; 2794 DELAY(100); 2795 } 2796 if (timeout >= 1000 || !found) { 2797 if (bootverbose) { 2798 device_printf(ch->dev, 2799 "SATA connect timeout time=%dus status=%08x\n", 2800 timeout * 100, status); 2801 } 2802 return (0); 2803 } 2804 if (bootverbose) { 2805 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n", 2806 timeout * 100, status); 2807 } 2808 /* Clear SATA error register */ 2809 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 2810 return (1); 2811} 2812 2813static int 2814ahci_sata_phy_reset(device_t dev) 2815{ 2816 struct ahci_channel *ch = device_get_softc(dev); 2817 int sata_rev; 2818 uint32_t val; 2819 2820 if (ch->listening) { 2821 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2822 val |= AHCI_P_CMD_SUD; 2823 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2824 ch->listening = 0; 2825 } 2826 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 2827 if (sata_rev == 1) 2828 val = ATA_SC_SPD_SPEED_GEN1; 2829 else if (sata_rev == 2) 2830 val = ATA_SC_SPD_SPEED_GEN2; 2831 else if (sata_rev == 3) 2832 val = ATA_SC_SPD_SPEED_GEN3; 2833 else 2834 val = 0; 2835 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2836 ATA_SC_DET_RESET | val | 2837 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 2838 DELAY(1000); 2839 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2840 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 2841 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 2842 if (!ahci_sata_connect(ch)) { 2843 if (ch->caps & AHCI_CAP_SSS) { 2844 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2845 val &= ~AHCI_P_CMD_SUD; 2846 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2847 ch->listening = 1; 2848 } else if (ch->pm_level > 0) 2849 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 2850 return (0); 2851 } 2852 return (1); 2853} 2854 2855static int 2856ahci_check_ids(device_t dev, union ccb *ccb) 2857{ 2858 struct ahci_channel *ch = device_get_softc(dev); 2859 2860 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) { 2861 ccb->ccb_h.status = CAM_TID_INVALID; 2862 ahci_done(ch, ccb); 2863 return (-1); 2864 } 2865 if (ccb->ccb_h.target_lun != 0) { 2866 ccb->ccb_h.status = CAM_LUN_INVALID; 2867 ahci_done(ch, ccb); 2868 return (-1); 2869 } 2870 return (0); 2871} 2872 2873static void 2874ahciaction(struct cam_sim *sim, union ccb *ccb) 2875{ 2876 device_t dev, parent; 2877 struct ahci_channel *ch; 2878 2879 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 2880 ccb->ccb_h.func_code)); 2881 2882 ch = (struct ahci_channel *)cam_sim_softc(sim); 2883 dev = ch->dev; 2884 switch (ccb->ccb_h.func_code) { 2885 /* Common cases first */ 2886 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2887 case XPT_SCSI_IO: 2888 if (ahci_check_ids(dev, ccb)) 2889 return; 2890 if (ch->devices == 0 || 2891 (ch->pm_present == 0 && 2892 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 2893 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2894 break; 2895 } 2896 ccb->ccb_h.recovery_type = RECOVERY_NONE; 2897 /* Check for command collision. */ 2898 if (ahci_check_collision(dev, ccb)) { 2899 /* Freeze command. */ 2900 ch->frozen = ccb; 2901 /* We have only one frozen slot, so freeze simq also. */ 2902 xpt_freeze_simq(ch->sim, 1); 2903 return; 2904 } 2905 ahci_begin_transaction(dev, ccb); 2906 return; 2907 case XPT_EN_LUN: /* Enable LUN as a target */ 2908 case XPT_TARGET_IO: /* Execute target I/O request */ 2909 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2910 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2911 case XPT_ABORT: /* Abort the specified CCB */ 2912 /* XXX Implement */ 2913 ccb->ccb_h.status = CAM_REQ_INVALID; 2914 break; 2915 case XPT_SET_TRAN_SETTINGS: 2916 { 2917 struct ccb_trans_settings *cts = &ccb->cts; 2918 struct ahci_device *d; 2919 2920 if (ahci_check_ids(dev, ccb)) 2921 return; 2922 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2923 d = &ch->curr[ccb->ccb_h.target_id]; 2924 else 2925 d = &ch->user[ccb->ccb_h.target_id]; 2926 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2927 d->revision = cts->xport_specific.sata.revision; 2928 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2929 d->mode = cts->xport_specific.sata.mode; 2930 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 2931 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 2932 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2933 d->tags = min(ch->numslots, cts->xport_specific.sata.tags); 2934 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2935 ch->pm_present = cts->xport_specific.sata.pm_present; 2936 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2937 d->atapi = cts->xport_specific.sata.atapi; 2938 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 2939 d->caps = cts->xport_specific.sata.caps; 2940 ccb->ccb_h.status = CAM_REQ_CMP; 2941 break; 2942 } 2943 case XPT_GET_TRAN_SETTINGS: 2944 /* Get default/user set transfer settings for the target */ 2945 { 2946 struct ccb_trans_settings *cts = &ccb->cts; 2947 struct ahci_device *d; 2948 uint32_t status; 2949 2950 if (ahci_check_ids(dev, ccb)) 2951 return; 2952 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2953 d = &ch->curr[ccb->ccb_h.target_id]; 2954 else 2955 d = &ch->user[ccb->ccb_h.target_id]; 2956 cts->protocol = PROTO_UNSPECIFIED; 2957 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2958 cts->transport = XPORT_SATA; 2959 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2960 cts->proto_specific.valid = 0; 2961 cts->xport_specific.sata.valid = 0; 2962 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 2963 (ccb->ccb_h.target_id == 15 || 2964 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 2965 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 2966 if (status & 0x0f0) { 2967 cts->xport_specific.sata.revision = 2968 (status & 0x0f0) >> 4; 2969 cts->xport_specific.sata.valid |= 2970 CTS_SATA_VALID_REVISION; 2971 } 2972 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 2973 if (ch->pm_level) { 2974 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC)) 2975 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 2976 if (ch->caps2 & AHCI_CAP2_APST) 2977 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST; 2978 } 2979 if ((ch->caps & AHCI_CAP_SNCQ) && 2980 (ch->quirks & AHCI_Q_NOAA) == 0) 2981 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA; 2982 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN; 2983 cts->xport_specific.sata.caps &= 2984 ch->user[ccb->ccb_h.target_id].caps; 2985 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2986 } else { 2987 cts->xport_specific.sata.revision = d->revision; 2988 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 2989 cts->xport_specific.sata.caps = d->caps; 2990 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2991 } 2992 cts->xport_specific.sata.mode = d->mode; 2993 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 2994 cts->xport_specific.sata.bytecount = d->bytecount; 2995 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 2996 cts->xport_specific.sata.pm_present = ch->pm_present; 2997 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2998 cts->xport_specific.sata.tags = d->tags; 2999 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 3000 cts->xport_specific.sata.atapi = d->atapi; 3001 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 3002 ccb->ccb_h.status = CAM_REQ_CMP; 3003 break; 3004 } 3005 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 3006 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 3007 ahci_reset(dev); 3008 ccb->ccb_h.status = CAM_REQ_CMP; 3009 break; 3010 case XPT_TERM_IO: /* Terminate the I/O process */ 3011 /* XXX Implement */ 3012 ccb->ccb_h.status = CAM_REQ_INVALID; 3013 break; 3014 case XPT_PATH_INQ: /* Path routing inquiry */ 3015 { 3016 struct ccb_pathinq *cpi = &ccb->cpi; 3017 3018 parent = device_get_parent(dev); 3019 cpi->version_num = 1; /* XXX??? */ 3020 cpi->hba_inquiry = PI_SDTR_ABLE; 3021 if (ch->caps & AHCI_CAP_SNCQ) 3022 cpi->hba_inquiry |= PI_TAG_ABLE; 3023 if (ch->caps & AHCI_CAP_SPM) 3024 cpi->hba_inquiry |= PI_SATAPM; 3025 cpi->target_sprt = 0; 3026 cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED; 3027 cpi->hba_eng_cnt = 0; 3028 if (ch->caps & AHCI_CAP_SPM) 3029 cpi->max_target = 15; 3030 else 3031 cpi->max_target = 0; 3032 cpi->max_lun = 0; 3033 cpi->initiator_id = 0; 3034 cpi->bus_id = cam_sim_bus(sim); 3035 cpi->base_transfer_speed = 150000; 3036 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 3037 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 3038 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 3039 cpi->unit_number = cam_sim_unit(sim); 3040 cpi->transport = XPORT_SATA; 3041 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 3042 cpi->protocol = PROTO_ATA; 3043 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 3044 cpi->maxio = MAXPHYS; 3045 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 3046 if (pci_get_devid(parent) == 0x43801002) 3047 cpi->maxio = min(cpi->maxio, 128 * 512); 3048 cpi->hba_vendor = pci_get_vendor(parent); 3049 cpi->hba_device = pci_get_device(parent); 3050 cpi->hba_subvendor = pci_get_subvendor(parent); 3051 cpi->hba_subdevice = pci_get_subdevice(parent); 3052 cpi->ccb_h.status = CAM_REQ_CMP; 3053 break; 3054 } 3055 default: 3056 ccb->ccb_h.status = CAM_REQ_INVALID; 3057 break; 3058 } 3059 ahci_done(ch, ccb); 3060} 3061 3062static void 3063ahcipoll(struct cam_sim *sim) 3064{ 3065 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 3066 uint32_t istatus; 3067 3068 /* Read interrupt statuses and process if any. */ 3069 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 3070 if (istatus != 0) 3071 ahci_ch_intr_main(ch, istatus); 3072 if (ch->resetting != 0 && 3073 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) { 3074 ch->resetpolldiv = 1000; 3075 ahci_reset_to(ch->dev); 3076 } 3077} 3078