ahci_pci.c revision 203030
189857Sobrien/*- 2104834Sobrien * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org> 389857Sobrien * All rights reserved. 489857Sobrien * 589857Sobrien * Redistribution and use in source and binary forms, with or without 689857Sobrien * modification, are permitted provided that the following conditions 789857Sobrien * are met: 889857Sobrien * 1. Redistributions of source code must retain the above copyright 989857Sobrien * notice, this list of conditions and the following disclaimer, 1089857Sobrien * without modification, immediately at the beginning of the file. 1189857Sobrien * 2. Redistributions in binary form must reproduce the above copyright 1289857Sobrien * notice, this list of conditions and the following disclaimer in the 1389857Sobrien * documentation and/or other materials provided with the distribution. 1489857Sobrien * 1589857Sobrien * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1689857Sobrien * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1789857Sobrien * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1889857Sobrien * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19218822Sdim * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20218822Sdim * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2189857Sobrien * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2289857Sobrien * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2389857Sobrien * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2489857Sobrien * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2589857Sobrien */ 2689857Sobrien 2789857Sobrien#include <sys/cdefs.h> 2889857Sobrien__FBSDID("$FreeBSD: head/sys/dev/ahci/ahci.c 203030 2010-01-26 15:25:24Z mav $"); 2989857Sobrien 3089857Sobrien#include <sys/param.h> 3189857Sobrien#include <sys/module.h> 3289857Sobrien#include <sys/systm.h> 3389857Sobrien#include <sys/kernel.h> 3489857Sobrien#include <sys/ata.h> 3589857Sobrien#include <sys/bus.h> 3689857Sobrien#include <sys/endian.h> 3789857Sobrien#include <sys/malloc.h> 3889857Sobrien#include <sys/lock.h> 3989857Sobrien#include <sys/mutex.h> 4089857Sobrien#include <sys/sema.h> 4189857Sobrien#include <sys/taskqueue.h> 4289857Sobrien#include <vm/uma.h> 43104834Sobrien#include <machine/stdarg.h> 4489857Sobrien#include <machine/resource.h> 4589857Sobrien#include <machine/bus.h> 4689857Sobrien#include <sys/rman.h> 4789857Sobrien#include <dev/pci/pcivar.h> 4889857Sobrien#include <dev/pci/pcireg.h> 4989857Sobrien#include "ahci.h" 5089857Sobrien 5189857Sobrien#include <cam/cam.h> 5289857Sobrien#include <cam/cam_ccb.h> 5389857Sobrien#include <cam/cam_sim.h> 5489857Sobrien#include <cam/cam_xpt_sim.h> 5589857Sobrien#include <cam/cam_xpt_periph.h> 5689857Sobrien#include <cam/cam_debug.h> 5789857Sobrien 5889857Sobrien/* local prototypes */ 5989857Sobrienstatic int ahci_setup_interrupt(device_t dev); 6089857Sobrienstatic void ahci_intr(void *data); 6189857Sobrienstatic void ahci_intr_one(void *data); 62218822Sdimstatic int ahci_suspend(device_t dev); 63130561Sobrienstatic int ahci_resume(device_t dev); 64130561Sobrienstatic int ahci_ch_suspend(device_t dev); 65130561Sobrienstatic int ahci_ch_resume(device_t dev); 6689857Sobrienstatic void ahci_ch_pm(void *arg); 6789857Sobrienstatic void ahci_ch_intr_locked(void *data); 68130561Sobrienstatic void ahci_ch_intr(void *data); 6989857Sobrienstatic int ahci_ctlr_reset(device_t dev); 7089857Sobrienstatic void ahci_begin_transaction(device_t dev, union ccb *ccb); 71218822Sdimstatic void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 72218822Sdimstatic void ahci_execute_transaction(struct ahci_slot *slot); 73218822Sdimstatic void ahci_timeout(struct ahci_slot *slot); 74218822Sdimstatic void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 75218822Sdimstatic int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 76218822Sdimstatic void ahci_dmainit(device_t dev); 77218822Sdimstatic void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 78218822Sdimstatic void ahci_dmafini(device_t dev); 79218822Sdimstatic void ahci_slotsalloc(device_t dev); 80218822Sdimstatic void ahci_slotsfree(device_t dev); 81218822Sdimstatic void ahci_reset(device_t dev); 82218822Sdimstatic void ahci_start(device_t dev); 83218822Sdimstatic void ahci_stop(device_t dev); 84218822Sdimstatic void ahci_clo(device_t dev); 8589857Sobrienstatic void ahci_start_fr(device_t dev); 8689857Sobrienstatic void ahci_stop_fr(device_t dev); 87 88static int ahci_sata_connect(struct ahci_channel *ch); 89static int ahci_sata_phy_reset(device_t dev, int quick); 90 91static void ahci_issue_read_log(device_t dev); 92static void ahci_process_read_log(device_t dev, union ccb *ccb); 93 94static void ahciaction(struct cam_sim *sim, union ccb *ccb); 95static void ahcipoll(struct cam_sim *sim); 96 97MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 98 99static struct { 100 uint32_t id; 101 uint8_t rev; 102 const char *name; 103 int quirks; 104#define AHCI_Q_NOFORCE 1 105#define AHCI_Q_NOPMP 2 106#define AHCI_Q_NONCQ 4 107#define AHCI_Q_1CH 8 108#define AHCI_Q_2CH 16 109#define AHCI_Q_4CH 32 110#define AHCI_Q_EDGEIS 64 111#define AHCI_Q_SATA2 128 112} ahci_ids[] = { 113 {0x43801002, 0x00, "ATI IXP600", 0}, 114 {0x43901002, 0x00, "ATI IXP700", 0}, 115 {0x43911002, 0x00, "ATI IXP700", 0}, 116 {0x43921002, 0x00, "ATI IXP700", 0}, 117 {0x43931002, 0x00, "ATI IXP700", 0}, 118 {0x43941002, 0x00, "ATI IXP800", 0}, 119 {0x43951002, 0x00, "ATI IXP800", 0}, 120 {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE}, 121 {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE}, 122 {0x26818086, 0x00, "Intel ESB2", 0}, 123 {0x26828086, 0x00, "Intel ESB2", 0}, 124 {0x26838086, 0x00, "Intel ESB2", 0}, 125 {0x27c18086, 0x00, "Intel ICH7", 0}, 126 {0x27c38086, 0x00, "Intel ICH7", 0}, 127 {0x27c58086, 0x00, "Intel ICH7M", 0}, 128 {0x27c68086, 0x00, "Intel ICH7M", 0}, 129 {0x28218086, 0x00, "Intel ICH8", 0}, 130 {0x28228086, 0x00, "Intel ICH8", 0}, 131 {0x28248086, 0x00, "Intel ICH8", 0}, 132 {0x28298086, 0x00, "Intel ICH8M", 0}, 133 {0x282a8086, 0x00, "Intel ICH8M", 0}, 134 {0x29228086, 0x00, "Intel ICH9", 0}, 135 {0x29238086, 0x00, "Intel ICH9", 0}, 136 {0x29248086, 0x00, "Intel ICH9", 0}, 137 {0x29258086, 0x00, "Intel ICH9", 0}, 138 {0x29278086, 0x00, "Intel ICH9", 0}, 139 {0x29298086, 0x00, "Intel ICH9M", 0}, 140 {0x292a8086, 0x00, "Intel ICH9M", 0}, 141 {0x292b8086, 0x00, "Intel ICH9M", 0}, 142 {0x292c8086, 0x00, "Intel ICH9M", 0}, 143 {0x292f8086, 0x00, "Intel ICH9M", 0}, 144 {0x294d8086, 0x00, "Intel ICH9", 0}, 145 {0x294e8086, 0x00, "Intel ICH9M", 0}, 146 {0x3a058086, 0x00, "Intel ICH10", 0}, 147 {0x3a228086, 0x00, "Intel ICH10", 0}, 148 {0x3a258086, 0x00, "Intel ICH10", 0}, 149 {0x3b228086, 0x00, "Intel PCH", 0}, 150 {0x3b238086, 0x00, "Intel PCH", 0}, 151 {0x3b248086, 0x00, "Intel PCH", 0}, 152 {0x3b258086, 0x00, "Intel PCH", 0}, 153 {0x3b298086, 0x00, "Intel PCH", 0}, 154 {0x3b2b8086, 0x00, "Intel PCH", 0}, 155 {0x3b2c8086, 0x00, "Intel PCH", 0}, 156 {0x3b2f8086, 0x00, "Intel PCH", 0}, 157 {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE}, 158 {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE}, 159 {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE}, 160 {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE}, 161 {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE}, 162 {0x611111ab, 0x00, "Marvell 88SX6111", AHCI_Q_NOFORCE|AHCI_Q_1CH|AHCI_Q_EDGEIS}, 163 {0x612111ab, 0x00, "Marvell 88SX6121", AHCI_Q_NOFORCE|AHCI_Q_2CH|AHCI_Q_EDGEIS}, 164 {0x614111ab, 0x00, "Marvell 88SX6141", AHCI_Q_NOFORCE|AHCI_Q_4CH|AHCI_Q_EDGEIS}, 165 {0x614511ab, 0x00, "Marvell 88SX6145", AHCI_Q_NOFORCE|AHCI_Q_4CH|AHCI_Q_EDGEIS}, 166 {0x91231b4b, 0x11, "Marvell 88SE912x", 0}, 167 {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2}, 168 {0x044c10de, 0x00, "NVIDIA MCP65", 0}, 169 {0x044d10de, 0x00, "NVIDIA MCP65", 0}, 170 {0x044e10de, 0x00, "NVIDIA MCP65", 0}, 171 {0x044f10de, 0x00, "NVIDIA MCP65", 0}, 172 {0x045c10de, 0x00, "NVIDIA MCP65", 0}, 173 {0x045d10de, 0x00, "NVIDIA MCP65", 0}, 174 {0x045e10de, 0x00, "NVIDIA MCP65", 0}, 175 {0x045f10de, 0x00, "NVIDIA MCP65", 0}, 176 {0x055010de, 0x00, "NVIDIA MCP67", 0}, 177 {0x055110de, 0x00, "NVIDIA MCP67", 0}, 178 {0x055210de, 0x00, "NVIDIA MCP67", 0}, 179 {0x055310de, 0x00, "NVIDIA MCP67", 0}, 180 {0x055410de, 0x00, "NVIDIA MCP67", 0}, 181 {0x055510de, 0x00, "NVIDIA MCP67", 0}, 182 {0x055610de, 0x00, "NVIDIA MCP67", 0}, 183 {0x055710de, 0x00, "NVIDIA MCP67", 0}, 184 {0x055810de, 0x00, "NVIDIA MCP67", 0}, 185 {0x055910de, 0x00, "NVIDIA MCP67", 0}, 186 {0x055A10de, 0x00, "NVIDIA MCP67", 0}, 187 {0x055B10de, 0x00, "NVIDIA MCP67", 0}, 188 {0x058410de, 0x00, "NVIDIA MCP67", 0}, 189 {0x07f010de, 0x00, "NVIDIA MCP73", 0}, 190 {0x07f110de, 0x00, "NVIDIA MCP73", 0}, 191 {0x07f210de, 0x00, "NVIDIA MCP73", 0}, 192 {0x07f310de, 0x00, "NVIDIA MCP73", 0}, 193 {0x07f410de, 0x00, "NVIDIA MCP73", 0}, 194 {0x07f510de, 0x00, "NVIDIA MCP73", 0}, 195 {0x07f610de, 0x00, "NVIDIA MCP73", 0}, 196 {0x07f710de, 0x00, "NVIDIA MCP73", 0}, 197 {0x07f810de, 0x00, "NVIDIA MCP73", 0}, 198 {0x07f910de, 0x00, "NVIDIA MCP73", 0}, 199 {0x07fa10de, 0x00, "NVIDIA MCP73", 0}, 200 {0x07fb10de, 0x00, "NVIDIA MCP73", 0}, 201 {0x0ad010de, 0x00, "NVIDIA MCP77", 0}, 202 {0x0ad110de, 0x00, "NVIDIA MCP77", 0}, 203 {0x0ad210de, 0x00, "NVIDIA MCP77", 0}, 204 {0x0ad310de, 0x00, "NVIDIA MCP77", 0}, 205 {0x0ad410de, 0x00, "NVIDIA MCP77", 0}, 206 {0x0ad510de, 0x00, "NVIDIA MCP77", 0}, 207 {0x0ad610de, 0x00, "NVIDIA MCP77", 0}, 208 {0x0ad710de, 0x00, "NVIDIA MCP77", 0}, 209 {0x0ad810de, 0x00, "NVIDIA MCP77", 0}, 210 {0x0ad910de, 0x00, "NVIDIA MCP77", 0}, 211 {0x0ada10de, 0x00, "NVIDIA MCP77", 0}, 212 {0x0adb10de, 0x00, "NVIDIA MCP77", 0}, 213 {0x0ab410de, 0x00, "NVIDIA MCP79", 0}, 214 {0x0ab510de, 0x00, "NVIDIA MCP79", 0}, 215 {0x0ab610de, 0x00, "NVIDIA MCP79", 0}, 216 {0x0ab710de, 0x00, "NVIDIA MCP79", 0}, 217 {0x0ab810de, 0x00, "NVIDIA MCP79", 0}, 218 {0x0ab910de, 0x00, "NVIDIA MCP79", 0}, 219 {0x0aba10de, 0x00, "NVIDIA MCP79", 0}, 220 {0x0abb10de, 0x00, "NVIDIA MCP79", 0}, 221 {0x0abc10de, 0x00, "NVIDIA MCP79", 0}, 222 {0x0abd10de, 0x00, "NVIDIA MCP79", 0}, 223 {0x0abe10de, 0x00, "NVIDIA MCP79", 0}, 224 {0x0abf10de, 0x00, "NVIDIA MCP79", 0}, 225 {0x0d8410de, 0x00, "NVIDIA MCP89", 0}, 226 {0x0d8510de, 0x00, "NVIDIA MCP89", 0}, 227 {0x0d8610de, 0x00, "NVIDIA MCP89", 0}, 228 {0x0d8710de, 0x00, "NVIDIA MCP89", 0}, 229 {0x0d8810de, 0x00, "NVIDIA MCP89", 0}, 230 {0x0d8910de, 0x00, "NVIDIA MCP89", 0}, 231 {0x0d8a10de, 0x00, "NVIDIA MCP89", 0}, 232 {0x0d8b10de, 0x00, "NVIDIA MCP89", 0}, 233 {0x0d8c10de, 0x00, "NVIDIA MCP89", 0}, 234 {0x0d8d10de, 0x00, "NVIDIA MCP89", 0}, 235 {0x0d8e10de, 0x00, "NVIDIA MCP89", 0}, 236 {0x0d8f10de, 0x00, "NVIDIA MCP89", 0}, 237 {0x33491106, 0x00, "VIA VT8251", 0}, 238 {0x62871106, 0x00, "VIA VT8251", 0}, 239 {0x11841039, 0x00, "SiS 966", 0}, 240 {0x11851039, 0x00, "SiS 968", 0}, 241 {0x01861039, 0x00, "SiS 968", 0}, 242 {0x00000000, 0x00, NULL, 0} 243}; 244 245static int 246ahci_probe(device_t dev) 247{ 248 char buf[64]; 249 int i, valid = 0; 250 uint32_t devid = pci_get_devid(dev); 251 uint8_t revid = pci_get_revid(dev); 252 253 /* Is this a possible AHCI candidate? */ 254 if (pci_get_class(dev) == PCIC_STORAGE && 255 pci_get_subclass(dev) == PCIS_STORAGE_SATA && 256 pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0) 257 valid = 1; 258 /* Is this a known AHCI chip? */ 259 for (i = 0; ahci_ids[i].id != 0; i++) { 260 if (ahci_ids[i].id == devid && 261 ahci_ids[i].rev <= revid && 262 (valid || !(ahci_ids[i].quirks & AHCI_Q_NOFORCE))) { 263 /* Do not attach JMicrons with single PCI function. */ 264 if (pci_get_vendor(dev) == 0x197b && 265 (pci_read_config(dev, 0xdf, 1) & 0x40) == 0) 266 return (ENXIO); 267 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 268 ahci_ids[i].name); 269 device_set_desc_copy(dev, buf); 270 return (BUS_PROBE_VENDOR); 271 } 272 } 273 if (!valid) 274 return (ENXIO); 275 device_set_desc_copy(dev, "AHCI SATA controller"); 276 return (BUS_PROBE_VENDOR); 277} 278 279static int 280ahci_ata_probe(device_t dev) 281{ 282 char buf[64]; 283 int i; 284 uint32_t devid = pci_get_devid(dev); 285 uint8_t revid = pci_get_revid(dev); 286 287 if ((intptr_t)device_get_ivars(dev) >= 0) 288 return (ENXIO); 289 /* Is this a known AHCI chip? */ 290 for (i = 0; ahci_ids[i].id != 0; i++) { 291 if (ahci_ids[i].id == devid && 292 ahci_ids[i].rev <= revid) { 293 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 294 ahci_ids[i].name); 295 device_set_desc_copy(dev, buf); 296 return (BUS_PROBE_VENDOR); 297 } 298 } 299 device_set_desc_copy(dev, "AHCI SATA controller"); 300 return (BUS_PROBE_VENDOR); 301} 302 303static int 304ahci_attach(device_t dev) 305{ 306 struct ahci_controller *ctlr = device_get_softc(dev); 307 device_t child; 308 int error, unit, speed, i; 309 uint32_t devid = pci_get_devid(dev); 310 uint8_t revid = pci_get_revid(dev); 311 u_int32_t version; 312 313 ctlr->dev = dev; 314 i = 0; 315 while (ahci_ids[i].id != 0 && 316 (ahci_ids[i].id != devid || 317 ahci_ids[i].rev > revid)) 318 i++; 319 ctlr->quirks = ahci_ids[i].quirks; 320 resource_int_value(device_get_name(dev), 321 device_get_unit(dev), "ccc", &ctlr->ccc); 322 /* if we have a memory BAR(5) we are likely on an AHCI part */ 323 ctlr->r_rid = PCIR_BAR(5); 324 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 325 &ctlr->r_rid, RF_ACTIVE))) 326 return ENXIO; 327 /* Setup our own memory management for channels. */ 328 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 329 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 330 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 331 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 332 return (error); 333 } 334 if ((error = rman_manage_region(&ctlr->sc_iomem, 335 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 336 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 337 rman_fini(&ctlr->sc_iomem); 338 return (error); 339 } 340 /* Reset controller */ 341 if ((error = ahci_ctlr_reset(dev)) != 0) { 342 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 343 rman_fini(&ctlr->sc_iomem); 344 return (error); 345 }; 346 /* Get the HW capabilities */ 347 version = ATA_INL(ctlr->r_mem, AHCI_VS); 348 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 349 if (version >= 0x00010020) 350 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 351 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 352 if (ctlr->quirks & AHCI_Q_1CH) { 353 ctlr->caps &= ~AHCI_CAP_NPMASK; 354 ctlr->ichannels &= 0x01; 355 } 356 if (ctlr->quirks & AHCI_Q_2CH) { 357 ctlr->caps &= ~AHCI_CAP_NPMASK; 358 ctlr->caps |= 1; 359 ctlr->ichannels &= 0x03; 360 } 361 if (ctlr->quirks & AHCI_Q_4CH) { 362 ctlr->caps &= ~AHCI_CAP_NPMASK; 363 ctlr->caps |= 3; 364 ctlr->ichannels &= 0x0f; 365 } 366 ctlr->channels = MAX(flsl(ctlr->ichannels), 367 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 368 if (ctlr->quirks & AHCI_Q_NOPMP) 369 ctlr->caps &= ~AHCI_CAP_SPM; 370 if (ctlr->quirks & AHCI_Q_NONCQ) 371 ctlr->caps &= ~AHCI_CAP_SNCQ; 372 /* Setup interrupts. */ 373 if (ahci_setup_interrupt(dev)) { 374 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 375 rman_fini(&ctlr->sc_iomem); 376 return ENXIO; 377 } 378 /* Announce HW capabilities. */ 379 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 380 device_printf(dev, 381 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s\n", 382 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 383 ((version >> 4) & 0xf0) + (version & 0x0f), 384 (ctlr->caps & AHCI_CAP_NPMASK) + 1, 385 ((speed == 1) ? "1.5":((speed == 2) ? "3": 386 ((speed == 3) ? "6":"?"))), 387 (ctlr->caps & AHCI_CAP_SPM) ? 388 "supported" : "not supported"); 389 if (bootverbose) { 390 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 391 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 392 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 393 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 394 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 395 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 396 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 397 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 398 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 399 ((speed == 1) ? "1.5":((speed == 2) ? "3": 400 ((speed == 3) ? "6":"?")))); 401 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 402 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 403 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 404 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 405 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 406 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 407 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 408 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 409 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 410 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 411 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 412 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 413 } 414 if (bootverbose && version >= 0x00010020) { 415 device_printf(dev, "Caps2:%s%s%s\n", 416 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 417 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 418 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 419 } 420 /* Attach all channels on this controller */ 421 for (unit = 0; unit < ctlr->channels; unit++) { 422 if ((ctlr->ichannels & (1 << unit)) == 0) 423 continue; 424 child = device_add_child(dev, "ahcich", -1); 425 if (child == NULL) 426 device_printf(dev, "failed to add channel device\n"); 427 else 428 device_set_ivars(child, (void *)(intptr_t)unit); 429 } 430 bus_generic_attach(dev); 431 return 0; 432} 433 434static int 435ahci_detach(device_t dev) 436{ 437 struct ahci_controller *ctlr = device_get_softc(dev); 438 device_t *children; 439 int nchildren, i; 440 441 /* Detach & delete all children */ 442 if (!device_get_children(dev, &children, &nchildren)) { 443 for (i = 0; i < nchildren; i++) 444 device_delete_child(dev, children[i]); 445 free(children, M_TEMP); 446 } 447 /* Free interrupts. */ 448 for (i = 0; i < ctlr->numirqs; i++) { 449 if (ctlr->irqs[i].r_irq) { 450 bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 451 ctlr->irqs[i].handle); 452 bus_release_resource(dev, SYS_RES_IRQ, 453 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 454 } 455 } 456 pci_release_msi(dev); 457 /* Free memory. */ 458 rman_fini(&ctlr->sc_iomem); 459 if (ctlr->r_mem) 460 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 461 return (0); 462} 463 464static int 465ahci_ctlr_reset(device_t dev) 466{ 467 struct ahci_controller *ctlr = device_get_softc(dev); 468 int timeout; 469 470 if (pci_read_config(dev, 0x00, 4) == 0x28298086 && 471 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04) 472 pci_write_config(dev, 0x92, 0x01, 1); 473 /* Enable AHCI mode */ 474 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 475 /* Reset AHCI controller */ 476 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 477 for (timeout = 1000; timeout > 0; timeout--) { 478 DELAY(1000); 479 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 480 break; 481 } 482 if (timeout == 0) { 483 device_printf(dev, "AHCI controller reset failure\n"); 484 return ENXIO; 485 } 486 /* Reenable AHCI mode */ 487 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 488 /* Clear interrupts */ 489 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 490 /* Configure CCC */ 491 if (ctlr->ccc) { 492 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 493 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 494 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 495 (4 << AHCI_CCCC_CC_SHIFT) | 496 AHCI_CCCC_EN); 497 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 498 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 499 if (bootverbose) { 500 device_printf(dev, 501 "CCC with %dms/4cmd enabled on vector %d\n", 502 ctlr->ccc, ctlr->cccv); 503 } 504 } 505 /* Enable AHCI interrupts */ 506 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 507 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 508 return (0); 509} 510 511static int 512ahci_suspend(device_t dev) 513{ 514 struct ahci_controller *ctlr = device_get_softc(dev); 515 516 bus_generic_suspend(dev); 517 /* Disable interupts, so the state change(s) doesn't trigger */ 518 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 519 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE)); 520 return 0; 521} 522 523static int 524ahci_resume(device_t dev) 525{ 526 int res; 527 528 if ((res = ahci_ctlr_reset(dev)) != 0) 529 return (res); 530 return (bus_generic_resume(dev)); 531} 532 533static int 534ahci_setup_interrupt(device_t dev) 535{ 536 struct ahci_controller *ctlr = device_get_softc(dev); 537 int i, msi = 1; 538 539 /* Process hints. */ 540 resource_int_value(device_get_name(dev), 541 device_get_unit(dev), "msi", &msi); 542 if (msi < 0) 543 msi = 0; 544 else if (msi == 1) 545 msi = min(1, pci_msi_count(dev)); 546 else if (msi > 1) 547 msi = pci_msi_count(dev); 548 /* Allocate MSI if needed/present. */ 549 if (msi && pci_alloc_msi(dev, &msi) == 0) { 550 ctlr->numirqs = msi; 551 } else { 552 msi = 0; 553 ctlr->numirqs = 1; 554 } 555 /* Check for single MSI vector fallback. */ 556 if (ctlr->numirqs > 1 && 557 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 558 device_printf(dev, "Falling back to one MSI\n"); 559 ctlr->numirqs = 1; 560 } 561 /* Allocate all IRQs. */ 562 for (i = 0; i < ctlr->numirqs; i++) { 563 ctlr->irqs[i].ctlr = ctlr; 564 ctlr->irqs[i].r_irq_rid = i + (msi ? 1 : 0); 565 if (ctlr->numirqs == 1 || i >= ctlr->channels || 566 (ctlr->ccc && i == ctlr->cccv)) 567 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 568 else if (i == ctlr->numirqs - 1) 569 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 570 else 571 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 572 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 573 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 574 device_printf(dev, "unable to map interrupt\n"); 575 return ENXIO; 576 } 577 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 578 (ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE) ? ahci_intr_one : ahci_intr, 579 &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 580 /* SOS XXX release r_irq */ 581 device_printf(dev, "unable to setup interrupt\n"); 582 return ENXIO; 583 } 584 if (ctlr->numirqs > 1) { 585 bus_describe_intr(dev, ctlr->irqs[i].r_irq, 586 ctlr->irqs[i].handle, 587 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ? 588 "ch%d" : "%d", i); 589 } 590 } 591 return (0); 592} 593 594/* 595 * Common case interrupt handler. 596 */ 597static void 598ahci_intr(void *data) 599{ 600 struct ahci_controller_irq *irq = data; 601 struct ahci_controller *ctlr = irq->ctlr; 602 u_int32_t is; 603 void *arg; 604 int unit; 605 606 if (irq->mode == AHCI_IRQ_MODE_ALL) { 607 unit = 0; 608 if (ctlr->ccc) 609 is = ctlr->ichannels; 610 else 611 is = ATA_INL(ctlr->r_mem, AHCI_IS); 612 } else { /* AHCI_IRQ_MODE_AFTER */ 613 unit = irq->r_irq_rid - 1; 614 is = ATA_INL(ctlr->r_mem, AHCI_IS); 615 } 616 /* Some controllers have edge triggered IS. */ 617 if (ctlr->quirks & AHCI_Q_EDGEIS) 618 ATA_OUTL(ctlr->r_mem, AHCI_IS, is); 619 for (; unit < ctlr->channels; unit++) { 620 if ((is & (1 << unit)) != 0 && 621 (arg = ctlr->interrupt[unit].argument)) { 622 ctlr->interrupt[unit].function(arg); 623 } 624 } 625 /* AHCI declares level triggered IS. */ 626 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 627 ATA_OUTL(ctlr->r_mem, AHCI_IS, is); 628} 629 630/* 631 * Simplified interrupt handler for multivector MSI mode. 632 */ 633static void 634ahci_intr_one(void *data) 635{ 636 struct ahci_controller_irq *irq = data; 637 struct ahci_controller *ctlr = irq->ctlr; 638 void *arg; 639 int unit; 640 641 unit = irq->r_irq_rid - 1; 642 /* Some controllers have edge triggered IS. */ 643 if (ctlr->quirks & AHCI_Q_EDGEIS) 644 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 645 if ((arg = ctlr->interrupt[unit].argument)) 646 ctlr->interrupt[unit].function(arg); 647 /* AHCI declares level triggered IS. */ 648 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 649 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 650} 651 652static struct resource * 653ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 654 u_long start, u_long end, u_long count, u_int flags) 655{ 656 struct ahci_controller *ctlr = device_get_softc(dev); 657 int unit = ((struct ahci_channel *)device_get_softc(child))->unit; 658 struct resource *res = NULL; 659 int offset = AHCI_OFFSET + (unit << 7); 660 long st; 661 662 switch (type) { 663 case SYS_RES_MEMORY: 664 st = rman_get_start(ctlr->r_mem); 665 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 666 st + offset + 127, 128, RF_ACTIVE, child); 667 if (res) { 668 bus_space_handle_t bsh; 669 bus_space_tag_t bst; 670 bsh = rman_get_bushandle(ctlr->r_mem); 671 bst = rman_get_bustag(ctlr->r_mem); 672 bus_space_subregion(bst, bsh, offset, 128, &bsh); 673 rman_set_bushandle(res, bsh); 674 rman_set_bustag(res, bst); 675 } 676 break; 677 case SYS_RES_IRQ: 678 if (*rid == ATA_IRQ_RID) 679 res = ctlr->irqs[0].r_irq; 680 break; 681 } 682 return (res); 683} 684 685static int 686ahci_release_resource(device_t dev, device_t child, int type, int rid, 687 struct resource *r) 688{ 689 690 switch (type) { 691 case SYS_RES_MEMORY: 692 rman_release_resource(r); 693 return (0); 694 case SYS_RES_IRQ: 695 if (rid != ATA_IRQ_RID) 696 return ENOENT; 697 return (0); 698 } 699 return (EINVAL); 700} 701 702static int 703ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 704 int flags, driver_filter_t *filter, driver_intr_t *function, 705 void *argument, void **cookiep) 706{ 707 struct ahci_controller *ctlr = device_get_softc(dev); 708 int unit = (intptr_t)device_get_ivars(child); 709 710 if (filter != NULL) { 711 printf("ahci.c: we cannot use a filter here\n"); 712 return (EINVAL); 713 } 714 ctlr->interrupt[unit].function = function; 715 ctlr->interrupt[unit].argument = argument; 716 return (0); 717} 718 719static int 720ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 721 void *cookie) 722{ 723 struct ahci_controller *ctlr = device_get_softc(dev); 724 int unit = (intptr_t)device_get_ivars(child); 725 726 ctlr->interrupt[unit].function = NULL; 727 ctlr->interrupt[unit].argument = NULL; 728 return (0); 729} 730 731static int 732ahci_print_child(device_t dev, device_t child) 733{ 734 int retval; 735 736 retval = bus_print_child_header(dev, child); 737 retval += printf(" at channel %d", 738 (int)(intptr_t)device_get_ivars(child)); 739 retval += bus_print_child_footer(dev, child); 740 741 return (retval); 742} 743 744devclass_t ahci_devclass; 745static device_method_t ahci_methods[] = { 746 DEVMETHOD(device_probe, ahci_probe), 747 DEVMETHOD(device_attach, ahci_attach), 748 DEVMETHOD(device_detach, ahci_detach), 749 DEVMETHOD(device_suspend, ahci_suspend), 750 DEVMETHOD(device_resume, ahci_resume), 751 DEVMETHOD(bus_print_child, ahci_print_child), 752 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 753 DEVMETHOD(bus_release_resource, ahci_release_resource), 754 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 755 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 756 { 0, 0 } 757}; 758static driver_t ahci_driver = { 759 "ahci", 760 ahci_methods, 761 sizeof(struct ahci_controller) 762}; 763DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0); 764static device_method_t ahci_ata_methods[] = { 765 DEVMETHOD(device_probe, ahci_ata_probe), 766 DEVMETHOD(device_attach, ahci_attach), 767 DEVMETHOD(device_detach, ahci_detach), 768 DEVMETHOD(device_suspend, ahci_suspend), 769 DEVMETHOD(device_resume, ahci_resume), 770 DEVMETHOD(bus_print_child, ahci_print_child), 771 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 772 DEVMETHOD(bus_release_resource, ahci_release_resource), 773 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 774 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 775 { 0, 0 } 776}; 777static driver_t ahci_ata_driver = { 778 "ahci", 779 ahci_ata_methods, 780 sizeof(struct ahci_controller) 781}; 782DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, 0, 0); 783MODULE_VERSION(ahci, 1); 784MODULE_DEPEND(ahci, cam, 1, 1, 1); 785 786static int 787ahci_ch_probe(device_t dev) 788{ 789 790 device_set_desc_copy(dev, "AHCI channel"); 791 return (0); 792} 793 794static int 795ahci_ch_attach(device_t dev) 796{ 797 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 798 struct ahci_channel *ch = device_get_softc(dev); 799 struct cam_devq *devq; 800 int rid, error, i, sata_rev = 0; 801 802 ch->dev = dev; 803 ch->unit = (intptr_t)device_get_ivars(dev); 804 ch->caps = ctlr->caps; 805 ch->caps2 = ctlr->caps2; 806 ch->quirks = ctlr->quirks; 807 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 808 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 809 resource_int_value(device_get_name(dev), 810 device_get_unit(dev), "pm_level", &ch->pm_level); 811 if (ch->pm_level > 3) 812 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 813 /* Limit speed for my onboard JMicron external port. 814 * It is not eSATA really. */ 815 if (pci_get_devid(ctlr->dev) == 0x2363197b && 816 pci_get_subvendor(ctlr->dev) == 0x1043 && 817 pci_get_subdevice(ctlr->dev) == 0x81e4 && 818 ch->unit == 0) 819 sata_rev = 1; 820 if (ch->quirks & AHCI_Q_SATA2) 821 sata_rev = 2; 822 resource_int_value(device_get_name(dev), 823 device_get_unit(dev), "sata_rev", &sata_rev); 824 for (i = 0; i < 16; i++) { 825 ch->user[i].revision = sata_rev; 826 ch->user[i].mode = 0; 827 ch->user[i].bytecount = 8192; 828 ch->user[i].tags = ch->numslots; 829 ch->curr[i] = ch->user[i]; 830 } 831 rid = ch->unit; 832 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 833 &rid, RF_ACTIVE))) 834 return (ENXIO); 835 ahci_dmainit(dev); 836 ahci_slotsalloc(dev); 837 ahci_ch_resume(dev); 838 mtx_lock(&ch->mtx); 839 rid = ATA_IRQ_RID; 840 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 841 &rid, RF_SHAREABLE | RF_ACTIVE))) { 842 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 843 device_printf(dev, "Unable to map interrupt\n"); 844 return (ENXIO); 845 } 846 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 847 ahci_ch_intr_locked, dev, &ch->ih))) { 848 device_printf(dev, "Unable to setup interrupt\n"); 849 error = ENXIO; 850 goto err1; 851 } 852 /* Create the device queue for our SIM. */ 853 devq = cam_simq_alloc(ch->numslots); 854 if (devq == NULL) { 855 device_printf(dev, "Unable to allocate simq\n"); 856 error = ENOMEM; 857 goto err1; 858 } 859 /* Construct SIM entry */ 860 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 861 device_get_unit(dev), &ch->mtx, 862 min(2, ch->numslots), 863 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0, 864 devq); 865 if (ch->sim == NULL) { 866 device_printf(dev, "unable to allocate sim\n"); 867 error = ENOMEM; 868 goto err2; 869 } 870 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 871 device_printf(dev, "unable to register xpt bus\n"); 872 error = ENXIO; 873 goto err2; 874 } 875 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 876 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 877 device_printf(dev, "unable to create path\n"); 878 error = ENXIO; 879 goto err3; 880 } 881 if (ch->pm_level > 3) { 882 callout_reset(&ch->pm_timer, 883 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 884 ahci_ch_pm, dev); 885 } 886 mtx_unlock(&ch->mtx); 887 return (0); 888 889err3: 890 xpt_bus_deregister(cam_sim_path(ch->sim)); 891err2: 892 cam_sim_free(ch->sim, /*free_devq*/TRUE); 893err1: 894 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 895 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 896 mtx_unlock(&ch->mtx); 897 return (error); 898} 899 900static int 901ahci_ch_detach(device_t dev) 902{ 903 struct ahci_channel *ch = device_get_softc(dev); 904 905 mtx_lock(&ch->mtx); 906 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 907 xpt_free_path(ch->path); 908 xpt_bus_deregister(cam_sim_path(ch->sim)); 909 cam_sim_free(ch->sim, /*free_devq*/TRUE); 910 mtx_unlock(&ch->mtx); 911 912 if (ch->pm_level > 3) 913 callout_drain(&ch->pm_timer); 914 bus_teardown_intr(dev, ch->r_irq, ch->ih); 915 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 916 917 ahci_ch_suspend(dev); 918 ahci_slotsfree(dev); 919 ahci_dmafini(dev); 920 921 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 922 mtx_destroy(&ch->mtx); 923 return (0); 924} 925 926static int 927ahci_ch_suspend(device_t dev) 928{ 929 struct ahci_channel *ch = device_get_softc(dev); 930 931 /* Disable port interrupts. */ 932 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 933 /* Reset command register. */ 934 ahci_stop(dev); 935 ahci_stop_fr(dev); 936 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 937 /* Allow everything, including partial and slumber modes. */ 938 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 939 /* Request slumber mode transition and give some time to get there. */ 940 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 941 DELAY(100); 942 /* Disable PHY. */ 943 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 944 return (0); 945} 946 947static int 948ahci_ch_resume(device_t dev) 949{ 950 struct ahci_channel *ch = device_get_softc(dev); 951 uint64_t work; 952 953 /* Disable port interrupts */ 954 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 955 /* Setup work areas */ 956 work = ch->dma.work_bus + AHCI_CL_OFFSET; 957 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 958 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 959 work = ch->dma.rfis_bus; 960 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 961 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 962 /* Activate the channel and power/spin up device */ 963 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 964 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 965 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 966 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 967 ahci_start_fr(dev); 968 ahci_start(dev); 969 return (0); 970} 971 972devclass_t ahcich_devclass; 973static device_method_t ahcich_methods[] = { 974 DEVMETHOD(device_probe, ahci_ch_probe), 975 DEVMETHOD(device_attach, ahci_ch_attach), 976 DEVMETHOD(device_detach, ahci_ch_detach), 977 DEVMETHOD(device_suspend, ahci_ch_suspend), 978 DEVMETHOD(device_resume, ahci_ch_resume), 979 { 0, 0 } 980}; 981static driver_t ahcich_driver = { 982 "ahcich", 983 ahcich_methods, 984 sizeof(struct ahci_channel) 985}; 986DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, 0, 0); 987 988struct ahci_dc_cb_args { 989 bus_addr_t maddr; 990 int error; 991}; 992 993static void 994ahci_dmainit(device_t dev) 995{ 996 struct ahci_channel *ch = device_get_softc(dev); 997 struct ahci_dc_cb_args dcba; 998 999 if (ch->caps & AHCI_CAP_64BIT) 1000 ch->dma.max_address = BUS_SPACE_MAXADDR; 1001 else 1002 ch->dma.max_address = BUS_SPACE_MAXADDR_32BIT; 1003 /* Command area. */ 1004 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 1005 ch->dma.max_address, BUS_SPACE_MAXADDR, 1006 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 1007 0, NULL, NULL, &ch->dma.work_tag)) 1008 goto error; 1009 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 0, 1010 &ch->dma.work_map)) 1011 goto error; 1012 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 1013 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1014 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1015 goto error; 1016 } 1017 ch->dma.work_bus = dcba.maddr; 1018 /* FIS receive area. */ 1019 if (bus_dma_tag_create(bus_get_dma_tag(dev), 4096, 0, 1020 ch->dma.max_address, BUS_SPACE_MAXADDR, 1021 NULL, NULL, 4096, 1, 4096, 1022 0, NULL, NULL, &ch->dma.rfis_tag)) 1023 goto error; 1024 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 1025 &ch->dma.rfis_map)) 1026 goto error; 1027 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 1028 4096, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1029 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1030 goto error; 1031 } 1032 ch->dma.rfis_bus = dcba.maddr; 1033 /* Data area. */ 1034 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 1035 ch->dma.max_address, BUS_SPACE_MAXADDR, 1036 NULL, NULL, 1037 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 1038 AHCI_SG_ENTRIES, AHCI_PRD_MAX, 1039 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 1040 goto error; 1041 } 1042 return; 1043 1044error: 1045 device_printf(dev, "WARNING - DMA initialization failed\n"); 1046 ahci_dmafini(dev); 1047} 1048 1049static void 1050ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1051{ 1052 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 1053 1054 if (!(dcba->error = error)) 1055 dcba->maddr = segs[0].ds_addr; 1056} 1057 1058static void 1059ahci_dmafini(device_t dev) 1060{ 1061 struct ahci_channel *ch = device_get_softc(dev); 1062 1063 if (ch->dma.data_tag) { 1064 bus_dma_tag_destroy(ch->dma.data_tag); 1065 ch->dma.data_tag = NULL; 1066 } 1067 if (ch->dma.rfis_bus) { 1068 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 1069 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1070 ch->dma.rfis_bus = 0; 1071 ch->dma.rfis_map = NULL; 1072 ch->dma.rfis = NULL; 1073 } 1074 if (ch->dma.work_bus) { 1075 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 1076 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1077 ch->dma.work_bus = 0; 1078 ch->dma.work_map = NULL; 1079 ch->dma.work = NULL; 1080 } 1081 if (ch->dma.work_tag) { 1082 bus_dma_tag_destroy(ch->dma.work_tag); 1083 ch->dma.work_tag = NULL; 1084 } 1085} 1086 1087static void 1088ahci_slotsalloc(device_t dev) 1089{ 1090 struct ahci_channel *ch = device_get_softc(dev); 1091 int i; 1092 1093 /* Alloc and setup command/dma slots */ 1094 bzero(ch->slot, sizeof(ch->slot)); 1095 for (i = 0; i < ch->numslots; i++) { 1096 struct ahci_slot *slot = &ch->slot[i]; 1097 1098 slot->dev = dev; 1099 slot->slot = i; 1100 slot->state = AHCI_SLOT_EMPTY; 1101 slot->ccb = NULL; 1102 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 1103 1104 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 1105 device_printf(ch->dev, "FAILURE - create data_map\n"); 1106 } 1107} 1108 1109static void 1110ahci_slotsfree(device_t dev) 1111{ 1112 struct ahci_channel *ch = device_get_softc(dev); 1113 int i; 1114 1115 /* Free all dma slots */ 1116 for (i = 0; i < ch->numslots; i++) { 1117 struct ahci_slot *slot = &ch->slot[i]; 1118 1119 callout_drain(&slot->timeout); 1120 if (slot->dma.data_map) { 1121 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 1122 slot->dma.data_map = NULL; 1123 } 1124 } 1125} 1126 1127static void 1128ahci_phy_check_events(device_t dev, u_int32_t serr) 1129{ 1130 struct ahci_channel *ch = device_get_softc(dev); 1131 1132 if ((serr & ATA_SE_PHY_CHANGED) && (ch->pm_level == 0)) { 1133 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1134 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 1135 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 1136 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) { 1137 if (bootverbose) 1138 device_printf(dev, "CONNECT requested\n"); 1139 ahci_reset(dev); 1140 } else { 1141 if (bootverbose) 1142 device_printf(dev, "DISCONNECT requested\n"); 1143 ch->devices = 0; 1144 } 1145 } 1146} 1147 1148static void 1149ahci_notify_events(device_t dev, u_int32_t status) 1150{ 1151 struct ahci_channel *ch = device_get_softc(dev); 1152 struct cam_path *dpath; 1153 int i; 1154 1155 if (ch->caps & AHCI_CAP_SSNTF) 1156 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 1157 if (bootverbose) 1158 device_printf(dev, "SNTF 0x%04x\n", status); 1159 for (i = 0; i < 16; i++) { 1160 if ((status & (1 << i)) == 0) 1161 continue; 1162 if (xpt_create_path(&dpath, NULL, 1163 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 1164 xpt_async(AC_SCSI_AEN, dpath, NULL); 1165 xpt_free_path(dpath); 1166 } 1167 } 1168} 1169 1170static void 1171ahci_ch_intr_locked(void *data) 1172{ 1173 device_t dev = (device_t)data; 1174 struct ahci_channel *ch = device_get_softc(dev); 1175 1176 mtx_lock(&ch->mtx); 1177 ahci_ch_intr(data); 1178 mtx_unlock(&ch->mtx); 1179} 1180 1181static void 1182ahci_ch_pm(void *arg) 1183{ 1184 device_t dev = (device_t)arg; 1185 struct ahci_channel *ch = device_get_softc(dev); 1186 uint32_t work; 1187 1188 if (ch->numrslots != 0) 1189 return; 1190 work = ATA_INL(ch->r_mem, AHCI_P_CMD); 1191 if (ch->pm_level == 4) 1192 work |= AHCI_P_CMD_PARTIAL; 1193 else 1194 work |= AHCI_P_CMD_SLUMBER; 1195 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 1196} 1197 1198static void 1199ahci_ch_intr(void *data) 1200{ 1201 device_t dev = (device_t)data; 1202 struct ahci_channel *ch = device_get_softc(dev); 1203 uint32_t istatus, sstatus, cstatus, serr = 0, sntf = 0, ok, err; 1204 enum ahci_err_type et; 1205 int i, ccs, ncq_err = 0; 1206 1207 /* Read and clear interrupt statuses. */ 1208 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1209 if (istatus == 0) 1210 return; 1211 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 1212 /* Read command statuses. */ 1213 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1214 cstatus = ATA_INL(ch->r_mem, AHCI_P_CI); 1215 if (istatus & AHCI_P_IX_SDB) { 1216 if (ch->caps & AHCI_CAP_SSNTF) 1217 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 1218 else { 1219 u_int8_t *fis = ch->dma.rfis + 0x58; 1220 1221 if (fis[1] & 0x80) 1222 sntf = (1 << (fis[1] & 0x0f)); 1223 } 1224 } 1225 /* Process PHY events */ 1226 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 1227 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1228 serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 1229 if (serr) { 1230 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 1231 ahci_phy_check_events(dev, serr); 1232 } 1233 } 1234 /* Process command errors */ 1235 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 1236 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1237//device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x\n", 1238// __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 1239// serr); 1240 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1241 >> AHCI_P_CMD_CCS_SHIFT; 1242 err = ch->rslots & (cstatus | sstatus); 1243 /* Kick controller into sane state */ 1244 ahci_stop(dev); 1245 ahci_start(dev); 1246 } else { 1247 ccs = 0; 1248 err = 0; 1249 } 1250 /* Complete all successfull commands. */ 1251 ok = ch->rslots & ~(cstatus | sstatus); 1252 for (i = 0; i < ch->numslots; i++) { 1253 if ((ok >> i) & 1) 1254 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 1255 } 1256 /* On error, complete the rest of commands with error statuses. */ 1257 if (err) { 1258 if (ch->frozen) { 1259 union ccb *fccb = ch->frozen; 1260 ch->frozen = NULL; 1261 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1262 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1263 xpt_freeze_devq(fccb->ccb_h.path, 1); 1264 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1265 } 1266 xpt_done(fccb); 1267 } 1268 for (i = 0; i < ch->numslots; i++) { 1269 /* XXX: reqests in loading state. */ 1270 if (((err >> i) & 1) == 0) 1271 continue; 1272 if (istatus & AHCI_P_IX_TFE) { 1273 /* Task File Error */ 1274 if (ch->numtslots == 0) { 1275 /* Untagged operation. */ 1276 if (i == ccs) 1277 et = AHCI_ERR_TFE; 1278 else 1279 et = AHCI_ERR_INNOCENT; 1280 } else { 1281 /* Tagged operation. */ 1282 et = AHCI_ERR_NCQ; 1283 ncq_err = 1; 1284 } 1285 } else if (istatus & AHCI_P_IX_IF) { 1286 if (ch->numtslots == 0 && i != ccs) 1287 et = AHCI_ERR_INNOCENT; 1288 else 1289 et = AHCI_ERR_SATA; 1290 } else 1291 et = AHCI_ERR_INVALID; 1292 ahci_end_transaction(&ch->slot[i], et); 1293 } 1294 if (ncq_err) 1295 ahci_issue_read_log(dev); 1296 } 1297 /* Process NOTIFY events */ 1298 if (sntf) 1299 ahci_notify_events(dev, sntf); 1300} 1301 1302/* Must be called with channel locked. */ 1303static int 1304ahci_check_collision(device_t dev, union ccb *ccb) 1305{ 1306 struct ahci_channel *ch = device_get_softc(dev); 1307 1308 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1309 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1310 /* Tagged command while untagged are active. */ 1311 if (ch->numrslots != 0 && ch->numtslots == 0) 1312 return (1); 1313 /* Tagged command while tagged to other target is active. */ 1314 if (ch->numtslots != 0 && 1315 ch->taggedtarget != ccb->ccb_h.target_id) 1316 return (1); 1317 /* Tagged command while we have no supported tag free. */ 1318 if (((~ch->oslots) & (0xffffffff >> (32 - 1319 ch->curr[ccb->ccb_h.target_id].tags))) == 0) 1320 return (1); 1321 } else { 1322 /* Untagged command while tagged are active. */ 1323 if (ch->numrslots != 0 && ch->numtslots != 0) 1324 return (1); 1325 } 1326 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1327 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1328 /* Atomic command while anything active. */ 1329 if (ch->numrslots != 0) 1330 return (1); 1331 } 1332 /* We have some atomic command running. */ 1333 if (ch->aslots != 0) 1334 return (1); 1335 return (0); 1336} 1337 1338/* Must be called with channel locked. */ 1339static void 1340ahci_begin_transaction(device_t dev, union ccb *ccb) 1341{ 1342 struct ahci_channel *ch = device_get_softc(dev); 1343 struct ahci_slot *slot; 1344 int tag, tags; 1345 1346 /* Choose empty slot. */ 1347 tags = ch->numslots; 1348 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1349 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) 1350 tags = ch->curr[ccb->ccb_h.target_id].tags; 1351 tag = ch->lastslot; 1352 while (1) { 1353 if (tag >= tags) 1354 tag = 0; 1355 if (ch->slot[tag].state == AHCI_SLOT_EMPTY) 1356 break; 1357 tag++; 1358 }; 1359 ch->lastslot = tag; 1360 /* Occupy chosen slot. */ 1361 slot = &ch->slot[tag]; 1362 slot->ccb = ccb; 1363 /* Stop PM timer. */ 1364 if (ch->numrslots == 0 && ch->pm_level > 3) 1365 callout_stop(&ch->pm_timer); 1366 /* Update channel stats. */ 1367 ch->oslots |= (1 << slot->slot); 1368 ch->numrslots++; 1369 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1370 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1371 ch->numtslots++; 1372 ch->taggedtarget = ccb->ccb_h.target_id; 1373 } 1374 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1375 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1376 ch->aslots |= (1 << slot->slot); 1377 slot->dma.nsegs = 0; 1378 /* If request moves data, setup and load SG list */ 1379 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1380 void *buf; 1381 bus_size_t size; 1382 1383 slot->state = AHCI_SLOT_LOADING; 1384 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1385 buf = ccb->ataio.data_ptr; 1386 size = ccb->ataio.dxfer_len; 1387 } else { 1388 buf = ccb->csio.data_ptr; 1389 size = ccb->csio.dxfer_len; 1390 } 1391 bus_dmamap_load(ch->dma.data_tag, slot->dma.data_map, 1392 buf, size, ahci_dmasetprd, slot, 0); 1393 } else 1394 ahci_execute_transaction(slot); 1395} 1396 1397/* Locked by busdma engine. */ 1398static void 1399ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1400{ 1401 struct ahci_slot *slot = arg; 1402 struct ahci_channel *ch = device_get_softc(slot->dev); 1403 struct ahci_cmd_tab *ctp; 1404 struct ahci_dma_prd *prd; 1405 int i; 1406 1407 if (error) { 1408 device_printf(slot->dev, "DMA load error\n"); 1409 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1410 return; 1411 } 1412 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1413 /* Get a piece of the workspace for this request */ 1414 ctp = (struct ahci_cmd_tab *) 1415 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1416 /* Fill S/G table */ 1417 prd = &ctp->prd_tab[0]; 1418 for (i = 0; i < nsegs; i++) { 1419 prd[i].dba = htole64(segs[i].ds_addr); 1420 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1421 } 1422 slot->dma.nsegs = nsegs; 1423 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1424 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1425 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1426 ahci_execute_transaction(slot); 1427} 1428 1429/* Must be called with channel locked. */ 1430static void 1431ahci_execute_transaction(struct ahci_slot *slot) 1432{ 1433 device_t dev = slot->dev; 1434 struct ahci_channel *ch = device_get_softc(dev); 1435 struct ahci_cmd_tab *ctp; 1436 struct ahci_cmd_list *clp; 1437 union ccb *ccb = slot->ccb; 1438 int port = ccb->ccb_h.target_id & 0x0f; 1439 int fis_size; 1440 1441 /* Get a piece of the workspace for this request */ 1442 ctp = (struct ahci_cmd_tab *) 1443 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1444 /* Setup the FIS for this request */ 1445 if (!(fis_size = ahci_setup_fis(dev, ctp, ccb, slot->slot))) { 1446 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1447 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1448 return; 1449 } 1450 /* Setup the command list entry */ 1451 clp = (struct ahci_cmd_list *) 1452 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1453 clp->prd_length = slot->dma.nsegs; 1454 clp->cmd_flags = (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1455 (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1456 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1457 (fis_size / sizeof(u_int32_t)) | 1458 (port << 12); 1459 /* Special handling for Soft Reset command. */ 1460 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1461 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1462 (ccb->ataio.cmd.control & ATA_A_RESET)) { 1463 /* Kick controller into sane state */ 1464 ahci_stop(dev); 1465 ahci_clo(dev); 1466 ahci_start(dev); 1467 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1468 } 1469 clp->bytecount = 0; 1470 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1471 (AHCI_CT_SIZE * slot->slot)); 1472 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1473 BUS_DMASYNC_PREWRITE); 1474 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1475 BUS_DMASYNC_PREREAD); 1476 /* Set ACTIVE bit for NCQ commands. */ 1477 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1478 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1479 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1480 } 1481 /* Issue command to the controller. */ 1482 slot->state = AHCI_SLOT_RUNNING; 1483 ch->rslots |= (1 << slot->slot); 1484 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1485 /* Device reset commands doesn't interrupt. Poll them. */ 1486 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1487 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || 1488 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL))) { 1489 int count, timeout = ccb->ccb_h.timeout; 1490 enum ahci_err_type et = AHCI_ERR_NONE; 1491 1492 for (count = 0; count < timeout; count++) { 1493 DELAY(1000); 1494 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1495 break; 1496 if (ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) { 1497 device_printf(ch->dev, 1498 "Poll error on slot %d, TFD: %04x\n", 1499 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1500 et = AHCI_ERR_TFE; 1501 break; 1502 } 1503 /* Workaround for ATI SB600/SB700 chipsets. */ 1504 if (ccb->ccb_h.target_id == 15 && 1505 pci_get_vendor(device_get_parent(dev)) == 0x1002 && 1506 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) { 1507 et = AHCI_ERR_TIMEOUT; 1508 break; 1509 } 1510 } 1511 if (timeout && (count >= timeout)) { 1512 device_printf(ch->dev, 1513 "Poll timeout on slot %d\n", slot->slot); 1514 et = AHCI_ERR_TIMEOUT; 1515 } 1516 if (et != AHCI_ERR_NONE) { 1517 /* Kick controller into sane state */ 1518 ahci_stop(ch->dev); 1519 ahci_start(ch->dev); 1520 } 1521 ahci_end_transaction(slot, et); 1522 return; 1523 } 1524 /* Start command execution timeout */ 1525 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000, 1526 (timeout_t*)ahci_timeout, slot); 1527 return; 1528} 1529 1530/* Locked by callout mechanism. */ 1531static void 1532ahci_timeout(struct ahci_slot *slot) 1533{ 1534 device_t dev = slot->dev; 1535 struct ahci_channel *ch = device_get_softc(dev); 1536 uint32_t sstatus; 1537 int ccs; 1538 int i; 1539 1540 /* Check for stale timeout. */ 1541 if (slot->state < AHCI_SLOT_RUNNING) 1542 return; 1543 1544 /* Check if slot was not being executed last time we checked. */ 1545 if (slot->state < AHCI_SLOT_EXECUTING) { 1546 /* Check if slot started executing. */ 1547 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1548 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1549 >> AHCI_P_CMD_CCS_SHIFT; 1550 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot) 1551 slot->state = AHCI_SLOT_EXECUTING; 1552 1553 callout_reset(&slot->timeout, 1554 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1555 (timeout_t*)ahci_timeout, slot); 1556 return; 1557 } 1558 1559 device_printf(dev, "Timeout on slot %d\n", slot->slot); 1560 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x\n", 1561 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 1562 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1563 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR)); 1564 1565 ch->fatalerr = 1; 1566 /* Handle frozen command. */ 1567 if (ch->frozen) { 1568 union ccb *fccb = ch->frozen; 1569 ch->frozen = NULL; 1570 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1571 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1572 xpt_freeze_devq(fccb->ccb_h.path, 1); 1573 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1574 } 1575 xpt_done(fccb); 1576 } 1577 /* Handle command with timeout. */ 1578 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 1579 /* Handle the rest of commands. */ 1580 for (i = 0; i < ch->numslots; i++) { 1581 /* Do we have a running request on slot? */ 1582 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1583 continue; 1584 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 1585 } 1586} 1587 1588/* Must be called with channel locked. */ 1589static void 1590ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 1591{ 1592 device_t dev = slot->dev; 1593 struct ahci_channel *ch = device_get_softc(dev); 1594 union ccb *ccb = slot->ccb; 1595 1596 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1597 BUS_DMASYNC_POSTWRITE); 1598 /* Read result registers to the result struct 1599 * May be incorrect if several commands finished same time, 1600 * so read only when sure or have to. 1601 */ 1602 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1603 struct ata_res *res = &ccb->ataio.res; 1604 1605 if ((et == AHCI_ERR_TFE) || 1606 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 1607 u_int8_t *fis = ch->dma.rfis + 0x40; 1608 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 1609 1610 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1611 BUS_DMASYNC_POSTREAD); 1612 res->status = tfd; 1613 res->error = tfd >> 8; 1614 res->lba_low = fis[4]; 1615 res->lba_mid = fis[5]; 1616 res->lba_high = fis[6]; 1617 res->device = fis[7]; 1618 res->lba_low_exp = fis[8]; 1619 res->lba_mid_exp = fis[9]; 1620 res->lba_high_exp = fis[10]; 1621 res->sector_count = fis[12]; 1622 res->sector_count_exp = fis[13]; 1623 } else 1624 bzero(res, sizeof(*res)); 1625 } 1626 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1627 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1628 (ccb->ccb_h.flags & CAM_DIR_IN) ? 1629 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1630 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 1631 } 1632 /* In case of error, freeze device for proper recovery. */ 1633 if ((et != AHCI_ERR_NONE) && (!ch->readlog) && 1634 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 1635 xpt_freeze_devq(ccb->ccb_h.path, 1); 1636 ccb->ccb_h.status |= CAM_DEV_QFRZN; 1637 } 1638 /* Set proper result status. */ 1639 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1640 switch (et) { 1641 case AHCI_ERR_NONE: 1642 ccb->ccb_h.status |= CAM_REQ_CMP; 1643 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 1644 ccb->csio.scsi_status = SCSI_STATUS_OK; 1645 break; 1646 case AHCI_ERR_INVALID: 1647 ch->fatalerr = 1; 1648 ccb->ccb_h.status |= CAM_REQ_INVALID; 1649 break; 1650 case AHCI_ERR_INNOCENT: 1651 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 1652 break; 1653 case AHCI_ERR_TFE: 1654 case AHCI_ERR_NCQ: 1655 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 1656 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 1657 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 1658 } else { 1659 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 1660 } 1661 break; 1662 case AHCI_ERR_SATA: 1663 ch->fatalerr = 1; 1664 if (!ch->readlog) { 1665 xpt_freeze_simq(ch->sim, 1); 1666 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1667 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1668 } 1669 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 1670 break; 1671 case AHCI_ERR_TIMEOUT: 1672 /* Do no treat soft-reset timeout as fatal here. */ 1673 if (ccb->ccb_h.func_code != XPT_ATA_IO || 1674 !(ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) 1675 ch->fatalerr = 1; 1676 if (!ch->readlog) { 1677 xpt_freeze_simq(ch->sim, 1); 1678 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1679 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1680 } 1681 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 1682 break; 1683 default: 1684 ch->fatalerr = 1; 1685 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 1686 } 1687 /* Free slot. */ 1688 ch->oslots &= ~(1 << slot->slot); 1689 ch->rslots &= ~(1 << slot->slot); 1690 ch->aslots &= ~(1 << slot->slot); 1691 slot->state = AHCI_SLOT_EMPTY; 1692 slot->ccb = NULL; 1693 /* Update channel stats. */ 1694 ch->numrslots--; 1695 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1696 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1697 ch->numtslots--; 1698 } 1699 /* If it was first request of reset sequence and there is no error, 1700 * proceed to second request. */ 1701 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1702 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1703 (ccb->ataio.cmd.control & ATA_A_RESET) && 1704 et == AHCI_ERR_NONE) { 1705 ccb->ataio.cmd.control &= ~ATA_A_RESET; 1706 ahci_begin_transaction(dev, ccb); 1707 return; 1708 } 1709 /* If it was our READ LOG command - process it. */ 1710 if (ch->readlog) { 1711 ahci_process_read_log(dev, ccb); 1712 /* If it was NCQ command error, put result on hold. */ 1713 } else if (et == AHCI_ERR_NCQ) { 1714 ch->hold[slot->slot] = ccb; 1715 } else 1716 xpt_done(ccb); 1717 /* Unfreeze frozen command. */ 1718 if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) { 1719 union ccb *fccb = ch->frozen; 1720 ch->frozen = NULL; 1721 ahci_begin_transaction(dev, fccb); 1722 xpt_release_simq(ch->sim, TRUE); 1723 } 1724 /* If we have no other active commands, ... */ 1725 if (ch->rslots == 0) { 1726 /* if there was fatal error - reset port. */ 1727 if (ch->fatalerr) { 1728 ahci_reset(dev); 1729 } 1730 } 1731 /* Start PM timer. */ 1732 if (ch->numrslots == 0 && ch->pm_level > 3) { 1733 callout_schedule(&ch->pm_timer, 1734 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 1735 } 1736} 1737 1738static void 1739ahci_issue_read_log(device_t dev) 1740{ 1741 struct ahci_channel *ch = device_get_softc(dev); 1742 union ccb *ccb; 1743 struct ccb_ataio *ataio; 1744 int i; 1745 1746 ch->readlog = 1; 1747 /* Find some holden command. */ 1748 for (i = 0; i < ch->numslots; i++) { 1749 if (ch->hold[i]) 1750 break; 1751 } 1752 ccb = xpt_alloc_ccb_nowait(); 1753 if (ccb == NULL) { 1754 device_printf(dev, "Unable allocate READ LOG command"); 1755 return; /* XXX */ 1756 } 1757 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 1758 ccb->ccb_h.func_code = XPT_ATA_IO; 1759 ccb->ccb_h.flags = CAM_DIR_IN; 1760 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 1761 ataio = &ccb->ataio; 1762 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 1763 if (ataio->data_ptr == NULL) { 1764 device_printf(dev, "Unable allocate memory for READ LOG command"); 1765 return; /* XXX */ 1766 } 1767 ataio->dxfer_len = 512; 1768 bzero(&ataio->cmd, sizeof(ataio->cmd)); 1769 ataio->cmd.flags = CAM_ATAIO_48BIT; 1770 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 1771 ataio->cmd.sector_count = 1; 1772 ataio->cmd.sector_count_exp = 0; 1773 ataio->cmd.lba_low = 0x10; 1774 ataio->cmd.lba_mid = 0; 1775 ataio->cmd.lba_mid_exp = 0; 1776 /* Freeze SIM while doing READ LOG EXT. */ 1777 xpt_freeze_simq(ch->sim, 1); 1778 ahci_begin_transaction(dev, ccb); 1779} 1780 1781static void 1782ahci_process_read_log(device_t dev, union ccb *ccb) 1783{ 1784 struct ahci_channel *ch = device_get_softc(dev); 1785 uint8_t *data; 1786 struct ata_res *res; 1787 int i; 1788 1789 ch->readlog = 0; 1790 1791 data = ccb->ataio.data_ptr; 1792 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 1793 (data[0] & 0x80) == 0) { 1794 for (i = 0; i < ch->numslots; i++) { 1795 if (!ch->hold[i]) 1796 continue; 1797 if ((data[0] & 0x1F) == i) { 1798 res = &ch->hold[i]->ataio.res; 1799 res->status = data[2]; 1800 res->error = data[3]; 1801 res->lba_low = data[4]; 1802 res->lba_mid = data[5]; 1803 res->lba_high = data[6]; 1804 res->device = data[7]; 1805 res->lba_low_exp = data[8]; 1806 res->lba_mid_exp = data[9]; 1807 res->lba_high_exp = data[10]; 1808 res->sector_count = data[12]; 1809 res->sector_count_exp = data[13]; 1810 } else { 1811 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 1812 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 1813 } 1814 xpt_done(ch->hold[i]); 1815 ch->hold[i] = NULL; 1816 } 1817 } else { 1818 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 1819 device_printf(dev, "Error while READ LOG EXT\n"); 1820 else if ((data[0] & 0x80) == 0) { 1821 device_printf(dev, "Non-queued command error in READ LOG EXT\n"); 1822 } 1823 for (i = 0; i < ch->numslots; i++) { 1824 if (!ch->hold[i]) 1825 continue; 1826 xpt_done(ch->hold[i]); 1827 ch->hold[i] = NULL; 1828 } 1829 } 1830 free(ccb->ataio.data_ptr, M_AHCI); 1831 xpt_free_ccb(ccb); 1832 xpt_release_simq(ch->sim, TRUE); 1833} 1834 1835static void 1836ahci_start(device_t dev) 1837{ 1838 struct ahci_channel *ch = device_get_softc(dev); 1839 u_int32_t cmd; 1840 1841 /* Clear SATA error register */ 1842 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 1843 /* Clear any interrupts pending on this channel */ 1844 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 1845 /* Start operations on this channel */ 1846 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1847 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 1848 (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 1849} 1850 1851static void 1852ahci_stop(device_t dev) 1853{ 1854 struct ahci_channel *ch = device_get_softc(dev); 1855 u_int32_t cmd; 1856 int timeout; 1857 1858 /* Kill all activity on this channel */ 1859 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1860 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 1861 /* Wait for activity stop. */ 1862 timeout = 0; 1863 do { 1864 DELAY(1000); 1865 if (timeout++ > 1000) { 1866 device_printf(dev, "stopping AHCI engine failed\n"); 1867 break; 1868 } 1869 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 1870} 1871 1872static void 1873ahci_clo(device_t dev) 1874{ 1875 struct ahci_channel *ch = device_get_softc(dev); 1876 u_int32_t cmd; 1877 int timeout; 1878 1879 /* Issue Command List Override if supported */ 1880 if (ch->caps & AHCI_CAP_SCLO) { 1881 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1882 cmd |= AHCI_P_CMD_CLO; 1883 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 1884 timeout = 0; 1885 do { 1886 DELAY(1000); 1887 if (timeout++ > 1000) { 1888 device_printf(dev, "executing CLO failed\n"); 1889 break; 1890 } 1891 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 1892 } 1893} 1894 1895static void 1896ahci_stop_fr(device_t dev) 1897{ 1898 struct ahci_channel *ch = device_get_softc(dev); 1899 u_int32_t cmd; 1900 int timeout; 1901 1902 /* Kill all FIS reception on this channel */ 1903 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1904 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 1905 /* Wait for FIS reception stop. */ 1906 timeout = 0; 1907 do { 1908 DELAY(1000); 1909 if (timeout++ > 1000) { 1910 device_printf(dev, "stopping AHCI FR engine failed\n"); 1911 break; 1912 } 1913 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 1914} 1915 1916static void 1917ahci_start_fr(device_t dev) 1918{ 1919 struct ahci_channel *ch = device_get_softc(dev); 1920 u_int32_t cmd; 1921 1922 /* Start FIS reception on this channel */ 1923 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1924 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 1925} 1926 1927static int 1928ahci_wait_ready(device_t dev, int t) 1929{ 1930 struct ahci_channel *ch = device_get_softc(dev); 1931 int timeout = 0; 1932 uint32_t val; 1933 1934 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 1935 (ATA_S_BUSY | ATA_S_DRQ)) { 1936 DELAY(1000); 1937 if (timeout++ > t) { 1938 device_printf(dev, "port is not ready (timeout %dms) " 1939 "tfd = %08x\n", t, val); 1940 return (EBUSY); 1941 } 1942 } 1943 if (bootverbose) 1944 device_printf(dev, "ready wait time=%dms\n", timeout); 1945 return (0); 1946} 1947 1948static void 1949ahci_reset(device_t dev) 1950{ 1951 struct ahci_channel *ch = device_get_softc(dev); 1952 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1953 int i; 1954 1955 if (bootverbose) 1956 device_printf(dev, "AHCI reset...\n"); 1957 /* Requeue freezed command. */ 1958 if (ch->frozen) { 1959 union ccb *fccb = ch->frozen; 1960 ch->frozen = NULL; 1961 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1962 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1963 xpt_freeze_devq(fccb->ccb_h.path, 1); 1964 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1965 } 1966 xpt_done(fccb); 1967 } 1968 /* Kill the engine and requeue all running commands. */ 1969 ahci_stop(dev); 1970 for (i = 0; i < ch->numslots; i++) { 1971 /* Do we have a running request on slot? */ 1972 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1973 continue; 1974 /* XXX; Commands in loading state. */ 1975 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 1976 } 1977 for (i = 0; i < ch->numslots; i++) { 1978 if (!ch->hold[i]) 1979 continue; 1980 xpt_done(ch->hold[i]); 1981 ch->hold[i] = NULL; 1982 } 1983 ch->fatalerr = 0; 1984 /* Tell the XPT about the event */ 1985 xpt_async(AC_BUS_RESET, ch->path, NULL); 1986 /* Disable port interrupts */ 1987 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1988 /* Reset and reconnect PHY, */ 1989 if (!ahci_sata_phy_reset(dev, 0)) { 1990 if (bootverbose) 1991 device_printf(dev, 1992 "AHCI reset done: phy reset found no device\n"); 1993 ch->devices = 0; 1994 /* Enable wanted port interrupts */ 1995 ATA_OUTL(ch->r_mem, AHCI_P_IE, 1996 (AHCI_P_IX_CPD | AHCI_P_IX_PRC | AHCI_P_IX_PC)); 1997 return; 1998 } 1999 /* Wait for clearing busy status. */ 2000 if (ahci_wait_ready(dev, 10000)) { 2001 device_printf(dev, "device ready timeout\n"); 2002 ahci_clo(dev); 2003 } 2004 ahci_start(dev); 2005 ch->devices = 1; 2006 /* Enable wanted port interrupts */ 2007 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2008 (AHCI_P_IX_CPD | AHCI_P_IX_TFE | AHCI_P_IX_HBF | 2009 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 2010 ((ch->pm_level == 0) ? AHCI_P_IX_PRC | AHCI_P_IX_PC : 0) | 2011 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 2012 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 2013 if (bootverbose) 2014 device_printf(dev, "AHCI reset done: device found\n"); 2015} 2016 2017static int 2018ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 2019{ 2020 struct ahci_channel *ch = device_get_softc(dev); 2021 u_int8_t *fis = &ctp->cfis[0]; 2022 2023 bzero(ctp->cfis, 64); 2024 fis[0] = 0x27; /* host to device */ 2025 fis[1] = (ccb->ccb_h.target_id & 0x0f); 2026 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2027 fis[1] |= 0x80; 2028 fis[2] = ATA_PACKET_CMD; 2029 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2030 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 2031 fis[3] = ATA_F_DMA; 2032 else { 2033 fis[5] = ccb->csio.dxfer_len; 2034 fis[6] = ccb->csio.dxfer_len >> 8; 2035 } 2036 fis[7] = ATA_D_LBA; 2037 fis[15] = ATA_A_4BIT; 2038 bzero(ctp->acmd, 32); 2039 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 2040 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 2041 ctp->acmd, ccb->csio.cdb_len); 2042 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 2043 fis[1] |= 0x80; 2044 fis[2] = ccb->ataio.cmd.command; 2045 fis[3] = ccb->ataio.cmd.features; 2046 fis[4] = ccb->ataio.cmd.lba_low; 2047 fis[5] = ccb->ataio.cmd.lba_mid; 2048 fis[6] = ccb->ataio.cmd.lba_high; 2049 fis[7] = ccb->ataio.cmd.device; 2050 fis[8] = ccb->ataio.cmd.lba_low_exp; 2051 fis[9] = ccb->ataio.cmd.lba_mid_exp; 2052 fis[10] = ccb->ataio.cmd.lba_high_exp; 2053 fis[11] = ccb->ataio.cmd.features_exp; 2054 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 2055 fis[12] = tag << 3; 2056 fis[13] = 0; 2057 } else { 2058 fis[12] = ccb->ataio.cmd.sector_count; 2059 fis[13] = ccb->ataio.cmd.sector_count_exp; 2060 } 2061 fis[15] = ATA_A_4BIT; 2062 } else { 2063 fis[15] = ccb->ataio.cmd.control; 2064 } 2065 return (20); 2066} 2067 2068static int 2069ahci_sata_connect(struct ahci_channel *ch) 2070{ 2071 u_int32_t status; 2072 int timeout; 2073 2074 /* Wait up to 100ms for "connect well" */ 2075 for (timeout = 0; timeout < 100 ; timeout++) { 2076 status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 2077 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 2078 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 2079 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 2080 break; 2081 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 2082 if (bootverbose) { 2083 device_printf(ch->dev, "SATA offline status=%08x\n", 2084 status); 2085 } 2086 return (0); 2087 } 2088 DELAY(1000); 2089 } 2090 if (timeout >= 100) { 2091 if (bootverbose) { 2092 device_printf(ch->dev, "SATA connect timeout status=%08x\n", 2093 status); 2094 } 2095 return (0); 2096 } 2097 if (bootverbose) { 2098 device_printf(ch->dev, "SATA connect time=%dms status=%08x\n", 2099 timeout, status); 2100 } 2101 /* Clear SATA error register */ 2102 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 2103 return (1); 2104} 2105 2106static int 2107ahci_sata_phy_reset(device_t dev, int quick) 2108{ 2109 struct ahci_channel *ch = device_get_softc(dev); 2110 int sata_rev; 2111 uint32_t val; 2112 2113 if (quick) { 2114 val = ATA_INL(ch->r_mem, AHCI_P_SCTL); 2115 if ((val & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE) 2116 return (ahci_sata_connect(ch)); 2117 } 2118 2119 if (bootverbose) 2120 device_printf(dev, "hardware reset ...\n"); 2121 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 2122 if (sata_rev == 1) 2123 val = ATA_SC_SPD_SPEED_GEN1; 2124 else if (sata_rev == 2) 2125 val = ATA_SC_SPD_SPEED_GEN2; 2126 else if (sata_rev == 3) 2127 val = ATA_SC_SPD_SPEED_GEN3; 2128 else 2129 val = 0; 2130 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2131 ATA_SC_DET_RESET | val | 2132 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 2133 DELAY(5000); 2134 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2135 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 2136 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 2137 DELAY(5000); 2138 return (ahci_sata_connect(ch)); 2139} 2140 2141static void 2142ahciaction(struct cam_sim *sim, union ccb *ccb) 2143{ 2144 device_t dev; 2145 struct ahci_channel *ch; 2146 2147 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 2148 ccb->ccb_h.func_code)); 2149 2150 ch = (struct ahci_channel *)cam_sim_softc(sim); 2151 dev = ch->dev; 2152 switch (ccb->ccb_h.func_code) { 2153 /* Common cases first */ 2154 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2155 case XPT_SCSI_IO: 2156 if (ch->devices == 0) { 2157 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2158 xpt_done(ccb); 2159 break; 2160 } 2161 /* Check for command collision. */ 2162 if (ahci_check_collision(dev, ccb)) { 2163 /* Freeze command. */ 2164 ch->frozen = ccb; 2165 /* We have only one frozen slot, so freeze simq also. */ 2166 xpt_freeze_simq(ch->sim, 1); 2167 return; 2168 } 2169 ahci_begin_transaction(dev, ccb); 2170 break; 2171 case XPT_EN_LUN: /* Enable LUN as a target */ 2172 case XPT_TARGET_IO: /* Execute target I/O request */ 2173 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2174 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2175 case XPT_ABORT: /* Abort the specified CCB */ 2176 /* XXX Implement */ 2177 ccb->ccb_h.status = CAM_REQ_INVALID; 2178 xpt_done(ccb); 2179 break; 2180 case XPT_SET_TRAN_SETTINGS: 2181 { 2182 struct ccb_trans_settings *cts = &ccb->cts; 2183 struct ahci_device *d; 2184 2185 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2186 d = &ch->curr[ccb->ccb_h.target_id]; 2187 else 2188 d = &ch->user[ccb->ccb_h.target_id]; 2189 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2190 d->revision = cts->xport_specific.sata.revision; 2191 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2192 d->mode = cts->xport_specific.sata.mode; 2193 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 2194 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 2195 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2196 d->tags = min(ch->numslots, cts->xport_specific.sata.tags); 2197 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2198 ch->pm_present = cts->xport_specific.sata.pm_present; 2199 ccb->ccb_h.status = CAM_REQ_CMP; 2200 xpt_done(ccb); 2201 break; 2202 } 2203 case XPT_GET_TRAN_SETTINGS: 2204 /* Get default/user set transfer settings for the target */ 2205 { 2206 struct ccb_trans_settings *cts = &ccb->cts; 2207 struct ahci_device *d; 2208 uint32_t status; 2209 2210 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2211 d = &ch->curr[ccb->ccb_h.target_id]; 2212 else 2213 d = &ch->user[ccb->ccb_h.target_id]; 2214 cts->protocol = PROTO_ATA; 2215 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2216 cts->transport = XPORT_SATA; 2217 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2218 cts->proto_specific.valid = 0; 2219 cts->xport_specific.sata.valid = 0; 2220 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 2221 (ccb->ccb_h.target_id == 15 || 2222 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 2223 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 2224 if (status & 0x0f0) { 2225 cts->xport_specific.sata.revision = 2226 (status & 0x0f0) >> 4; 2227 cts->xport_specific.sata.valid |= 2228 CTS_SATA_VALID_REVISION; 2229 } 2230 } else { 2231 cts->xport_specific.sata.revision = d->revision; 2232 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 2233 } 2234 cts->xport_specific.sata.mode = d->mode; 2235 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 2236 cts->xport_specific.sata.bytecount = d->bytecount; 2237 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 2238 cts->xport_specific.sata.pm_present = ch->pm_present; 2239 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2240 cts->xport_specific.sata.tags = d->tags; 2241 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 2242 ccb->ccb_h.status = CAM_REQ_CMP; 2243 xpt_done(ccb); 2244 break; 2245 } 2246#if 0 2247 case XPT_CALC_GEOMETRY: 2248 { 2249 struct ccb_calc_geometry *ccg; 2250 uint32_t size_mb; 2251 uint32_t secs_per_cylinder; 2252 2253 ccg = &ccb->ccg; 2254 size_mb = ccg->volume_size 2255 / ((1024L * 1024L) / ccg->block_size); 2256 if (size_mb >= 1024 && (aha->extended_trans != 0)) { 2257 if (size_mb >= 2048) { 2258 ccg->heads = 255; 2259 ccg->secs_per_track = 63; 2260 } else { 2261 ccg->heads = 128; 2262 ccg->secs_per_track = 32; 2263 } 2264 } else { 2265 ccg->heads = 64; 2266 ccg->secs_per_track = 32; 2267 } 2268 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 2269 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 2270 ccb->ccb_h.status = CAM_REQ_CMP; 2271 xpt_done(ccb); 2272 break; 2273 } 2274#endif 2275 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2276 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2277 ahci_reset(dev); 2278 ccb->ccb_h.status = CAM_REQ_CMP; 2279 xpt_done(ccb); 2280 break; 2281 case XPT_TERM_IO: /* Terminate the I/O process */ 2282 /* XXX Implement */ 2283 ccb->ccb_h.status = CAM_REQ_INVALID; 2284 xpt_done(ccb); 2285 break; 2286 case XPT_PATH_INQ: /* Path routing inquiry */ 2287 { 2288 struct ccb_pathinq *cpi = &ccb->cpi; 2289 2290 cpi->version_num = 1; /* XXX??? */ 2291 cpi->hba_inquiry = PI_SDTR_ABLE; 2292 if (ch->caps & AHCI_CAP_SNCQ) 2293 cpi->hba_inquiry |= PI_TAG_ABLE; 2294 if (ch->caps & AHCI_CAP_SPM) 2295 cpi->hba_inquiry |= PI_SATAPM; 2296 cpi->target_sprt = 0; 2297 cpi->hba_misc = PIM_SEQSCAN; 2298 cpi->hba_eng_cnt = 0; 2299 if (ch->caps & AHCI_CAP_SPM) 2300 cpi->max_target = 15; 2301 else 2302 cpi->max_target = 0; 2303 cpi->max_lun = 0; 2304 cpi->initiator_id = 0; 2305 cpi->bus_id = cam_sim_bus(sim); 2306 cpi->base_transfer_speed = 150000; 2307 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2308 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 2309 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2310 cpi->unit_number = cam_sim_unit(sim); 2311 cpi->transport = XPORT_SATA; 2312 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 2313 cpi->protocol = PROTO_ATA; 2314 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 2315 cpi->maxio = MAXPHYS; 2316 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 2317 if (pci_get_devid(device_get_parent(dev)) == 0x43801002) 2318 cpi->maxio = min(cpi->maxio, 128 * 512); 2319 cpi->ccb_h.status = CAM_REQ_CMP; 2320 xpt_done(ccb); 2321 break; 2322 } 2323 default: 2324 ccb->ccb_h.status = CAM_REQ_INVALID; 2325 xpt_done(ccb); 2326 break; 2327 } 2328} 2329 2330static void 2331ahcipoll(struct cam_sim *sim) 2332{ 2333 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 2334 2335 ahci_ch_intr(ch->dev); 2336} 2337