agp_amd.c revision 113506
1/*-
2 * Copyright (c) 2000 Doug Rabson
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 *	$FreeBSD: head/sys/dev/agp/agp_amd.c 113506 2003-04-15 06:37:30Z mdodd $
27 */
28
29#include "opt_bus.h"
30
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/malloc.h>
34#include <sys/kernel.h>
35#include <sys/bus.h>
36#include <sys/lock.h>
37#include <sys/lockmgr.h>
38#include <sys/mutex.h>
39#include <sys/proc.h>
40
41#include <pci/pcivar.h>
42#include <pci/pcireg.h>
43#include <pci/agppriv.h>
44#include <pci/agpreg.h>
45
46#include <vm/vm.h>
47#include <vm/vm_object.h>
48#include <vm/pmap.h>
49#include <machine/bus.h>
50#include <machine/resource.h>
51#include <sys/rman.h>
52
53MALLOC_DECLARE(M_AGP);
54
55#define READ2(off)	bus_space_read_2(sc->bst, sc->bsh, off)
56#define READ4(off)	bus_space_read_4(sc->bst, sc->bsh, off)
57#define WRITE2(off,v)	bus_space_write_2(sc->bst, sc->bsh, off, v)
58#define WRITE4(off,v)	bus_space_write_4(sc->bst, sc->bsh, off, v)
59
60struct agp_amd_gatt {
61	u_int32_t	ag_entries;
62	u_int32_t      *ag_virtual;	/* virtual address of gatt */
63	vm_offset_t     ag_physical;
64	u_int32_t      *ag_vdir;	/* virtual address of page dir */
65	vm_offset_t	ag_pdir;	/* physical address of page dir */
66};
67
68struct agp_amd_softc {
69	struct agp_softc agp;
70	struct resource *regs;	/* memory mapped control registers */
71	bus_space_tag_t bst;	/* bus_space tag */
72	bus_space_handle_t bsh;	/* bus_space handle */
73	u_int32_t	initial_aperture; /* aperture size at startup */
74	struct agp_amd_gatt *gatt;
75};
76
77static struct agp_amd_gatt *
78agp_amd_alloc_gatt(device_t dev)
79{
80	u_int32_t apsize = AGP_GET_APERTURE(dev);
81	u_int32_t entries = apsize >> AGP_PAGE_SHIFT;
82	struct agp_amd_gatt *gatt;
83	int i, npages, pdir_offset;
84
85	if (bootverbose)
86		device_printf(dev,
87			      "allocating GATT for aperture of size %dM\n",
88			      apsize / (1024*1024));
89
90	gatt = malloc(sizeof(struct agp_amd_gatt), M_AGP, M_NOWAIT);
91	if (!gatt)
92		return 0;
93
94	/*
95	 * The AMD751 uses a page directory to map a non-contiguous
96	 * gatt so we don't need to use contigmalloc.
97	 * Malloc individual gatt pages and map them into the page
98	 * directory.
99	 */
100	gatt->ag_entries = entries;
101	gatt->ag_virtual = malloc(entries * sizeof(u_int32_t),
102				  M_AGP, M_NOWAIT);
103	if (!gatt->ag_virtual) {
104		if (bootverbose)
105			device_printf(dev, "allocation failed\n");
106		free(gatt, M_AGP);
107		return 0;
108	}
109	bzero(gatt->ag_virtual, entries * sizeof(u_int32_t));
110
111	/*
112	 * Allocate the page directory.
113	 */
114	gatt->ag_vdir = malloc(AGP_PAGE_SIZE, M_AGP, M_NOWAIT);
115	if (!gatt->ag_vdir) {
116		if (bootverbose)
117			device_printf(dev,
118				      "failed to allocate page directory\n");
119		free(gatt->ag_virtual, M_AGP);
120		free(gatt, M_AGP);
121		return 0;
122	}
123	bzero(gatt->ag_vdir, AGP_PAGE_SIZE);
124
125	gatt->ag_pdir = vtophys((vm_offset_t) gatt->ag_vdir);
126	if(bootverbose)
127		device_printf(dev, "gatt -> ag_pdir %#lx\n",
128		    (u_long)gatt->ag_pdir);
129	/*
130	 * Allocate the gatt pages
131	 */
132	gatt->ag_entries = entries;
133	if(bootverbose)
134		device_printf(dev, "allocating GATT for %d AGP page entries\n",
135			gatt->ag_entries);
136
137	gatt->ag_physical = vtophys((vm_offset_t) gatt->ag_virtual);
138
139	/*
140	 * Map the pages of the GATT into the page directory.
141	 *
142	 * The GATT page addresses are mapped into the directory offset by
143	 * an amount dependent on the base address of the aperture. This
144	 * is and offset into the page directory, not an offset added to
145	 * the addresses of the gatt pages.
146	 */
147
148	pdir_offset = pci_read_config(dev, AGP_AMD751_APBASE, 4) >> 22;
149
150	npages = ((entries * sizeof(u_int32_t) + AGP_PAGE_SIZE - 1)
151		  >> AGP_PAGE_SHIFT);
152
153	for (i = 0; i < npages; i++) {
154		vm_offset_t va;
155		vm_offset_t pa;
156
157		va = ((vm_offset_t) gatt->ag_virtual) + i * AGP_PAGE_SIZE;
158		pa = vtophys(va);
159		gatt->ag_vdir[i + pdir_offset] = pa | 1;
160	}
161
162	/*
163	 * Make sure the chipset can see everything.
164	 */
165	agp_flush_cache();
166
167	return gatt;
168}
169
170static void
171agp_amd_free_gatt(struct agp_amd_gatt *gatt)
172{
173	free(gatt->ag_virtual, M_AGP);
174	free(gatt->ag_vdir, M_AGP);
175	free(gatt, M_AGP);
176}
177
178static const char*
179agp_amd_match(device_t dev)
180{
181	if (pci_get_class(dev) != PCIC_BRIDGE
182	    || pci_get_subclass(dev) != PCIS_BRIDGE_HOST)
183		return NULL;
184
185	if (agp_find_caps(dev) == 0)
186		return NULL;
187
188	switch (pci_get_devid(dev)) {
189
190	case 0x700e1022:
191		return ("AMD 761 host to AGP bridge");
192
193	case 0x70061022:
194		return ("AMD 751 host to AGP bridge");
195
196	case 0x700c1022:
197		return ("AMD 762 host to AGP bridge");
198
199	};
200
201	return NULL;
202}
203
204static int
205agp_amd_probe(device_t dev)
206{
207	const char *desc;
208
209	desc = agp_amd_match(dev);
210	if (desc) {
211		device_verbose(dev);
212		device_set_desc(dev, desc);
213		return 0;
214	}
215
216	return ENXIO;
217}
218
219static int
220agp_amd_attach(device_t dev)
221{
222	struct agp_amd_softc *sc = device_get_softc(dev);
223	struct agp_amd_gatt *gatt;
224	int error, rid;
225
226	error = agp_generic_attach(dev);
227	if (error)
228		return error;
229
230	rid = AGP_AMD751_REGISTERS;
231	sc->regs = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
232				      0, ~0, 1, RF_ACTIVE);
233	if (!sc->regs) {
234		agp_generic_detach(dev);
235		return ENOMEM;
236	}
237
238	sc->bst = rman_get_bustag(sc->regs);
239	sc->bsh = rman_get_bushandle(sc->regs);
240
241	sc->initial_aperture = AGP_GET_APERTURE(dev);
242
243	for (;;) {
244		gatt = agp_amd_alloc_gatt(dev);
245		if (gatt)
246			break;
247
248		/*
249		 * Probably contigmalloc failure. Try reducing the
250		 * aperture so that the gatt size reduces.
251		 */
252		if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2))
253			return ENOMEM;
254	}
255	sc->gatt = gatt;
256
257	/* Install the gatt. */
258	WRITE4(AGP_AMD751_ATTBASE, gatt->ag_pdir);
259
260	/* Enable synchronisation between host and agp. */
261	pci_write_config(dev,
262			 AGP_AMD751_MODECTRL,
263			 AGP_AMD751_MODECTRL_SYNEN, 1);
264
265	/* Set indexing mode for two-level and enable page dir cache */
266	pci_write_config(dev,
267			 AGP_AMD751_MODECTRL2,
268			 AGP_AMD751_MODECTRL2_GPDCE, 1);
269
270	/* Enable the TLB and flush */
271	WRITE2(AGP_AMD751_STATUS,
272	       READ2(AGP_AMD751_STATUS) | AGP_AMD751_STATUS_GCE);
273	AGP_FLUSH_TLB(dev);
274
275	return 0;
276}
277
278static int
279agp_amd_detach(device_t dev)
280{
281	struct agp_amd_softc *sc = device_get_softc(dev);
282	int error;
283
284	error = agp_generic_detach(dev);
285	if (error)
286		return error;
287
288	/* Disable the TLB.. */
289	WRITE2(AGP_AMD751_STATUS,
290	       READ2(AGP_AMD751_STATUS) & ~AGP_AMD751_STATUS_GCE);
291
292	/* Disable host-agp sync */
293	pci_write_config(dev, AGP_AMD751_MODECTRL, 0x00, 1);
294
295	/* Clear the GATT base */
296	WRITE4(AGP_AMD751_ATTBASE, 0);
297
298	/* Put the aperture back the way it started. */
299	AGP_SET_APERTURE(dev, sc->initial_aperture);
300
301	agp_amd_free_gatt(sc->gatt);
302
303	bus_release_resource(dev, SYS_RES_MEMORY,
304			     AGP_AMD751_REGISTERS, sc->regs);
305
306	return 0;
307}
308
309static u_int32_t
310agp_amd_get_aperture(device_t dev)
311{
312	int vas;
313
314	/*
315	 * The aperture size is equal to 32M<<vas.
316	 */
317	vas = (pci_read_config(dev, AGP_AMD751_APCTRL, 1) & 0x06) >> 1;
318	return (32*1024*1024) << vas;
319}
320
321static int
322agp_amd_set_aperture(device_t dev, u_int32_t aperture)
323{
324	int vas;
325
326	/*
327	 * Check for a power of two and make sure its within the
328	 * programmable range.
329	 */
330	if (aperture & (aperture - 1)
331	    || aperture < 32*1024*1024
332	    || aperture > 2U*1024*1024*1024)
333		return EINVAL;
334
335	vas = ffs(aperture / 32*1024*1024) - 1;
336
337	/*
338	 * While the size register is bits 1-3 of APCTRL, bit 0 must be
339	 * set for the size value to be 'valid'
340	 */
341	pci_write_config(dev, AGP_AMD751_APCTRL,
342			 (((pci_read_config(dev, AGP_AMD751_APCTRL, 1) & ~0x06)
343			  | ((vas << 1) | 1))), 1);
344
345	return 0;
346}
347
348static int
349agp_amd_bind_page(device_t dev, int offset, vm_offset_t physical)
350{
351	struct agp_amd_softc *sc = device_get_softc(dev);
352
353	if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
354		return EINVAL;
355
356	sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 1;
357
358	/* invalidate the cache */
359	AGP_FLUSH_TLB(dev);
360	return 0;
361}
362
363static int
364agp_amd_unbind_page(device_t dev, int offset)
365{
366	struct agp_amd_softc *sc = device_get_softc(dev);
367
368	if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
369		return EINVAL;
370
371	sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
372	return 0;
373}
374
375static void
376agp_amd_flush_tlb(device_t dev)
377{
378	struct agp_amd_softc *sc = device_get_softc(dev);
379
380	/* Set the cache invalidate bit and wait for the chipset to clear */
381	WRITE4(AGP_AMD751_TLBCTRL, 1);
382	do {
383		DELAY(1);
384	} while (READ4(AGP_AMD751_TLBCTRL));
385}
386
387static device_method_t agp_amd_methods[] = {
388	/* Device interface */
389	DEVMETHOD(device_probe,		agp_amd_probe),
390	DEVMETHOD(device_attach,	agp_amd_attach),
391	DEVMETHOD(device_detach,	agp_amd_detach),
392	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
393	DEVMETHOD(device_suspend,	bus_generic_suspend),
394	DEVMETHOD(device_resume,	bus_generic_resume),
395
396	/* AGP interface */
397	DEVMETHOD(agp_get_aperture,	agp_amd_get_aperture),
398	DEVMETHOD(agp_set_aperture,	agp_amd_set_aperture),
399	DEVMETHOD(agp_bind_page,	agp_amd_bind_page),
400	DEVMETHOD(agp_unbind_page,	agp_amd_unbind_page),
401	DEVMETHOD(agp_flush_tlb,	agp_amd_flush_tlb),
402	DEVMETHOD(agp_enable,		agp_generic_enable),
403	DEVMETHOD(agp_alloc_memory,	agp_generic_alloc_memory),
404	DEVMETHOD(agp_free_memory,	agp_generic_free_memory),
405	DEVMETHOD(agp_bind_memory,	agp_generic_bind_memory),
406	DEVMETHOD(agp_unbind_memory,	agp_generic_unbind_memory),
407
408	{ 0, 0 }
409};
410
411static driver_t agp_amd_driver = {
412	"agp",
413	agp_amd_methods,
414	sizeof(struct agp_amd_softc),
415};
416
417static devclass_t agp_devclass;
418
419DRIVER_MODULE(agp_amd, pci, agp_amd_driver, agp_devclass, 0, 0);
420MODULE_DEPEND(agp_amd, agp, 1, 1, 1);
421MODULE_DEPEND(agp_amd, pci, 1, 1, 1);
422