if_ae.c revision 227452
1/*- 2 * Copyright (c) 2008 Stanislav Sedov <stas@FreeBSD.org>. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * Driver for Attansic Technology Corp. L2 FastEthernet adapter. 26 * 27 * This driver is heavily based on age(4) Attansic L1 driver by Pyun YongHyeon. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/ae/if_ae.c 227452 2011-11-11 19:15:32Z yongari $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/kernel.h> 38#include <sys/malloc.h> 39#include <sys/mbuf.h> 40#include <sys/rman.h> 41#include <sys/module.h> 42#include <sys/queue.h> 43#include <sys/socket.h> 44#include <sys/sockio.h> 45#include <sys/sysctl.h> 46#include <sys/taskqueue.h> 47 48#include <net/bpf.h> 49#include <net/if.h> 50#include <net/if_arp.h> 51#include <net/ethernet.h> 52#include <net/if_dl.h> 53#include <net/if_media.h> 54#include <net/if_types.h> 55#include <net/if_vlan_var.h> 56 57#include <netinet/in.h> 58#include <netinet/in_systm.h> 59#include <netinet/ip.h> 60#include <netinet/tcp.h> 61 62#include <dev/mii/mii.h> 63#include <dev/mii/miivar.h> 64#include <dev/pci/pcireg.h> 65#include <dev/pci/pcivar.h> 66 67#include <machine/bus.h> 68 69#include "miibus_if.h" 70 71#include "if_aereg.h" 72#include "if_aevar.h" 73 74/* 75 * Devices supported by this driver. 76 */ 77static struct ae_dev { 78 uint16_t vendorid; 79 uint16_t deviceid; 80 const char *name; 81} ae_devs[] = { 82 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L2, 83 "Attansic Technology Corp, L2 FastEthernet" }, 84}; 85#define AE_DEVS_COUNT (sizeof(ae_devs) / sizeof(*ae_devs)) 86 87static struct resource_spec ae_res_spec_mem[] = { 88 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 89 { -1, 0, 0 } 90}; 91static struct resource_spec ae_res_spec_irq[] = { 92 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 93 { -1, 0, 0 } 94}; 95static struct resource_spec ae_res_spec_msi[] = { 96 { SYS_RES_IRQ, 1, RF_ACTIVE }, 97 { -1, 0, 0 } 98}; 99 100static int ae_probe(device_t dev); 101static int ae_attach(device_t dev); 102static void ae_pcie_init(ae_softc_t *sc); 103static void ae_phy_reset(ae_softc_t *sc); 104static void ae_phy_init(ae_softc_t *sc); 105static int ae_reset(ae_softc_t *sc); 106static void ae_init(void *arg); 107static int ae_init_locked(ae_softc_t *sc); 108static int ae_detach(device_t dev); 109static int ae_miibus_readreg(device_t dev, int phy, int reg); 110static int ae_miibus_writereg(device_t dev, int phy, int reg, int val); 111static void ae_miibus_statchg(device_t dev); 112static void ae_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr); 113static int ae_mediachange(struct ifnet *ifp); 114static void ae_retrieve_address(ae_softc_t *sc); 115static void ae_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, 116 int error); 117static int ae_alloc_rings(ae_softc_t *sc); 118static void ae_dma_free(ae_softc_t *sc); 119static int ae_shutdown(device_t dev); 120static int ae_suspend(device_t dev); 121static void ae_powersave_disable(ae_softc_t *sc); 122static void ae_powersave_enable(ae_softc_t *sc); 123static int ae_resume(device_t dev); 124static unsigned int ae_tx_avail_size(ae_softc_t *sc); 125static int ae_encap(ae_softc_t *sc, struct mbuf **m_head); 126static void ae_start(struct ifnet *ifp); 127static void ae_start_locked(struct ifnet *ifp); 128static void ae_link_task(void *arg, int pending); 129static void ae_stop_rxmac(ae_softc_t *sc); 130static void ae_stop_txmac(ae_softc_t *sc); 131static void ae_mac_config(ae_softc_t *sc); 132static int ae_intr(void *arg); 133static void ae_int_task(void *arg, int pending); 134static void ae_tx_intr(ae_softc_t *sc); 135static int ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd); 136static void ae_rx_intr(ae_softc_t *sc); 137static void ae_watchdog(ae_softc_t *sc); 138static void ae_tick(void *arg); 139static void ae_rxfilter(ae_softc_t *sc); 140static void ae_rxvlan(ae_softc_t *sc); 141static int ae_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 142static void ae_stop(ae_softc_t *sc); 143static int ae_check_eeprom_present(ae_softc_t *sc, int *vpdc); 144static int ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word); 145static int ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr); 146static int ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr); 147static void ae_update_stats_rx(uint16_t flags, ae_stats_t *stats); 148static void ae_update_stats_tx(uint16_t flags, ae_stats_t *stats); 149static void ae_init_tunables(ae_softc_t *sc); 150 151static device_method_t ae_methods[] = { 152 /* Device interface. */ 153 DEVMETHOD(device_probe, ae_probe), 154 DEVMETHOD(device_attach, ae_attach), 155 DEVMETHOD(device_detach, ae_detach), 156 DEVMETHOD(device_shutdown, ae_shutdown), 157 DEVMETHOD(device_suspend, ae_suspend), 158 DEVMETHOD(device_resume, ae_resume), 159 160 /* MII interface. */ 161 DEVMETHOD(miibus_readreg, ae_miibus_readreg), 162 DEVMETHOD(miibus_writereg, ae_miibus_writereg), 163 DEVMETHOD(miibus_statchg, ae_miibus_statchg), 164 165 { NULL, NULL } 166}; 167static driver_t ae_driver = { 168 "ae", 169 ae_methods, 170 sizeof(ae_softc_t) 171}; 172static devclass_t ae_devclass; 173 174DRIVER_MODULE(ae, pci, ae_driver, ae_devclass, 0, 0); 175DRIVER_MODULE(miibus, ae, miibus_driver, miibus_devclass, 0, 0); 176MODULE_DEPEND(ae, pci, 1, 1, 1); 177MODULE_DEPEND(ae, ether, 1, 1, 1); 178MODULE_DEPEND(ae, miibus, 1, 1, 1); 179 180/* 181 * Tunables. 182 */ 183static int msi_disable = 0; 184TUNABLE_INT("hw.ae.msi_disable", &msi_disable); 185 186#define AE_READ_4(sc, reg) \ 187 bus_read_4((sc)->mem[0], (reg)) 188#define AE_READ_2(sc, reg) \ 189 bus_read_2((sc)->mem[0], (reg)) 190#define AE_READ_1(sc, reg) \ 191 bus_read_1((sc)->mem[0], (reg)) 192#define AE_WRITE_4(sc, reg, val) \ 193 bus_write_4((sc)->mem[0], (reg), (val)) 194#define AE_WRITE_2(sc, reg, val) \ 195 bus_write_2((sc)->mem[0], (reg), (val)) 196#define AE_WRITE_1(sc, reg, val) \ 197 bus_write_1((sc)->mem[0], (reg), (val)) 198#define AE_PHY_READ(sc, reg) \ 199 ae_miibus_readreg(sc->dev, 0, reg) 200#define AE_PHY_WRITE(sc, reg, val) \ 201 ae_miibus_writereg(sc->dev, 0, reg, val) 202#define AE_CHECK_EADDR_VALID(eaddr) \ 203 ((eaddr[0] == 0 && eaddr[1] == 0) || \ 204 (eaddr[0] == 0xffffffff && eaddr[1] == 0xffff)) 205#define AE_RXD_VLAN(vtag) \ 206 (((vtag) >> 4) | (((vtag) & 0x07) << 13) | (((vtag) & 0x08) << 9)) 207#define AE_TXD_VLAN(vtag) \ 208 (((vtag) << 4) | (((vtag) >> 13) & 0x07) | (((vtag) >> 9) & 0x08)) 209 210static int 211ae_probe(device_t dev) 212{ 213 uint16_t deviceid, vendorid; 214 int i; 215 216 vendorid = pci_get_vendor(dev); 217 deviceid = pci_get_device(dev); 218 219 /* 220 * Search through the list of supported devs for matching one. 221 */ 222 for (i = 0; i < AE_DEVS_COUNT; i++) { 223 if (vendorid == ae_devs[i].vendorid && 224 deviceid == ae_devs[i].deviceid) { 225 device_set_desc(dev, ae_devs[i].name); 226 return (BUS_PROBE_DEFAULT); 227 } 228 } 229 return (ENXIO); 230} 231 232static int 233ae_attach(device_t dev) 234{ 235 ae_softc_t *sc; 236 struct ifnet *ifp; 237 uint8_t chiprev; 238 uint32_t pcirev; 239 int nmsi, pmc; 240 int error; 241 242 sc = device_get_softc(dev); /* Automatically allocated and zeroed 243 on attach. */ 244 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 245 sc->dev = dev; 246 247 /* 248 * Initialize mutexes and tasks. 249 */ 250 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); 251 callout_init_mtx(&sc->tick_ch, &sc->mtx, 0); 252 TASK_INIT(&sc->int_task, 0, ae_int_task, sc); 253 TASK_INIT(&sc->link_task, 0, ae_link_task, sc); 254 255 pci_enable_busmaster(dev); /* Enable bus mastering. */ 256 257 sc->spec_mem = ae_res_spec_mem; 258 259 /* 260 * Allocate memory-mapped registers. 261 */ 262 error = bus_alloc_resources(dev, sc->spec_mem, sc->mem); 263 if (error != 0) { 264 device_printf(dev, "could not allocate memory resources.\n"); 265 sc->spec_mem = NULL; 266 goto fail; 267 } 268 269 /* 270 * Retrieve PCI and chip revisions. 271 */ 272 pcirev = pci_get_revid(dev); 273 chiprev = (AE_READ_4(sc, AE_MASTER_REG) >> AE_MASTER_REVNUM_SHIFT) & 274 AE_MASTER_REVNUM_MASK; 275 if (bootverbose) { 276 device_printf(dev, "pci device revision: %#04x\n", pcirev); 277 device_printf(dev, "chip id: %#02x\n", chiprev); 278 } 279 nmsi = pci_msi_count(dev); 280 if (bootverbose) 281 device_printf(dev, "MSI count: %d.\n", nmsi); 282 283 /* 284 * Allocate interrupt resources. 285 */ 286 if (msi_disable == 0 && nmsi == 1) { 287 error = pci_alloc_msi(dev, &nmsi); 288 if (error == 0) { 289 device_printf(dev, "Using MSI messages.\n"); 290 sc->spec_irq = ae_res_spec_msi; 291 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq); 292 if (error != 0) { 293 device_printf(dev, "MSI allocation failed.\n"); 294 sc->spec_irq = NULL; 295 pci_release_msi(dev); 296 } else { 297 sc->flags |= AE_FLAG_MSI; 298 } 299 } 300 } 301 if (sc->spec_irq == NULL) { 302 sc->spec_irq = ae_res_spec_irq; 303 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq); 304 if (error != 0) { 305 device_printf(dev, "could not allocate IRQ resources.\n"); 306 sc->spec_irq = NULL; 307 goto fail; 308 } 309 } 310 311 ae_init_tunables(sc); 312 313 ae_phy_reset(sc); /* Reset PHY. */ 314 error = ae_reset(sc); /* Reset the controller itself. */ 315 if (error != 0) 316 goto fail; 317 318 ae_pcie_init(sc); 319 320 ae_retrieve_address(sc); /* Load MAC address. */ 321 322 error = ae_alloc_rings(sc); /* Allocate ring buffers. */ 323 if (error != 0) 324 goto fail; 325 326 ifp = sc->ifp = if_alloc(IFT_ETHER); 327 if (ifp == NULL) { 328 device_printf(dev, "could not allocate ifnet structure.\n"); 329 error = ENXIO; 330 goto fail; 331 } 332 333 ifp->if_softc = sc; 334 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 335 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 336 ifp->if_ioctl = ae_ioctl; 337 ifp->if_start = ae_start; 338 ifp->if_init = ae_init; 339 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 340 ifp->if_hwassist = 0; 341 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 342 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 343 IFQ_SET_READY(&ifp->if_snd); 344 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 345 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 346 sc->flags |= AE_FLAG_PMG; 347 } 348 ifp->if_capenable = ifp->if_capabilities; 349 350 /* 351 * Configure and attach MII bus. 352 */ 353 error = mii_attach(dev, &sc->miibus, ifp, ae_mediachange, 354 ae_mediastatus, BMSR_DEFCAPMASK, AE_PHYADDR_DEFAULT, 355 MII_OFFSET_ANY, 0); 356 if (error != 0) { 357 device_printf(dev, "attaching PHYs failed\n"); 358 goto fail; 359 } 360 361 ether_ifattach(ifp, sc->eaddr); 362 /* Tell the upper layer(s) we support long frames. */ 363 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 364 365 /* 366 * Create and run all helper tasks. 367 */ 368 sc->tq = taskqueue_create_fast("ae_taskq", M_WAITOK, 369 taskqueue_thread_enqueue, &sc->tq); 370 if (sc->tq == NULL) { 371 device_printf(dev, "could not create taskqueue.\n"); 372 ether_ifdetach(ifp); 373 error = ENXIO; 374 goto fail; 375 } 376 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq", 377 device_get_nameunit(sc->dev)); 378 379 /* 380 * Configure interrupt handlers. 381 */ 382 error = bus_setup_intr(dev, sc->irq[0], INTR_TYPE_NET | INTR_MPSAFE, 383 ae_intr, NULL, sc, &sc->intrhand); 384 if (error != 0) { 385 device_printf(dev, "could not set up interrupt handler.\n"); 386 taskqueue_free(sc->tq); 387 sc->tq = NULL; 388 ether_ifdetach(ifp); 389 goto fail; 390 } 391 392fail: 393 if (error != 0) 394 ae_detach(dev); 395 396 return (error); 397} 398 399#define AE_SYSCTL(stx, parent, name, desc, ptr) \ 400 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, name, CTLFLAG_RD, ptr, 0, desc) 401 402static void 403ae_init_tunables(ae_softc_t *sc) 404{ 405 struct sysctl_ctx_list *ctx; 406 struct sysctl_oid *root, *stats, *stats_rx, *stats_tx; 407 struct ae_stats *ae_stats; 408 409 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 410 ae_stats = &sc->stats; 411 412 ctx = device_get_sysctl_ctx(sc->dev); 413 root = device_get_sysctl_tree(sc->dev); 414 stats = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(root), OID_AUTO, "stats", 415 CTLFLAG_RD, NULL, "ae statistics"); 416 417 /* 418 * Receiver statistcics. 419 */ 420 stats_rx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "rx", 421 CTLFLAG_RD, NULL, "Rx MAC statistics"); 422 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "bcast", 423 "broadcast frames", &ae_stats->rx_bcast); 424 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "mcast", 425 "multicast frames", &ae_stats->rx_mcast); 426 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "pause", 427 "PAUSE frames", &ae_stats->rx_pause); 428 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "control", 429 "control frames", &ae_stats->rx_ctrl); 430 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "crc_errors", 431 "frames with CRC errors", &ae_stats->rx_crcerr); 432 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "code_errors", 433 "frames with invalid opcode", &ae_stats->rx_codeerr); 434 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "runt", 435 "runt frames", &ae_stats->rx_runt); 436 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "frag", 437 "fragmented frames", &ae_stats->rx_frag); 438 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "align_errors", 439 "frames with alignment errors", &ae_stats->rx_align); 440 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "truncated", 441 "frames truncated due to Rx FIFO inderrun", &ae_stats->rx_trunc); 442 443 /* 444 * Receiver statistcics. 445 */ 446 stats_tx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "tx", 447 CTLFLAG_RD, NULL, "Tx MAC statistics"); 448 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "bcast", 449 "broadcast frames", &ae_stats->tx_bcast); 450 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "mcast", 451 "multicast frames", &ae_stats->tx_mcast); 452 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "pause", 453 "PAUSE frames", &ae_stats->tx_pause); 454 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "control", 455 "control frames", &ae_stats->tx_ctrl); 456 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "defers", 457 "deferrals occuried", &ae_stats->tx_defer); 458 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "exc_defers", 459 "excessive deferrals occuried", &ae_stats->tx_excdefer); 460 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "singlecols", 461 "single collisions occuried", &ae_stats->tx_singlecol); 462 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "multicols", 463 "multiple collisions occuried", &ae_stats->tx_multicol); 464 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "latecols", 465 "late collisions occuried", &ae_stats->tx_latecol); 466 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "aborts", 467 "transmit aborts due collisions", &ae_stats->tx_abortcol); 468 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "underruns", 469 "Tx FIFO underruns", &ae_stats->tx_underrun); 470} 471 472static void 473ae_pcie_init(ae_softc_t *sc) 474{ 475 476 AE_WRITE_4(sc, AE_PCIE_LTSSM_TESTMODE_REG, AE_PCIE_LTSSM_TESTMODE_DEFAULT); 477 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, AE_PCIE_DLL_TX_CTRL_DEFAULT); 478} 479 480static void 481ae_phy_reset(ae_softc_t *sc) 482{ 483 484 AE_WRITE_4(sc, AE_PHY_ENABLE_REG, AE_PHY_ENABLE); 485 DELAY(1000); /* XXX: pause(9) ? */ 486} 487 488static int 489ae_reset(ae_softc_t *sc) 490{ 491 int i; 492 493 /* 494 * Issue a soft reset. 495 */ 496 AE_WRITE_4(sc, AE_MASTER_REG, AE_MASTER_SOFT_RESET); 497 bus_barrier(sc->mem[0], AE_MASTER_REG, 4, 498 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 499 500 /* 501 * Wait for reset to complete. 502 */ 503 for (i = 0; i < AE_RESET_TIMEOUT; i++) { 504 if ((AE_READ_4(sc, AE_MASTER_REG) & AE_MASTER_SOFT_RESET) == 0) 505 break; 506 DELAY(10); 507 } 508 if (i == AE_RESET_TIMEOUT) { 509 device_printf(sc->dev, "reset timeout.\n"); 510 return (ENXIO); 511 } 512 513 /* 514 * Wait for everything to enter idle state. 515 */ 516 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 517 if (AE_READ_4(sc, AE_IDLE_REG) == 0) 518 break; 519 DELAY(100); 520 } 521 if (i == AE_IDLE_TIMEOUT) { 522 device_printf(sc->dev, "could not enter idle state.\n"); 523 return (ENXIO); 524 } 525 return (0); 526} 527 528static void 529ae_init(void *arg) 530{ 531 ae_softc_t *sc; 532 533 sc = (ae_softc_t *)arg; 534 AE_LOCK(sc); 535 ae_init_locked(sc); 536 AE_UNLOCK(sc); 537} 538 539static void 540ae_phy_init(ae_softc_t *sc) 541{ 542 543 /* 544 * Enable link status change interrupt. 545 * XXX magic numbers. 546 */ 547#ifdef notyet 548 AE_PHY_WRITE(sc, 18, 0xc00); 549#endif 550} 551 552static int 553ae_init_locked(ae_softc_t *sc) 554{ 555 struct ifnet *ifp; 556 struct mii_data *mii; 557 uint8_t eaddr[ETHER_ADDR_LEN]; 558 uint32_t val; 559 bus_addr_t addr; 560 561 AE_LOCK_ASSERT(sc); 562 563 ifp = sc->ifp; 564 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 565 return (0); 566 mii = device_get_softc(sc->miibus); 567 568 ae_stop(sc); 569 ae_reset(sc); 570 ae_pcie_init(sc); /* Initialize PCIE stuff. */ 571 ae_phy_init(sc); 572 ae_powersave_disable(sc); 573 574 /* 575 * Clear and disable interrupts. 576 */ 577 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff); 578 579 /* 580 * Set the MAC address. 581 */ 582 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 583 val = eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]; 584 AE_WRITE_4(sc, AE_EADDR0_REG, val); 585 val = eaddr[0] << 8 | eaddr[1]; 586 AE_WRITE_4(sc, AE_EADDR1_REG, val); 587 588 /* 589 * Set ring buffers base addresses. 590 */ 591 addr = sc->dma_rxd_busaddr; 592 AE_WRITE_4(sc, AE_DESC_ADDR_HI_REG, BUS_ADDR_HI(addr)); 593 AE_WRITE_4(sc, AE_RXD_ADDR_LO_REG, BUS_ADDR_LO(addr)); 594 addr = sc->dma_txd_busaddr; 595 AE_WRITE_4(sc, AE_TXD_ADDR_LO_REG, BUS_ADDR_LO(addr)); 596 addr = sc->dma_txs_busaddr; 597 AE_WRITE_4(sc, AE_TXS_ADDR_LO_REG, BUS_ADDR_LO(addr)); 598 599 /* 600 * Configure ring buffers sizes. 601 */ 602 AE_WRITE_2(sc, AE_RXD_COUNT_REG, AE_RXD_COUNT_DEFAULT); 603 AE_WRITE_2(sc, AE_TXD_BUFSIZE_REG, AE_TXD_BUFSIZE_DEFAULT / 4); 604 AE_WRITE_2(sc, AE_TXS_COUNT_REG, AE_TXS_COUNT_DEFAULT); 605 606 /* 607 * Configure interframe gap parameters. 608 */ 609 val = ((AE_IFG_TXIPG_DEFAULT << AE_IFG_TXIPG_SHIFT) & 610 AE_IFG_TXIPG_MASK) | 611 ((AE_IFG_RXIPG_DEFAULT << AE_IFG_RXIPG_SHIFT) & 612 AE_IFG_RXIPG_MASK) | 613 ((AE_IFG_IPGR1_DEFAULT << AE_IFG_IPGR1_SHIFT) & 614 AE_IFG_IPGR1_MASK) | 615 ((AE_IFG_IPGR2_DEFAULT << AE_IFG_IPGR2_SHIFT) & 616 AE_IFG_IPGR2_MASK); 617 AE_WRITE_4(sc, AE_IFG_REG, val); 618 619 /* 620 * Configure half-duplex operation. 621 */ 622 val = ((AE_HDPX_LCOL_DEFAULT << AE_HDPX_LCOL_SHIFT) & 623 AE_HDPX_LCOL_MASK) | 624 ((AE_HDPX_RETRY_DEFAULT << AE_HDPX_RETRY_SHIFT) & 625 AE_HDPX_RETRY_MASK) | 626 ((AE_HDPX_ABEBT_DEFAULT << AE_HDPX_ABEBT_SHIFT) & 627 AE_HDPX_ABEBT_MASK) | 628 ((AE_HDPX_JAMIPG_DEFAULT << AE_HDPX_JAMIPG_SHIFT) & 629 AE_HDPX_JAMIPG_MASK) | AE_HDPX_EXC_EN; 630 AE_WRITE_4(sc, AE_HDPX_REG, val); 631 632 /* 633 * Configure interrupt moderate timer. 634 */ 635 AE_WRITE_2(sc, AE_IMT_REG, AE_IMT_DEFAULT); 636 val = AE_READ_4(sc, AE_MASTER_REG); 637 val |= AE_MASTER_IMT_EN; 638 AE_WRITE_4(sc, AE_MASTER_REG, val); 639 640 /* 641 * Configure interrupt clearing timer. 642 */ 643 AE_WRITE_2(sc, AE_ICT_REG, AE_ICT_DEFAULT); 644 645 /* 646 * Configure MTU. 647 */ 648 val = ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 649 ETHER_CRC_LEN; 650 AE_WRITE_2(sc, AE_MTU_REG, val); 651 652 /* 653 * Configure cut-through threshold. 654 */ 655 AE_WRITE_4(sc, AE_CUT_THRESH_REG, AE_CUT_THRESH_DEFAULT); 656 657 /* 658 * Configure flow control. 659 */ 660 AE_WRITE_2(sc, AE_FLOW_THRESH_HI_REG, (AE_RXD_COUNT_DEFAULT / 8) * 7); 661 AE_WRITE_2(sc, AE_FLOW_THRESH_LO_REG, (AE_RXD_COUNT_MIN / 8) > 662 (AE_RXD_COUNT_DEFAULT / 12) ? (AE_RXD_COUNT_MIN / 8) : 663 (AE_RXD_COUNT_DEFAULT / 12)); 664 665 /* 666 * Init mailboxes. 667 */ 668 sc->txd_cur = sc->rxd_cur = 0; 669 sc->txs_ack = sc->txd_ack = 0; 670 sc->rxd_cur = 0; 671 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur); 672 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur); 673 674 sc->tx_inproc = 0; /* Number of packets the chip processes now. */ 675 sc->flags |= AE_FLAG_TXAVAIL; /* Free Tx's available. */ 676 677 /* 678 * Enable DMA. 679 */ 680 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN); 681 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN); 682 683 /* 684 * Check if everything is OK. 685 */ 686 val = AE_READ_4(sc, AE_ISR_REG); 687 if ((val & AE_ISR_PHY_LINKDOWN) != 0) { 688 device_printf(sc->dev, "Initialization failed.\n"); 689 return (ENXIO); 690 } 691 692 /* 693 * Clear interrupt status. 694 */ 695 AE_WRITE_4(sc, AE_ISR_REG, 0x3fffffff); 696 AE_WRITE_4(sc, AE_ISR_REG, 0x0); 697 698 /* 699 * Enable interrupts. 700 */ 701 val = AE_READ_4(sc, AE_MASTER_REG); 702 AE_WRITE_4(sc, AE_MASTER_REG, val | AE_MASTER_MANUAL_INT); 703 AE_WRITE_4(sc, AE_IMR_REG, AE_IMR_DEFAULT); 704 705 /* 706 * Disable WOL. 707 */ 708 AE_WRITE_4(sc, AE_WOL_REG, 0); 709 710 /* 711 * Configure MAC. 712 */ 713 val = AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD | 714 AE_MAC_FULL_DUPLEX | AE_MAC_CLK_PHY | 715 AE_MAC_TX_FLOW_EN | AE_MAC_RX_FLOW_EN | 716 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & AE_HALFBUF_MASK) | 717 ((AE_MAC_PREAMBLE_DEFAULT << AE_MAC_PREAMBLE_SHIFT) & 718 AE_MAC_PREAMBLE_MASK); 719 AE_WRITE_4(sc, AE_MAC_REG, val); 720 721 /* 722 * Configure Rx MAC. 723 */ 724 ae_rxfilter(sc); 725 ae_rxvlan(sc); 726 727 /* 728 * Enable Tx/Rx. 729 */ 730 val = AE_READ_4(sc, AE_MAC_REG); 731 AE_WRITE_4(sc, AE_MAC_REG, val | AE_MAC_TX_EN | AE_MAC_RX_EN); 732 733 sc->flags &= ~AE_FLAG_LINK; 734 mii_mediachg(mii); /* Switch to the current media. */ 735 736 callout_reset(&sc->tick_ch, hz, ae_tick, sc); 737 738 ifp->if_drv_flags |= IFF_DRV_RUNNING; 739 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 740 741#ifdef AE_DEBUG 742 device_printf(sc->dev, "Initialization complete.\n"); 743#endif 744 745 return (0); 746} 747 748static int 749ae_detach(device_t dev) 750{ 751 struct ae_softc *sc; 752 struct ifnet *ifp; 753 754 sc = device_get_softc(dev); 755 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__)); 756 ifp = sc->ifp; 757 if (device_is_attached(dev)) { 758 AE_LOCK(sc); 759 sc->flags |= AE_FLAG_DETACH; 760 ae_stop(sc); 761 AE_UNLOCK(sc); 762 callout_drain(&sc->tick_ch); 763 taskqueue_drain(sc->tq, &sc->int_task); 764 taskqueue_drain(taskqueue_swi, &sc->link_task); 765 ether_ifdetach(ifp); 766 } 767 if (sc->tq != NULL) { 768 taskqueue_drain(sc->tq, &sc->int_task); 769 taskqueue_free(sc->tq); 770 sc->tq = NULL; 771 } 772 if (sc->miibus != NULL) { 773 device_delete_child(dev, sc->miibus); 774 sc->miibus = NULL; 775 } 776 bus_generic_detach(sc->dev); 777 ae_dma_free(sc); 778 if (sc->intrhand != NULL) { 779 bus_teardown_intr(dev, sc->irq[0], sc->intrhand); 780 sc->intrhand = NULL; 781 } 782 if (ifp != NULL) { 783 if_free(ifp); 784 sc->ifp = NULL; 785 } 786 if (sc->spec_irq != NULL) 787 bus_release_resources(dev, sc->spec_irq, sc->irq); 788 if (sc->spec_mem != NULL) 789 bus_release_resources(dev, sc->spec_mem, sc->mem); 790 if ((sc->flags & AE_FLAG_MSI) != 0) 791 pci_release_msi(dev); 792 mtx_destroy(&sc->mtx); 793 794 return (0); 795} 796 797static int 798ae_miibus_readreg(device_t dev, int phy, int reg) 799{ 800 ae_softc_t *sc; 801 uint32_t val; 802 int i; 803 804 sc = device_get_softc(dev); 805 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 806 807 /* 808 * Locking is done in upper layers. 809 */ 810 811 val = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) | 812 AE_MDIO_START | AE_MDIO_READ | AE_MDIO_SUP_PREAMBLE | 813 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK); 814 AE_WRITE_4(sc, AE_MDIO_REG, val); 815 816 /* 817 * Wait for operation to complete. 818 */ 819 for (i = 0; i < AE_MDIO_TIMEOUT; i++) { 820 DELAY(2); 821 val = AE_READ_4(sc, AE_MDIO_REG); 822 if ((val & (AE_MDIO_START | AE_MDIO_BUSY)) == 0) 823 break; 824 } 825 if (i == AE_MDIO_TIMEOUT) { 826 device_printf(sc->dev, "phy read timeout: %d.\n", reg); 827 return (0); 828 } 829 return ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK); 830} 831 832static int 833ae_miibus_writereg(device_t dev, int phy, int reg, int val) 834{ 835 ae_softc_t *sc; 836 uint32_t aereg; 837 int i; 838 839 sc = device_get_softc(dev); 840 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 841 842 /* 843 * Locking is done in upper layers. 844 */ 845 846 aereg = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) | 847 AE_MDIO_START | AE_MDIO_SUP_PREAMBLE | 848 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK) | 849 ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK); 850 AE_WRITE_4(sc, AE_MDIO_REG, aereg); 851 852 /* 853 * Wait for operation to complete. 854 */ 855 for (i = 0; i < AE_MDIO_TIMEOUT; i++) { 856 DELAY(2); 857 aereg = AE_READ_4(sc, AE_MDIO_REG); 858 if ((aereg & (AE_MDIO_START | AE_MDIO_BUSY)) == 0) 859 break; 860 } 861 if (i == AE_MDIO_TIMEOUT) { 862 device_printf(sc->dev, "phy write timeout: %d.\n", reg); 863 } 864 return (0); 865} 866 867static void 868ae_miibus_statchg(device_t dev) 869{ 870 ae_softc_t *sc; 871 872 sc = device_get_softc(dev); 873 taskqueue_enqueue(taskqueue_swi, &sc->link_task); 874} 875 876static void 877ae_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 878{ 879 ae_softc_t *sc; 880 struct mii_data *mii; 881 882 sc = ifp->if_softc; 883 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 884 885 AE_LOCK(sc); 886 mii = device_get_softc(sc->miibus); 887 mii_pollstat(mii); 888 ifmr->ifm_status = mii->mii_media_status; 889 ifmr->ifm_active = mii->mii_media_active; 890 AE_UNLOCK(sc); 891} 892 893static int 894ae_mediachange(struct ifnet *ifp) 895{ 896 ae_softc_t *sc; 897 struct mii_data *mii; 898 struct mii_softc *mii_sc; 899 int error; 900 901 /* XXX: check IFF_UP ?? */ 902 sc = ifp->if_softc; 903 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 904 AE_LOCK(sc); 905 mii = device_get_softc(sc->miibus); 906 LIST_FOREACH(mii_sc, &mii->mii_phys, mii_list) 907 PHY_RESET(mii_sc); 908 error = mii_mediachg(mii); 909 AE_UNLOCK(sc); 910 911 return (error); 912} 913 914static int 915ae_check_eeprom_present(ae_softc_t *sc, int *vpdc) 916{ 917 int error; 918 uint32_t val; 919 920 KASSERT(vpdc != NULL, ("[ae, %d]: vpdc is NULL!\n", __LINE__)); 921 922 /* 923 * Not sure why, but Linux does this. 924 */ 925 val = AE_READ_4(sc, AE_SPICTL_REG); 926 if ((val & AE_SPICTL_VPD_EN) != 0) { 927 val &= ~AE_SPICTL_VPD_EN; 928 AE_WRITE_4(sc, AE_SPICTL_REG, val); 929 } 930 error = pci_find_cap(sc->dev, PCIY_VPD, vpdc); 931 return (error); 932} 933 934static int 935ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word) 936{ 937 uint32_t val; 938 int i; 939 940 AE_WRITE_4(sc, AE_VPD_DATA_REG, 0); /* Clear register value. */ 941 942 /* 943 * VPD registers start at offset 0x100. Read them. 944 */ 945 val = 0x100 + reg * 4; 946 AE_WRITE_4(sc, AE_VPD_CAP_REG, (val << AE_VPD_CAP_ADDR_SHIFT) & 947 AE_VPD_CAP_ADDR_MASK); 948 for (i = 0; i < AE_VPD_TIMEOUT; i++) { 949 DELAY(2000); 950 val = AE_READ_4(sc, AE_VPD_CAP_REG); 951 if ((val & AE_VPD_CAP_DONE) != 0) 952 break; 953 } 954 if (i == AE_VPD_TIMEOUT) { 955 device_printf(sc->dev, "timeout reading VPD register %d.\n", 956 reg); 957 return (ETIMEDOUT); 958 } 959 *word = AE_READ_4(sc, AE_VPD_DATA_REG); 960 return (0); 961} 962 963static int 964ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr) 965{ 966 uint32_t word, reg, val; 967 int error; 968 int found; 969 int vpdc; 970 int i; 971 972 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 973 KASSERT(eaddr != NULL, ("[ae, %d]: eaddr is NULL", __LINE__)); 974 975 /* 976 * Check for EEPROM. 977 */ 978 error = ae_check_eeprom_present(sc, &vpdc); 979 if (error != 0) 980 return (error); 981 982 /* 983 * Read the VPD configuration space. 984 * Each register is prefixed with signature, 985 * so we can check if it is valid. 986 */ 987 for (i = 0, found = 0; i < AE_VPD_NREGS; i++) { 988 error = ae_vpd_read_word(sc, i, &word); 989 if (error != 0) 990 break; 991 992 /* 993 * Check signature. 994 */ 995 if ((word & AE_VPD_SIG_MASK) != AE_VPD_SIG) 996 break; 997 reg = word >> AE_VPD_REG_SHIFT; 998 i++; /* Move to the next word. */ 999 1000 if (reg != AE_EADDR0_REG && reg != AE_EADDR1_REG) 1001 continue; 1002 1003 error = ae_vpd_read_word(sc, i, &val); 1004 if (error != 0) 1005 break; 1006 if (reg == AE_EADDR0_REG) 1007 eaddr[0] = val; 1008 else 1009 eaddr[1] = val; 1010 found++; 1011 } 1012 1013 if (found < 2) 1014 return (ENOENT); 1015 1016 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */ 1017 if (AE_CHECK_EADDR_VALID(eaddr) != 0) { 1018 if (bootverbose) 1019 device_printf(sc->dev, 1020 "VPD ethernet address registers are invalid.\n"); 1021 return (EINVAL); 1022 } 1023 return (0); 1024} 1025 1026static int 1027ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr) 1028{ 1029 1030 /* 1031 * BIOS is supposed to set this. 1032 */ 1033 eaddr[0] = AE_READ_4(sc, AE_EADDR0_REG); 1034 eaddr[1] = AE_READ_4(sc, AE_EADDR1_REG); 1035 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */ 1036 1037 if (AE_CHECK_EADDR_VALID(eaddr) != 0) { 1038 if (bootverbose) 1039 device_printf(sc->dev, 1040 "Ethernet address registers are invalid.\n"); 1041 return (EINVAL); 1042 } 1043 return (0); 1044} 1045 1046static void 1047ae_retrieve_address(ae_softc_t *sc) 1048{ 1049 uint32_t eaddr[2] = {0, 0}; 1050 int error; 1051 1052 /* 1053 *Check for EEPROM. 1054 */ 1055 error = ae_get_vpd_eaddr(sc, eaddr); 1056 if (error != 0) 1057 error = ae_get_reg_eaddr(sc, eaddr); 1058 if (error != 0) { 1059 if (bootverbose) 1060 device_printf(sc->dev, 1061 "Generating random ethernet address.\n"); 1062 eaddr[0] = arc4random(); 1063 1064 /* 1065 * Set OUI to ASUSTek COMPUTER INC. 1066 */ 1067 sc->eaddr[0] = 0x02; /* U/L bit set. */ 1068 sc->eaddr[1] = 0x1f; 1069 sc->eaddr[2] = 0xc6; 1070 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff; 1071 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff; 1072 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff; 1073 } else { 1074 sc->eaddr[0] = (eaddr[1] >> 8) & 0xff; 1075 sc->eaddr[1] = (eaddr[1] >> 0) & 0xff; 1076 sc->eaddr[2] = (eaddr[0] >> 24) & 0xff; 1077 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff; 1078 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff; 1079 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff; 1080 } 1081} 1082 1083static void 1084ae_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1085{ 1086 bus_addr_t *addr = arg; 1087 1088 if (error != 0) 1089 return; 1090 KASSERT(nsegs == 1, ("[ae, %d]: %d segments instead of 1!", __LINE__, 1091 nsegs)); 1092 *addr = segs[0].ds_addr; 1093} 1094 1095static int 1096ae_alloc_rings(ae_softc_t *sc) 1097{ 1098 bus_addr_t busaddr; 1099 int error; 1100 1101 /* 1102 * Create parent DMA tag. 1103 */ 1104 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1105 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1106 NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0, 1107 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 1108 &sc->dma_parent_tag); 1109 if (error != 0) { 1110 device_printf(sc->dev, "could not creare parent DMA tag.\n"); 1111 return (error); 1112 } 1113 1114 /* 1115 * Create DMA tag for TxD. 1116 */ 1117 error = bus_dma_tag_create(sc->dma_parent_tag, 1118 4, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1119 NULL, NULL, AE_TXD_BUFSIZE_DEFAULT, 1, 1120 AE_TXD_BUFSIZE_DEFAULT, 0, NULL, NULL, 1121 &sc->dma_txd_tag); 1122 if (error != 0) { 1123 device_printf(sc->dev, "could not creare TxD DMA tag.\n"); 1124 return (error); 1125 } 1126 1127 /* 1128 * Create DMA tag for TxS. 1129 */ 1130 error = bus_dma_tag_create(sc->dma_parent_tag, 1131 4, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1132 NULL, NULL, AE_TXS_COUNT_DEFAULT * 4, 1, 1133 AE_TXS_COUNT_DEFAULT * 4, 0, NULL, NULL, 1134 &sc->dma_txs_tag); 1135 if (error != 0) { 1136 device_printf(sc->dev, "could not creare TxS DMA tag.\n"); 1137 return (error); 1138 } 1139 1140 /* 1141 * Create DMA tag for RxD. 1142 */ 1143 error = bus_dma_tag_create(sc->dma_parent_tag, 1144 128, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1145 NULL, NULL, AE_RXD_COUNT_DEFAULT * 1536 + 120, 1, 1146 AE_RXD_COUNT_DEFAULT * 1536 + 120, 0, NULL, NULL, 1147 &sc->dma_rxd_tag); 1148 if (error != 0) { 1149 device_printf(sc->dev, "could not creare TxS DMA tag.\n"); 1150 return (error); 1151 } 1152 1153 /* 1154 * Allocate TxD DMA memory. 1155 */ 1156 error = bus_dmamem_alloc(sc->dma_txd_tag, (void **)&sc->txd_base, 1157 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1158 &sc->dma_txd_map); 1159 if (error != 0) { 1160 device_printf(sc->dev, 1161 "could not allocate DMA memory for TxD ring.\n"); 1162 return (error); 1163 } 1164 error = bus_dmamap_load(sc->dma_txd_tag, sc->dma_txd_map, sc->txd_base, 1165 AE_TXD_BUFSIZE_DEFAULT, ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT); 1166 if (error != 0 || busaddr == 0) { 1167 device_printf(sc->dev, 1168 "could not load DMA map for TxD ring.\n"); 1169 return (error); 1170 } 1171 sc->dma_txd_busaddr = busaddr; 1172 1173 /* 1174 * Allocate TxS DMA memory. 1175 */ 1176 error = bus_dmamem_alloc(sc->dma_txs_tag, (void **)&sc->txs_base, 1177 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1178 &sc->dma_txs_map); 1179 if (error != 0) { 1180 device_printf(sc->dev, 1181 "could not allocate DMA memory for TxS ring.\n"); 1182 return (error); 1183 } 1184 error = bus_dmamap_load(sc->dma_txs_tag, sc->dma_txs_map, sc->txs_base, 1185 AE_TXS_COUNT_DEFAULT * 4, ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT); 1186 if (error != 0 || busaddr == 0) { 1187 device_printf(sc->dev, 1188 "could not load DMA map for TxS ring.\n"); 1189 return (error); 1190 } 1191 sc->dma_txs_busaddr = busaddr; 1192 1193 /* 1194 * Allocate RxD DMA memory. 1195 */ 1196 error = bus_dmamem_alloc(sc->dma_rxd_tag, (void **)&sc->rxd_base_dma, 1197 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1198 &sc->dma_rxd_map); 1199 if (error != 0) { 1200 device_printf(sc->dev, 1201 "could not allocate DMA memory for RxD ring.\n"); 1202 return (error); 1203 } 1204 error = bus_dmamap_load(sc->dma_rxd_tag, sc->dma_rxd_map, 1205 sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + 120, ae_dmamap_cb, 1206 &busaddr, BUS_DMA_NOWAIT); 1207 if (error != 0 || busaddr == 0) { 1208 device_printf(sc->dev, 1209 "could not load DMA map for RxD ring.\n"); 1210 return (error); 1211 } 1212 sc->dma_rxd_busaddr = busaddr + 120; 1213 sc->rxd_base = (ae_rxd_t *)(sc->rxd_base_dma + 120); 1214 1215 return (0); 1216} 1217 1218static void 1219ae_dma_free(ae_softc_t *sc) 1220{ 1221 1222 if (sc->dma_txd_tag != NULL) { 1223 if (sc->dma_txd_map != NULL) { 1224 bus_dmamap_unload(sc->dma_txd_tag, sc->dma_txd_map); 1225 if (sc->txd_base != NULL) 1226 bus_dmamem_free(sc->dma_txd_tag, sc->txd_base, 1227 sc->dma_txd_map); 1228 1229 } 1230 bus_dma_tag_destroy(sc->dma_txd_tag); 1231 sc->dma_txd_map = NULL; 1232 sc->dma_txd_tag = NULL; 1233 sc->txd_base = NULL; 1234 } 1235 if (sc->dma_txs_tag != NULL) { 1236 if (sc->dma_txs_map != NULL) { 1237 bus_dmamap_unload(sc->dma_txs_tag, sc->dma_txs_map); 1238 if (sc->txs_base != NULL) 1239 bus_dmamem_free(sc->dma_txs_tag, sc->txs_base, 1240 sc->dma_txs_map); 1241 1242 } 1243 bus_dma_tag_destroy(sc->dma_txs_tag); 1244 sc->dma_txs_map = NULL; 1245 sc->dma_txs_tag = NULL; 1246 sc->txs_base = NULL; 1247 } 1248 if (sc->dma_rxd_tag != NULL) { 1249 if (sc->dma_rxd_map != NULL) { 1250 bus_dmamap_unload(sc->dma_rxd_tag, sc->dma_rxd_map); 1251 if (sc->rxd_base_dma != NULL) 1252 bus_dmamem_free(sc->dma_rxd_tag, 1253 sc->rxd_base_dma, sc->dma_rxd_map); 1254 1255 } 1256 bus_dma_tag_destroy(sc->dma_rxd_tag); 1257 sc->dma_rxd_map = NULL; 1258 sc->dma_rxd_tag = NULL; 1259 sc->rxd_base_dma = NULL; 1260 } 1261 if (sc->dma_parent_tag != NULL) { 1262 bus_dma_tag_destroy(sc->dma_parent_tag); 1263 sc->dma_parent_tag = NULL; 1264 } 1265} 1266 1267static int 1268ae_shutdown(device_t dev) 1269{ 1270 ae_softc_t *sc; 1271 int error; 1272 1273 sc = device_get_softc(dev); 1274 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__)); 1275 1276 error = ae_suspend(dev); 1277 AE_LOCK(sc); 1278 ae_powersave_enable(sc); 1279 AE_UNLOCK(sc); 1280 return (error); 1281} 1282 1283static void 1284ae_powersave_disable(ae_softc_t *sc) 1285{ 1286 uint32_t val; 1287 1288 AE_LOCK_ASSERT(sc); 1289 1290 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0); 1291 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA); 1292 if (val & AE_PHY_DBG_POWERSAVE) { 1293 val &= ~AE_PHY_DBG_POWERSAVE; 1294 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, val); 1295 DELAY(1000); 1296 } 1297} 1298 1299static void 1300ae_powersave_enable(ae_softc_t *sc) 1301{ 1302 uint32_t val; 1303 1304 AE_LOCK_ASSERT(sc); 1305 1306 /* 1307 * XXX magic numbers. 1308 */ 1309 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0); 1310 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA); 1311 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, val | 0x1000); 1312 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 2); 1313 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0x3000); 1314 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 3); 1315 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0); 1316} 1317 1318static void 1319ae_pm_init(ae_softc_t *sc) 1320{ 1321 struct ifnet *ifp; 1322 uint32_t val; 1323 uint16_t pmstat; 1324 struct mii_data *mii; 1325 int pmc; 1326 1327 AE_LOCK_ASSERT(sc); 1328 1329 ifp = sc->ifp; 1330 if ((sc->flags & AE_FLAG_PMG) == 0) { 1331 /* Disable WOL entirely. */ 1332 AE_WRITE_4(sc, AE_WOL_REG, 0); 1333 return; 1334 } 1335 1336 /* 1337 * Configure WOL if enabled. 1338 */ 1339 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1340 mii = device_get_softc(sc->miibus); 1341 mii_pollstat(mii); 1342 if ((mii->mii_media_status & IFM_AVALID) != 0 && 1343 (mii->mii_media_status & IFM_ACTIVE) != 0) { 1344 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_MAGIC | \ 1345 AE_WOL_MAGIC_PME); 1346 1347 /* 1348 * Configure MAC. 1349 */ 1350 val = AE_MAC_RX_EN | AE_MAC_CLK_PHY | \ 1351 AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD | \ 1352 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & \ 1353 AE_HALFBUF_MASK) | \ 1354 ((AE_MAC_PREAMBLE_DEFAULT << \ 1355 AE_MAC_PREAMBLE_SHIFT) & AE_MAC_PREAMBLE_MASK) | \ 1356 AE_MAC_BCAST_EN | AE_MAC_MCAST_EN; 1357 if ((IFM_OPTIONS(mii->mii_media_active) & \ 1358 IFM_FDX) != 0) 1359 val |= AE_MAC_FULL_DUPLEX; 1360 AE_WRITE_4(sc, AE_MAC_REG, val); 1361 1362 } else { /* No link. */ 1363 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_LNKCHG | \ 1364 AE_WOL_LNKCHG_PME); 1365 AE_WRITE_4(sc, AE_MAC_REG, 0); 1366 } 1367 } else { 1368 ae_powersave_enable(sc); 1369 } 1370 1371 /* 1372 * PCIE hacks. Magic numbers. 1373 */ 1374 val = AE_READ_4(sc, AE_PCIE_PHYMISC_REG); 1375 val |= AE_PCIE_PHYMISC_FORCE_RCV_DET; 1376 AE_WRITE_4(sc, AE_PCIE_PHYMISC_REG, val); 1377 val = AE_READ_4(sc, AE_PCIE_DLL_TX_CTRL_REG); 1378 val |= AE_PCIE_DLL_TX_CTRL_SEL_NOR_CLK; 1379 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, val); 1380 1381 /* 1382 * Configure PME. 1383 */ 1384 pci_find_cap(sc->dev, PCIY_PMG, &pmc); 1385 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1386 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1387 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1388 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1389 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1390} 1391 1392static int 1393ae_suspend(device_t dev) 1394{ 1395 ae_softc_t *sc; 1396 1397 sc = device_get_softc(dev); 1398 1399 AE_LOCK(sc); 1400 ae_stop(sc); 1401 ae_pm_init(sc); 1402 AE_UNLOCK(sc); 1403 1404 return (0); 1405} 1406 1407static int 1408ae_resume(device_t dev) 1409{ 1410 ae_softc_t *sc; 1411 1412 sc = device_get_softc(dev); 1413 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1414 1415 AE_LOCK(sc); 1416 AE_READ_4(sc, AE_WOL_REG); /* Clear WOL status. */ 1417 if ((sc->ifp->if_flags & IFF_UP) != 0) 1418 ae_init_locked(sc); 1419 AE_UNLOCK(sc); 1420 1421 return (0); 1422} 1423 1424static unsigned int 1425ae_tx_avail_size(ae_softc_t *sc) 1426{ 1427 unsigned int avail; 1428 1429 if (sc->txd_cur >= sc->txd_ack) 1430 avail = AE_TXD_BUFSIZE_DEFAULT - (sc->txd_cur - sc->txd_ack); 1431 else 1432 avail = sc->txd_ack - sc->txd_cur; 1433 1434 return (avail); 1435} 1436 1437static int 1438ae_encap(ae_softc_t *sc, struct mbuf **m_head) 1439{ 1440 struct mbuf *m0; 1441 ae_txd_t *hdr; 1442 unsigned int to_end; 1443 uint16_t len; 1444 1445 AE_LOCK_ASSERT(sc); 1446 1447 m0 = *m_head; 1448 len = m0->m_pkthdr.len; 1449 1450 if ((sc->flags & AE_FLAG_TXAVAIL) == 0 || 1451 len + sizeof(ae_txd_t) + 3 > ae_tx_avail_size(sc)) { 1452#ifdef AE_DEBUG 1453 if_printf(sc->ifp, "No free Tx available.\n"); 1454#endif 1455 return ENOBUFS; 1456 } 1457 1458 hdr = (ae_txd_t *)(sc->txd_base + sc->txd_cur); 1459 bzero(hdr, sizeof(*hdr)); 1460 /* Skip header size. */ 1461 sc->txd_cur = (sc->txd_cur + sizeof(ae_txd_t)) % AE_TXD_BUFSIZE_DEFAULT; 1462 /* Space available to the end of the ring */ 1463 to_end = AE_TXD_BUFSIZE_DEFAULT - sc->txd_cur; 1464 if (to_end >= len) { 1465 m_copydata(m0, 0, len, (caddr_t)(sc->txd_base + sc->txd_cur)); 1466 } else { 1467 m_copydata(m0, 0, to_end, (caddr_t)(sc->txd_base + 1468 sc->txd_cur)); 1469 m_copydata(m0, to_end, len - to_end, (caddr_t)sc->txd_base); 1470 } 1471 1472 /* 1473 * Set TxD flags and parameters. 1474 */ 1475 if ((m0->m_flags & M_VLANTAG) != 0) { 1476 hdr->vlan = htole16(AE_TXD_VLAN(m0->m_pkthdr.ether_vtag)); 1477 hdr->len = htole16(len | AE_TXD_INSERT_VTAG); 1478 } else { 1479 hdr->len = htole16(len); 1480 } 1481 1482 /* 1483 * Set current TxD position and round up to a 4-byte boundary. 1484 */ 1485 sc->txd_cur = ((sc->txd_cur + len + 3) & ~3) % AE_TXD_BUFSIZE_DEFAULT; 1486 if (sc->txd_cur == sc->txd_ack) 1487 sc->flags &= ~AE_FLAG_TXAVAIL; 1488#ifdef AE_DEBUG 1489 if_printf(sc->ifp, "New txd_cur = %d.\n", sc->txd_cur); 1490#endif 1491 1492 /* 1493 * Update TxS position and check if there are empty TxS available. 1494 */ 1495 sc->txs_base[sc->txs_cur].flags &= ~htole16(AE_TXS_UPDATE); 1496 sc->txs_cur = (sc->txs_cur + 1) % AE_TXS_COUNT_DEFAULT; 1497 if (sc->txs_cur == sc->txs_ack) 1498 sc->flags &= ~AE_FLAG_TXAVAIL; 1499 1500 /* 1501 * Synchronize DMA memory. 1502 */ 1503 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, BUS_DMASYNC_PREREAD | 1504 BUS_DMASYNC_PREWRITE); 1505 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1506 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1507 1508 return (0); 1509} 1510 1511static void 1512ae_start(struct ifnet *ifp) 1513{ 1514 ae_softc_t *sc; 1515 1516 sc = ifp->if_softc; 1517 AE_LOCK(sc); 1518 ae_start_locked(ifp); 1519 AE_UNLOCK(sc); 1520} 1521 1522static void 1523ae_start_locked(struct ifnet *ifp) 1524{ 1525 ae_softc_t *sc; 1526 unsigned int count; 1527 struct mbuf *m0; 1528 int error; 1529 1530 sc = ifp->if_softc; 1531 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1532 AE_LOCK_ASSERT(sc); 1533 1534#ifdef AE_DEBUG 1535 if_printf(ifp, "Start called.\n"); 1536#endif 1537 1538 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1539 IFF_DRV_RUNNING || (sc->flags & AE_FLAG_LINK) == 0) 1540 return; 1541 1542 count = 0; 1543 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 1544 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); 1545 if (m0 == NULL) 1546 break; /* Nothing to do. */ 1547 1548 error = ae_encap(sc, &m0); 1549 if (error != 0) { 1550 if (m0 != NULL) { 1551 IFQ_DRV_PREPEND(&ifp->if_snd, m0); 1552 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1553#ifdef AE_DEBUG 1554 if_printf(ifp, "Setting OACTIVE.\n"); 1555#endif 1556 } 1557 break; 1558 } 1559 count++; 1560 sc->tx_inproc++; 1561 1562 /* Bounce a copy of the frame to BPF. */ 1563 ETHER_BPF_MTAP(ifp, m0); 1564 1565 m_freem(m0); 1566 } 1567 1568 if (count > 0) { /* Something was dequeued. */ 1569 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur / 4); 1570 sc->wd_timer = AE_TX_TIMEOUT; /* Load watchdog. */ 1571#ifdef AE_DEBUG 1572 if_printf(ifp, "%d packets dequeued.\n", count); 1573 if_printf(ifp, "Tx pos now is %d.\n", sc->txd_cur); 1574#endif 1575 } 1576} 1577 1578static void 1579ae_link_task(void *arg, int pending) 1580{ 1581 ae_softc_t *sc; 1582 struct mii_data *mii; 1583 struct ifnet *ifp; 1584 uint32_t val; 1585 1586 sc = (ae_softc_t *)arg; 1587 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1588 AE_LOCK(sc); 1589 1590 ifp = sc->ifp; 1591 mii = device_get_softc(sc->miibus); 1592 if (mii == NULL || ifp == NULL || 1593 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1594 AE_UNLOCK(sc); /* XXX: could happen? */ 1595 return; 1596 } 1597 1598 sc->flags &= ~AE_FLAG_LINK; 1599 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 1600 (IFM_AVALID | IFM_ACTIVE)) { 1601 switch(IFM_SUBTYPE(mii->mii_media_active)) { 1602 case IFM_10_T: 1603 case IFM_100_TX: 1604 sc->flags |= AE_FLAG_LINK; 1605 break; 1606 default: 1607 break; 1608 } 1609 } 1610 1611 /* 1612 * Stop Rx/Tx MACs. 1613 */ 1614 ae_stop_rxmac(sc); 1615 ae_stop_txmac(sc); 1616 1617 if ((sc->flags & AE_FLAG_LINK) != 0) { 1618 ae_mac_config(sc); 1619 1620 /* 1621 * Restart DMA engines. 1622 */ 1623 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN); 1624 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN); 1625 1626 /* 1627 * Enable Rx and Tx MACs. 1628 */ 1629 val = AE_READ_4(sc, AE_MAC_REG); 1630 val |= AE_MAC_TX_EN | AE_MAC_RX_EN; 1631 AE_WRITE_4(sc, AE_MAC_REG, val); 1632 } 1633 AE_UNLOCK(sc); 1634} 1635 1636static void 1637ae_stop_rxmac(ae_softc_t *sc) 1638{ 1639 uint32_t val; 1640 int i; 1641 1642 AE_LOCK_ASSERT(sc); 1643 1644 /* 1645 * Stop Rx MAC engine. 1646 */ 1647 val = AE_READ_4(sc, AE_MAC_REG); 1648 if ((val & AE_MAC_RX_EN) != 0) { 1649 val &= ~AE_MAC_RX_EN; 1650 AE_WRITE_4(sc, AE_MAC_REG, val); 1651 } 1652 1653 /* 1654 * Stop Rx DMA engine. 1655 */ 1656 if (AE_READ_1(sc, AE_DMAWRITE_REG) == AE_DMAWRITE_EN) 1657 AE_WRITE_1(sc, AE_DMAWRITE_REG, 0); 1658 1659 /* 1660 * Wait for IDLE state. 1661 */ 1662 for (i = 0; i < AE_IDLE_TIMEOUT; i--) { 1663 val = AE_READ_4(sc, AE_IDLE_REG); 1664 if ((val & (AE_IDLE_RXMAC | AE_IDLE_DMAWRITE)) == 0) 1665 break; 1666 DELAY(100); 1667 } 1668 if (i == AE_IDLE_TIMEOUT) 1669 device_printf(sc->dev, "timed out while stopping Rx MAC.\n"); 1670} 1671 1672static void 1673ae_stop_txmac(ae_softc_t *sc) 1674{ 1675 uint32_t val; 1676 int i; 1677 1678 AE_LOCK_ASSERT(sc); 1679 1680 /* 1681 * Stop Tx MAC engine. 1682 */ 1683 val = AE_READ_4(sc, AE_MAC_REG); 1684 if ((val & AE_MAC_TX_EN) != 0) { 1685 val &= ~AE_MAC_TX_EN; 1686 AE_WRITE_4(sc, AE_MAC_REG, val); 1687 } 1688 1689 /* 1690 * Stop Tx DMA engine. 1691 */ 1692 if (AE_READ_1(sc, AE_DMAREAD_REG) == AE_DMAREAD_EN) 1693 AE_WRITE_1(sc, AE_DMAREAD_REG, 0); 1694 1695 /* 1696 * Wait for IDLE state. 1697 */ 1698 for (i = 0; i < AE_IDLE_TIMEOUT; i--) { 1699 val = AE_READ_4(sc, AE_IDLE_REG); 1700 if ((val & (AE_IDLE_TXMAC | AE_IDLE_DMAREAD)) == 0) 1701 break; 1702 DELAY(100); 1703 } 1704 if (i == AE_IDLE_TIMEOUT) 1705 device_printf(sc->dev, "timed out while stopping Tx MAC.\n"); 1706} 1707 1708static void 1709ae_mac_config(ae_softc_t *sc) 1710{ 1711 struct mii_data *mii; 1712 uint32_t val; 1713 1714 AE_LOCK_ASSERT(sc); 1715 1716 mii = device_get_softc(sc->miibus); 1717 val = AE_READ_4(sc, AE_MAC_REG); 1718 val &= ~AE_MAC_FULL_DUPLEX; 1719 /* XXX disable AE_MAC_TX_FLOW_EN? */ 1720 1721 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1722 val |= AE_MAC_FULL_DUPLEX; 1723 1724 AE_WRITE_4(sc, AE_MAC_REG, val); 1725} 1726 1727static int 1728ae_intr(void *arg) 1729{ 1730 ae_softc_t *sc; 1731 uint32_t val; 1732 1733 sc = (ae_softc_t *)arg; 1734 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1735 1736 val = AE_READ_4(sc, AE_ISR_REG); 1737 if (val == 0 || (val & AE_IMR_DEFAULT) == 0) 1738 return (FILTER_STRAY); 1739 1740 /* Disable interrupts. */ 1741 AE_WRITE_4(sc, AE_ISR_REG, AE_ISR_DISABLE); 1742 1743 /* Schedule interrupt processing. */ 1744 taskqueue_enqueue(sc->tq, &sc->int_task); 1745 1746 return (FILTER_HANDLED); 1747} 1748 1749static void 1750ae_int_task(void *arg, int pending) 1751{ 1752 ae_softc_t *sc; 1753 struct ifnet *ifp; 1754 uint32_t val; 1755 1756 sc = (ae_softc_t *)arg; 1757 1758 AE_LOCK(sc); 1759 1760 ifp = sc->ifp; 1761 1762 val = AE_READ_4(sc, AE_ISR_REG); /* Read interrupt status. */ 1763 1764 /* 1765 * Clear interrupts and disable them. 1766 */ 1767 AE_WRITE_4(sc, AE_ISR_REG, val | AE_ISR_DISABLE); 1768 1769#ifdef AE_DEBUG 1770 if_printf(ifp, "Interrupt received: 0x%08x\n", val); 1771#endif 1772 1773 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1774 if ((val & (AE_ISR_DMAR_TIMEOUT | AE_ISR_DMAW_TIMEOUT | 1775 AE_ISR_PHY_LINKDOWN)) != 0) { 1776 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1777 ae_init_locked(sc); 1778 AE_UNLOCK(sc); 1779 return; 1780 } 1781 if ((val & AE_ISR_TX_EVENT) != 0) 1782 ae_tx_intr(sc); 1783 if ((val & AE_ISR_RX_EVENT) != 0) 1784 ae_rx_intr(sc); 1785 } 1786 1787 /* 1788 * Re-enable interrupts. 1789 */ 1790 AE_WRITE_4(sc, AE_ISR_REG, 0); 1791 1792 AE_UNLOCK(sc); 1793} 1794 1795static void 1796ae_tx_intr(ae_softc_t *sc) 1797{ 1798 struct ifnet *ifp; 1799 ae_txd_t *txd; 1800 ae_txs_t *txs; 1801 uint16_t flags; 1802 1803 AE_LOCK_ASSERT(sc); 1804 1805 ifp = sc->ifp; 1806 1807#ifdef AE_DEBUG 1808 if_printf(ifp, "Tx interrupt occuried.\n"); 1809#endif 1810 1811 /* 1812 * Syncronize DMA buffers. 1813 */ 1814 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, 1815 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1816 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1817 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1818 1819 for (;;) { 1820 txs = sc->txs_base + sc->txs_ack; 1821 flags = le16toh(txs->flags); 1822 if ((flags & AE_TXS_UPDATE) == 0) 1823 break; 1824 txs->flags = htole16(flags & ~AE_TXS_UPDATE); 1825 /* Update stats. */ 1826 ae_update_stats_tx(flags, &sc->stats); 1827 1828 /* 1829 * Update TxS position. 1830 */ 1831 sc->txs_ack = (sc->txs_ack + 1) % AE_TXS_COUNT_DEFAULT; 1832 sc->flags |= AE_FLAG_TXAVAIL; 1833 1834 txd = (ae_txd_t *)(sc->txd_base + sc->txd_ack); 1835 if (txs->len != txd->len) 1836 device_printf(sc->dev, "Size mismatch: TxS:%d TxD:%d\n", 1837 le16toh(txs->len), le16toh(txd->len)); 1838 1839 /* 1840 * Move txd ack and align on 4-byte boundary. 1841 */ 1842 sc->txd_ack = ((sc->txd_ack + le16toh(txd->len) + 1843 sizeof(ae_txs_t) + 3) & ~3) % AE_TXD_BUFSIZE_DEFAULT; 1844 1845 if ((flags & AE_TXS_SUCCESS) != 0) 1846 ifp->if_opackets++; 1847 else 1848 ifp->if_oerrors++; 1849 1850 sc->tx_inproc--; 1851 1852 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1853 } 1854 1855 if (sc->tx_inproc < 0) { 1856 if_printf(ifp, "Received stray Tx interrupt(s).\n"); 1857 sc->tx_inproc = 0; 1858 } 1859 1860 if (sc->tx_inproc == 0) 1861 sc->wd_timer = 0; /* Unarm watchdog. */ 1862 1863 if ((sc->flags & AE_FLAG_TXAVAIL) != 0) { 1864 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1865 ae_start_locked(ifp); 1866 } 1867 1868 /* 1869 * Syncronize DMA buffers. 1870 */ 1871 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, 1872 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1873 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1874 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1875} 1876 1877static int 1878ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd) 1879{ 1880 struct ifnet *ifp; 1881 struct mbuf *m; 1882 unsigned int size; 1883 uint16_t flags; 1884 1885 AE_LOCK_ASSERT(sc); 1886 1887 ifp = sc->ifp; 1888 flags = le16toh(rxd->flags); 1889 1890#ifdef AE_DEBUG 1891 if_printf(ifp, "Rx interrupt occuried.\n"); 1892#endif 1893 size = le16toh(rxd->len) - ETHER_CRC_LEN; 1894 if (size < (ETHER_MIN_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN)) { 1895 if_printf(ifp, "Runt frame received."); 1896 return (EIO); 1897 } 1898 1899 m = m_devget(&rxd->data[0], size, ETHER_ALIGN, ifp, NULL); 1900 if (m == NULL) 1901 return (ENOBUFS); 1902 1903 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 1904 (flags & AE_RXD_HAS_VLAN) != 0) { 1905 m->m_pkthdr.ether_vtag = AE_RXD_VLAN(le16toh(rxd->vlan)); 1906 m->m_flags |= M_VLANTAG; 1907 } 1908 1909 /* 1910 * Pass it through. 1911 */ 1912 AE_UNLOCK(sc); 1913 (*ifp->if_input)(ifp, m); 1914 AE_LOCK(sc); 1915 1916 return (0); 1917} 1918 1919static void 1920ae_rx_intr(ae_softc_t *sc) 1921{ 1922 ae_rxd_t *rxd; 1923 struct ifnet *ifp; 1924 uint16_t flags; 1925 int error; 1926 1927 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 1928 1929 AE_LOCK_ASSERT(sc); 1930 1931 ifp = sc->ifp; 1932 1933 /* 1934 * Syncronize DMA buffers. 1935 */ 1936 bus_dmamap_sync(sc->dma_rxd_tag, sc->dma_rxd_map, 1937 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1938 1939 for (;;) { 1940 rxd = (ae_rxd_t *)(sc->rxd_base + sc->rxd_cur); 1941 flags = le16toh(rxd->flags); 1942 if ((flags & AE_RXD_UPDATE) == 0) 1943 break; 1944 rxd->flags = htole16(flags & ~AE_RXD_UPDATE); 1945 /* Update stats. */ 1946 ae_update_stats_rx(flags, &sc->stats); 1947 1948 /* 1949 * Update position index. 1950 */ 1951 sc->rxd_cur = (sc->rxd_cur + 1) % AE_RXD_COUNT_DEFAULT; 1952 1953 if ((flags & AE_RXD_SUCCESS) == 0) { 1954 ifp->if_ierrors++; 1955 continue; 1956 } 1957 error = ae_rxeof(sc, rxd); 1958 if (error != 0) { 1959 ifp->if_ierrors++; 1960 continue; 1961 } else { 1962 ifp->if_ipackets++; 1963 } 1964 } 1965 1966 /* 1967 * Update Rx index. 1968 */ 1969 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur); 1970} 1971 1972static void 1973ae_watchdog(ae_softc_t *sc) 1974{ 1975 struct ifnet *ifp; 1976 1977 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 1978 AE_LOCK_ASSERT(sc); 1979 ifp = sc->ifp; 1980 1981 if (sc->wd_timer == 0 || --sc->wd_timer != 0) 1982 return; /* Noting to do. */ 1983 1984 if ((sc->flags & AE_FLAG_LINK) == 0) 1985 if_printf(ifp, "watchdog timeout (missed link).\n"); 1986 else 1987 if_printf(ifp, "watchdog timeout - resetting.\n"); 1988 1989 ifp->if_oerrors++; 1990 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1991 ae_init_locked(sc); 1992 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1993 ae_start_locked(ifp); 1994} 1995 1996static void 1997ae_tick(void *arg) 1998{ 1999 ae_softc_t *sc; 2000 struct mii_data *mii; 2001 2002 sc = (ae_softc_t *)arg; 2003 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 2004 AE_LOCK_ASSERT(sc); 2005 2006 mii = device_get_softc(sc->miibus); 2007 mii_tick(mii); 2008 ae_watchdog(sc); /* Watchdog check. */ 2009 callout_reset(&sc->tick_ch, hz, ae_tick, sc); 2010} 2011 2012static void 2013ae_rxvlan(ae_softc_t *sc) 2014{ 2015 struct ifnet *ifp; 2016 uint32_t val; 2017 2018 AE_LOCK_ASSERT(sc); 2019 ifp = sc->ifp; 2020 val = AE_READ_4(sc, AE_MAC_REG); 2021 val &= ~AE_MAC_RMVLAN_EN; 2022 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2023 val |= AE_MAC_RMVLAN_EN; 2024 AE_WRITE_4(sc, AE_MAC_REG, val); 2025} 2026 2027static void 2028ae_rxfilter(ae_softc_t *sc) 2029{ 2030 struct ifnet *ifp; 2031 struct ifmultiaddr *ifma; 2032 uint32_t crc; 2033 uint32_t mchash[2]; 2034 uint32_t rxcfg; 2035 2036 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 2037 2038 AE_LOCK_ASSERT(sc); 2039 2040 ifp = sc->ifp; 2041 2042 rxcfg = AE_READ_4(sc, AE_MAC_REG); 2043 rxcfg &= ~(AE_MAC_MCAST_EN | AE_MAC_BCAST_EN | AE_MAC_PROMISC_EN); 2044 2045 if ((ifp->if_flags & IFF_BROADCAST) != 0) 2046 rxcfg |= AE_MAC_BCAST_EN; 2047 if ((ifp->if_flags & IFF_PROMISC) != 0) 2048 rxcfg |= AE_MAC_PROMISC_EN; 2049 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 2050 rxcfg |= AE_MAC_MCAST_EN; 2051 2052 /* 2053 * Wipe old settings. 2054 */ 2055 AE_WRITE_4(sc, AE_REG_MHT0, 0); 2056 AE_WRITE_4(sc, AE_REG_MHT1, 0); 2057 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2058 AE_WRITE_4(sc, AE_REG_MHT0, 0xffffffff); 2059 AE_WRITE_4(sc, AE_REG_MHT1, 0xffffffff); 2060 AE_WRITE_4(sc, AE_MAC_REG, rxcfg); 2061 return; 2062 } 2063 2064 /* 2065 * Load multicast tables. 2066 */ 2067 bzero(mchash, sizeof(mchash)); 2068 if_maddr_rlock(ifp); 2069 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2070 if (ifma->ifma_addr->sa_family != AF_LINK) 2071 continue; 2072 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 2073 ifma->ifma_addr), ETHER_ADDR_LEN); 2074 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2075 } 2076 if_maddr_runlock(ifp); 2077 AE_WRITE_4(sc, AE_REG_MHT0, mchash[0]); 2078 AE_WRITE_4(sc, AE_REG_MHT1, mchash[1]); 2079 AE_WRITE_4(sc, AE_MAC_REG, rxcfg); 2080} 2081 2082static int 2083ae_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2084{ 2085 struct ae_softc *sc; 2086 struct ifreq *ifr; 2087 struct mii_data *mii; 2088 int error, mask; 2089 2090 sc = ifp->if_softc; 2091 ifr = (struct ifreq *)data; 2092 error = 0; 2093 2094 switch (cmd) { 2095 case SIOCSIFMTU: 2096 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) 2097 error = EINVAL; 2098 else if (ifp->if_mtu != ifr->ifr_mtu) { 2099 AE_LOCK(sc); 2100 ifp->if_mtu = ifr->ifr_mtu; 2101 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2102 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2103 ae_init_locked(sc); 2104 } 2105 AE_UNLOCK(sc); 2106 } 2107 break; 2108 case SIOCSIFFLAGS: 2109 AE_LOCK(sc); 2110 if ((ifp->if_flags & IFF_UP) != 0) { 2111 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2112 if (((ifp->if_flags ^ sc->if_flags) 2113 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2114 ae_rxfilter(sc); 2115 } else { 2116 if ((sc->flags & AE_FLAG_DETACH) == 0) 2117 ae_init_locked(sc); 2118 } 2119 } else { 2120 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2121 ae_stop(sc); 2122 } 2123 sc->if_flags = ifp->if_flags; 2124 AE_UNLOCK(sc); 2125 break; 2126 case SIOCADDMULTI: 2127 case SIOCDELMULTI: 2128 AE_LOCK(sc); 2129 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2130 ae_rxfilter(sc); 2131 AE_UNLOCK(sc); 2132 break; 2133 case SIOCSIFMEDIA: 2134 case SIOCGIFMEDIA: 2135 mii = device_get_softc(sc->miibus); 2136 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2137 break; 2138 case SIOCSIFCAP: 2139 AE_LOCK(sc); 2140 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2141 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2142 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2143 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2144 ae_rxvlan(sc); 2145 } 2146 VLAN_CAPABILITIES(ifp); 2147 AE_UNLOCK(sc); 2148 break; 2149 default: 2150 error = ether_ioctl(ifp, cmd, data); 2151 break; 2152 } 2153 return (error); 2154} 2155 2156static void 2157ae_stop(ae_softc_t *sc) 2158{ 2159 struct ifnet *ifp; 2160 int i; 2161 2162 AE_LOCK_ASSERT(sc); 2163 2164 ifp = sc->ifp; 2165 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2166 sc->flags &= ~AE_FLAG_LINK; 2167 sc->wd_timer = 0; /* Cancel watchdog. */ 2168 callout_stop(&sc->tick_ch); 2169 2170 /* 2171 * Clear and disable interrupts. 2172 */ 2173 AE_WRITE_4(sc, AE_IMR_REG, 0); 2174 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff); 2175 2176 /* 2177 * Stop Rx/Tx MACs. 2178 */ 2179 ae_stop_txmac(sc); 2180 ae_stop_rxmac(sc); 2181 2182 /* 2183 * Stop DMA engines. 2184 */ 2185 AE_WRITE_1(sc, AE_DMAREAD_REG, ~AE_DMAREAD_EN); 2186 AE_WRITE_1(sc, AE_DMAWRITE_REG, ~AE_DMAWRITE_EN); 2187 2188 /* 2189 * Wait for everything to enter idle state. 2190 */ 2191 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 2192 if (AE_READ_4(sc, AE_IDLE_REG) == 0) 2193 break; 2194 DELAY(100); 2195 } 2196 if (i == AE_IDLE_TIMEOUT) 2197 device_printf(sc->dev, "could not enter idle state in stop.\n"); 2198} 2199 2200static void 2201ae_update_stats_tx(uint16_t flags, ae_stats_t *stats) 2202{ 2203 2204 if ((flags & AE_TXS_BCAST) != 0) 2205 stats->tx_bcast++; 2206 if ((flags & AE_TXS_MCAST) != 0) 2207 stats->tx_mcast++; 2208 if ((flags & AE_TXS_PAUSE) != 0) 2209 stats->tx_pause++; 2210 if ((flags & AE_TXS_CTRL) != 0) 2211 stats->tx_ctrl++; 2212 if ((flags & AE_TXS_DEFER) != 0) 2213 stats->tx_defer++; 2214 if ((flags & AE_TXS_EXCDEFER) != 0) 2215 stats->tx_excdefer++; 2216 if ((flags & AE_TXS_SINGLECOL) != 0) 2217 stats->tx_singlecol++; 2218 if ((flags & AE_TXS_MULTICOL) != 0) 2219 stats->tx_multicol++; 2220 if ((flags & AE_TXS_LATECOL) != 0) 2221 stats->tx_latecol++; 2222 if ((flags & AE_TXS_ABORTCOL) != 0) 2223 stats->tx_abortcol++; 2224 if ((flags & AE_TXS_UNDERRUN) != 0) 2225 stats->tx_underrun++; 2226} 2227 2228static void 2229ae_update_stats_rx(uint16_t flags, ae_stats_t *stats) 2230{ 2231 2232 if ((flags & AE_RXD_BCAST) != 0) 2233 stats->rx_bcast++; 2234 if ((flags & AE_RXD_MCAST) != 0) 2235 stats->rx_mcast++; 2236 if ((flags & AE_RXD_PAUSE) != 0) 2237 stats->rx_pause++; 2238 if ((flags & AE_RXD_CTRL) != 0) 2239 stats->rx_ctrl++; 2240 if ((flags & AE_RXD_CRCERR) != 0) 2241 stats->rx_crcerr++; 2242 if ((flags & AE_RXD_CODEERR) != 0) 2243 stats->rx_codeerr++; 2244 if ((flags & AE_RXD_RUNT) != 0) 2245 stats->rx_runt++; 2246 if ((flags & AE_RXD_FRAG) != 0) 2247 stats->rx_frag++; 2248 if ((flags & AE_RXD_TRUNC) != 0) 2249 stats->rx_trunc++; 2250 if ((flags & AE_RXD_ALIGN) != 0) 2251 stats->rx_align++; 2252} 2253