if_ae.c revision 219902
1/*- 2 * Copyright (c) 2008 Stanislav Sedov <stas@FreeBSD.org>. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * Driver for Attansic Technology Corp. L2 FastEthernet adapter. 26 * 27 * This driver is heavily based on age(4) Attansic L1 driver by Pyun YongHyeon. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/ae/if_ae.c 219902 2011-03-23 13:10:15Z jhb $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/kernel.h> 38#include <sys/malloc.h> 39#include <sys/mbuf.h> 40#include <sys/rman.h> 41#include <sys/module.h> 42#include <sys/queue.h> 43#include <sys/socket.h> 44#include <sys/sockio.h> 45#include <sys/sysctl.h> 46#include <sys/taskqueue.h> 47 48#include <net/bpf.h> 49#include <net/if.h> 50#include <net/if_arp.h> 51#include <net/ethernet.h> 52#include <net/if_dl.h> 53#include <net/if_media.h> 54#include <net/if_types.h> 55#include <net/if_vlan_var.h> 56 57#include <netinet/in.h> 58#include <netinet/in_systm.h> 59#include <netinet/ip.h> 60#include <netinet/tcp.h> 61 62#include <dev/mii/mii.h> 63#include <dev/mii/miivar.h> 64#include <dev/pci/pcireg.h> 65#include <dev/pci/pcivar.h> 66 67#include <machine/bus.h> 68 69#include "miibus_if.h" 70 71#include "if_aereg.h" 72#include "if_aevar.h" 73 74/* 75 * Devices supported by this driver. 76 */ 77static struct ae_dev { 78 uint16_t vendorid; 79 uint16_t deviceid; 80 const char *name; 81} ae_devs[] = { 82 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L2, 83 "Attansic Technology Corp, L2 FastEthernet" }, 84}; 85#define AE_DEVS_COUNT (sizeof(ae_devs) / sizeof(*ae_devs)) 86 87static struct resource_spec ae_res_spec_mem[] = { 88 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 89 { -1, 0, 0 } 90}; 91static struct resource_spec ae_res_spec_irq[] = { 92 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 93 { -1, 0, 0 } 94}; 95static struct resource_spec ae_res_spec_msi[] = { 96 { SYS_RES_IRQ, 1, RF_ACTIVE }, 97 { -1, 0, 0 } 98}; 99 100static int ae_probe(device_t dev); 101static int ae_attach(device_t dev); 102static void ae_pcie_init(ae_softc_t *sc); 103static void ae_phy_reset(ae_softc_t *sc); 104static void ae_phy_init(ae_softc_t *sc); 105static int ae_reset(ae_softc_t *sc); 106static void ae_init(void *arg); 107static int ae_init_locked(ae_softc_t *sc); 108static int ae_detach(device_t dev); 109static int ae_miibus_readreg(device_t dev, int phy, int reg); 110static int ae_miibus_writereg(device_t dev, int phy, int reg, int val); 111static void ae_miibus_statchg(device_t dev); 112static void ae_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr); 113static int ae_mediachange(struct ifnet *ifp); 114static void ae_retrieve_address(ae_softc_t *sc); 115static void ae_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, 116 int error); 117static int ae_alloc_rings(ae_softc_t *sc); 118static void ae_dma_free(ae_softc_t *sc); 119static int ae_shutdown(device_t dev); 120static int ae_suspend(device_t dev); 121static void ae_powersave_disable(ae_softc_t *sc); 122static void ae_powersave_enable(ae_softc_t *sc); 123static int ae_resume(device_t dev); 124static unsigned int ae_tx_avail_size(ae_softc_t *sc); 125static int ae_encap(ae_softc_t *sc, struct mbuf **m_head); 126static void ae_start(struct ifnet *ifp); 127static void ae_start_locked(struct ifnet *ifp); 128static void ae_link_task(void *arg, int pending); 129static void ae_stop_rxmac(ae_softc_t *sc); 130static void ae_stop_txmac(ae_softc_t *sc); 131static void ae_mac_config(ae_softc_t *sc); 132static int ae_intr(void *arg); 133static void ae_int_task(void *arg, int pending); 134static void ae_tx_intr(ae_softc_t *sc); 135static int ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd); 136static void ae_rx_intr(ae_softc_t *sc); 137static void ae_watchdog(ae_softc_t *sc); 138static void ae_tick(void *arg); 139static void ae_rxfilter(ae_softc_t *sc); 140static void ae_rxvlan(ae_softc_t *sc); 141static int ae_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 142static void ae_stop(ae_softc_t *sc); 143static int ae_check_eeprom_present(ae_softc_t *sc, int *vpdc); 144static int ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word); 145static int ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr); 146static int ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr); 147static void ae_update_stats_rx(uint16_t flags, ae_stats_t *stats); 148static void ae_update_stats_tx(uint16_t flags, ae_stats_t *stats); 149static void ae_init_tunables(ae_softc_t *sc); 150 151static device_method_t ae_methods[] = { 152 /* Device interface. */ 153 DEVMETHOD(device_probe, ae_probe), 154 DEVMETHOD(device_attach, ae_attach), 155 DEVMETHOD(device_detach, ae_detach), 156 DEVMETHOD(device_shutdown, ae_shutdown), 157 DEVMETHOD(device_suspend, ae_suspend), 158 DEVMETHOD(device_resume, ae_resume), 159 160 /* MII interface. */ 161 DEVMETHOD(miibus_readreg, ae_miibus_readreg), 162 DEVMETHOD(miibus_writereg, ae_miibus_writereg), 163 DEVMETHOD(miibus_statchg, ae_miibus_statchg), 164 165 { NULL, NULL } 166}; 167static driver_t ae_driver = { 168 "ae", 169 ae_methods, 170 sizeof(ae_softc_t) 171}; 172static devclass_t ae_devclass; 173 174DRIVER_MODULE(ae, pci, ae_driver, ae_devclass, 0, 0); 175DRIVER_MODULE(miibus, ae, miibus_driver, miibus_devclass, 0, 0); 176MODULE_DEPEND(ae, pci, 1, 1, 1); 177MODULE_DEPEND(ae, ether, 1, 1, 1); 178MODULE_DEPEND(ae, miibus, 1, 1, 1); 179 180/* 181 * Tunables. 182 */ 183static int msi_disable = 0; 184TUNABLE_INT("hw.ae.msi_disable", &msi_disable); 185 186#define AE_READ_4(sc, reg) \ 187 bus_read_4((sc)->mem[0], (reg)) 188#define AE_READ_2(sc, reg) \ 189 bus_read_2((sc)->mem[0], (reg)) 190#define AE_READ_1(sc, reg) \ 191 bus_read_1((sc)->mem[0], (reg)) 192#define AE_WRITE_4(sc, reg, val) \ 193 bus_write_4((sc)->mem[0], (reg), (val)) 194#define AE_WRITE_2(sc, reg, val) \ 195 bus_write_2((sc)->mem[0], (reg), (val)) 196#define AE_WRITE_1(sc, reg, val) \ 197 bus_write_1((sc)->mem[0], (reg), (val)) 198#define AE_PHY_READ(sc, reg) \ 199 ae_miibus_readreg(sc->dev, 0, reg) 200#define AE_PHY_WRITE(sc, reg, val) \ 201 ae_miibus_writereg(sc->dev, 0, reg, val) 202#define AE_CHECK_EADDR_VALID(eaddr) \ 203 ((eaddr[0] == 0 && eaddr[1] == 0) || \ 204 (eaddr[0] == 0xffffffff && eaddr[1] == 0xffff)) 205#define AE_RXD_VLAN(vtag) \ 206 (((vtag) >> 4) | (((vtag) & 0x07) << 13) | (((vtag) & 0x08) << 9)) 207#define AE_TXD_VLAN(vtag) \ 208 (((vtag) << 4) | (((vtag) >> 13) & 0x07) | (((vtag) >> 9) & 0x08)) 209 210static int 211ae_probe(device_t dev) 212{ 213 uint16_t deviceid, vendorid; 214 int i; 215 216 vendorid = pci_get_vendor(dev); 217 deviceid = pci_get_device(dev); 218 219 /* 220 * Search through the list of supported devs for matching one. 221 */ 222 for (i = 0; i < AE_DEVS_COUNT; i++) { 223 if (vendorid == ae_devs[i].vendorid && 224 deviceid == ae_devs[i].deviceid) { 225 device_set_desc(dev, ae_devs[i].name); 226 return (BUS_PROBE_DEFAULT); 227 } 228 } 229 return (ENXIO); 230} 231 232static int 233ae_attach(device_t dev) 234{ 235 ae_softc_t *sc; 236 struct ifnet *ifp; 237 uint8_t chiprev; 238 uint32_t pcirev; 239 int nmsi, pmc; 240 int error; 241 242 sc = device_get_softc(dev); /* Automatically allocated and zeroed 243 on attach. */ 244 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 245 sc->dev = dev; 246 247 /* 248 * Initialize mutexes and tasks. 249 */ 250 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); 251 callout_init_mtx(&sc->tick_ch, &sc->mtx, 0); 252 TASK_INIT(&sc->int_task, 0, ae_int_task, sc); 253 TASK_INIT(&sc->link_task, 0, ae_link_task, sc); 254 255 pci_enable_busmaster(dev); /* Enable bus mastering. */ 256 257 sc->spec_mem = ae_res_spec_mem; 258 259 /* 260 * Allocate memory-mapped registers. 261 */ 262 error = bus_alloc_resources(dev, sc->spec_mem, sc->mem); 263 if (error != 0) { 264 device_printf(dev, "could not allocate memory resources.\n"); 265 sc->spec_mem = NULL; 266 goto fail; 267 } 268 269 /* 270 * Retrieve PCI and chip revisions. 271 */ 272 pcirev = pci_get_revid(dev); 273 chiprev = (AE_READ_4(sc, AE_MASTER_REG) >> AE_MASTER_REVNUM_SHIFT) & 274 AE_MASTER_REVNUM_MASK; 275 if (bootverbose) { 276 device_printf(dev, "pci device revision: %#04x\n", pcirev); 277 device_printf(dev, "chip id: %#02x\n", chiprev); 278 } 279 nmsi = pci_msi_count(dev); 280 if (bootverbose) 281 device_printf(dev, "MSI count: %d.\n", nmsi); 282 283 /* 284 * Allocate interrupt resources. 285 */ 286 if (msi_disable == 0 && nmsi == 1) { 287 error = pci_alloc_msi(dev, &nmsi); 288 if (error == 0) { 289 device_printf(dev, "Using MSI messages.\n"); 290 sc->spec_irq = ae_res_spec_msi; 291 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq); 292 if (error != 0) { 293 device_printf(dev, "MSI allocation failed.\n"); 294 sc->spec_irq = NULL; 295 pci_release_msi(dev); 296 } else { 297 sc->flags |= AE_FLAG_MSI; 298 } 299 } 300 } 301 if (sc->spec_irq == NULL) { 302 sc->spec_irq = ae_res_spec_irq; 303 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq); 304 if (error != 0) { 305 device_printf(dev, "could not allocate IRQ resources.\n"); 306 sc->spec_irq = NULL; 307 goto fail; 308 } 309 } 310 311 ae_init_tunables(sc); 312 313 ae_phy_reset(sc); /* Reset PHY. */ 314 error = ae_reset(sc); /* Reset the controller itself. */ 315 if (error != 0) 316 goto fail; 317 318 ae_pcie_init(sc); 319 320 ae_retrieve_address(sc); /* Load MAC address. */ 321 322 error = ae_alloc_rings(sc); /* Allocate ring buffers. */ 323 if (error != 0) 324 goto fail; 325 326 ifp = sc->ifp = if_alloc(IFT_ETHER); 327 if (ifp == NULL) { 328 device_printf(dev, "could not allocate ifnet structure.\n"); 329 error = ENXIO; 330 goto fail; 331 } 332 333 ifp->if_softc = sc; 334 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 335 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 336 ifp->if_ioctl = ae_ioctl; 337 ifp->if_start = ae_start; 338 ifp->if_init = ae_init; 339 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 340 ifp->if_hwassist = 0; 341 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 342 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 343 IFQ_SET_READY(&ifp->if_snd); 344 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 345 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 346 sc->flags |= AE_FLAG_PMG; 347 } 348 ifp->if_capenable = ifp->if_capabilities; 349 350 /* 351 * Configure and attach MII bus. 352 */ 353 error = mii_attach(dev, &sc->miibus, ifp, ae_mediachange, 354 ae_mediastatus, BMSR_DEFCAPMASK, AE_PHYADDR_DEFAULT, 355 MII_OFFSET_ANY, 0); 356 if (error != 0) { 357 device_printf(dev, "attaching PHYs failed\n"); 358 goto fail; 359 } 360 361 ether_ifattach(ifp, sc->eaddr); 362 /* Tell the upper layer(s) we support long frames. */ 363 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 364 365 /* 366 * Create and run all helper tasks. 367 */ 368 sc->tq = taskqueue_create_fast("ae_taskq", M_WAITOK, 369 taskqueue_thread_enqueue, &sc->tq); 370 if (sc->tq == NULL) { 371 device_printf(dev, "could not create taskqueue.\n"); 372 ether_ifdetach(ifp); 373 error = ENXIO; 374 goto fail; 375 } 376 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq", 377 device_get_nameunit(sc->dev)); 378 379 /* 380 * Configure interrupt handlers. 381 */ 382 error = bus_setup_intr(dev, sc->irq[0], INTR_TYPE_NET | INTR_MPSAFE, 383 ae_intr, NULL, sc, &sc->intrhand); 384 if (error != 0) { 385 device_printf(dev, "could not set up interrupt handler.\n"); 386 taskqueue_free(sc->tq); 387 sc->tq = NULL; 388 ether_ifdetach(ifp); 389 goto fail; 390 } 391 392fail: 393 if (error != 0) 394 ae_detach(dev); 395 396 return (error); 397} 398 399#define AE_SYSCTL(stx, parent, name, desc, ptr) \ 400 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, name, CTLFLAG_RD, ptr, 0, desc) 401 402static void 403ae_init_tunables(ae_softc_t *sc) 404{ 405 struct sysctl_ctx_list *ctx; 406 struct sysctl_oid *root, *stats, *stats_rx, *stats_tx; 407 struct ae_stats *ae_stats; 408 409 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 410 ae_stats = &sc->stats; 411 412 ctx = device_get_sysctl_ctx(sc->dev); 413 root = device_get_sysctl_tree(sc->dev); 414 stats = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(root), OID_AUTO, "stats", 415 CTLFLAG_RD, NULL, "ae statistics"); 416 417 /* 418 * Receiver statistcics. 419 */ 420 stats_rx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "rx", 421 CTLFLAG_RD, NULL, "Rx MAC statistics"); 422 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "bcast", 423 "broadcast frames", &ae_stats->rx_bcast); 424 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "mcast", 425 "multicast frames", &ae_stats->rx_mcast); 426 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "pause", 427 "PAUSE frames", &ae_stats->rx_pause); 428 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "control", 429 "control frames", &ae_stats->rx_ctrl); 430 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "crc_errors", 431 "frames with CRC errors", &ae_stats->rx_crcerr); 432 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "code_errors", 433 "frames with invalid opcode", &ae_stats->rx_codeerr); 434 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "runt", 435 "runt frames", &ae_stats->rx_runt); 436 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "frag", 437 "fragmented frames", &ae_stats->rx_frag); 438 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "align_errors", 439 "frames with alignment errors", &ae_stats->rx_align); 440 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "truncated", 441 "frames truncated due to Rx FIFO inderrun", &ae_stats->rx_trunc); 442 443 /* 444 * Receiver statistcics. 445 */ 446 stats_tx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "tx", 447 CTLFLAG_RD, NULL, "Tx MAC statistics"); 448 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "bcast", 449 "broadcast frames", &ae_stats->tx_bcast); 450 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "mcast", 451 "multicast frames", &ae_stats->tx_mcast); 452 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "pause", 453 "PAUSE frames", &ae_stats->tx_pause); 454 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "control", 455 "control frames", &ae_stats->tx_ctrl); 456 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "defers", 457 "deferrals occuried", &ae_stats->tx_defer); 458 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "exc_defers", 459 "excessive deferrals occuried", &ae_stats->tx_excdefer); 460 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "singlecols", 461 "single collisions occuried", &ae_stats->tx_singlecol); 462 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "multicols", 463 "multiple collisions occuried", &ae_stats->tx_multicol); 464 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "latecols", 465 "late collisions occuried", &ae_stats->tx_latecol); 466 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "aborts", 467 "transmit aborts due collisions", &ae_stats->tx_abortcol); 468 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "underruns", 469 "Tx FIFO underruns", &ae_stats->tx_underrun); 470} 471 472static void 473ae_pcie_init(ae_softc_t *sc) 474{ 475 476 AE_WRITE_4(sc, AE_PCIE_LTSSM_TESTMODE_REG, AE_PCIE_LTSSM_TESTMODE_DEFAULT); 477 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, AE_PCIE_DLL_TX_CTRL_DEFAULT); 478} 479 480static void 481ae_phy_reset(ae_softc_t *sc) 482{ 483 484 AE_WRITE_4(sc, AE_PHY_ENABLE_REG, AE_PHY_ENABLE); 485 DELAY(1000); /* XXX: pause(9) ? */ 486} 487 488static int 489ae_reset(ae_softc_t *sc) 490{ 491 int i; 492 493 /* 494 * Issue a soft reset. 495 */ 496 AE_WRITE_4(sc, AE_MASTER_REG, AE_MASTER_SOFT_RESET); 497 bus_barrier(sc->mem[0], AE_MASTER_REG, 4, 498 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 499 500 /* 501 * Wait for reset to complete. 502 */ 503 for (i = 0; i < AE_RESET_TIMEOUT; i++) { 504 if ((AE_READ_4(sc, AE_MASTER_REG) & AE_MASTER_SOFT_RESET) == 0) 505 break; 506 DELAY(10); 507 } 508 if (i == AE_RESET_TIMEOUT) { 509 device_printf(sc->dev, "reset timeout.\n"); 510 return (ENXIO); 511 } 512 513 /* 514 * Wait for everything to enter idle state. 515 */ 516 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 517 if (AE_READ_4(sc, AE_IDLE_REG) == 0) 518 break; 519 DELAY(100); 520 } 521 if (i == AE_IDLE_TIMEOUT) { 522 device_printf(sc->dev, "could not enter idle state.\n"); 523 return (ENXIO); 524 } 525 return (0); 526} 527 528static void 529ae_init(void *arg) 530{ 531 ae_softc_t *sc; 532 533 sc = (ae_softc_t *)arg; 534 AE_LOCK(sc); 535 ae_init_locked(sc); 536 AE_UNLOCK(sc); 537} 538 539static void 540ae_phy_init(ae_softc_t *sc) 541{ 542 543 /* 544 * Enable link status change interrupt. 545 * XXX magic numbers. 546 */ 547#ifdef notyet 548 AE_PHY_WRITE(sc, 18, 0xc00); 549#endif 550} 551 552static int 553ae_init_locked(ae_softc_t *sc) 554{ 555 struct ifnet *ifp; 556 struct mii_data *mii; 557 uint8_t eaddr[ETHER_ADDR_LEN]; 558 uint32_t val; 559 bus_addr_t addr; 560 561 AE_LOCK_ASSERT(sc); 562 563 ifp = sc->ifp; 564 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 565 return (0); 566 mii = device_get_softc(sc->miibus); 567 568 ae_stop(sc); 569 ae_reset(sc); 570 ae_pcie_init(sc); /* Initialize PCIE stuff. */ 571 ae_phy_init(sc); 572 ae_powersave_disable(sc); 573 574 /* 575 * Clear and disable interrupts. 576 */ 577 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff); 578 579 /* 580 * Set the MAC address. 581 */ 582 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 583 val = eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]; 584 AE_WRITE_4(sc, AE_EADDR0_REG, val); 585 val = eaddr[0] << 8 | eaddr[1]; 586 AE_WRITE_4(sc, AE_EADDR1_REG, val); 587 588 /* 589 * Set ring buffers base addresses. 590 */ 591 addr = sc->dma_rxd_busaddr; 592 AE_WRITE_4(sc, AE_DESC_ADDR_HI_REG, BUS_ADDR_HI(addr)); 593 AE_WRITE_4(sc, AE_RXD_ADDR_LO_REG, BUS_ADDR_LO(addr)); 594 addr = sc->dma_txd_busaddr; 595 AE_WRITE_4(sc, AE_TXD_ADDR_LO_REG, BUS_ADDR_LO(addr)); 596 addr = sc->dma_txs_busaddr; 597 AE_WRITE_4(sc, AE_TXS_ADDR_LO_REG, BUS_ADDR_LO(addr)); 598 599 /* 600 * Configure ring buffers sizes. 601 */ 602 AE_WRITE_2(sc, AE_RXD_COUNT_REG, AE_RXD_COUNT_DEFAULT); 603 AE_WRITE_2(sc, AE_TXD_BUFSIZE_REG, AE_TXD_BUFSIZE_DEFAULT / 4); 604 AE_WRITE_2(sc, AE_TXS_COUNT_REG, AE_TXS_COUNT_DEFAULT); 605 606 /* 607 * Configure interframe gap parameters. 608 */ 609 val = ((AE_IFG_TXIPG_DEFAULT << AE_IFG_TXIPG_SHIFT) & 610 AE_IFG_TXIPG_MASK) | 611 ((AE_IFG_RXIPG_DEFAULT << AE_IFG_RXIPG_SHIFT) & 612 AE_IFG_RXIPG_MASK) | 613 ((AE_IFG_IPGR1_DEFAULT << AE_IFG_IPGR1_SHIFT) & 614 AE_IFG_IPGR1_MASK) | 615 ((AE_IFG_IPGR2_DEFAULT << AE_IFG_IPGR2_SHIFT) & 616 AE_IFG_IPGR2_MASK); 617 AE_WRITE_4(sc, AE_IFG_REG, val); 618 619 /* 620 * Configure half-duplex operation. 621 */ 622 val = ((AE_HDPX_LCOL_DEFAULT << AE_HDPX_LCOL_SHIFT) & 623 AE_HDPX_LCOL_MASK) | 624 ((AE_HDPX_RETRY_DEFAULT << AE_HDPX_RETRY_SHIFT) & 625 AE_HDPX_RETRY_MASK) | 626 ((AE_HDPX_ABEBT_DEFAULT << AE_HDPX_ABEBT_SHIFT) & 627 AE_HDPX_ABEBT_MASK) | 628 ((AE_HDPX_JAMIPG_DEFAULT << AE_HDPX_JAMIPG_SHIFT) & 629 AE_HDPX_JAMIPG_MASK) | AE_HDPX_EXC_EN; 630 AE_WRITE_4(sc, AE_HDPX_REG, val); 631 632 /* 633 * Configure interrupt moderate timer. 634 */ 635 AE_WRITE_2(sc, AE_IMT_REG, AE_IMT_DEFAULT); 636 val = AE_READ_4(sc, AE_MASTER_REG); 637 val |= AE_MASTER_IMT_EN; 638 AE_WRITE_4(sc, AE_MASTER_REG, val); 639 640 /* 641 * Configure interrupt clearing timer. 642 */ 643 AE_WRITE_2(sc, AE_ICT_REG, AE_ICT_DEFAULT); 644 645 /* 646 * Configure MTU. 647 */ 648 val = ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 649 ETHER_CRC_LEN; 650 AE_WRITE_2(sc, AE_MTU_REG, val); 651 652 /* 653 * Configure cut-through threshold. 654 */ 655 AE_WRITE_4(sc, AE_CUT_THRESH_REG, AE_CUT_THRESH_DEFAULT); 656 657 /* 658 * Configure flow control. 659 */ 660 AE_WRITE_2(sc, AE_FLOW_THRESH_HI_REG, (AE_RXD_COUNT_DEFAULT / 8) * 7); 661 AE_WRITE_2(sc, AE_FLOW_THRESH_LO_REG, (AE_RXD_COUNT_MIN / 8) > 662 (AE_RXD_COUNT_DEFAULT / 12) ? (AE_RXD_COUNT_MIN / 8) : 663 (AE_RXD_COUNT_DEFAULT / 12)); 664 665 /* 666 * Init mailboxes. 667 */ 668 sc->txd_cur = sc->rxd_cur = 0; 669 sc->txs_ack = sc->txd_ack = 0; 670 sc->rxd_cur = 0; 671 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur); 672 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur); 673 674 sc->tx_inproc = 0; /* Number of packets the chip processes now. */ 675 sc->flags |= AE_FLAG_TXAVAIL; /* Free Tx's available. */ 676 677 /* 678 * Enable DMA. 679 */ 680 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN); 681 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN); 682 683 /* 684 * Check if everything is OK. 685 */ 686 val = AE_READ_4(sc, AE_ISR_REG); 687 if ((val & AE_ISR_PHY_LINKDOWN) != 0) { 688 device_printf(sc->dev, "Initialization failed.\n"); 689 return (ENXIO); 690 } 691 692 /* 693 * Clear interrupt status. 694 */ 695 AE_WRITE_4(sc, AE_ISR_REG, 0x3fffffff); 696 AE_WRITE_4(sc, AE_ISR_REG, 0x0); 697 698 /* 699 * Enable interrupts. 700 */ 701 val = AE_READ_4(sc, AE_MASTER_REG); 702 AE_WRITE_4(sc, AE_MASTER_REG, val | AE_MASTER_MANUAL_INT); 703 AE_WRITE_4(sc, AE_IMR_REG, AE_IMR_DEFAULT); 704 705 /* 706 * Disable WOL. 707 */ 708 AE_WRITE_4(sc, AE_WOL_REG, 0); 709 710 /* 711 * Configure MAC. 712 */ 713 val = AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD | 714 AE_MAC_FULL_DUPLEX | AE_MAC_CLK_PHY | 715 AE_MAC_TX_FLOW_EN | AE_MAC_RX_FLOW_EN | 716 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & AE_HALFBUF_MASK) | 717 ((AE_MAC_PREAMBLE_DEFAULT << AE_MAC_PREAMBLE_SHIFT) & 718 AE_MAC_PREAMBLE_MASK); 719 AE_WRITE_4(sc, AE_MAC_REG, val); 720 721 /* 722 * Configure Rx MAC. 723 */ 724 ae_rxfilter(sc); 725 ae_rxvlan(sc); 726 727 /* 728 * Enable Tx/Rx. 729 */ 730 val = AE_READ_4(sc, AE_MAC_REG); 731 AE_WRITE_4(sc, AE_MAC_REG, val | AE_MAC_TX_EN | AE_MAC_RX_EN); 732 733 sc->flags &= ~AE_FLAG_LINK; 734 mii_mediachg(mii); /* Switch to the current media. */ 735 736 callout_reset(&sc->tick_ch, hz, ae_tick, sc); 737 738 ifp->if_drv_flags |= IFF_DRV_RUNNING; 739 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 740 741#ifdef AE_DEBUG 742 device_printf(sc->dev, "Initialization complete.\n"); 743#endif 744 745 return (0); 746} 747 748static int 749ae_detach(device_t dev) 750{ 751 struct ae_softc *sc; 752 struct ifnet *ifp; 753 754 sc = device_get_softc(dev); 755 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__)); 756 ifp = sc->ifp; 757 if (device_is_attached(dev)) { 758 AE_LOCK(sc); 759 sc->flags |= AE_FLAG_DETACH; 760 ae_stop(sc); 761 AE_UNLOCK(sc); 762 callout_drain(&sc->tick_ch); 763 taskqueue_drain(sc->tq, &sc->int_task); 764 taskqueue_drain(taskqueue_swi, &sc->link_task); 765 ether_ifdetach(ifp); 766 } 767 if (sc->tq != NULL) { 768 taskqueue_drain(sc->tq, &sc->int_task); 769 taskqueue_free(sc->tq); 770 sc->tq = NULL; 771 } 772 if (sc->miibus != NULL) { 773 device_delete_child(dev, sc->miibus); 774 sc->miibus = NULL; 775 } 776 bus_generic_detach(sc->dev); 777 ae_dma_free(sc); 778 if (sc->intrhand != NULL) { 779 bus_teardown_intr(dev, sc->irq[0], sc->intrhand); 780 sc->intrhand = NULL; 781 } 782 if (ifp != NULL) { 783 if_free(ifp); 784 sc->ifp = NULL; 785 } 786 if (sc->spec_irq != NULL) 787 bus_release_resources(dev, sc->spec_irq, sc->irq); 788 if (sc->spec_mem != NULL) 789 bus_release_resources(dev, sc->spec_mem, sc->mem); 790 if ((sc->flags & AE_FLAG_MSI) != 0) 791 pci_release_msi(dev); 792 mtx_destroy(&sc->mtx); 793 794 return (0); 795} 796 797static int 798ae_miibus_readreg(device_t dev, int phy, int reg) 799{ 800 ae_softc_t *sc; 801 uint32_t val; 802 int i; 803 804 sc = device_get_softc(dev); 805 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 806 807 /* 808 * Locking is done in upper layers. 809 */ 810 811 val = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) | 812 AE_MDIO_START | AE_MDIO_READ | AE_MDIO_SUP_PREAMBLE | 813 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK); 814 AE_WRITE_4(sc, AE_MDIO_REG, val); 815 816 /* 817 * Wait for operation to complete. 818 */ 819 for (i = 0; i < AE_MDIO_TIMEOUT; i++) { 820 DELAY(2); 821 val = AE_READ_4(sc, AE_MDIO_REG); 822 if ((val & (AE_MDIO_START | AE_MDIO_BUSY)) == 0) 823 break; 824 } 825 if (i == AE_MDIO_TIMEOUT) { 826 device_printf(sc->dev, "phy read timeout: %d.\n", reg); 827 return (0); 828 } 829 return ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK); 830} 831 832static int 833ae_miibus_writereg(device_t dev, int phy, int reg, int val) 834{ 835 ae_softc_t *sc; 836 uint32_t aereg; 837 int i; 838 839 sc = device_get_softc(dev); 840 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 841 842 /* 843 * Locking is done in upper layers. 844 */ 845 846 aereg = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) | 847 AE_MDIO_START | AE_MDIO_SUP_PREAMBLE | 848 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK) | 849 ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK); 850 AE_WRITE_4(sc, AE_MDIO_REG, aereg); 851 852 /* 853 * Wait for operation to complete. 854 */ 855 for (i = 0; i < AE_MDIO_TIMEOUT; i++) { 856 DELAY(2); 857 aereg = AE_READ_4(sc, AE_MDIO_REG); 858 if ((aereg & (AE_MDIO_START | AE_MDIO_BUSY)) == 0) 859 break; 860 } 861 if (i == AE_MDIO_TIMEOUT) { 862 device_printf(sc->dev, "phy write timeout: %d.\n", reg); 863 } 864 return (0); 865} 866 867static void 868ae_miibus_statchg(device_t dev) 869{ 870 ae_softc_t *sc; 871 872 sc = device_get_softc(dev); 873 taskqueue_enqueue(taskqueue_swi, &sc->link_task); 874} 875 876static void 877ae_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 878{ 879 ae_softc_t *sc; 880 struct mii_data *mii; 881 882 sc = ifp->if_softc; 883 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 884 885 AE_LOCK(sc); 886 mii = device_get_softc(sc->miibus); 887 mii_pollstat(mii); 888 ifmr->ifm_status = mii->mii_media_status; 889 ifmr->ifm_active = mii->mii_media_active; 890 AE_UNLOCK(sc); 891} 892 893static int 894ae_mediachange(struct ifnet *ifp) 895{ 896 ae_softc_t *sc; 897 struct mii_data *mii; 898 struct mii_softc *mii_sc; 899 int error; 900 901 /* XXX: check IFF_UP ?? */ 902 sc = ifp->if_softc; 903 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 904 AE_LOCK(sc); 905 mii = device_get_softc(sc->miibus); 906 if (mii->mii_instance != 0) { 907 LIST_FOREACH(mii_sc, &mii->mii_phys, mii_list) 908 mii_phy_reset(mii_sc); 909 } 910 error = mii_mediachg(mii); 911 AE_UNLOCK(sc); 912 913 return (error); 914} 915 916static int 917ae_check_eeprom_present(ae_softc_t *sc, int *vpdc) 918{ 919 int error; 920 uint32_t val; 921 922 KASSERT(vpdc != NULL, ("[ae, %d]: vpdc is NULL!\n", __LINE__)); 923 924 /* 925 * Not sure why, but Linux does this. 926 */ 927 val = AE_READ_4(sc, AE_SPICTL_REG); 928 if ((val & AE_SPICTL_VPD_EN) != 0) { 929 val &= ~AE_SPICTL_VPD_EN; 930 AE_WRITE_4(sc, AE_SPICTL_REG, val); 931 } 932 error = pci_find_cap(sc->dev, PCIY_VPD, vpdc); 933 return (error); 934} 935 936static int 937ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word) 938{ 939 uint32_t val; 940 int i; 941 942 AE_WRITE_4(sc, AE_VPD_DATA_REG, 0); /* Clear register value. */ 943 944 /* 945 * VPD registers start at offset 0x100. Read them. 946 */ 947 val = 0x100 + reg * 4; 948 AE_WRITE_4(sc, AE_VPD_CAP_REG, (val << AE_VPD_CAP_ADDR_SHIFT) & 949 AE_VPD_CAP_ADDR_MASK); 950 for (i = 0; i < AE_VPD_TIMEOUT; i++) { 951 DELAY(2000); 952 val = AE_READ_4(sc, AE_VPD_CAP_REG); 953 if ((val & AE_VPD_CAP_DONE) != 0) 954 break; 955 } 956 if (i == AE_VPD_TIMEOUT) { 957 device_printf(sc->dev, "timeout reading VPD register %d.\n", 958 reg); 959 return (ETIMEDOUT); 960 } 961 *word = AE_READ_4(sc, AE_VPD_DATA_REG); 962 return (0); 963} 964 965static int 966ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr) 967{ 968 uint32_t word, reg, val; 969 int error; 970 int found; 971 int vpdc; 972 int i; 973 974 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 975 KASSERT(eaddr != NULL, ("[ae, %d]: eaddr is NULL", __LINE__)); 976 977 /* 978 * Check for EEPROM. 979 */ 980 error = ae_check_eeprom_present(sc, &vpdc); 981 if (error != 0) 982 return (error); 983 984 /* 985 * Read the VPD configuration space. 986 * Each register is prefixed with signature, 987 * so we can check if it is valid. 988 */ 989 for (i = 0, found = 0; i < AE_VPD_NREGS; i++) { 990 error = ae_vpd_read_word(sc, i, &word); 991 if (error != 0) 992 break; 993 994 /* 995 * Check signature. 996 */ 997 if ((word & AE_VPD_SIG_MASK) != AE_VPD_SIG) 998 break; 999 reg = word >> AE_VPD_REG_SHIFT; 1000 i++; /* Move to the next word. */ 1001 1002 if (reg != AE_EADDR0_REG && reg != AE_EADDR1_REG) 1003 continue; 1004 1005 error = ae_vpd_read_word(sc, i, &val); 1006 if (error != 0) 1007 break; 1008 if (reg == AE_EADDR0_REG) 1009 eaddr[0] = val; 1010 else 1011 eaddr[1] = val; 1012 found++; 1013 } 1014 1015 if (found < 2) 1016 return (ENOENT); 1017 1018 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */ 1019 if (AE_CHECK_EADDR_VALID(eaddr) != 0) { 1020 if (bootverbose) 1021 device_printf(sc->dev, 1022 "VPD ethernet address registers are invalid.\n"); 1023 return (EINVAL); 1024 } 1025 return (0); 1026} 1027 1028static int 1029ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr) 1030{ 1031 1032 /* 1033 * BIOS is supposed to set this. 1034 */ 1035 eaddr[0] = AE_READ_4(sc, AE_EADDR0_REG); 1036 eaddr[1] = AE_READ_4(sc, AE_EADDR1_REG); 1037 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */ 1038 1039 if (AE_CHECK_EADDR_VALID(eaddr) != 0) { 1040 if (bootverbose) 1041 device_printf(sc->dev, 1042 "Ethernet address registers are invalid.\n"); 1043 return (EINVAL); 1044 } 1045 return (0); 1046} 1047 1048static void 1049ae_retrieve_address(ae_softc_t *sc) 1050{ 1051 uint32_t eaddr[2] = {0, 0}; 1052 int error; 1053 1054 /* 1055 *Check for EEPROM. 1056 */ 1057 error = ae_get_vpd_eaddr(sc, eaddr); 1058 if (error != 0) 1059 error = ae_get_reg_eaddr(sc, eaddr); 1060 if (error != 0) { 1061 if (bootverbose) 1062 device_printf(sc->dev, 1063 "Generating random ethernet address.\n"); 1064 eaddr[0] = arc4random(); 1065 1066 /* 1067 * Set OUI to ASUSTek COMPUTER INC. 1068 */ 1069 sc->eaddr[0] = 0x02; /* U/L bit set. */ 1070 sc->eaddr[1] = 0x1f; 1071 sc->eaddr[2] = 0xc6; 1072 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff; 1073 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff; 1074 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff; 1075 } else { 1076 sc->eaddr[0] = (eaddr[1] >> 8) & 0xff; 1077 sc->eaddr[1] = (eaddr[1] >> 0) & 0xff; 1078 sc->eaddr[2] = (eaddr[0] >> 24) & 0xff; 1079 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff; 1080 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff; 1081 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff; 1082 } 1083} 1084 1085static void 1086ae_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1087{ 1088 bus_addr_t *addr = arg; 1089 1090 if (error != 0) 1091 return; 1092 KASSERT(nsegs == 1, ("[ae, %d]: %d segments instead of 1!", __LINE__, 1093 nsegs)); 1094 *addr = segs[0].ds_addr; 1095} 1096 1097static int 1098ae_alloc_rings(ae_softc_t *sc) 1099{ 1100 bus_addr_t busaddr; 1101 int error; 1102 1103 /* 1104 * Create parent DMA tag. 1105 */ 1106 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1107 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1108 NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0, 1109 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 1110 &sc->dma_parent_tag); 1111 if (error != 0) { 1112 device_printf(sc->dev, "could not creare parent DMA tag.\n"); 1113 return (error); 1114 } 1115 1116 /* 1117 * Create DMA tag for TxD. 1118 */ 1119 error = bus_dma_tag_create(sc->dma_parent_tag, 1120 4, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1121 NULL, NULL, AE_TXD_BUFSIZE_DEFAULT, 1, 1122 AE_TXD_BUFSIZE_DEFAULT, 0, NULL, NULL, 1123 &sc->dma_txd_tag); 1124 if (error != 0) { 1125 device_printf(sc->dev, "could not creare TxD DMA tag.\n"); 1126 return (error); 1127 } 1128 1129 /* 1130 * Create DMA tag for TxS. 1131 */ 1132 error = bus_dma_tag_create(sc->dma_parent_tag, 1133 4, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1134 NULL, NULL, AE_TXS_COUNT_DEFAULT * 4, 1, 1135 AE_TXS_COUNT_DEFAULT * 4, 0, NULL, NULL, 1136 &sc->dma_txs_tag); 1137 if (error != 0) { 1138 device_printf(sc->dev, "could not creare TxS DMA tag.\n"); 1139 return (error); 1140 } 1141 1142 /* 1143 * Create DMA tag for RxD. 1144 */ 1145 error = bus_dma_tag_create(sc->dma_parent_tag, 1146 128, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1147 NULL, NULL, AE_RXD_COUNT_DEFAULT * 1536 + 120, 1, 1148 AE_RXD_COUNT_DEFAULT * 1536 + 120, 0, NULL, NULL, 1149 &sc->dma_rxd_tag); 1150 if (error != 0) { 1151 device_printf(sc->dev, "could not creare TxS DMA tag.\n"); 1152 return (error); 1153 } 1154 1155 /* 1156 * Allocate TxD DMA memory. 1157 */ 1158 error = bus_dmamem_alloc(sc->dma_txd_tag, (void **)&sc->txd_base, 1159 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1160 &sc->dma_txd_map); 1161 if (error != 0) { 1162 device_printf(sc->dev, 1163 "could not allocate DMA memory for TxD ring.\n"); 1164 return (error); 1165 } 1166 error = bus_dmamap_load(sc->dma_txd_tag, sc->dma_txd_map, sc->txd_base, 1167 AE_TXD_BUFSIZE_DEFAULT, ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT); 1168 if (error != 0 || busaddr == 0) { 1169 device_printf(sc->dev, 1170 "could not load DMA map for TxD ring.\n"); 1171 return (error); 1172 } 1173 sc->dma_txd_busaddr = busaddr; 1174 1175 /* 1176 * Allocate TxS DMA memory. 1177 */ 1178 error = bus_dmamem_alloc(sc->dma_txs_tag, (void **)&sc->txs_base, 1179 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1180 &sc->dma_txs_map); 1181 if (error != 0) { 1182 device_printf(sc->dev, 1183 "could not allocate DMA memory for TxS ring.\n"); 1184 return (error); 1185 } 1186 error = bus_dmamap_load(sc->dma_txs_tag, sc->dma_txs_map, sc->txs_base, 1187 AE_TXS_COUNT_DEFAULT * 4, ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT); 1188 if (error != 0 || busaddr == 0) { 1189 device_printf(sc->dev, 1190 "could not load DMA map for TxS ring.\n"); 1191 return (error); 1192 } 1193 sc->dma_txs_busaddr = busaddr; 1194 1195 /* 1196 * Allocate RxD DMA memory. 1197 */ 1198 error = bus_dmamem_alloc(sc->dma_rxd_tag, (void **)&sc->rxd_base_dma, 1199 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1200 &sc->dma_rxd_map); 1201 if (error != 0) { 1202 device_printf(sc->dev, 1203 "could not allocate DMA memory for RxD ring.\n"); 1204 return (error); 1205 } 1206 error = bus_dmamap_load(sc->dma_rxd_tag, sc->dma_rxd_map, 1207 sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + 120, ae_dmamap_cb, 1208 &busaddr, BUS_DMA_NOWAIT); 1209 if (error != 0 || busaddr == 0) { 1210 device_printf(sc->dev, 1211 "could not load DMA map for RxD ring.\n"); 1212 return (error); 1213 } 1214 sc->dma_rxd_busaddr = busaddr + 120; 1215 sc->rxd_base = (ae_rxd_t *)(sc->rxd_base_dma + 120); 1216 1217 return (0); 1218} 1219 1220static void 1221ae_dma_free(ae_softc_t *sc) 1222{ 1223 1224 if (sc->dma_txd_tag != NULL) { 1225 if (sc->dma_txd_map != NULL) { 1226 bus_dmamap_unload(sc->dma_txd_tag, sc->dma_txd_map); 1227 if (sc->txd_base != NULL) 1228 bus_dmamem_free(sc->dma_txd_tag, sc->txd_base, 1229 sc->dma_txd_map); 1230 1231 } 1232 bus_dma_tag_destroy(sc->dma_txd_tag); 1233 sc->dma_txd_map = NULL; 1234 sc->dma_txd_tag = NULL; 1235 sc->txd_base = NULL; 1236 } 1237 if (sc->dma_txs_tag != NULL) { 1238 if (sc->dma_txs_map != NULL) { 1239 bus_dmamap_unload(sc->dma_txs_tag, sc->dma_txs_map); 1240 if (sc->txs_base != NULL) 1241 bus_dmamem_free(sc->dma_txs_tag, sc->txs_base, 1242 sc->dma_txs_map); 1243 1244 } 1245 bus_dma_tag_destroy(sc->dma_txs_tag); 1246 sc->dma_txs_map = NULL; 1247 sc->dma_txs_tag = NULL; 1248 sc->txs_base = NULL; 1249 } 1250 if (sc->dma_rxd_tag != NULL) { 1251 if (sc->dma_rxd_map != NULL) { 1252 bus_dmamap_unload(sc->dma_rxd_tag, sc->dma_rxd_map); 1253 if (sc->rxd_base_dma != NULL) 1254 bus_dmamem_free(sc->dma_rxd_tag, 1255 sc->rxd_base_dma, sc->dma_rxd_map); 1256 1257 } 1258 bus_dma_tag_destroy(sc->dma_rxd_tag); 1259 sc->dma_rxd_map = NULL; 1260 sc->dma_rxd_tag = NULL; 1261 sc->rxd_base_dma = NULL; 1262 } 1263 if (sc->dma_parent_tag != NULL) { 1264 bus_dma_tag_destroy(sc->dma_parent_tag); 1265 sc->dma_parent_tag = NULL; 1266 } 1267} 1268 1269static int 1270ae_shutdown(device_t dev) 1271{ 1272 ae_softc_t *sc; 1273 int error; 1274 1275 sc = device_get_softc(dev); 1276 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__)); 1277 1278 error = ae_suspend(dev); 1279 AE_LOCK(sc); 1280 ae_powersave_enable(sc); 1281 AE_UNLOCK(sc); 1282 return (error); 1283} 1284 1285static void 1286ae_powersave_disable(ae_softc_t *sc) 1287{ 1288 uint32_t val; 1289 1290 AE_LOCK_ASSERT(sc); 1291 1292 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0); 1293 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA); 1294 if (val & AE_PHY_DBG_POWERSAVE) { 1295 val &= ~AE_PHY_DBG_POWERSAVE; 1296 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, val); 1297 DELAY(1000); 1298 } 1299} 1300 1301static void 1302ae_powersave_enable(ae_softc_t *sc) 1303{ 1304 uint32_t val; 1305 1306 AE_LOCK_ASSERT(sc); 1307 1308 /* 1309 * XXX magic numbers. 1310 */ 1311 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0); 1312 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA); 1313 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, val | 0x1000); 1314 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 2); 1315 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0x3000); 1316 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 3); 1317 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0); 1318} 1319 1320static void 1321ae_pm_init(ae_softc_t *sc) 1322{ 1323 struct ifnet *ifp; 1324 uint32_t val; 1325 uint16_t pmstat; 1326 struct mii_data *mii; 1327 int pmc; 1328 1329 AE_LOCK_ASSERT(sc); 1330 1331 ifp = sc->ifp; 1332 if ((sc->flags & AE_FLAG_PMG) == 0) { 1333 /* Disable WOL entirely. */ 1334 AE_WRITE_4(sc, AE_WOL_REG, 0); 1335 return; 1336 } 1337 1338 /* 1339 * Configure WOL if enabled. 1340 */ 1341 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1342 mii = device_get_softc(sc->miibus); 1343 mii_pollstat(mii); 1344 if ((mii->mii_media_status & IFM_AVALID) != 0 && 1345 (mii->mii_media_status & IFM_ACTIVE) != 0) { 1346 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_MAGIC | \ 1347 AE_WOL_MAGIC_PME); 1348 1349 /* 1350 * Configure MAC. 1351 */ 1352 val = AE_MAC_RX_EN | AE_MAC_CLK_PHY | \ 1353 AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD | \ 1354 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & \ 1355 AE_HALFBUF_MASK) | \ 1356 ((AE_MAC_PREAMBLE_DEFAULT << \ 1357 AE_MAC_PREAMBLE_SHIFT) & AE_MAC_PREAMBLE_MASK) | \ 1358 AE_MAC_BCAST_EN | AE_MAC_MCAST_EN; 1359 if ((IFM_OPTIONS(mii->mii_media_active) & \ 1360 IFM_FDX) != 0) 1361 val |= AE_MAC_FULL_DUPLEX; 1362 AE_WRITE_4(sc, AE_MAC_REG, val); 1363 1364 } else { /* No link. */ 1365 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_LNKCHG | \ 1366 AE_WOL_LNKCHG_PME); 1367 AE_WRITE_4(sc, AE_MAC_REG, 0); 1368 } 1369 } else { 1370 ae_powersave_enable(sc); 1371 } 1372 1373 /* 1374 * PCIE hacks. Magic numbers. 1375 */ 1376 val = AE_READ_4(sc, AE_PCIE_PHYMISC_REG); 1377 val |= AE_PCIE_PHYMISC_FORCE_RCV_DET; 1378 AE_WRITE_4(sc, AE_PCIE_PHYMISC_REG, val); 1379 val = AE_READ_4(sc, AE_PCIE_DLL_TX_CTRL_REG); 1380 val |= AE_PCIE_DLL_TX_CTRL_SEL_NOR_CLK; 1381 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, val); 1382 1383 /* 1384 * Configure PME. 1385 */ 1386 pci_find_cap(sc->dev, PCIY_PMG, &pmc); 1387 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1388 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1389 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1390 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1391 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1392} 1393 1394static int 1395ae_suspend(device_t dev) 1396{ 1397 ae_softc_t *sc; 1398 1399 sc = device_get_softc(dev); 1400 1401 AE_LOCK(sc); 1402 ae_stop(sc); 1403 ae_pm_init(sc); 1404 AE_UNLOCK(sc); 1405 1406 return (0); 1407} 1408 1409static int 1410ae_resume(device_t dev) 1411{ 1412 ae_softc_t *sc; 1413 1414 sc = device_get_softc(dev); 1415 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1416 1417 AE_LOCK(sc); 1418 AE_READ_4(sc, AE_WOL_REG); /* Clear WOL status. */ 1419 if ((sc->ifp->if_flags & IFF_UP) != 0) 1420 ae_init_locked(sc); 1421 AE_UNLOCK(sc); 1422 1423 return (0); 1424} 1425 1426static unsigned int 1427ae_tx_avail_size(ae_softc_t *sc) 1428{ 1429 unsigned int avail; 1430 1431 if (sc->txd_cur >= sc->txd_ack) 1432 avail = AE_TXD_BUFSIZE_DEFAULT - (sc->txd_cur - sc->txd_ack); 1433 else 1434 avail = sc->txd_ack - sc->txd_cur; 1435 1436 return (avail - 4); /* 4-byte header. */ 1437} 1438 1439static int 1440ae_encap(ae_softc_t *sc, struct mbuf **m_head) 1441{ 1442 struct mbuf *m0; 1443 ae_txd_t *hdr; 1444 unsigned int to_end; 1445 uint16_t len; 1446 1447 AE_LOCK_ASSERT(sc); 1448 1449 m0 = *m_head; 1450 len = m0->m_pkthdr.len; 1451 1452 if ((sc->flags & AE_FLAG_TXAVAIL) == 0 || 1453 ae_tx_avail_size(sc) < len) { 1454#ifdef AE_DEBUG 1455 if_printf(sc->ifp, "No free Tx available.\n"); 1456#endif 1457 return ENOBUFS; 1458 } 1459 1460 hdr = (ae_txd_t *)(sc->txd_base + sc->txd_cur); 1461 bzero(hdr, sizeof(*hdr)); 1462 sc->txd_cur = (sc->txd_cur + 4) % AE_TXD_BUFSIZE_DEFAULT; /* Header 1463 size. */ 1464 to_end = AE_TXD_BUFSIZE_DEFAULT - sc->txd_cur; /* Space available to 1465 * the end of the ring 1466 */ 1467 if (to_end >= len) { 1468 m_copydata(m0, 0, len, (caddr_t)(sc->txd_base + sc->txd_cur)); 1469 } else { 1470 m_copydata(m0, 0, to_end, (caddr_t)(sc->txd_base + 1471 sc->txd_cur)); 1472 m_copydata(m0, to_end, len - to_end, (caddr_t)sc->txd_base); 1473 } 1474 1475 /* 1476 * Set TxD flags and parameters. 1477 */ 1478 if ((m0->m_flags & M_VLANTAG) != 0) { 1479 hdr->vlan = htole16(AE_TXD_VLAN(m0->m_pkthdr.ether_vtag)); 1480 hdr->len = htole16(len | AE_TXD_INSERT_VTAG); 1481 } else { 1482 hdr->len = htole16(len); 1483 } 1484 1485 /* 1486 * Set current TxD position and round up to a 4-byte boundary. 1487 */ 1488 sc->txd_cur = ((sc->txd_cur + len + 3) & ~3) % AE_TXD_BUFSIZE_DEFAULT; 1489 if (sc->txd_cur == sc->txd_ack) 1490 sc->flags &= ~AE_FLAG_TXAVAIL; 1491#ifdef AE_DEBUG 1492 if_printf(sc->ifp, "New txd_cur = %d.\n", sc->txd_cur); 1493#endif 1494 1495 /* 1496 * Update TxS position and check if there are empty TxS available. 1497 */ 1498 sc->txs_base[sc->txs_cur].flags &= ~htole16(AE_TXS_UPDATE); 1499 sc->txs_cur = (sc->txs_cur + 1) % AE_TXS_COUNT_DEFAULT; 1500 if (sc->txs_cur == sc->txs_ack) 1501 sc->flags &= ~AE_FLAG_TXAVAIL; 1502 1503 /* 1504 * Synchronize DMA memory. 1505 */ 1506 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, BUS_DMASYNC_PREREAD | 1507 BUS_DMASYNC_PREWRITE); 1508 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1509 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1510 1511 return (0); 1512} 1513 1514static void 1515ae_start(struct ifnet *ifp) 1516{ 1517 ae_softc_t *sc; 1518 1519 sc = ifp->if_softc; 1520 AE_LOCK(sc); 1521 ae_start_locked(ifp); 1522 AE_UNLOCK(sc); 1523} 1524 1525static void 1526ae_start_locked(struct ifnet *ifp) 1527{ 1528 ae_softc_t *sc; 1529 unsigned int count; 1530 struct mbuf *m0; 1531 int error; 1532 1533 sc = ifp->if_softc; 1534 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1535 AE_LOCK_ASSERT(sc); 1536 1537#ifdef AE_DEBUG 1538 if_printf(ifp, "Start called.\n"); 1539#endif 1540 1541 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1542 IFF_DRV_RUNNING || (sc->flags & AE_FLAG_LINK) == 0) 1543 return; 1544 1545 count = 0; 1546 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 1547 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); 1548 if (m0 == NULL) 1549 break; /* Nothing to do. */ 1550 1551 error = ae_encap(sc, &m0); 1552 if (error != 0) { 1553 if (m0 != NULL) { 1554 IFQ_DRV_PREPEND(&ifp->if_snd, m0); 1555 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1556#ifdef AE_DEBUG 1557 if_printf(ifp, "Setting OACTIVE.\n"); 1558#endif 1559 } 1560 break; 1561 } 1562 count++; 1563 sc->tx_inproc++; 1564 1565 /* Bounce a copy of the frame to BPF. */ 1566 ETHER_BPF_MTAP(ifp, m0); 1567 1568 m_freem(m0); 1569 } 1570 1571 if (count > 0) { /* Something was dequeued. */ 1572 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur / 4); 1573 sc->wd_timer = AE_TX_TIMEOUT; /* Load watchdog. */ 1574#ifdef AE_DEBUG 1575 if_printf(ifp, "%d packets dequeued.\n", count); 1576 if_printf(ifp, "Tx pos now is %d.\n", sc->txd_cur); 1577#endif 1578 } 1579} 1580 1581static void 1582ae_link_task(void *arg, int pending) 1583{ 1584 ae_softc_t *sc; 1585 struct mii_data *mii; 1586 struct ifnet *ifp; 1587 uint32_t val; 1588 1589 sc = (ae_softc_t *)arg; 1590 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1591 AE_LOCK(sc); 1592 1593 ifp = sc->ifp; 1594 mii = device_get_softc(sc->miibus); 1595 if (mii == NULL || ifp == NULL || 1596 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1597 AE_UNLOCK(sc); /* XXX: could happen? */ 1598 return; 1599 } 1600 1601 sc->flags &= ~AE_FLAG_LINK; 1602 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 1603 (IFM_AVALID | IFM_ACTIVE)) { 1604 switch(IFM_SUBTYPE(mii->mii_media_active)) { 1605 case IFM_10_T: 1606 case IFM_100_TX: 1607 sc->flags |= AE_FLAG_LINK; 1608 break; 1609 default: 1610 break; 1611 } 1612 } 1613 1614 /* 1615 * Stop Rx/Tx MACs. 1616 */ 1617 ae_stop_rxmac(sc); 1618 ae_stop_txmac(sc); 1619 1620 if ((sc->flags & AE_FLAG_LINK) != 0) { 1621 ae_mac_config(sc); 1622 1623 /* 1624 * Restart DMA engines. 1625 */ 1626 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN); 1627 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN); 1628 1629 /* 1630 * Enable Rx and Tx MACs. 1631 */ 1632 val = AE_READ_4(sc, AE_MAC_REG); 1633 val |= AE_MAC_TX_EN | AE_MAC_RX_EN; 1634 AE_WRITE_4(sc, AE_MAC_REG, val); 1635 } 1636 AE_UNLOCK(sc); 1637} 1638 1639static void 1640ae_stop_rxmac(ae_softc_t *sc) 1641{ 1642 uint32_t val; 1643 int i; 1644 1645 AE_LOCK_ASSERT(sc); 1646 1647 /* 1648 * Stop Rx MAC engine. 1649 */ 1650 val = AE_READ_4(sc, AE_MAC_REG); 1651 if ((val & AE_MAC_RX_EN) != 0) { 1652 val &= ~AE_MAC_RX_EN; 1653 AE_WRITE_4(sc, AE_MAC_REG, val); 1654 } 1655 1656 /* 1657 * Stop Rx DMA engine. 1658 */ 1659 if (AE_READ_1(sc, AE_DMAWRITE_REG) == AE_DMAWRITE_EN) 1660 AE_WRITE_1(sc, AE_DMAWRITE_REG, 0); 1661 1662 /* 1663 * Wait for IDLE state. 1664 */ 1665 for (i = 0; i < AE_IDLE_TIMEOUT; i--) { 1666 val = AE_READ_4(sc, AE_IDLE_REG); 1667 if ((val & (AE_IDLE_RXMAC | AE_IDLE_DMAWRITE)) == 0) 1668 break; 1669 DELAY(100); 1670 } 1671 if (i == AE_IDLE_TIMEOUT) 1672 device_printf(sc->dev, "timed out while stopping Rx MAC.\n"); 1673} 1674 1675static void 1676ae_stop_txmac(ae_softc_t *sc) 1677{ 1678 uint32_t val; 1679 int i; 1680 1681 AE_LOCK_ASSERT(sc); 1682 1683 /* 1684 * Stop Tx MAC engine. 1685 */ 1686 val = AE_READ_4(sc, AE_MAC_REG); 1687 if ((val & AE_MAC_TX_EN) != 0) { 1688 val &= ~AE_MAC_TX_EN; 1689 AE_WRITE_4(sc, AE_MAC_REG, val); 1690 } 1691 1692 /* 1693 * Stop Tx DMA engine. 1694 */ 1695 if (AE_READ_1(sc, AE_DMAREAD_REG) == AE_DMAREAD_EN) 1696 AE_WRITE_1(sc, AE_DMAREAD_REG, 0); 1697 1698 /* 1699 * Wait for IDLE state. 1700 */ 1701 for (i = 0; i < AE_IDLE_TIMEOUT; i--) { 1702 val = AE_READ_4(sc, AE_IDLE_REG); 1703 if ((val & (AE_IDLE_TXMAC | AE_IDLE_DMAREAD)) == 0) 1704 break; 1705 DELAY(100); 1706 } 1707 if (i == AE_IDLE_TIMEOUT) 1708 device_printf(sc->dev, "timed out while stopping Tx MAC.\n"); 1709} 1710 1711static void 1712ae_mac_config(ae_softc_t *sc) 1713{ 1714 struct mii_data *mii; 1715 uint32_t val; 1716 1717 AE_LOCK_ASSERT(sc); 1718 1719 mii = device_get_softc(sc->miibus); 1720 val = AE_READ_4(sc, AE_MAC_REG); 1721 val &= ~AE_MAC_FULL_DUPLEX; 1722 /* XXX disable AE_MAC_TX_FLOW_EN? */ 1723 1724 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1725 val |= AE_MAC_FULL_DUPLEX; 1726 1727 AE_WRITE_4(sc, AE_MAC_REG, val); 1728} 1729 1730static int 1731ae_intr(void *arg) 1732{ 1733 ae_softc_t *sc; 1734 uint32_t val; 1735 1736 sc = (ae_softc_t *)arg; 1737 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1738 1739 val = AE_READ_4(sc, AE_ISR_REG); 1740 if (val == 0 || (val & AE_IMR_DEFAULT) == 0) 1741 return (FILTER_STRAY); 1742 1743 /* Disable interrupts. */ 1744 AE_WRITE_4(sc, AE_ISR_REG, AE_ISR_DISABLE); 1745 1746 /* Schedule interrupt processing. */ 1747 taskqueue_enqueue(sc->tq, &sc->int_task); 1748 1749 return (FILTER_HANDLED); 1750} 1751 1752static void 1753ae_int_task(void *arg, int pending) 1754{ 1755 ae_softc_t *sc; 1756 struct ifnet *ifp; 1757 uint32_t val; 1758 1759 sc = (ae_softc_t *)arg; 1760 1761 AE_LOCK(sc); 1762 1763 ifp = sc->ifp; 1764 1765 val = AE_READ_4(sc, AE_ISR_REG); /* Read interrupt status. */ 1766 1767 /* 1768 * Clear interrupts and disable them. 1769 */ 1770 AE_WRITE_4(sc, AE_ISR_REG, val | AE_ISR_DISABLE); 1771 1772#ifdef AE_DEBUG 1773 if_printf(ifp, "Interrupt received: 0x%08x\n", val); 1774#endif 1775 1776 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1777 if ((val & (AE_ISR_DMAR_TIMEOUT | AE_ISR_DMAW_TIMEOUT | 1778 AE_ISR_PHY_LINKDOWN)) != 0) { 1779 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1780 ae_init_locked(sc); 1781 AE_UNLOCK(sc); 1782 return; 1783 } 1784 if ((val & AE_ISR_TX_EVENT) != 0) 1785 ae_tx_intr(sc); 1786 if ((val & AE_ISR_RX_EVENT) != 0) 1787 ae_rx_intr(sc); 1788 } 1789 1790 /* 1791 * Re-enable interrupts. 1792 */ 1793 AE_WRITE_4(sc, AE_ISR_REG, 0); 1794 1795 AE_UNLOCK(sc); 1796} 1797 1798static void 1799ae_tx_intr(ae_softc_t *sc) 1800{ 1801 struct ifnet *ifp; 1802 ae_txd_t *txd; 1803 ae_txs_t *txs; 1804 uint16_t flags; 1805 1806 AE_LOCK_ASSERT(sc); 1807 1808 ifp = sc->ifp; 1809 1810#ifdef AE_DEBUG 1811 if_printf(ifp, "Tx interrupt occuried.\n"); 1812#endif 1813 1814 /* 1815 * Syncronize DMA buffers. 1816 */ 1817 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, 1818 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1819 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1820 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1821 1822 for (;;) { 1823 txs = sc->txs_base + sc->txs_ack; 1824 flags = le16toh(txs->flags); 1825 if ((flags & AE_TXS_UPDATE) == 0) 1826 break; 1827 txs->flags = htole16(flags & ~AE_TXS_UPDATE); 1828 /* Update stats. */ 1829 ae_update_stats_tx(flags, &sc->stats); 1830 1831 /* 1832 * Update TxS position. 1833 */ 1834 sc->txs_ack = (sc->txs_ack + 1) % AE_TXS_COUNT_DEFAULT; 1835 sc->flags |= AE_FLAG_TXAVAIL; 1836 1837 txd = (ae_txd_t *)(sc->txd_base + sc->txd_ack); 1838 if (txs->len != txd->len) 1839 device_printf(sc->dev, "Size mismatch: TxS:%d TxD:%d\n", 1840 le16toh(txs->len), le16toh(txd->len)); 1841 1842 /* 1843 * Move txd ack and align on 4-byte boundary. 1844 */ 1845 sc->txd_ack = ((sc->txd_ack + le16toh(txd->len) + 4 + 3) & ~3) % 1846 AE_TXD_BUFSIZE_DEFAULT; 1847 1848 if ((flags & AE_TXS_SUCCESS) != 0) 1849 ifp->if_opackets++; 1850 else 1851 ifp->if_oerrors++; 1852 1853 sc->tx_inproc--; 1854 1855 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1856 } 1857 1858 if (sc->tx_inproc < 0) { 1859 if_printf(ifp, "Received stray Tx interrupt(s).\n"); 1860 sc->tx_inproc = 0; 1861 } 1862 1863 if (sc->tx_inproc == 0) 1864 sc->wd_timer = 0; /* Unarm watchdog. */ 1865 1866 if ((sc->flags & AE_FLAG_TXAVAIL) != 0) { 1867 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1868 ae_start_locked(ifp); 1869 } 1870 1871 /* 1872 * Syncronize DMA buffers. 1873 */ 1874 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, 1875 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1876 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1877 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1878} 1879 1880static int 1881ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd) 1882{ 1883 struct ifnet *ifp; 1884 struct mbuf *m; 1885 unsigned int size; 1886 uint16_t flags; 1887 1888 AE_LOCK_ASSERT(sc); 1889 1890 ifp = sc->ifp; 1891 flags = le16toh(rxd->flags); 1892 1893#ifdef AE_DEBUG 1894 if_printf(ifp, "Rx interrupt occuried.\n"); 1895#endif 1896 size = le16toh(rxd->len) - ETHER_CRC_LEN; 1897 if (size < (ETHER_MIN_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN)) { 1898 if_printf(ifp, "Runt frame received."); 1899 return (EIO); 1900 } 1901 1902 m = m_devget(&rxd->data[0], size, ETHER_ALIGN, ifp, NULL); 1903 if (m == NULL) 1904 return (ENOBUFS); 1905 1906 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 1907 (flags & AE_RXD_HAS_VLAN) != 0) { 1908 m->m_pkthdr.ether_vtag = AE_RXD_VLAN(le16toh(rxd->vlan)); 1909 m->m_flags |= M_VLANTAG; 1910 } 1911 1912 /* 1913 * Pass it through. 1914 */ 1915 AE_UNLOCK(sc); 1916 (*ifp->if_input)(ifp, m); 1917 AE_LOCK(sc); 1918 1919 return (0); 1920} 1921 1922static void 1923ae_rx_intr(ae_softc_t *sc) 1924{ 1925 ae_rxd_t *rxd; 1926 struct ifnet *ifp; 1927 uint16_t flags; 1928 int error; 1929 1930 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 1931 1932 AE_LOCK_ASSERT(sc); 1933 1934 ifp = sc->ifp; 1935 1936 /* 1937 * Syncronize DMA buffers. 1938 */ 1939 bus_dmamap_sync(sc->dma_rxd_tag, sc->dma_rxd_map, 1940 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1941 1942 for (;;) { 1943 rxd = (ae_rxd_t *)(sc->rxd_base + sc->rxd_cur); 1944 flags = le16toh(rxd->flags); 1945 if ((flags & AE_RXD_UPDATE) == 0) 1946 break; 1947 rxd->flags = htole16(flags & ~AE_RXD_UPDATE); 1948 /* Update stats. */ 1949 ae_update_stats_rx(flags, &sc->stats); 1950 1951 /* 1952 * Update position index. 1953 */ 1954 sc->rxd_cur = (sc->rxd_cur + 1) % AE_RXD_COUNT_DEFAULT; 1955 1956 if ((flags & AE_RXD_SUCCESS) == 0) { 1957 ifp->if_ierrors++; 1958 continue; 1959 } 1960 error = ae_rxeof(sc, rxd); 1961 if (error != 0) { 1962 ifp->if_ierrors++; 1963 continue; 1964 } else { 1965 ifp->if_ipackets++; 1966 } 1967 } 1968 1969 /* 1970 * Update Rx index. 1971 */ 1972 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur); 1973} 1974 1975static void 1976ae_watchdog(ae_softc_t *sc) 1977{ 1978 struct ifnet *ifp; 1979 1980 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 1981 AE_LOCK_ASSERT(sc); 1982 ifp = sc->ifp; 1983 1984 if (sc->wd_timer == 0 || --sc->wd_timer != 0) 1985 return; /* Noting to do. */ 1986 1987 if ((sc->flags & AE_FLAG_LINK) == 0) 1988 if_printf(ifp, "watchdog timeout (missed link).\n"); 1989 else 1990 if_printf(ifp, "watchdog timeout - resetting.\n"); 1991 1992 ifp->if_oerrors++; 1993 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1994 ae_init_locked(sc); 1995 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1996 ae_start_locked(ifp); 1997} 1998 1999static void 2000ae_tick(void *arg) 2001{ 2002 ae_softc_t *sc; 2003 struct mii_data *mii; 2004 2005 sc = (ae_softc_t *)arg; 2006 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 2007 AE_LOCK_ASSERT(sc); 2008 2009 mii = device_get_softc(sc->miibus); 2010 mii_tick(mii); 2011 ae_watchdog(sc); /* Watchdog check. */ 2012 callout_reset(&sc->tick_ch, hz, ae_tick, sc); 2013} 2014 2015static void 2016ae_rxvlan(ae_softc_t *sc) 2017{ 2018 struct ifnet *ifp; 2019 uint32_t val; 2020 2021 AE_LOCK_ASSERT(sc); 2022 ifp = sc->ifp; 2023 val = AE_READ_4(sc, AE_MAC_REG); 2024 val &= ~AE_MAC_RMVLAN_EN; 2025 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2026 val |= AE_MAC_RMVLAN_EN; 2027 AE_WRITE_4(sc, AE_MAC_REG, val); 2028} 2029 2030static void 2031ae_rxfilter(ae_softc_t *sc) 2032{ 2033 struct ifnet *ifp; 2034 struct ifmultiaddr *ifma; 2035 uint32_t crc; 2036 uint32_t mchash[2]; 2037 uint32_t rxcfg; 2038 2039 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 2040 2041 AE_LOCK_ASSERT(sc); 2042 2043 ifp = sc->ifp; 2044 2045 rxcfg = AE_READ_4(sc, AE_MAC_REG); 2046 rxcfg &= ~(AE_MAC_MCAST_EN | AE_MAC_BCAST_EN | AE_MAC_PROMISC_EN); 2047 2048 if ((ifp->if_flags & IFF_BROADCAST) != 0) 2049 rxcfg |= AE_MAC_BCAST_EN; 2050 if ((ifp->if_flags & IFF_PROMISC) != 0) 2051 rxcfg |= AE_MAC_PROMISC_EN; 2052 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 2053 rxcfg |= AE_MAC_MCAST_EN; 2054 2055 /* 2056 * Wipe old settings. 2057 */ 2058 AE_WRITE_4(sc, AE_REG_MHT0, 0); 2059 AE_WRITE_4(sc, AE_REG_MHT1, 0); 2060 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2061 AE_WRITE_4(sc, AE_REG_MHT0, 0xffffffff); 2062 AE_WRITE_4(sc, AE_REG_MHT1, 0xffffffff); 2063 AE_WRITE_4(sc, AE_MAC_REG, rxcfg); 2064 return; 2065 } 2066 2067 /* 2068 * Load multicast tables. 2069 */ 2070 bzero(mchash, sizeof(mchash)); 2071 if_maddr_rlock(ifp); 2072 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2073 if (ifma->ifma_addr->sa_family != AF_LINK) 2074 continue; 2075 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 2076 ifma->ifma_addr), ETHER_ADDR_LEN); 2077 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2078 } 2079 if_maddr_runlock(ifp); 2080 AE_WRITE_4(sc, AE_REG_MHT0, mchash[0]); 2081 AE_WRITE_4(sc, AE_REG_MHT1, mchash[1]); 2082 AE_WRITE_4(sc, AE_MAC_REG, rxcfg); 2083} 2084 2085static int 2086ae_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2087{ 2088 struct ae_softc *sc; 2089 struct ifreq *ifr; 2090 struct mii_data *mii; 2091 int error, mask; 2092 2093 sc = ifp->if_softc; 2094 ifr = (struct ifreq *)data; 2095 error = 0; 2096 2097 switch (cmd) { 2098 case SIOCSIFMTU: 2099 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) 2100 error = EINVAL; 2101 else if (ifp->if_mtu != ifr->ifr_mtu) { 2102 AE_LOCK(sc); 2103 ifp->if_mtu = ifr->ifr_mtu; 2104 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2105 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2106 ae_init_locked(sc); 2107 } 2108 AE_UNLOCK(sc); 2109 } 2110 break; 2111 case SIOCSIFFLAGS: 2112 AE_LOCK(sc); 2113 if ((ifp->if_flags & IFF_UP) != 0) { 2114 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2115 if (((ifp->if_flags ^ sc->if_flags) 2116 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2117 ae_rxfilter(sc); 2118 } else { 2119 if ((sc->flags & AE_FLAG_DETACH) == 0) 2120 ae_init_locked(sc); 2121 } 2122 } else { 2123 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2124 ae_stop(sc); 2125 } 2126 sc->if_flags = ifp->if_flags; 2127 AE_UNLOCK(sc); 2128 break; 2129 case SIOCADDMULTI: 2130 case SIOCDELMULTI: 2131 AE_LOCK(sc); 2132 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2133 ae_rxfilter(sc); 2134 AE_UNLOCK(sc); 2135 break; 2136 case SIOCSIFMEDIA: 2137 case SIOCGIFMEDIA: 2138 mii = device_get_softc(sc->miibus); 2139 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2140 break; 2141 case SIOCSIFCAP: 2142 AE_LOCK(sc); 2143 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2144 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2145 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2146 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2147 ae_rxvlan(sc); 2148 } 2149 VLAN_CAPABILITIES(ifp); 2150 AE_UNLOCK(sc); 2151 break; 2152 default: 2153 error = ether_ioctl(ifp, cmd, data); 2154 break; 2155 } 2156 return (error); 2157} 2158 2159static void 2160ae_stop(ae_softc_t *sc) 2161{ 2162 struct ifnet *ifp; 2163 int i; 2164 2165 AE_LOCK_ASSERT(sc); 2166 2167 ifp = sc->ifp; 2168 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2169 sc->flags &= ~AE_FLAG_LINK; 2170 sc->wd_timer = 0; /* Cancel watchdog. */ 2171 callout_stop(&sc->tick_ch); 2172 2173 /* 2174 * Clear and disable interrupts. 2175 */ 2176 AE_WRITE_4(sc, AE_IMR_REG, 0); 2177 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff); 2178 2179 /* 2180 * Stop Rx/Tx MACs. 2181 */ 2182 ae_stop_txmac(sc); 2183 ae_stop_rxmac(sc); 2184 2185 /* 2186 * Stop DMA engines. 2187 */ 2188 AE_WRITE_1(sc, AE_DMAREAD_REG, ~AE_DMAREAD_EN); 2189 AE_WRITE_1(sc, AE_DMAWRITE_REG, ~AE_DMAWRITE_EN); 2190 2191 /* 2192 * Wait for everything to enter idle state. 2193 */ 2194 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 2195 if (AE_READ_4(sc, AE_IDLE_REG) == 0) 2196 break; 2197 DELAY(100); 2198 } 2199 if (i == AE_IDLE_TIMEOUT) 2200 device_printf(sc->dev, "could not enter idle state in stop.\n"); 2201} 2202 2203static void 2204ae_update_stats_tx(uint16_t flags, ae_stats_t *stats) 2205{ 2206 2207 if ((flags & AE_TXS_BCAST) != 0) 2208 stats->tx_bcast++; 2209 if ((flags & AE_TXS_MCAST) != 0) 2210 stats->tx_mcast++; 2211 if ((flags & AE_TXS_PAUSE) != 0) 2212 stats->tx_pause++; 2213 if ((flags & AE_TXS_CTRL) != 0) 2214 stats->tx_ctrl++; 2215 if ((flags & AE_TXS_DEFER) != 0) 2216 stats->tx_defer++; 2217 if ((flags & AE_TXS_EXCDEFER) != 0) 2218 stats->tx_excdefer++; 2219 if ((flags & AE_TXS_SINGLECOL) != 0) 2220 stats->tx_singlecol++; 2221 if ((flags & AE_TXS_MULTICOL) != 0) 2222 stats->tx_multicol++; 2223 if ((flags & AE_TXS_LATECOL) != 0) 2224 stats->tx_latecol++; 2225 if ((flags & AE_TXS_ABORTCOL) != 0) 2226 stats->tx_abortcol++; 2227 if ((flags & AE_TXS_UNDERRUN) != 0) 2228 stats->tx_underrun++; 2229} 2230 2231static void 2232ae_update_stats_rx(uint16_t flags, ae_stats_t *stats) 2233{ 2234 2235 if ((flags & AE_RXD_BCAST) != 0) 2236 stats->rx_bcast++; 2237 if ((flags & AE_RXD_MCAST) != 0) 2238 stats->rx_mcast++; 2239 if ((flags & AE_RXD_PAUSE) != 0) 2240 stats->rx_pause++; 2241 if ((flags & AE_RXD_CTRL) != 0) 2242 stats->rx_ctrl++; 2243 if ((flags & AE_RXD_CRCERR) != 0) 2244 stats->rx_crcerr++; 2245 if ((flags & AE_RXD_CODEERR) != 0) 2246 stats->rx_codeerr++; 2247 if ((flags & AE_RXD_RUNT) != 0) 2248 stats->rx_runt++; 2249 if ((flags & AE_RXD_FRAG) != 0) 2250 stats->rx_frag++; 2251 if ((flags & AE_RXD_TRUNC) != 0) 2252 stats->rx_trunc++; 2253 if ((flags & AE_RXD_ALIGN) != 0) 2254 stats->rx_align++; 2255} 2256