cvmx-l2c.h revision 215990
1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41 42 43 44 45 46/** 47 * @file 48 * 49 * Interface to the Level 2 Cache (L2C) control, measurement, and debugging 50 * facilities. 51 * 52 * <hr>$Revision: 52004 $<hr> 53 * 54 */ 55 56#ifndef __CVMX_L2C_H__ 57#define __CVMX_L2C_H__ 58 59#define CVMX_L2_ASSOC cvmx_l2c_get_num_assoc() /* Deprecated macro, use function */ 60#define CVMX_L2_SET_BITS cvmx_l2c_get_set_bits() /* Deprecated macro, use function */ 61#define CVMX_L2_SETS cvmx_l2c_get_num_sets() /* Deprecated macro, use function */ 62 63 64#define CVMX_L2C_IDX_ADDR_SHIFT 7 /* based on 128 byte cache line size */ 65#define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1) 66 67/* Defines for index aliasing computations */ 68#define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits()) 69#define CVMX_L2C_ALIAS_MASK (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) 70#define CVMX_L2C_MEMBANK_SELECT_SIZE 4096 71 72/* Defines for Virtualizations, valid only from Octeon II onwards. */ 73#define CVMX_L2C_VRT_MAX_VIRTID_ALLOWED ((OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 64 : 0) 74#define CVMX_L2C_VRT_MAX_MEMSZ_ALLOWED ((OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 32 : 0) 75 76 /*------------*/ 77 /* TYPEDEFS */ 78 /*------------*/ 79 80typedef union 81{ 82 uint64_t u64; 83#if __BYTE_ORDER == __BIG_ENDIAN 84 struct 85 { 86 uint64_t reserved : 28; 87 uint64_t V : 1; // Line valid 88 uint64_t D : 1; // Line dirty 89 uint64_t L : 1; // Line locked 90 uint64_t U : 1; // Use, LRU eviction 91 uint64_t addr : 32; // Phys mem (not all bits valid) 92 } s; 93#endif 94} cvmx_l2c_tag_t; 95 96/* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */ 97#define CVMX_L2C_TADS 1 98 99 /* L2C Performance Counter events. */ 100typedef enum 101{ 102 CVMX_L2C_EVENT_CYCLES = 0, /**< Cycles */ 103 CVMX_L2C_EVENT_INSTRUCTION_MISS = 1, /**< L2 Instruction Miss */ 104 CVMX_L2C_EVENT_INSTRUCTION_HIT = 2, /**< L2 Instruction Hit */ 105 CVMX_L2C_EVENT_DATA_MISS = 3, /**< L2 Data Miss */ 106 CVMX_L2C_EVENT_DATA_HIT = 4, /**< L2 Data Hit */ 107 CVMX_L2C_EVENT_MISS = 5, /**< L2 Miss (I/D) */ 108 CVMX_L2C_EVENT_HIT = 6, /**< L2 Hit (I/D) */ 109 CVMX_L2C_EVENT_VICTIM_HIT = 7, /**< L2 Victim Buffer Hit (Retry Probe) */ 110 CVMX_L2C_EVENT_INDEX_CONFLICT = 8, /**< LFB-NQ Index Conflict */ 111 CVMX_L2C_EVENT_TAG_PROBE = 9, /**< L2 Tag Probe (issued - could be VB-Retried) */ 112 CVMX_L2C_EVENT_TAG_UPDATE = 10, /**< L2 Tag Update (completed). Note: Some CMD types do not update */ 113 CVMX_L2C_EVENT_TAG_COMPLETE = 11, /**< L2 Tag Probe Completed (beyond VB-RTY window) */ 114 CVMX_L2C_EVENT_TAG_DIRTY = 12, /**< L2 Tag Dirty Victim */ 115 CVMX_L2C_EVENT_DATA_STORE_NOP = 13, /**< L2 Data Store NOP */ 116 CVMX_L2C_EVENT_DATA_STORE_READ = 14, /**< L2 Data Store READ */ 117 CVMX_L2C_EVENT_DATA_STORE_WRITE = 15, /**< L2 Data Store WRITE */ 118 CVMX_L2C_EVENT_FILL_DATA_VALID = 16, /**< Memory Fill Data valid */ 119 CVMX_L2C_EVENT_WRITE_REQUEST = 17, /**< Memory Write Request */ 120 CVMX_L2C_EVENT_READ_REQUEST = 18, /**< Memory Read Request */ 121 CVMX_L2C_EVENT_WRITE_DATA_VALID = 19, /**< Memory Write Data valid */ 122 CVMX_L2C_EVENT_XMC_NOP = 20, /**< XMC NOP */ 123 CVMX_L2C_EVENT_XMC_LDT = 21, /**< XMC LDT */ 124 CVMX_L2C_EVENT_XMC_LDI = 22, /**< XMC LDI */ 125 CVMX_L2C_EVENT_XMC_LDD = 23, /**< XMC LDD */ 126 CVMX_L2C_EVENT_XMC_STF = 24, /**< XMC STF */ 127 CVMX_L2C_EVENT_XMC_STT = 25, /**< XMC STT */ 128 CVMX_L2C_EVENT_XMC_STP = 26, /**< XMC STP */ 129 CVMX_L2C_EVENT_XMC_STC = 27, /**< XMC STC */ 130 CVMX_L2C_EVENT_XMC_DWB = 28, /**< XMC DWB */ 131 CVMX_L2C_EVENT_XMC_PL2 = 29, /**< XMC PL2 */ 132 CVMX_L2C_EVENT_XMC_PSL1 = 30, /**< XMC PSL1 */ 133 CVMX_L2C_EVENT_XMC_IOBLD = 31, /**< XMC IOBLD */ 134 CVMX_L2C_EVENT_XMC_IOBST = 32, /**< XMC IOBST */ 135 CVMX_L2C_EVENT_XMC_IOBDMA = 33, /**< XMC IOBDMA */ 136 CVMX_L2C_EVENT_XMC_IOBRSP = 34, /**< XMC IOBRSP */ 137 CVMX_L2C_EVENT_XMC_BUS_VALID = 35, /**< XMC Bus valid (all) */ 138 CVMX_L2C_EVENT_XMC_MEM_DATA = 36, /**< XMC Bus valid (DST=L2C) Memory */ 139 CVMX_L2C_EVENT_XMC_REFL_DATA = 37, /**< XMC Bus valid (DST=IOB) REFL Data */ 140 CVMX_L2C_EVENT_XMC_IOBRSP_DATA = 38, /**< XMC Bus valid (DST=PP) IOBRSP Data */ 141 CVMX_L2C_EVENT_RSC_NOP = 39, /**< RSC NOP */ 142 CVMX_L2C_EVENT_RSC_STDN = 40, /**< RSC STDN */ 143 CVMX_L2C_EVENT_RSC_FILL = 41, /**< RSC FILL */ 144 CVMX_L2C_EVENT_RSC_REFL = 42, /**< RSC REFL */ 145 CVMX_L2C_EVENT_RSC_STIN = 43, /**< RSC STIN */ 146 CVMX_L2C_EVENT_RSC_SCIN = 44, /**< RSC SCIN */ 147 CVMX_L2C_EVENT_RSC_SCFL = 45, /**< RSC SCFL */ 148 CVMX_L2C_EVENT_RSC_SCDN = 46, /**< RSC SCDN */ 149 CVMX_L2C_EVENT_RSC_DATA_VALID = 47, /**< RSC Data Valid */ 150 CVMX_L2C_EVENT_RSC_VALID_FILL = 48, /**< RSC Data Valid (FILL) */ 151 CVMX_L2C_EVENT_RSC_VALID_STRSP = 49, /**< RSC Data Valid (STRSP) */ 152 CVMX_L2C_EVENT_RSC_VALID_REFL = 50, /**< RSC Data Valid (REFL) */ 153 CVMX_L2C_EVENT_LRF_REQ = 51, /**< LRF-REQ (LFB-NQ) */ 154 CVMX_L2C_EVENT_DT_RD_ALLOC = 52, /**< DT RD-ALLOC */ 155 CVMX_L2C_EVENT_DT_WR_INVAL = 53, /**< DT WR-INVAL */ 156 CVMX_L2C_EVENT_MAX 157} cvmx_l2c_event_t; 158 159/* L2C Performance Counter events for Octeon2. */ 160typedef enum 161{ 162 CVMX_L2C_TAD_EVENT_NONE = 0, /* None */ 163 CVMX_L2C_TAD_EVENT_TAG_HIT = 1, /* L2 Tag Hit */ 164 CVMX_L2C_TAD_EVENT_TAG_MISS = 2, /* L2 Tag Miss */ 165 CVMX_L2C_TAD_EVENT_TAG_NOALLOC = 3, /* L2 Tag NoAlloc (forced no-allocate) */ 166 CVMX_L2C_TAD_EVENT_TAG_VICTIM = 4, /* L2 Tag Victim */ 167 CVMX_L2C_TAD_EVENT_SC_FAIL = 5, /* SC Fail */ 168 CVMX_L2C_TAD_EVENT_SC_PASS = 6, /* SC Pass */ 169 CVMX_L2C_TAD_EVENT_LFB_VALID = 7, /* LFB Occupancy (each cycle adds \# of LFBs valid) */ 170 CVMX_L2C_TAD_EVENT_LFB_WAIT_LFB = 8, /* LFB Wait LFB (each cycle adds \# LFBs waiting for other LFBs) */ 171 CVMX_L2C_TAD_EVENT_LFB_WAIT_VAB = 9, /* LFB Wait VAB (each cycle adds \# LFBs waiting for VAB) */ 172 CVMX_L2C_TAD_EVENT_QUAD0_INDEX = 128, /* Quad 0 index bus inuse */ 173 CVMX_L2C_TAD_EVENT_QUAD0_READ = 129, /* Quad 0 read data bus inuse */ 174 CVMX_L2C_TAD_EVENT_QUAD0_BANK = 130, /* Quad 0 \# banks inuse (0-4/cycle) */ 175 CVMX_L2C_TAD_EVENT_QUAD0_WDAT = 131, /* Quad 0 wdat flops inuse (0-4/cycle) */ 176 CVMX_L2C_TAD_EVENT_QUAD1_INDEX = 144, /* Quad 1 index bus inuse */ 177 CVMX_L2C_TAD_EVENT_QUAD1_READ = 145, /* Quad 1 read data bus inuse */ 178 CVMX_L2C_TAD_EVENT_QUAD1_BANK = 146, /* Quad 1 \# banks inuse (0-4/cycle) */ 179 CVMX_L2C_TAD_EVENT_QUAD1_WDAT = 147, /* Quad 1 wdat flops inuse (0-4/cycle) */ 180 CVMX_L2C_TAD_EVENT_QUAD2_INDEX = 160, /* Quad 2 index bus inuse */ 181 CVMX_L2C_TAD_EVENT_QUAD2_READ = 161, /* Quad 2 read data bus inuse */ 182 CVMX_L2C_TAD_EVENT_QUAD2_BANK = 162, /* Quad 2 \# banks inuse (0-4/cycle) */ 183 CVMX_L2C_TAD_EVENT_QUAD2_WDAT = 163, /* Quad 2 wdat flops inuse (0-4/cycle) */ 184 CVMX_L2C_TAD_EVENT_QUAD3_INDEX = 176, /* Quad 3 index bus inuse */ 185 CVMX_L2C_TAD_EVENT_QUAD3_READ = 177, /* Quad 3 read data bus inuse */ 186 CVMX_L2C_TAD_EVENT_QUAD3_BANK = 178, /* Quad 3 \# banks inuse (0-4/cycle) */ 187 CVMX_L2C_TAD_EVENT_QUAD3_WDAT = 179, /* Quad 3 wdat flops inuse (0-4/cycle) */ 188 CVMX_L2C_TAD_EVENT_MAX 189} cvmx_l2c_tad_event_t; 190 191/** 192 * Configure one of the four L2 Cache performance counters to capture event 193 * occurences. 194 * 195 * @param counter The counter to configure. Range 0..3. 196 * @param event The type of L2 Cache event occurrence to count. 197 * @param clear_on_read When asserted, any read of the performance counter 198 * clears the counter. 199 * 200 * @note The routine does not clear the counter. 201 */ 202void cvmx_l2c_config_perf(uint32_t counter, cvmx_l2c_event_t event, uint32_t clear_on_read); 203 204/** 205 * Read the given L2 Cache performance counter. The counter must be configured 206 * before reading, but this routine does not enforce this requirement. 207 * 208 * @param counter The counter to configure. Range 0..3. 209 * 210 * @return The current counter value. 211 */ 212uint64_t cvmx_l2c_read_perf(uint32_t counter); 213 214/** 215 * Return the L2 Cache way partitioning for a given core. 216 * 217 * @param core The core processor of interest. 218 * 219 * @return The mask specifying the partitioning. 0 bits in mask indicates 220 * the cache 'ways' that a core can evict from. 221 * -1 on error 222 */ 223int cvmx_l2c_get_core_way_partition(uint32_t core); 224 225/** 226 * Partitions the L2 cache for a core 227 * 228 * @param core The core that the partitioning applies to. 229 * @param mask The partitioning of the ways expressed as a binary mask. A 0 bit allows the core 230 * to evict cache lines from a way, while a 1 bit blocks the core from evicting any lines 231 * from that way. There must be at least one allowed way (0 bit) in the mask. 232 * 233 * @note If any ways are blocked for all cores and the HW blocks, then those ways will never have 234 * any cache lines evicted from them. All cores and the hardware blocks are free to read from 235 * all ways regardless of the partitioning. 236 */ 237int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask); 238 239/** 240 * Return the L2 Cache way partitioning for the hw blocks. 241 * 242 * @return The mask specifying the reserved way. 0 bits in mask indicates 243 * the cache 'ways' that a core can evict from. 244 * -1 on error 245 */ 246int cvmx_l2c_get_hw_way_partition(void); 247 248/** 249 * Partitions the L2 cache for the hardware blocks. 250 * 251 * @param mask The partitioning of the ways expressed as a binary mask. A 0 bit allows the core 252 * to evict cache lines from a way, while a 1 bit blocks the core from evicting any lines 253 * from that way. There must be at least one allowed way (0 bit) in the mask. 254 * 255 * @note If any ways are blocked for all cores and the HW blocks, then those ways will never have 256 * any cache lines evicted from them. All cores and the hardware blocks are free to read from 257 * all ways regardless of the partitioning. 258 */ 259int cvmx_l2c_set_hw_way_partition(uint32_t mask); 260 261 262/** 263 * Locks a line in the L2 cache at the specified physical address 264 * 265 * @param addr physical address of line to lock 266 * 267 * @return 0 on success, 268 * 1 if line not locked. 269 */ 270int cvmx_l2c_lock_line(uint64_t addr); 271 272/** 273 * Locks a specified memory region in the L2 cache. 274 * 275 * Note that if not all lines can be locked, that means that all 276 * but one of the ways (associations) available to the locking 277 * core are locked. Having only 1 association available for 278 * normal caching may have a significant adverse affect on performance. 279 * Care should be taken to ensure that enough of the L2 cache is left 280 * unlocked to allow for normal caching of DRAM. 281 * 282 * @param start Physical address of the start of the region to lock 283 * @param len Length (in bytes) of region to lock 284 * 285 * @return Number of requested lines that where not locked. 286 * 0 on success (all locked) 287 */ 288int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len); 289 290 291/** 292 * Unlock and flush a cache line from the L2 cache. 293 * IMPORTANT: Must only be run by one core at a time due to use 294 * of L2C debug features. 295 * Note that this function will flush a matching but unlocked cache line. 296 * (If address is not in L2, no lines are flushed.) 297 * 298 * @param address Physical address to unlock 299 * 300 * @return 0: line not unlocked 301 * 1: line unlocked 302 */ 303int cvmx_l2c_unlock_line(uint64_t address); 304 305/** 306 * Unlocks a region of memory that is locked in the L2 cache 307 * 308 * @param start start physical address 309 * @param len length (in bytes) to unlock 310 * 311 * @return Number of locked lines that the call unlocked 312 */ 313int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len); 314 315 316 317 318/** 319 * Read the L2 controller tag for a given location in L2 320 * 321 * @param association 322 * Which association to read line from 323 * @param index Which way to read from. 324 * 325 * @return l2c tag structure for line requested. 326 */ 327cvmx_l2c_tag_t cvmx_l2c_get_tag(uint32_t association, uint32_t index); 328 329/* Wrapper providing a deprecated old function name */ 330static inline cvmx_l2c_tag_t cvmx_get_l2c_tag(uint32_t association, uint32_t index) __attribute__((deprecated)); 331static inline cvmx_l2c_tag_t cvmx_get_l2c_tag(uint32_t association, uint32_t index) 332{ 333 return cvmx_l2c_get_tag(association, index); 334} 335 336 337/** 338 * Returns the cache index for a given physical address 339 * 340 * @param addr physical address 341 * 342 * @return L2 cache index 343 */ 344uint32_t cvmx_l2c_address_to_index (uint64_t addr); 345 346 347/** 348 * Flushes (and unlocks) the entire L2 cache. 349 * IMPORTANT: Must only be run by one core at a time due to use 350 * of L2C debug features. 351 */ 352void cvmx_l2c_flush(void); 353 354 355 356/** 357 * 358 * @return Returns the size of the L2 cache in bytes, 359 * -1 on error (unrecognized model) 360 */ 361int cvmx_l2c_get_cache_size_bytes(void); 362 363/** 364 * Return the number of sets in the L2 Cache 365 * 366 * @return 367 */ 368int cvmx_l2c_get_num_sets(void); 369 370/** 371 * Return log base 2 of the number of sets in the L2 cache 372 * @return 373 */ 374int cvmx_l2c_get_set_bits(void); 375/** 376 * Return the number of associations in the L2 Cache 377 * 378 * @return 379 */ 380int cvmx_l2c_get_num_assoc(void); 381 382/** 383 * Flush a line from the L2 cache 384 * This should only be called from one core at a time, as this routine 385 * sets the core to the 'debug' core in order to flush the line. 386 * 387 * @param assoc Association (or way) to flush 388 * @param index Index to flush 389 */ 390void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index); 391 392/* 393 * Set maxium number of Virtual IDS allowed in a machine. 394 * 395 * @param nvid Number of virtial ids allowed in a machine. 396 * @return Return 0 on success or -1 on failure. 397 */ 398int cvmx_l2c_vrt_set_max_virtids(int nvid); 399 400/** 401 * Get maxium number of virtual IDs allowed in a machine. 402 * 403 * @return Return number of virtual machine IDs. Return -1 on failure. 404 */ 405int cvmx_l2c_vrt_get_max_virtids(void); 406 407/** 408 * Set the maxium size of memory space to be allocated for virtualization. 409 * 410 * @param memsz Size of the virtual memory in GB 411 * @return Return 0 on success or -1 on failure. 412 */ 413int cvmx_l2c_vrt_set_max_memsz(int memsz); 414 415/** 416 * Set a Virtual ID to a set of cores. 417 * 418 * @param virtid Assign virtid to a set of cores. 419 * @param coremask The group of cores to assign a unique virtual id. 420 * @return Return 0 on success, otherwise -1. 421 */ 422int cvmx_l2c_vrt_assign_virtid(int virtid, uint32_t coremask); 423 424/** 425 * Remove a virt id assigned to a set of cores. Update the virtid mask and 426 * virtid stored for each core. 427 * 428 * @param coremask the group of cores whose virtual id is removed. 429 */ 430void cvmx_l2c_vrt_remove_virtid(int virtid); 431 432/** 433 * Block a memory region to be updated by a set of virtids. 434 * 435 * @param start_addr Starting address of memory region 436 * @param size Size of the memory to protect 437 * @param virtid_mask Virtual ID to use 438 * @param mode Allow/Disallow write access 439 * = 0, Allow write access by virtid 440 * = 1, Disallow write access by virtid 441 */ 442int cvmx_l2c_vrt_memprotect(uint64_t start_addr, int size, int virtid, int mode); 443 444/** 445 * Enable virtualization. 446 */ 447void cvmx_l2c_vrt_enable(int mode); 448 449/** 450 * Disable virtualization. 451 */ 452void cvmx_l2c_vrt_disable(void); 453 454#endif /* __CVMX_L2C_H__ */ 455