cvmx-l2c.h revision 232812
1210284Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2011 Cavium, Inc. (support@cavium.com). All rights 3215990Sjmallett * reserved. 4210284Sjmallett * 5210284Sjmallett * 6215990Sjmallett * Redistribution and use in source and binary forms, with or without 7215990Sjmallett * modification, are permitted provided that the following conditions are 8215990Sjmallett * met: 9210284Sjmallett * 10215990Sjmallett * * Redistributions of source code must retain the above copyright 11215990Sjmallett * notice, this list of conditions and the following disclaimer. 12210284Sjmallett * 13215990Sjmallett * * Redistributions in binary form must reproduce the above 14215990Sjmallett * copyright notice, this list of conditions and the following 15215990Sjmallett * disclaimer in the documentation and/or other materials provided 16215990Sjmallett * with the distribution. 17215990Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215990Sjmallett * its contributors may be used to endorse or promote products 20215990Sjmallett * derived from this software without specific prior written 21215990Sjmallett * permission. 22215990Sjmallett 23215990Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215990Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215990Sjmallett * regulations, and may be subject to export or import regulations in other 26215990Sjmallett * countries. 27215990Sjmallett 28215990Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215990Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215990Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215990Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215990Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215990Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215990Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215990Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215990Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38210284Sjmallett ***********************license end**************************************/ 39210284Sjmallett 40210284Sjmallett/** 41210284Sjmallett * @file 42210284Sjmallett * 43210284Sjmallett * Interface to the Level 2 Cache (L2C) control, measurement, and debugging 44210284Sjmallett * facilities. 45210284Sjmallett * 46232812Sjmallett * <hr>$Revision: 70030 $<hr> 47210284Sjmallett * 48210284Sjmallett */ 49210284Sjmallett 50210284Sjmallett#ifndef __CVMX_L2C_H__ 51210284Sjmallett#define __CVMX_L2C_H__ 52210284Sjmallett 53210284Sjmallett#define CVMX_L2C_IDX_ADDR_SHIFT 7 /* based on 128 byte cache line size */ 54210284Sjmallett#define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1) 55210284Sjmallett 56210284Sjmallett/* Defines for index aliasing computations */ 57210284Sjmallett#define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits()) 58210284Sjmallett#define CVMX_L2C_ALIAS_MASK (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) 59215990Sjmallett#define CVMX_L2C_MEMBANK_SELECT_SIZE 4096 60210284Sjmallett 61215990Sjmallett/* Defines for Virtualizations, valid only from Octeon II onwards. */ 62232812Sjmallett#define CVMX_L2C_VRT_MAX_VIRTID_ALLOWED ((OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) ? 64 : 0) 63232812Sjmallett#define CVMX_L2C_MAX_MEMSZ_ALLOWED ((OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) ? 32 : 0) 64210284Sjmallett 65210284Sjmallett /*------------*/ 66210284Sjmallett /* TYPEDEFS */ 67210284Sjmallett /*------------*/ 68210284Sjmallett 69232812Sjmallettunion cvmx_l2c_tag { 70232812Sjmallett uint64_t u64; 71232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 72232812Sjmallett struct { 73232812Sjmallett uint64_t reserved:28; 74232812Sjmallett uint64_t V:1; /* Line valid */ 75232812Sjmallett uint64_t D:1; /* Line dirty */ 76232812Sjmallett uint64_t L:1; /* Line locked */ 77232812Sjmallett uint64_t U:1; /* Use, LRU eviction */ 78232812Sjmallett uint64_t addr:32; /* Phys mem (not all bits valid) */ 79232812Sjmallett } s; 80232812Sjmallett#else 81232812Sjmallett struct { 82232812Sjmallett uint64_t addr:32; /* Phys mem (not all bits valid) */ 83232812Sjmallett uint64_t U:1; /* Use, LRU eviction */ 84232812Sjmallett uint64_t L:1; /* Line locked */ 85232812Sjmallett uint64_t D:1; /* Line dirty */ 86232812Sjmallett uint64_t V:1; /* Line valid */ 87232812Sjmallett uint64_t reserved:28; 88232812Sjmallett } s; 89232812Sjmallett 90210284Sjmallett#endif 91232812Sjmallett}; 92232812Sjmalletttypedef union cvmx_l2c_tag cvmx_l2c_tag_t; 93210284Sjmallett 94232812Sjmallett/* Maximium number of TADs */ 95232812Sjmallett#define CVMX_L2C_MAX_TADS 4 96232812Sjmallett/* Maximium number of L2C performance counters */ 97232812Sjmallett#define CVMX_L2C_MAX_PCNT 4 98232812Sjmallett 99215990Sjmallett/* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */ 100232812Sjmallett#define CVMX_L2C_TADS ((OCTEON_IS_MODEL(OCTEON_CN68XX)) ? 4 : 1) 101232812Sjmallett/* Number of L2C IOBs connected to LMC. */ 102232812Sjmallett#define CVMX_L2C_IOBS ((OCTEON_IS_MODEL(OCTEON_CN68XX)) ? 2 : 1) 103210284Sjmallett 104210284Sjmallett /* L2C Performance Counter events. */ 105232812Sjmallettenum cvmx_l2c_event { 106232812Sjmallett CVMX_L2C_EVENT_CYCLES = 0, /**< Cycles */ 107232812Sjmallett CVMX_L2C_EVENT_INSTRUCTION_MISS = 1, /**< L2 Instruction Miss */ 108232812Sjmallett CVMX_L2C_EVENT_INSTRUCTION_HIT = 2, /**< L2 Instruction Hit */ 109232812Sjmallett CVMX_L2C_EVENT_DATA_MISS = 3, /**< L2 Data Miss */ 110232812Sjmallett CVMX_L2C_EVENT_DATA_HIT = 4, /**< L2 Data Hit */ 111232812Sjmallett CVMX_L2C_EVENT_MISS = 5, /**< L2 Miss (I/D) */ 112232812Sjmallett CVMX_L2C_EVENT_HIT = 6, /**< L2 Hit (I/D) */ 113232812Sjmallett CVMX_L2C_EVENT_VICTIM_HIT = 7, /**< L2 Victim Buffer Hit (Retry Probe) */ 114232812Sjmallett CVMX_L2C_EVENT_INDEX_CONFLICT = 8, /**< LFB-NQ Index Conflict */ 115232812Sjmallett CVMX_L2C_EVENT_TAG_PROBE = 9, /**< L2 Tag Probe (issued - could be VB-Retried) */ 116232812Sjmallett CVMX_L2C_EVENT_TAG_UPDATE = 10, /**< L2 Tag Update (completed). Note: Some CMD types do not update */ 117232812Sjmallett CVMX_L2C_EVENT_TAG_COMPLETE = 11, /**< L2 Tag Probe Completed (beyond VB-RTY window) */ 118232812Sjmallett CVMX_L2C_EVENT_TAG_DIRTY = 12, /**< L2 Tag Dirty Victim */ 119232812Sjmallett CVMX_L2C_EVENT_DATA_STORE_NOP = 13, /**< L2 Data Store NOP */ 120232812Sjmallett CVMX_L2C_EVENT_DATA_STORE_READ = 14, /**< L2 Data Store READ */ 121232812Sjmallett CVMX_L2C_EVENT_DATA_STORE_WRITE = 15, /**< L2 Data Store WRITE */ 122232812Sjmallett CVMX_L2C_EVENT_FILL_DATA_VALID = 16, /**< Memory Fill Data valid */ 123232812Sjmallett CVMX_L2C_EVENT_WRITE_REQUEST = 17, /**< Memory Write Request */ 124232812Sjmallett CVMX_L2C_EVENT_READ_REQUEST = 18, /**< Memory Read Request */ 125232812Sjmallett CVMX_L2C_EVENT_WRITE_DATA_VALID = 19, /**< Memory Write Data valid */ 126232812Sjmallett CVMX_L2C_EVENT_XMC_NOP = 20, /**< XMC NOP */ 127232812Sjmallett CVMX_L2C_EVENT_XMC_LDT = 21, /**< XMC LDT */ 128232812Sjmallett CVMX_L2C_EVENT_XMC_LDI = 22, /**< XMC LDI */ 129232812Sjmallett CVMX_L2C_EVENT_XMC_LDD = 23, /**< XMC LDD */ 130232812Sjmallett CVMX_L2C_EVENT_XMC_STF = 24, /**< XMC STF */ 131232812Sjmallett CVMX_L2C_EVENT_XMC_STT = 25, /**< XMC STT */ 132232812Sjmallett CVMX_L2C_EVENT_XMC_STP = 26, /**< XMC STP */ 133232812Sjmallett CVMX_L2C_EVENT_XMC_STC = 27, /**< XMC STC */ 134232812Sjmallett CVMX_L2C_EVENT_XMC_DWB = 28, /**< XMC DWB */ 135232812Sjmallett CVMX_L2C_EVENT_XMC_PL2 = 29, /**< XMC PL2 */ 136232812Sjmallett CVMX_L2C_EVENT_XMC_PSL1 = 30, /**< XMC PSL1 */ 137232812Sjmallett CVMX_L2C_EVENT_XMC_IOBLD = 31, /**< XMC IOBLD */ 138232812Sjmallett CVMX_L2C_EVENT_XMC_IOBST = 32, /**< XMC IOBST */ 139232812Sjmallett CVMX_L2C_EVENT_XMC_IOBDMA = 33, /**< XMC IOBDMA */ 140232812Sjmallett CVMX_L2C_EVENT_XMC_IOBRSP = 34, /**< XMC IOBRSP */ 141232812Sjmallett CVMX_L2C_EVENT_XMC_BUS_VALID = 35, /**< XMC Bus valid (all) */ 142232812Sjmallett CVMX_L2C_EVENT_XMC_MEM_DATA = 36, /**< XMC Bus valid (DST=L2C) Memory */ 143232812Sjmallett CVMX_L2C_EVENT_XMC_REFL_DATA = 37, /**< XMC Bus valid (DST=IOB) REFL Data */ 144232812Sjmallett CVMX_L2C_EVENT_XMC_IOBRSP_DATA = 38, /**< XMC Bus valid (DST=PP) IOBRSP Data */ 145232812Sjmallett CVMX_L2C_EVENT_RSC_NOP = 39, /**< RSC NOP */ 146232812Sjmallett CVMX_L2C_EVENT_RSC_STDN = 40, /**< RSC STDN */ 147232812Sjmallett CVMX_L2C_EVENT_RSC_FILL = 41, /**< RSC FILL */ 148232812Sjmallett CVMX_L2C_EVENT_RSC_REFL = 42, /**< RSC REFL */ 149232812Sjmallett CVMX_L2C_EVENT_RSC_STIN = 43, /**< RSC STIN */ 150232812Sjmallett CVMX_L2C_EVENT_RSC_SCIN = 44, /**< RSC SCIN */ 151232812Sjmallett CVMX_L2C_EVENT_RSC_SCFL = 45, /**< RSC SCFL */ 152232812Sjmallett CVMX_L2C_EVENT_RSC_SCDN = 46, /**< RSC SCDN */ 153232812Sjmallett CVMX_L2C_EVENT_RSC_DATA_VALID = 47, /**< RSC Data Valid */ 154232812Sjmallett CVMX_L2C_EVENT_RSC_VALID_FILL = 48, /**< RSC Data Valid (FILL) */ 155232812Sjmallett CVMX_L2C_EVENT_RSC_VALID_STRSP = 49, /**< RSC Data Valid (STRSP) */ 156232812Sjmallett CVMX_L2C_EVENT_RSC_VALID_REFL = 50, /**< RSC Data Valid (REFL) */ 157232812Sjmallett CVMX_L2C_EVENT_LRF_REQ = 51, /**< LRF-REQ (LFB-NQ) */ 158232812Sjmallett CVMX_L2C_EVENT_DT_RD_ALLOC = 52, /**< DT RD-ALLOC */ 159232812Sjmallett CVMX_L2C_EVENT_DT_WR_INVAL = 53, /**< DT WR-INVAL */ 160232812Sjmallett CVMX_L2C_EVENT_MAX 161232812Sjmallett}; 162232812Sjmalletttypedef enum cvmx_l2c_event cvmx_l2c_event_t; 163210284Sjmallett 164215990Sjmallett/* L2C Performance Counter events for Octeon2. */ 165232812Sjmallettenum cvmx_l2c_tad_event { 166232812Sjmallett CVMX_L2C_TAD_EVENT_NONE = 0, /* None */ 167232812Sjmallett CVMX_L2C_TAD_EVENT_TAG_HIT = 1, /* L2 Tag Hit */ 168232812Sjmallett CVMX_L2C_TAD_EVENT_TAG_MISS = 2, /* L2 Tag Miss */ 169232812Sjmallett CVMX_L2C_TAD_EVENT_TAG_NOALLOC = 3, /* L2 Tag NoAlloc (forced no-allocate) */ 170232812Sjmallett CVMX_L2C_TAD_EVENT_TAG_VICTIM = 4, /* L2 Tag Victim */ 171232812Sjmallett CVMX_L2C_TAD_EVENT_SC_FAIL = 5, /* SC Fail */ 172232812Sjmallett CVMX_L2C_TAD_EVENT_SC_PASS = 6, /* SC Pass */ 173232812Sjmallett CVMX_L2C_TAD_EVENT_LFB_VALID = 7, /* LFB Occupancy (each cycle adds \# of LFBs valid) */ 174232812Sjmallett CVMX_L2C_TAD_EVENT_LFB_WAIT_LFB = 8, /* LFB Wait LFB (each cycle adds \# LFBs waiting for other LFBs) */ 175232812Sjmallett CVMX_L2C_TAD_EVENT_LFB_WAIT_VAB = 9, /* LFB Wait VAB (each cycle adds \# LFBs waiting for VAB) */ 176232812Sjmallett CVMX_L2C_TAD_EVENT_QUAD0_INDEX = 128, /* Quad 0 index bus inuse */ 177232812Sjmallett CVMX_L2C_TAD_EVENT_QUAD0_READ = 129, /* Quad 0 read data bus inuse */ 178232812Sjmallett CVMX_L2C_TAD_EVENT_QUAD0_BANK = 130, /* Quad 0 \# banks inuse (0-4/cycle) */ 179232812Sjmallett CVMX_L2C_TAD_EVENT_QUAD0_WDAT = 131, /* Quad 0 wdat flops inuse (0-4/cycle) */ 180232812Sjmallett CVMX_L2C_TAD_EVENT_QUAD1_INDEX = 144, /* Quad 1 index bus inuse */ 181232812Sjmallett CVMX_L2C_TAD_EVENT_QUAD1_READ = 145, /* Quad 1 read data bus inuse */ 182232812Sjmallett CVMX_L2C_TAD_EVENT_QUAD1_BANK = 146, /* Quad 1 \# banks inuse (0-4/cycle) */ 183232812Sjmallett CVMX_L2C_TAD_EVENT_QUAD1_WDAT = 147, /* Quad 1 wdat flops inuse (0-4/cycle) */ 184232812Sjmallett CVMX_L2C_TAD_EVENT_QUAD2_INDEX = 160, /* Quad 2 index bus inuse */ 185232812Sjmallett CVMX_L2C_TAD_EVENT_QUAD2_READ = 161, /* Quad 2 read data bus inuse */ 186232812Sjmallett CVMX_L2C_TAD_EVENT_QUAD2_BANK = 162, /* Quad 2 \# banks inuse (0-4/cycle) */ 187232812Sjmallett CVMX_L2C_TAD_EVENT_QUAD2_WDAT = 163, /* Quad 2 wdat flops inuse (0-4/cycle) */ 188232812Sjmallett CVMX_L2C_TAD_EVENT_QUAD3_INDEX = 176, /* Quad 3 index bus inuse */ 189232812Sjmallett CVMX_L2C_TAD_EVENT_QUAD3_READ = 177, /* Quad 3 read data bus inuse */ 190232812Sjmallett CVMX_L2C_TAD_EVENT_QUAD3_BANK = 178, /* Quad 3 \# banks inuse (0-4/cycle) */ 191232812Sjmallett CVMX_L2C_TAD_EVENT_QUAD3_WDAT = 179, /* Quad 3 wdat flops inuse (0-4/cycle) */ 192232812Sjmallett CVMX_L2C_TAD_EVENT_MAX 193232812Sjmallett}; 194232812Sjmalletttypedef enum cvmx_l2c_tad_event cvmx_l2c_tad_event_t; 195215990Sjmallett 196210284Sjmallett/** 197210284Sjmallett * Configure one of the four L2 Cache performance counters to capture event 198210284Sjmallett * occurences. 199210284Sjmallett * 200210284Sjmallett * @param counter The counter to configure. Range 0..3. 201210284Sjmallett * @param event The type of L2 Cache event occurrence to count. 202210284Sjmallett * @param clear_on_read When asserted, any read of the performance counter 203210284Sjmallett * clears the counter. 204210284Sjmallett * 205210284Sjmallett * @note The routine does not clear the counter. 206210284Sjmallett */ 207215990Sjmallettvoid cvmx_l2c_config_perf(uint32_t counter, cvmx_l2c_event_t event, uint32_t clear_on_read); 208215990Sjmallett 209210284Sjmallett/** 210210284Sjmallett * Read the given L2 Cache performance counter. The counter must be configured 211210284Sjmallett * before reading, but this routine does not enforce this requirement. 212210284Sjmallett * 213210284Sjmallett * @param counter The counter to configure. Range 0..3. 214210284Sjmallett * 215210284Sjmallett * @return The current counter value. 216210284Sjmallett */ 217210284Sjmallettuint64_t cvmx_l2c_read_perf(uint32_t counter); 218210284Sjmallett 219210284Sjmallett/** 220210284Sjmallett * Return the L2 Cache way partitioning for a given core. 221210284Sjmallett * 222210284Sjmallett * @param core The core processor of interest. 223210284Sjmallett * 224210284Sjmallett * @return The mask specifying the partitioning. 0 bits in mask indicates 225210284Sjmallett * the cache 'ways' that a core can evict from. 226210284Sjmallett * -1 on error 227210284Sjmallett */ 228210284Sjmallettint cvmx_l2c_get_core_way_partition(uint32_t core); 229210284Sjmallett 230210284Sjmallett/** 231210284Sjmallett * Partitions the L2 cache for a core 232210284Sjmallett * 233232812Sjmallett * @param core The core that the partitioning applies to. 234232812Sjmallett * @param mask The partitioning of the ways expressed as a binary 235232812Sjmallett * mask. A 0 bit allows the core to evict cache lines from 236232812Sjmallett * a way, while a 1 bit blocks the core from evicting any 237232812Sjmallett * lines from that way. There must be at least one allowed 238232812Sjmallett * way (0 bit) in the mask. 239210284Sjmallett * 240232812Sjmallett 241232812Sjmallett * @note If any ways are blocked for all cores and the HW blocks, then 242232812Sjmallett * those ways will never have any cache lines evicted from them. 243232812Sjmallett * All cores and the hardware blocks are free to read from all 244232812Sjmallett * ways regardless of the partitioning. 245210284Sjmallett */ 246210284Sjmallettint cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask); 247210284Sjmallett 248210284Sjmallett/** 249210284Sjmallett * Return the L2 Cache way partitioning for the hw blocks. 250210284Sjmallett * 251210284Sjmallett * @return The mask specifying the reserved way. 0 bits in mask indicates 252210284Sjmallett * the cache 'ways' that a core can evict from. 253210284Sjmallett * -1 on error 254210284Sjmallett */ 255210284Sjmallettint cvmx_l2c_get_hw_way_partition(void); 256210284Sjmallett 257210284Sjmallett/** 258210284Sjmallett * Partitions the L2 cache for the hardware blocks. 259210284Sjmallett * 260232812Sjmallett * @param mask The partitioning of the ways expressed as a binary 261232812Sjmallett * mask. A 0 bit allows the core to evict cache lines from 262232812Sjmallett * a way, while a 1 bit blocks the core from evicting any 263232812Sjmallett * lines from that way. There must be at least one allowed 264232812Sjmallett * way (0 bit) in the mask. 265210284Sjmallett * 266232812Sjmallett 267232812Sjmallett * @note If any ways are blocked for all cores and the HW blocks, then 268232812Sjmallett * those ways will never have any cache lines evicted from them. 269232812Sjmallett * All cores and the hardware blocks are free to read from all 270232812Sjmallett * ways regardless of the partitioning. 271210284Sjmallett */ 272210284Sjmallettint cvmx_l2c_set_hw_way_partition(uint32_t mask); 273210284Sjmallett 274210284Sjmallett 275210284Sjmallett/** 276232812Sjmallett * Return the L2 Cache way partitioning for the second set of hw blocks. 277232812Sjmallett * 278232812Sjmallett * @return The mask specifying the reserved way. 0 bits in mask indicates 279232812Sjmallett * the cache 'ways' that a core can evict from. 280232812Sjmallett * -1 on error 281232812Sjmallett */ 282232812Sjmallettint cvmx_l2c_get_hw_way_partition2(void); 283232812Sjmallett 284232812Sjmallett/** 285232812Sjmallett * Partitions the L2 cache for the second set of blocks. 286232812Sjmallett * 287232812Sjmallett * @param mask The partitioning of the ways expressed as a binary 288232812Sjmallett * mask. A 0 bit allows the core to evict cache lines from 289232812Sjmallett * a way, while a 1 bit blocks the core from evicting any 290232812Sjmallett * lines from that way. There must be at least one allowed 291232812Sjmallett * way (0 bit) in the mask. 292232812Sjmallett * 293232812Sjmallett 294232812Sjmallett * @note If any ways are blocked for all cores and the HW blocks, then 295232812Sjmallett * those ways will never have any cache lines evicted from them. 296232812Sjmallett * All cores and the hardware blocks are free to read from all 297232812Sjmallett * ways regardless of the partitioning. 298232812Sjmallett */ 299232812Sjmallettint cvmx_l2c_set_hw_way_partition2(uint32_t mask); 300232812Sjmallett 301232812Sjmallett/** 302210284Sjmallett * Locks a line in the L2 cache at the specified physical address 303210284Sjmallett * 304210284Sjmallett * @param addr physical address of line to lock 305210284Sjmallett * 306210284Sjmallett * @return 0 on success, 307210284Sjmallett * 1 if line not locked. 308210284Sjmallett */ 309210284Sjmallettint cvmx_l2c_lock_line(uint64_t addr); 310210284Sjmallett 311210284Sjmallett/** 312210284Sjmallett * Locks a specified memory region in the L2 cache. 313210284Sjmallett * 314210284Sjmallett * Note that if not all lines can be locked, that means that all 315210284Sjmallett * but one of the ways (associations) available to the locking 316210284Sjmallett * core are locked. Having only 1 association available for 317210284Sjmallett * normal caching may have a significant adverse affect on performance. 318210284Sjmallett * Care should be taken to ensure that enough of the L2 cache is left 319210284Sjmallett * unlocked to allow for normal caching of DRAM. 320210284Sjmallett * 321210284Sjmallett * @param start Physical address of the start of the region to lock 322210284Sjmallett * @param len Length (in bytes) of region to lock 323210284Sjmallett * 324210284Sjmallett * @return Number of requested lines that where not locked. 325210284Sjmallett * 0 on success (all locked) 326210284Sjmallett */ 327210284Sjmallettint cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len); 328210284Sjmallett 329210284Sjmallett 330210284Sjmallett/** 331210284Sjmallett * Unlock and flush a cache line from the L2 cache. 332210284Sjmallett * IMPORTANT: Must only be run by one core at a time due to use 333210284Sjmallett * of L2C debug features. 334210284Sjmallett * Note that this function will flush a matching but unlocked cache line. 335210284Sjmallett * (If address is not in L2, no lines are flushed.) 336210284Sjmallett * 337210284Sjmallett * @param address Physical address to unlock 338210284Sjmallett * 339210284Sjmallett * @return 0: line not unlocked 340210284Sjmallett * 1: line unlocked 341210284Sjmallett */ 342210284Sjmallettint cvmx_l2c_unlock_line(uint64_t address); 343210284Sjmallett 344210284Sjmallett/** 345210284Sjmallett * Unlocks a region of memory that is locked in the L2 cache 346210284Sjmallett * 347210284Sjmallett * @param start start physical address 348210284Sjmallett * @param len length (in bytes) to unlock 349210284Sjmallett * 350210284Sjmallett * @return Number of locked lines that the call unlocked 351210284Sjmallett */ 352210284Sjmallettint cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len); 353210284Sjmallett 354210284Sjmallett 355232812Sjmallett/** 356232812Sjmallett * Read the L2 controller tag for a given location in L2 357232812Sjmallett * 358232812Sjmallett * @param association 359232812Sjmallett * Which association to read line from 360232812Sjmallett * @param index Which way to read from. 361232812Sjmallett * 362232812Sjmallett * @return l2c tag structure for line requested. 363232812Sjmallett * 364232812Sjmallett * NOTE: This function is deprecated and cannot be used on devices with 365232812Sjmallett * multiple L2C interfaces such as the OCTEON CN68XX. 366232812Sjmallett * Please use cvmx_l2c_get_tag_v2 instead. 367232812Sjmallett */ 368232812Sjmallettcvmx_l2c_tag_t cvmx_l2c_get_tag(uint32_t association, uint32_t index) 369232812Sjmallett __attribute__ ((deprecated)); 370210284Sjmallett 371210284Sjmallett/** 372210284Sjmallett * Read the L2 controller tag for a given location in L2 373210284Sjmallett * 374210284Sjmallett * @param association 375210284Sjmallett * Which association to read line from 376210284Sjmallett * @param index Which way to read from. 377232812Sjmallett * 378232812Sjmallett * @param tad Which TAD to read from, set to 0 except on OCTEON CN68XX. 379210284Sjmallett * 380210284Sjmallett * @return l2c tag structure for line requested. 381210284Sjmallett */ 382232812Sjmallettcvmx_l2c_tag_t cvmx_l2c_get_tag_v2(uint32_t association, uint32_t index, uint32_t tad); 383210284Sjmallett 384232812Sjmallett/** 385232812Sjmallett * Find the TAD for the specified address 386232812Sjmallett * 387232812Sjmallett * @param addr physical address to get TAD for 388232812Sjmallett * 389232812Sjmallett * @return TAD number for address. 390232812Sjmallett */ 391232812Sjmallettint cvmx_l2c_address_to_tad(uint64_t addr); 392210284Sjmallett 393210284Sjmallett/** 394210284Sjmallett * Returns the cache index for a given physical address 395210284Sjmallett * 396210284Sjmallett * @param addr physical address 397210284Sjmallett * 398210284Sjmallett * @return L2 cache index 399210284Sjmallett */ 400210284Sjmallettuint32_t cvmx_l2c_address_to_index (uint64_t addr); 401210284Sjmallett 402232812Sjmallett/** 403232812Sjmallett * Returns the L2 tag that will be used for the given physical address 404232812Sjmallett * 405232812Sjmallett * @param addr physical address 406232812Sjmallett * @return L2 cache tag. Addreses in the LMC hole are not valid. 407232812Sjmallett * Returns 0xFFFFFFFF if the address specified is in the LMC hole. 408232812Sjmallett */ 409232812Sjmallettuint32_t cvmx_l2c_v2_address_to_tag(uint64_t addr); 410210284Sjmallett 411210284Sjmallett/** 412210284Sjmallett * Flushes (and unlocks) the entire L2 cache. 413210284Sjmallett * IMPORTANT: Must only be run by one core at a time due to use 414210284Sjmallett * of L2C debug features. 415210284Sjmallett */ 416210284Sjmallettvoid cvmx_l2c_flush(void); 417210284Sjmallett 418210284Sjmallett/** 419210284Sjmallett * 420210284Sjmallett * @return Returns the size of the L2 cache in bytes, 421210284Sjmallett * -1 on error (unrecognized model) 422210284Sjmallett */ 423210284Sjmallettint cvmx_l2c_get_cache_size_bytes(void); 424210284Sjmallett 425210284Sjmallett/** 426210284Sjmallett * Return the number of sets in the L2 Cache 427210284Sjmallett * 428210284Sjmallett * @return 429210284Sjmallett */ 430210284Sjmallettint cvmx_l2c_get_num_sets(void); 431210284Sjmallett 432210284Sjmallett/** 433210284Sjmallett * Return log base 2 of the number of sets in the L2 cache 434210284Sjmallett * @return 435210284Sjmallett */ 436210284Sjmallettint cvmx_l2c_get_set_bits(void); 437210284Sjmallett/** 438210284Sjmallett * Return the number of associations in the L2 Cache 439210284Sjmallett * 440210284Sjmallett * @return 441210284Sjmallett */ 442210284Sjmallettint cvmx_l2c_get_num_assoc(void); 443210284Sjmallett 444210284Sjmallett/** 445210284Sjmallett * Flush a line from the L2 cache 446210284Sjmallett * This should only be called from one core at a time, as this routine 447210284Sjmallett * sets the core to the 'debug' core in order to flush the line. 448210284Sjmallett * 449210284Sjmallett * @param assoc Association (or way) to flush 450210284Sjmallett * @param index Index to flush 451210284Sjmallett */ 452210284Sjmallettvoid cvmx_l2c_flush_line(uint32_t assoc, uint32_t index); 453210284Sjmallett 454232812Sjmallett/** 455232812Sjmallett * Initialize the BIG address in L2C+DRAM to generate proper error 456232812Sjmallett * on reading/writing to an non-existant memory location. 457232812Sjmallett * 458232812Sjmallett * @param mem_size Amount of DRAM configured in MB. 459232812Sjmallett * @param mode Allow/Disallow reporting errors L2C_INT_SUM[BIGRD,BIGWR]. 460232812Sjmallett */ 461232812Sjmallettvoid cvmx_l2c_set_big_size(uint64_t mem_size, int mode); 462232812Sjmallett 463232812Sjmallett#if !defined(CVMX_BUILD_FOR_LINUX_HOST) && !defined(CVMX_BUILD_FOR_LINUX_KERNEL) 464232812Sjmallett 465215990Sjmallett/* 466215990Sjmallett * Set maxium number of Virtual IDS allowed in a machine. 467215990Sjmallett * 468215990Sjmallett * @param nvid Number of virtial ids allowed in a machine. 469215990Sjmallett * @return Return 0 on success or -1 on failure. 470215990Sjmallett */ 471215990Sjmallettint cvmx_l2c_vrt_set_max_virtids(int nvid); 472215990Sjmallett 473215990Sjmallett/** 474215990Sjmallett * Get maxium number of virtual IDs allowed in a machine. 475215990Sjmallett * 476215990Sjmallett * @return Return number of virtual machine IDs. Return -1 on failure. 477215990Sjmallett */ 478215990Sjmallettint cvmx_l2c_vrt_get_max_virtids(void); 479215990Sjmallett 480215990Sjmallett/** 481215990Sjmallett * Set the maxium size of memory space to be allocated for virtualization. 482215990Sjmallett * 483215990Sjmallett * @param memsz Size of the virtual memory in GB 484215990Sjmallett * @return Return 0 on success or -1 on failure. 485215990Sjmallett */ 486215990Sjmallettint cvmx_l2c_vrt_set_max_memsz(int memsz); 487215990Sjmallett 488215990Sjmallett/** 489215990Sjmallett * Set a Virtual ID to a set of cores. 490215990Sjmallett * 491215990Sjmallett * @param virtid Assign virtid to a set of cores. 492215990Sjmallett * @param coremask The group of cores to assign a unique virtual id. 493215990Sjmallett * @return Return 0 on success, otherwise -1. 494215990Sjmallett */ 495215990Sjmallettint cvmx_l2c_vrt_assign_virtid(int virtid, uint32_t coremask); 496215990Sjmallett 497215990Sjmallett/** 498215990Sjmallett * Remove a virt id assigned to a set of cores. Update the virtid mask and 499215990Sjmallett * virtid stored for each core. 500215990Sjmallett * 501215990Sjmallett * @param coremask the group of cores whose virtual id is removed. 502215990Sjmallett */ 503215990Sjmallettvoid cvmx_l2c_vrt_remove_virtid(int virtid); 504215990Sjmallett 505215990Sjmallett/** 506215990Sjmallett * Block a memory region to be updated by a set of virtids. 507215990Sjmallett * 508215990Sjmallett * @param start_addr Starting address of memory region 509215990Sjmallett * @param size Size of the memory to protect 510215990Sjmallett * @param virtid_mask Virtual ID to use 511215990Sjmallett * @param mode Allow/Disallow write access 512215990Sjmallett * = 0, Allow write access by virtid 513215990Sjmallett * = 1, Disallow write access by virtid 514215990Sjmallett */ 515215990Sjmallettint cvmx_l2c_vrt_memprotect(uint64_t start_addr, int size, int virtid, int mode); 516215990Sjmallett 517215990Sjmallett/** 518215990Sjmallett * Enable virtualization. 519215990Sjmallett */ 520215990Sjmallettvoid cvmx_l2c_vrt_enable(int mode); 521215990Sjmallett 522215990Sjmallett/** 523215990Sjmallett * Disable virtualization. 524215990Sjmallett */ 525215990Sjmallettvoid cvmx_l2c_vrt_disable(void); 526215990Sjmallett 527232812Sjmallett#endif /* CVMX_BUILD_FOR_LINUX_HOST */ 528232812Sjmallett 529210284Sjmallett#endif /* __CVMX_L2C_H__ */ 530