cvmx-l2c.h revision 210284
1210284Sjmallett/***********************license start*************** 2210284Sjmallett * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights 3210284Sjmallett * reserved. 4210284Sjmallett * 5210284Sjmallett * 6210284Sjmallett * Redistribution and use in source and binary forms, with or without 7210284Sjmallett * modification, are permitted provided that the following conditions are 8210284Sjmallett * met: 9210284Sjmallett * 10210284Sjmallett * * Redistributions of source code must retain the above copyright 11210284Sjmallett * notice, this list of conditions and the following disclaimer. 12210284Sjmallett * 13210284Sjmallett * * Redistributions in binary form must reproduce the above 14210284Sjmallett * copyright notice, this list of conditions and the following 15210284Sjmallett * disclaimer in the documentation and/or other materials provided 16210284Sjmallett * with the distribution. 17210284Sjmallett * 18210284Sjmallett * * Neither the name of Cavium Networks nor the names of 19210284Sjmallett * its contributors may be used to endorse or promote products 20210284Sjmallett * derived from this software without specific prior written 21210284Sjmallett * permission. 22210284Sjmallett * 23210284Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 24210284Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS 25210284Sjmallett * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH 26210284Sjmallett * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY 27210284Sjmallett * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT 28210284Sjmallett * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES 29210284Sjmallett * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR 30210284Sjmallett * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET 31210284Sjmallett * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT 32210284Sjmallett * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 33210284Sjmallett * 34210284Sjmallett * 35210284Sjmallett * For any questions regarding licensing please contact marketing@caviumnetworks.com 36210284Sjmallett * 37210284Sjmallett ***********************license end**************************************/ 38210284Sjmallett 39210284Sjmallett 40210284Sjmallett 41210284Sjmallett 42210284Sjmallett 43210284Sjmallett 44210284Sjmallett/** 45210284Sjmallett * @file 46210284Sjmallett * 47210284Sjmallett * Interface to the Level 2 Cache (L2C) control, measurement, and debugging 48210284Sjmallett * facilities. 49210284Sjmallett * 50210284Sjmallett * <hr>$Revision: 41586 $<hr> 51210284Sjmallett * 52210284Sjmallett */ 53210284Sjmallett 54210284Sjmallett#ifndef __CVMX_L2C_H__ 55210284Sjmallett#define __CVMX_L2C_H__ 56210284Sjmallett 57210284Sjmallett#define CVMX_L2_ASSOC cvmx_l2c_get_num_assoc() /* Deprecated macro, use function */ 58210284Sjmallett#define CVMX_L2_SET_BITS cvmx_l2c_get_set_bits() /* Deprecated macro, use function */ 59210284Sjmallett#define CVMX_L2_SETS cvmx_l2c_get_num_sets() /* Deprecated macro, use function */ 60210284Sjmallett 61210284Sjmallett 62210284Sjmallett#define CVMX_L2C_IDX_ADDR_SHIFT 7 /* based on 128 byte cache line size */ 63210284Sjmallett#define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1) 64210284Sjmallett 65210284Sjmallett/* Defines for index aliasing computations */ 66210284Sjmallett#define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits()) 67210284Sjmallett#define CVMX_L2C_ALIAS_MASK (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) 68210284Sjmallett 69210284Sjmallett 70210284Sjmallett /*------------*/ 71210284Sjmallett /* TYPEDEFS */ 72210284Sjmallett /*------------*/ 73210284Sjmalletttypedef union { // L2C Tag/Data Store Debug Register 74210284Sjmallett uint64_t u64; 75210284Sjmallett struct { 76210284Sjmallett uint64_t reserved: 32, 77210284Sjmallett lfb_enum: 4, 78210284Sjmallett lfb_dmp: 1, 79210284Sjmallett ppnum: 4, 80210284Sjmallett set: 3, 81210284Sjmallett finv: 1, 82210284Sjmallett l2d: 1, 83210284Sjmallett l2t: 1; 84210284Sjmallett }; 85210284Sjmallett} cvmx_l2c_dbg; 86210284Sjmallett 87210284Sjmalletttypedef union 88210284Sjmallett{ 89210284Sjmallett uint64_t u64; 90210284Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 91210284Sjmallett struct 92210284Sjmallett { 93210284Sjmallett uint64_t reserved : 28; 94210284Sjmallett uint64_t V : 1; // Line valid 95210284Sjmallett uint64_t D : 1; // Line dirty 96210284Sjmallett uint64_t L : 1; // Line locked 97210284Sjmallett uint64_t U : 1; // Use, LRU eviction 98210284Sjmallett uint64_t addr : 32; // Phys mem (not all bits valid) 99210284Sjmallett } s; 100210284Sjmallett#endif 101210284Sjmallett} cvmx_l2c_tag_t; 102210284Sjmallett 103210284Sjmallett 104210284Sjmallett /* L2C Performance Counter events. */ 105210284Sjmalletttypedef enum 106210284Sjmallett{ 107210284Sjmallett CVMX_L2C_EVENT_CYCLES = 0, 108210284Sjmallett CVMX_L2C_EVENT_INSTRUCTION_MISS = 1, 109210284Sjmallett CVMX_L2C_EVENT_INSTRUCTION_HIT = 2, 110210284Sjmallett CVMX_L2C_EVENT_DATA_MISS = 3, 111210284Sjmallett CVMX_L2C_EVENT_DATA_HIT = 4, 112210284Sjmallett CVMX_L2C_EVENT_MISS = 5, 113210284Sjmallett CVMX_L2C_EVENT_HIT = 6, 114210284Sjmallett CVMX_L2C_EVENT_VICTIM_HIT = 7, 115210284Sjmallett CVMX_L2C_EVENT_INDEX_CONFLICT = 8, 116210284Sjmallett CVMX_L2C_EVENT_TAG_PROBE = 9, 117210284Sjmallett CVMX_L2C_EVENT_TAG_UPDATE = 10, 118210284Sjmallett CVMX_L2C_EVENT_TAG_COMPLETE = 11, 119210284Sjmallett CVMX_L2C_EVENT_TAG_DIRTY = 12, 120210284Sjmallett CVMX_L2C_EVENT_DATA_STORE_NOP = 13, 121210284Sjmallett CVMX_L2C_EVENT_DATA_STORE_READ = 14, 122210284Sjmallett CVMX_L2C_EVENT_DATA_STORE_WRITE = 15, 123210284Sjmallett CVMX_L2C_EVENT_FILL_DATA_VALID = 16, 124210284Sjmallett CVMX_L2C_EVENT_WRITE_REQUEST = 17, 125210284Sjmallett CVMX_L2C_EVENT_READ_REQUEST = 18, 126210284Sjmallett CVMX_L2C_EVENT_WRITE_DATA_VALID = 19, 127210284Sjmallett CVMX_L2C_EVENT_XMC_NOP = 20, 128210284Sjmallett CVMX_L2C_EVENT_XMC_LDT = 21, 129210284Sjmallett CVMX_L2C_EVENT_XMC_LDI = 22, 130210284Sjmallett CVMX_L2C_EVENT_XMC_LDD = 23, 131210284Sjmallett CVMX_L2C_EVENT_XMC_STF = 24, 132210284Sjmallett CVMX_L2C_EVENT_XMC_STT = 25, 133210284Sjmallett CVMX_L2C_EVENT_XMC_STP = 26, 134210284Sjmallett CVMX_L2C_EVENT_XMC_STC = 27, 135210284Sjmallett CVMX_L2C_EVENT_XMC_DWB = 28, 136210284Sjmallett CVMX_L2C_EVENT_XMC_PL2 = 29, 137210284Sjmallett CVMX_L2C_EVENT_XMC_PSL1 = 30, 138210284Sjmallett CVMX_L2C_EVENT_XMC_IOBLD = 31, 139210284Sjmallett CVMX_L2C_EVENT_XMC_IOBST = 32, 140210284Sjmallett CVMX_L2C_EVENT_XMC_IOBDMA = 33, 141210284Sjmallett CVMX_L2C_EVENT_XMC_IOBRSP = 34, 142210284Sjmallett CVMX_L2C_EVENT_XMC_BUS_VALID = 35, 143210284Sjmallett CVMX_L2C_EVENT_XMC_MEM_DATA = 36, 144210284Sjmallett CVMX_L2C_EVENT_XMC_REFL_DATA = 37, 145210284Sjmallett CVMX_L2C_EVENT_XMC_IOBRSP_DATA = 38, 146210284Sjmallett CVMX_L2C_EVENT_RSC_NOP = 39, 147210284Sjmallett CVMX_L2C_EVENT_RSC_STDN = 40, 148210284Sjmallett CVMX_L2C_EVENT_RSC_FILL = 41, 149210284Sjmallett CVMX_L2C_EVENT_RSC_REFL = 42, 150210284Sjmallett CVMX_L2C_EVENT_RSC_STIN = 43, 151210284Sjmallett CVMX_L2C_EVENT_RSC_SCIN = 44, 152210284Sjmallett CVMX_L2C_EVENT_RSC_SCFL = 45, 153210284Sjmallett CVMX_L2C_EVENT_RSC_SCDN = 46, 154210284Sjmallett CVMX_L2C_EVENT_RSC_DATA_VALID = 47, 155210284Sjmallett CVMX_L2C_EVENT_RSC_VALID_FILL = 48, 156210284Sjmallett CVMX_L2C_EVENT_RSC_VALID_STRSP = 49, 157210284Sjmallett CVMX_L2C_EVENT_RSC_VALID_REFL = 50, 158210284Sjmallett CVMX_L2C_EVENT_LRF_REQ = 51, 159210284Sjmallett CVMX_L2C_EVENT_DT_RD_ALLOC = 52, 160210284Sjmallett CVMX_L2C_EVENT_DT_WR_INVAL = 53 161210284Sjmallett} cvmx_l2c_event_t; 162210284Sjmallett 163210284Sjmallett/** 164210284Sjmallett * Configure one of the four L2 Cache performance counters to capture event 165210284Sjmallett * occurences. 166210284Sjmallett * 167210284Sjmallett * @param counter The counter to configure. Range 0..3. 168210284Sjmallett * @param event The type of L2 Cache event occurrence to count. 169210284Sjmallett * @param clear_on_read When asserted, any read of the performance counter 170210284Sjmallett * clears the counter. 171210284Sjmallett * 172210284Sjmallett * @note The routine does not clear the counter. 173210284Sjmallett */ 174210284Sjmallettvoid cvmx_l2c_config_perf(uint32_t counter, 175210284Sjmallett cvmx_l2c_event_t event, 176210284Sjmallett uint32_t clear_on_read); 177210284Sjmallett/** 178210284Sjmallett * Read the given L2 Cache performance counter. The counter must be configured 179210284Sjmallett * before reading, but this routine does not enforce this requirement. 180210284Sjmallett * 181210284Sjmallett * @param counter The counter to configure. Range 0..3. 182210284Sjmallett * 183210284Sjmallett * @return The current counter value. 184210284Sjmallett */ 185210284Sjmallettuint64_t cvmx_l2c_read_perf(uint32_t counter); 186210284Sjmallett 187210284Sjmallett/** 188210284Sjmallett * Return the L2 Cache way partitioning for a given core. 189210284Sjmallett * 190210284Sjmallett * @param core The core processor of interest. 191210284Sjmallett * 192210284Sjmallett * @return The mask specifying the partitioning. 0 bits in mask indicates 193210284Sjmallett * the cache 'ways' that a core can evict from. 194210284Sjmallett * -1 on error 195210284Sjmallett */ 196210284Sjmallettint cvmx_l2c_get_core_way_partition(uint32_t core); 197210284Sjmallett 198210284Sjmallett/** 199210284Sjmallett * Partitions the L2 cache for a core 200210284Sjmallett * 201210284Sjmallett * @param core The core that the partitioning applies to. 202210284Sjmallett * @param mask The partitioning of the ways expressed as a binary mask. A 0 bit allows the core 203210284Sjmallett * to evict cache lines from a way, while a 1 bit blocks the core from evicting any lines 204210284Sjmallett * from that way. There must be at least one allowed way (0 bit) in the mask. 205210284Sjmallett * 206210284Sjmallett * @note If any ways are blocked for all cores and the HW blocks, then those ways will never have 207210284Sjmallett * any cache lines evicted from them. All cores and the hardware blocks are free to read from 208210284Sjmallett * all ways regardless of the partitioning. 209210284Sjmallett */ 210210284Sjmallettint cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask); 211210284Sjmallett 212210284Sjmallett/** 213210284Sjmallett * Return the L2 Cache way partitioning for the hw blocks. 214210284Sjmallett * 215210284Sjmallett * @return The mask specifying the reserved way. 0 bits in mask indicates 216210284Sjmallett * the cache 'ways' that a core can evict from. 217210284Sjmallett * -1 on error 218210284Sjmallett */ 219210284Sjmallettint cvmx_l2c_get_hw_way_partition(void); 220210284Sjmallett 221210284Sjmallett/** 222210284Sjmallett * Partitions the L2 cache for the hardware blocks. 223210284Sjmallett * 224210284Sjmallett * @param mask The partitioning of the ways expressed as a binary mask. A 0 bit allows the core 225210284Sjmallett * to evict cache lines from a way, while a 1 bit blocks the core from evicting any lines 226210284Sjmallett * from that way. There must be at least one allowed way (0 bit) in the mask. 227210284Sjmallett * 228210284Sjmallett * @note If any ways are blocked for all cores and the HW blocks, then those ways will never have 229210284Sjmallett * any cache lines evicted from them. All cores and the hardware blocks are free to read from 230210284Sjmallett * all ways regardless of the partitioning. 231210284Sjmallett */ 232210284Sjmallettint cvmx_l2c_set_hw_way_partition(uint32_t mask); 233210284Sjmallett 234210284Sjmallett 235210284Sjmallett/** 236210284Sjmallett * Locks a line in the L2 cache at the specified physical address 237210284Sjmallett * 238210284Sjmallett * @param addr physical address of line to lock 239210284Sjmallett * 240210284Sjmallett * @return 0 on success, 241210284Sjmallett * 1 if line not locked. 242210284Sjmallett */ 243210284Sjmallettint cvmx_l2c_lock_line(uint64_t addr); 244210284Sjmallett 245210284Sjmallett/** 246210284Sjmallett * Locks a specified memory region in the L2 cache. 247210284Sjmallett * 248210284Sjmallett * Note that if not all lines can be locked, that means that all 249210284Sjmallett * but one of the ways (associations) available to the locking 250210284Sjmallett * core are locked. Having only 1 association available for 251210284Sjmallett * normal caching may have a significant adverse affect on performance. 252210284Sjmallett * Care should be taken to ensure that enough of the L2 cache is left 253210284Sjmallett * unlocked to allow for normal caching of DRAM. 254210284Sjmallett * 255210284Sjmallett * @param start Physical address of the start of the region to lock 256210284Sjmallett * @param len Length (in bytes) of region to lock 257210284Sjmallett * 258210284Sjmallett * @return Number of requested lines that where not locked. 259210284Sjmallett * 0 on success (all locked) 260210284Sjmallett */ 261210284Sjmallettint cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len); 262210284Sjmallett 263210284Sjmallett 264210284Sjmallett/** 265210284Sjmallett * Unlock and flush a cache line from the L2 cache. 266210284Sjmallett * IMPORTANT: Must only be run by one core at a time due to use 267210284Sjmallett * of L2C debug features. 268210284Sjmallett * Note that this function will flush a matching but unlocked cache line. 269210284Sjmallett * (If address is not in L2, no lines are flushed.) 270210284Sjmallett * 271210284Sjmallett * @param address Physical address to unlock 272210284Sjmallett * 273210284Sjmallett * @return 0: line not unlocked 274210284Sjmallett * 1: line unlocked 275210284Sjmallett */ 276210284Sjmallettint cvmx_l2c_unlock_line(uint64_t address); 277210284Sjmallett 278210284Sjmallett/** 279210284Sjmallett * Unlocks a region of memory that is locked in the L2 cache 280210284Sjmallett * 281210284Sjmallett * @param start start physical address 282210284Sjmallett * @param len length (in bytes) to unlock 283210284Sjmallett * 284210284Sjmallett * @return Number of locked lines that the call unlocked 285210284Sjmallett */ 286210284Sjmallettint cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len); 287210284Sjmallett 288210284Sjmallett 289210284Sjmallett 290210284Sjmallett 291210284Sjmallett/** 292210284Sjmallett * Read the L2 controller tag for a given location in L2 293210284Sjmallett * 294210284Sjmallett * @param association 295210284Sjmallett * Which association to read line from 296210284Sjmallett * @param index Which way to read from. 297210284Sjmallett * 298210284Sjmallett * @return l2c tag structure for line requested. 299210284Sjmallett */ 300210284Sjmallettcvmx_l2c_tag_t cvmx_l2c_get_tag(uint32_t association, uint32_t index); 301210284Sjmallett 302210284Sjmallett/* Wrapper around deprecated old function name */ 303210284Sjmallettstatic inline cvmx_l2c_tag_t cvmx_get_l2c_tag(uint32_t association, uint32_t index) 304210284Sjmallett{ 305210284Sjmallett return cvmx_l2c_get_tag(association, index); 306210284Sjmallett} 307210284Sjmallett 308210284Sjmallett 309210284Sjmallett/** 310210284Sjmallett * Returns the cache index for a given physical address 311210284Sjmallett * 312210284Sjmallett * @param addr physical address 313210284Sjmallett * 314210284Sjmallett * @return L2 cache index 315210284Sjmallett */ 316210284Sjmallettuint32_t cvmx_l2c_address_to_index (uint64_t addr); 317210284Sjmallett 318210284Sjmallett 319210284Sjmallett/** 320210284Sjmallett * Flushes (and unlocks) the entire L2 cache. 321210284Sjmallett * IMPORTANT: Must only be run by one core at a time due to use 322210284Sjmallett * of L2C debug features. 323210284Sjmallett */ 324210284Sjmallettvoid cvmx_l2c_flush(void); 325210284Sjmallett 326210284Sjmallett 327210284Sjmallett 328210284Sjmallett/** 329210284Sjmallett * 330210284Sjmallett * @return Returns the size of the L2 cache in bytes, 331210284Sjmallett * -1 on error (unrecognized model) 332210284Sjmallett */ 333210284Sjmallettint cvmx_l2c_get_cache_size_bytes(void); 334210284Sjmallett 335210284Sjmallett/** 336210284Sjmallett * Return the number of sets in the L2 Cache 337210284Sjmallett * 338210284Sjmallett * @return 339210284Sjmallett */ 340210284Sjmallettint cvmx_l2c_get_num_sets(void); 341210284Sjmallett 342210284Sjmallett/** 343210284Sjmallett * Return log base 2 of the number of sets in the L2 cache 344210284Sjmallett * @return 345210284Sjmallett */ 346210284Sjmallettint cvmx_l2c_get_set_bits(void); 347210284Sjmallett/** 348210284Sjmallett * Return the number of associations in the L2 Cache 349210284Sjmallett * 350210284Sjmallett * @return 351210284Sjmallett */ 352210284Sjmallettint cvmx_l2c_get_num_assoc(void); 353210284Sjmallett 354210284Sjmallett/** 355210284Sjmallett * Flush a line from the L2 cache 356210284Sjmallett * This should only be called from one core at a time, as this routine 357210284Sjmallett * sets the core to the 'debug' core in order to flush the line. 358210284Sjmallett * 359210284Sjmallett * @param assoc Association (or way) to flush 360210284Sjmallett * @param index Index to flush 361210284Sjmallett */ 362210284Sjmallettvoid cvmx_l2c_flush_line(uint32_t assoc, uint32_t index); 363210284Sjmallett 364210284Sjmallett#endif /* __CVMX_L2C_H__ */ 365