1210284Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights 3215990Sjmallett * reserved. 4210284Sjmallett * 5210284Sjmallett * 6215990Sjmallett * Redistribution and use in source and binary forms, with or without 7215990Sjmallett * modification, are permitted provided that the following conditions are 8215990Sjmallett * met: 9210284Sjmallett * 10215990Sjmallett * * Redistributions of source code must retain the above copyright 11215990Sjmallett * notice, this list of conditions and the following disclaimer. 12210284Sjmallett * 13215990Sjmallett * * Redistributions in binary form must reproduce the above 14215990Sjmallett * copyright notice, this list of conditions and the following 15215990Sjmallett * disclaimer in the documentation and/or other materials provided 16215990Sjmallett * with the distribution. 17215990Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215990Sjmallett * its contributors may be used to endorse or promote products 20215990Sjmallett * derived from this software without specific prior written 21215990Sjmallett * permission. 22215990Sjmallett 23215990Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215990Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215990Sjmallett * regulations, and may be subject to export or import regulations in other 26215990Sjmallett * countries. 27215990Sjmallett 28215990Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215990Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215990Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215990Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215990Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215990Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215990Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215990Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215990Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38210284Sjmallett ***********************license end**************************************/ 39210284Sjmallett 40210284Sjmallett 41210284Sjmallett 42210284Sjmallett 43210284Sjmallett 44210284Sjmallett 45215990Sjmallett 46210284Sjmallett/** 47210284Sjmallett * @file 48210284Sjmallett * 49210284Sjmallett * Functions and typedefs for using Octeon in HiGig/HiGig+/HiGig2 mode over 50210284Sjmallett * XAUI. 51210284Sjmallett * 52232812Sjmallett * <hr>$Revision: 70030 $<hr> 53210284Sjmallett */ 54210284Sjmallett 55210284Sjmallett#ifndef __CVMX_HIGIG_H__ 56210284Sjmallett#define __CVMX_HIGIG_H__ 57210284Sjmallett#include "cvmx-wqe.h" 58232812Sjmallett#include "cvmx-helper.h" 59232812Sjmallett#include "cvmx-helper-util.h" 60210284Sjmallett 61210284Sjmallett#ifdef __cplusplus 62210284Sjmallettextern "C" { 63210284Sjmallett#endif 64210284Sjmallett 65210284Sjmalletttypedef struct 66210284Sjmallett{ 67210284Sjmallett union 68210284Sjmallett { 69210284Sjmallett uint32_t u32; 70210284Sjmallett struct 71210284Sjmallett { 72210284Sjmallett uint32_t start : 8; /**< 8-bits of Preamble indicating start of frame */ 73210284Sjmallett uint32_t hgi : 2; /**< HiGig interface format indicator 74210284Sjmallett 00 = Reserved 75210284Sjmallett 01 = Pure preamble - IEEE standard framing of 10GE 76210284Sjmallett 10 = XGS header - framing based on XGS family definition In this 77210284Sjmallett format, the default length of the header is 12 bytes and additional 78210284Sjmallett bytes are indicated by the HDR_EXT_LEN field 79210284Sjmallett 11 = Reserved */ 80232812Sjmallett uint32_t cng_high : 1; /**< Congestion Bit High flag */ 81232812Sjmallett uint32_t hdr_ext_len : 3; /**< This field is valid only if the HGI field is a b'10' and it indicates the extension 82232812Sjmallett to the standard 12-bytes of XGS HiGig header. Each unit represents 4 83232812Sjmallett bytes, giving a total of 16 additional extension bytes. Value of b'101', b'110' 84232812Sjmallett and b'111' are reserved. For HGI field value of b'01' this field should be 85232812Sjmallett b'01'. For all other values of HGI it is don't care. */ 86232812Sjmallett uint32_t src_modid_6 : 1; /**< This field is valid only if the HGI field is a b'10' and it represents Bit 6 of 87232812Sjmallett SRC_MODID (bits 4:0 are in Byte 4 and bit 5 is in Byte 9). For HGI field 88232812Sjmallett value of b'01' this field should be b'0'. For all other values of HGI it is don't 89232812Sjmallett care. */ 90232812Sjmallett uint32_t dst_modid_6 : 1; /**< This field is valid only if the HGI field is a b'10' and it represents Bit 6 of 91232812Sjmallett DST_MODID (bits 4:0 are in Byte 7 and bit 5 is in Byte 9). ). For HGI field 92232812Sjmallett value of b'01' this field should be b'1'. For all other values of HGI it is don't 93232812Sjmallett care. */ 94210284Sjmallett uint32_t vid_high : 8; /**< 8-bits of the VLAN tag information */ 95210284Sjmallett uint32_t vid_low : 8; /**< 8 bits LSB of the VLAN tag information */ 96210284Sjmallett } s; 97210284Sjmallett } dw0; 98210284Sjmallett union 99210284Sjmallett { 100210284Sjmallett uint32_t u32; 101210284Sjmallett struct 102210284Sjmallett { 103232812Sjmallett uint32_t src_modid_low : 5; /**< Bits 4:0 of Module ID of the source module on which the packet ingress (bit 104232812Sjmallett 5 is in Byte 9 and bit 6 Is in Byte 1) */ 105210284Sjmallett uint32_t opcode : 3; /**< XGS HiGig op-code, indicating the type of packet 106210284Sjmallett 000 = Control frames used for CPU to CPU communications 107210284Sjmallett 001 = Unicast packet with destination resolved; The packet can be 108210284Sjmallett either Layer 2 unicast packet or L3 unicast packet that was 109210284Sjmallett routed in the ingress chip. 110210284Sjmallett 010 = Broadcast or unknown Unicast packet or unknown multicast, 111210284Sjmallett destined to all members of the VLAN 112210284Sjmallett 011 = L2 Multicast packet, destined to all ports of the group indicated 113210284Sjmallett in the L2MC_INDEX which is overlayed on DST_PORT/DST_MODID fields 114210284Sjmallett 100 = IP Multicast packet, destined to all ports of the group indicated 115210284Sjmallett in the IPMC_INDEX which is overlayed on DST_PORT/DST_MODID fields 116210284Sjmallett 101 = Reserved 117210284Sjmallett 110 = Reserved 118210284Sjmallett 111 = Reserved */ 119210284Sjmallett uint32_t pfm : 2; /**< Three Port Filtering Modes (0, 1, 2) used in handling registed/unregistered 120210284Sjmallett multicast (unknown L2 multicast and IPMC) packets. This field is used 121210284Sjmallett when OPCODE is 011 or 100 Semantics of PFM bits are as follows; 122210284Sjmallett For registered L2 multicast packets: 123210284Sjmallett PFM= 0 � Flood to VLAN 124210284Sjmallett PFM= 1 or 2 � Send to group members in the L2MC table 125210284Sjmallett For unregistered L2 multicast packets: 126210284Sjmallett PFM= 0 or 1 � Flood to VLAN 127210284Sjmallett PFM= 2 � Drop the packet */ 128232812Sjmallett uint32_t src_port_tgid : 6; /**< If the MSB of this field is set, then it indicates the LAG the packet ingressed 129232812Sjmallett on, else it represents the physical port the packet ingressed on. */ 130232812Sjmallett uint32_t dst_port : 5; /**< Port number of destination port on which the packet needs to egress. */ 131210284Sjmallett uint32_t priority : 3; /**< This is the internal priority of the packet. This internal priority will go through 132210284Sjmallett COS_SEL mapping registers to map to the actual MMU queues. */ 133232812Sjmallett uint32_t header_type : 2; /**< Indicates the format of the next 4 bytes of the XGS HiGig header 134232812Sjmallett 00 = Overlay 1 (default) 135232812Sjmallett 01 = Overlay 2 (Classification Tag) 136232812Sjmallett 10 = Reserved 137232812Sjmallett 11 = Reserved */ 138210284Sjmallett uint32_t cng_low : 1; /**< Semantics of CNG_HIGH and CNG_LOW are as follows: The following 139210284Sjmallett encodings are to make it backward compatible: 140232812Sjmallett [CNG_HIGH, CNG_LOW] - COLOR 141210284Sjmallett [0, 0] � Packet is green 142210284Sjmallett [0, 1] � Packet is red 143210284Sjmallett [1, 1] � Packet is yellow 144210284Sjmallett [1, 0] � Undefined */ 145232812Sjmallett uint32_t dst_modid_low : 5; /**< Bits [4-: 0] of Module ID of the destination port on which the packet needs to egress. */ 146210284Sjmallett } s; 147210284Sjmallett } dw1; 148210284Sjmallett union 149210284Sjmallett { 150210284Sjmallett uint32_t u32; 151210284Sjmallett struct 152210284Sjmallett { 153232812Sjmallett uint32_t dst_t : 1; /**< Destination Trunk: Indicates that the destination port is a member of a trunk 154232812Sjmallett group. */ 155232812Sjmallett uint32_t dst_tgid : 3; /**< Destination Trunk Group ID: Trunk group ID of the destination port. The 156232812Sjmallett DO_NOT_LEARN bit is overlaid on the second bit of this field. */ 157232812Sjmallett uint32_t ingress_tagged : 1; /**< Ingress Tagged: Indicates whether the packet was tagged when it originally 158232812Sjmallett ingressed the system. */ 159232812Sjmallett uint32_t mirror_only : 1; /**< Mirror Only: XGS 1/2 mode: Indicates that the packet was switched and only 160232812Sjmallett needs to be mirrored. */ 161232812Sjmallett uint32_t mirror_done : 1; /**< Mirroring Done: XGS1/2 mode: Indicates that the packet was mirrored and 162232812Sjmallett may still need to be switched. */ 163210284Sjmallett uint32_t mirror : 1; /**< Mirror: XGS3 mode: a mirror copy packet. XGS1/2 mode: Indicates that the 164210284Sjmallett packet was switched and only needs to be mirrored. */ 165232812Sjmallett 166232812Sjmallett uint32_t src_modid_5 : 1; /**< Source Module ID: Bit 5 of Src_ModID (bits 4:0 are in byte 4 and bit 6 is in 167232812Sjmallett byte 1) */ 168232812Sjmallett uint32_t dst_modid_5 : 1; /**< Destination Module ID: Bit 5 of Dst_ModID (bits 4:0 are in byte 7 and bit 6 169232812Sjmallett is in byte 1) */ 170232812Sjmallett uint32_t l3 : 1; /**< L3: Indicates that the packet is L3 switched */ 171210284Sjmallett uint32_t label_present : 1; /**< Label Present: Indicates that header contains a 20-bit VC label: HiGig+ 172210284Sjmallett added field. */ 173232812Sjmallett uint32_t vc_label_16_19 : 4; /**< VC Label: Bits 19:16 of VC label: HiGig+ added field */ 174210284Sjmallett uint32_t vc_label_0_15 : 16;/**< VC Label: Bits 15:0 of VC label: HiGig+ added field */ 175210284Sjmallett } o1; 176210284Sjmallett struct 177210284Sjmallett { 178210284Sjmallett uint32_t classification : 16; /**< Classification tag information from the HiGig device FFP */ 179210284Sjmallett uint32_t reserved_0_15 : 16; 180210284Sjmallett 181210284Sjmallett } o2; 182210284Sjmallett } dw2; 183210284Sjmallett} cvmx_higig_header_t; 184210284Sjmallett 185215990Sjmalletttypedef struct 186215990Sjmallett{ 187215990Sjmallett union 188215990Sjmallett { 189215990Sjmallett uint32_t u32; 190215990Sjmallett struct 191215990Sjmallett { 192215990Sjmallett uint32_t k_sop : 8; /**< The delimiter indicating the start of a packet transmission */ 193215990Sjmallett uint32_t reserved_21_23 : 3; 194215990Sjmallett uint32_t mcst : 1; /**< MCST indicates whether the packet should be unicast or 195215990Sjmallett multicast forwarded through the XGS switching fabric 196215990Sjmallett - 0: Unicast 197215990Sjmallett - 1: Mulitcast */ 198215990Sjmallett uint32_t tc : 4; /**< Traffic Class [3:0] indicates the distinctive Quality of Service (QoS) 199215990Sjmallett the switching fabric will provide when forwarding the packet 200215990Sjmallett through the fabric */ 201215990Sjmallett uint32_t dst_modid_mgid : 8; /**< When MCST=0, this field indicates the destination XGS module to 202215990Sjmallett which the packet will be delivered. When MCST=1, this field indicates 203215990Sjmallett higher order bits of the Multicast Group ID. */ 204215990Sjmallett uint32_t dst_pid_mgid : 8; /**< When MCST=0, this field indicates a port associated with the 205215990Sjmallett module indicated by the DST_MODID, through which the packet 206215990Sjmallett will exit the system. When MCST=1, this field indicates lower order 207215990Sjmallett bits of the Multicast Group ID */ 208215990Sjmallett } s; 209215990Sjmallett } dw0; 210215990Sjmallett union 211215990Sjmallett { 212215990Sjmallett uint32_t u32; 213215990Sjmallett struct 214215990Sjmallett { 215215990Sjmallett uint32_t src_modid : 8; /**< Source Module ID indicates the source XGS module from which 216215990Sjmallett the packet is originated. (It can also be used for the fabric multicast 217215990Sjmallett load balancing purpose.) */ 218215990Sjmallett uint32_t src_pid : 8; /**< Source Port ID indicates a port associated with the module 219215990Sjmallett indicated by the SRC_MODID, through which the packet has 220215990Sjmallett entered the system */ 221215990Sjmallett uint32_t lbid : 8; /**< Load Balancing ID indicates a packet flow hashing index 222215990Sjmallett computed by the ingress XGS module for statistical distribution of 223215990Sjmallett packet flows through a multipath fabric */ 224215990Sjmallett uint32_t dp : 2; /**< Drop Precedence indicates the traffic rate violation status of the 225215990Sjmallett packet measured by the ingress module. 226215990Sjmallett - 00: GREEN 227215990Sjmallett - 01: RED 228215990Sjmallett - 10: Reserved 229215990Sjmallett - 11: Yellow */ 230215990Sjmallett uint32_t reserved_3_5 : 3; 231215990Sjmallett uint32_t ppd_type : 3; /**< Packet Processing Descriptor Type 232215990Sjmallett - 000: PPD Overlay1 233215990Sjmallett - 001: PPD Overlay2 234215990Sjmallett - 010~111: Reserved */ 235215990Sjmallett } s; 236215990Sjmallett } dw1; 237215990Sjmallett union 238215990Sjmallett { 239215990Sjmallett uint32_t u32; 240215990Sjmallett struct 241215990Sjmallett { 242215990Sjmallett uint32_t dst_t : 1; /**< Destination Trunk: Indicates that the destination port is a member of a trunk 243215990Sjmallett group. */ 244215990Sjmallett uint32_t dst_tgid : 3; /**< Destination Trunk Group ID: Trunk group ID of the destination port. The 245215990Sjmallett DO_NOT_LEARN bit is overlaid on the second bit of this field. */ 246215990Sjmallett uint32_t ingress_tagged : 1; /**< Ingress Tagged: Indicates whether the packet was tagged when it originally 247215990Sjmallett ingressed the system. */ 248215990Sjmallett uint32_t mirror_only : 1; /**< Mirror Only: XGS 1/2 mode: Indicates that the packet was switched and only 249215990Sjmallett needs to be mirrored. */ 250215990Sjmallett uint32_t mirror_done : 1; /**< Mirroring Done: XGS1/2 mode: Indicates that the packet was mirrored and 251215990Sjmallett may still need to be switched. */ 252215990Sjmallett uint32_t mirror : 1; /**< Mirror: XGS3 mode: a mirror copy packet. XGS1/2 mode: Indicates that the 253215990Sjmallett packet was switched and only needs to be mirrored. */ 254215990Sjmallett uint32_t reserved_22_23 : 2; 255215990Sjmallett uint32_t l3 : 1; /**< L3: Indicates that the packet is L3 switched */ 256215990Sjmallett uint32_t label_present : 1; /**< Label Present: Indicates that header contains a 20-bit VC label: HiGig+ 257215990Sjmallett added field. */ 258215990Sjmallett uint32_t vc_label : 20; /**< Refer to the HiGig+ Architecture Specification */ 259215990Sjmallett } o1; 260215990Sjmallett struct 261215990Sjmallett { 262215990Sjmallett uint32_t classification : 16; /**< Classification tag information from the HiGig device FFP */ 263215990Sjmallett uint32_t reserved_0_15 : 16; 264215990Sjmallett } o2; 265215990Sjmallett } dw2; 266215990Sjmallett union 267215990Sjmallett { 268215990Sjmallett uint32_t u32; 269215990Sjmallett struct 270215990Sjmallett { 271215990Sjmallett uint32_t vid : 16; /**< VLAN tag information */ 272215990Sjmallett uint32_t pfm : 2; /**< Three Port Filtering Modes (0, 1, 2) used in handling registed/unregistered 273215990Sjmallett multicast (unknown L2 multicast and IPMC) packets. This field is used 274215990Sjmallett when OPCODE is 011 or 100 Semantics of PFM bits are as follows; 275215990Sjmallett For registered L2 multicast packets: 276215990Sjmallett PFM= 0 � Flood to VLAN 277215990Sjmallett PFM= 1 or 2 � Send to group members in the L2MC table 278215990Sjmallett For unregistered L2 multicast packets: 279215990Sjmallett PFM= 0 or 1 � Flood to VLAN 280215990Sjmallett PFM= 2 � Drop the packet */ 281215990Sjmallett uint32_t src_t : 1; /**< If the MSB of this field is set, then it indicates the LAG the packet ingressed 282215990Sjmallett on, else it represents the physical port the packet ingressed on. */ 283215990Sjmallett uint32_t reserved_11_12 : 2; 284215990Sjmallett uint32_t opcode : 3; /**< XGS HiGig op-code, indicating the type of packet 285215990Sjmallett 000 = Control frames used for CPU to CPU communications 286215990Sjmallett 001 = Unicast packet with destination resolved; The packet can be 287215990Sjmallett either Layer 2 unicast packet or L3 unicast packet that was 288215990Sjmallett routed in the ingress chip. 289215990Sjmallett 010 = Broadcast or unknown Unicast packet or unknown multicast, 290215990Sjmallett destined to all members of the VLAN 291215990Sjmallett 011 = L2 Multicast packet, destined to all ports of the group indicated 292215990Sjmallett in the L2MC_INDEX which is overlayed on DST_PORT/DST_MODID fields 293215990Sjmallett 100 = IP Multicast packet, destined to all ports of the group indicated 294215990Sjmallett in the IPMC_INDEX which is overlayed on DST_PORT/DST_MODID fields 295215990Sjmallett 101 = Reserved 296215990Sjmallett 110 = Reserved 297215990Sjmallett 111 = Reserved */ 298215990Sjmallett uint32_t hdr_ext_len : 3; /**< This field is valid only if the HGI field is a b'10' and it indicates the extension 299215990Sjmallett to the standard 12-bytes of XGS HiGig header. Each unit represents 4 300215990Sjmallett bytes, giving a total of 16 additional extension bytes. Value of b'101', b'110' 301215990Sjmallett and b'111' are reserved. For HGI field value of b'01' this field should be 302215990Sjmallett b'01'. For all other values of HGI it is don't care. */ 303215990Sjmallett uint32_t reserved_0_4 : 5; 304215990Sjmallett } s; 305215990Sjmallett } dw3; 306215990Sjmallett} cvmx_higig2_header_t; 307210284Sjmallett 308215990Sjmallett 309210284Sjmallett/** 310210284Sjmallett * Initialize the HiGig aspects of a XAUI interface. This function 311210284Sjmallett * should be called before the cvmx-helper generic init. 312210284Sjmallett * 313210284Sjmallett * @param interface Interface to initialize HiGig on (0-1) 314210284Sjmallett * @param enable_higig2 315210284Sjmallett * Non zero to enable HiGig2 support. Zero to support HiGig 316210284Sjmallett * and HiGig+. 317210284Sjmallett * 318210284Sjmallett * @return Zero on success, negative on failure 319210284Sjmallett */ 320210284Sjmallettstatic inline int cvmx_higig_initialize(int interface, int enable_higig2) 321210284Sjmallett{ 322210284Sjmallett cvmx_pip_prt_cfgx_t pip_prt_cfg; 323210284Sjmallett cvmx_gmxx_rxx_udd_skp_t gmx_rx_udd_skp; 324210284Sjmallett cvmx_gmxx_txx_min_pkt_t gmx_tx_min_pkt; 325210284Sjmallett cvmx_gmxx_txx_append_t gmx_tx_append; 326210284Sjmallett cvmx_gmxx_tx_ifg_t gmx_tx_ifg; 327210284Sjmallett cvmx_gmxx_tx_ovr_bp_t gmx_tx_ovr_bp; 328210284Sjmallett cvmx_gmxx_rxx_frm_ctl_t gmx_rx_frm_ctl; 329210284Sjmallett cvmx_gmxx_tx_xaui_ctl_t gmx_tx_xaui_ctl; 330232812Sjmallett int i, pknd; 331210284Sjmallett int header_size = (enable_higig2) ? 16 : 12; 332210284Sjmallett 333210284Sjmallett /* Setup PIP to handle HiGig */ 334232812Sjmallett if (octeon_has_feature(OCTEON_FEATURE_PKND)) 335232812Sjmallett pknd = cvmx_helper_get_pknd(interface, 0); 336232812Sjmallett else 337232812Sjmallett pknd = interface*16; 338232812Sjmallett pip_prt_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(pknd)); 339210284Sjmallett pip_prt_cfg.s.dsa_en = 0; 340210284Sjmallett pip_prt_cfg.s.higig_en = 1; 341210284Sjmallett pip_prt_cfg.s.hg_qos = 1; 342210284Sjmallett pip_prt_cfg.s.skip = header_size; 343232812Sjmallett cvmx_write_csr(CVMX_PIP_PRT_CFGX(pknd), pip_prt_cfg.u64); 344210284Sjmallett 345210284Sjmallett /* Setup some sample QoS defaults. These can be changed later */ 346232812Sjmallett if (!OCTEON_IS_MODEL(OCTEON_CN68XX)) 347210284Sjmallett { 348232812Sjmallett for (i=0; i<64; i++) 349232812Sjmallett { 350232812Sjmallett cvmx_pip_hg_pri_qos_t pip_hg_pri_qos; 351232812Sjmallett pip_hg_pri_qos.u64 = 0; 352232812Sjmallett pip_hg_pri_qos.s.up_qos = 1; 353232812Sjmallett pip_hg_pri_qos.s.pri = i; 354232812Sjmallett pip_hg_pri_qos.s.qos = i&7; 355232812Sjmallett cvmx_write_csr(CVMX_PIP_HG_PRI_QOS, pip_hg_pri_qos.u64); 356232812Sjmallett } 357210284Sjmallett } 358210284Sjmallett 359210284Sjmallett /* Setup GMX RX to treat the HiGig header as user data to ignore */ 360210284Sjmallett gmx_rx_udd_skp.u64 = cvmx_read_csr(CVMX_GMXX_RXX_UDD_SKP(0, interface)); 361210284Sjmallett gmx_rx_udd_skp.s.len = header_size; 362210284Sjmallett gmx_rx_udd_skp.s.fcssel = 0; 363210284Sjmallett cvmx_write_csr(CVMX_GMXX_RXX_UDD_SKP(0, interface), gmx_rx_udd_skp.u64); 364210284Sjmallett 365210284Sjmallett /* Disable GMX preamble checking */ 366210284Sjmallett gmx_rx_frm_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(0, interface)); 367210284Sjmallett gmx_rx_frm_ctl.s.pre_chk = 0; 368210284Sjmallett cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(0, interface), gmx_rx_frm_ctl.u64); 369210284Sjmallett 370210284Sjmallett /* Setup GMX TX to pad properly min sized packets */ 371210284Sjmallett gmx_tx_min_pkt.u64 = cvmx_read_csr(CVMX_GMXX_TXX_MIN_PKT(0, interface)); 372210284Sjmallett gmx_tx_min_pkt.s.min_size = 59 + header_size; 373210284Sjmallett cvmx_write_csr(CVMX_GMXX_TXX_MIN_PKT(0, interface), gmx_tx_min_pkt.u64); 374210284Sjmallett 375210284Sjmallett /* Setup GMX TX to not add a preamble */ 376210284Sjmallett gmx_tx_append.u64 = cvmx_read_csr(CVMX_GMXX_TXX_APPEND(0, interface)); 377210284Sjmallett gmx_tx_append.s.preamble = 0; 378210284Sjmallett cvmx_write_csr(CVMX_GMXX_TXX_APPEND(0, interface), gmx_tx_append.u64); 379210284Sjmallett 380210284Sjmallett /* Reduce the inter frame gap to 8 bytes */ 381210284Sjmallett gmx_tx_ifg.u64 = cvmx_read_csr(CVMX_GMXX_TX_IFG(interface)); 382210284Sjmallett gmx_tx_ifg.s.ifg1 = 4; 383210284Sjmallett gmx_tx_ifg.s.ifg2 = 4; 384210284Sjmallett cvmx_write_csr(CVMX_GMXX_TX_IFG(interface), gmx_tx_ifg.u64); 385210284Sjmallett 386210284Sjmallett /* Disable GMX backpressure */ 387210284Sjmallett gmx_tx_ovr_bp.u64 = cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface)); 388210284Sjmallett gmx_tx_ovr_bp.s.bp = 0; 389210284Sjmallett gmx_tx_ovr_bp.s.en = 0xf; 390210284Sjmallett gmx_tx_ovr_bp.s.ign_full = 0xf; 391210284Sjmallett cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp.u64); 392210284Sjmallett 393210284Sjmallett if (enable_higig2) 394210284Sjmallett { 395210284Sjmallett /* Enable HiGig2 support and forwarding of virtual port backpressure 396210284Sjmallett to PKO */ 397210284Sjmallett cvmx_gmxx_hg2_control_t gmx_hg2_control; 398210284Sjmallett gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface)); 399210284Sjmallett gmx_hg2_control.s.hg2rx_en = 1; 400210284Sjmallett gmx_hg2_control.s.hg2tx_en = 1; 401210284Sjmallett gmx_hg2_control.s.logl_en = 0xffff; 402210284Sjmallett gmx_hg2_control.s.phys_en = 1; 403210284Sjmallett cvmx_write_csr(CVMX_GMXX_HG2_CONTROL(interface), gmx_hg2_control.u64); 404210284Sjmallett } 405210284Sjmallett 406210284Sjmallett /* Enable HiGig */ 407210284Sjmallett gmx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface)); 408210284Sjmallett gmx_tx_xaui_ctl.s.hg_en = 1; 409210284Sjmallett cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmx_tx_xaui_ctl.u64); 410210284Sjmallett 411210284Sjmallett return 0; 412210284Sjmallett} 413210284Sjmallett 414210284Sjmallett#ifdef __cplusplus 415210284Sjmallett} 416210284Sjmallett#endif 417210284Sjmallett 418210284Sjmallett#endif // __CVMX_HIGIG_H__ 419