cvmx-coremask.c revision 210284
1210284Sjmallett/***********************license start*************** 2210284Sjmallett * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights 3210284Sjmallett * reserved. 4210284Sjmallett * 5210284Sjmallett * 6210284Sjmallett * Redistribution and use in source and binary forms, with or without 7210284Sjmallett * modification, are permitted provided that the following conditions are 8210284Sjmallett * met: 9210284Sjmallett * 10210284Sjmallett * * Redistributions of source code must retain the above copyright 11210284Sjmallett * notice, this list of conditions and the following disclaimer. 12210284Sjmallett * 13210284Sjmallett * * Redistributions in binary form must reproduce the above 14210284Sjmallett * copyright notice, this list of conditions and the following 15210284Sjmallett * disclaimer in the documentation and/or other materials provided 16210284Sjmallett * with the distribution. 17210284Sjmallett * 18210284Sjmallett * * Neither the name of Cavium Networks nor the names of 19210284Sjmallett * its contributors may be used to endorse or promote products 20210284Sjmallett * derived from this software without specific prior written 21210284Sjmallett * permission. 22210284Sjmallett * 23210284Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 24210284Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS 25210284Sjmallett * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH 26210284Sjmallett * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY 27210284Sjmallett * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT 28210284Sjmallett * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES 29210284Sjmallett * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR 30210284Sjmallett * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET 31210284Sjmallett * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT 32210284Sjmallett * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 33210284Sjmallett * 34210284Sjmallett * 35210284Sjmallett * For any questions regarding licensing please contact marketing@caviumnetworks.com 36210284Sjmallett * 37210284Sjmallett ***********************license end**************************************/ 38210284Sjmallett 39210284Sjmallett 40210284Sjmallett 41210284Sjmallett 42210284Sjmallett 43210284Sjmallett 44210284Sjmallett/** 45210284Sjmallett * @file 46210284Sjmallett * 47210284Sjmallett * Module to support operations on bitmap of cores. Coremask can be used to 48210284Sjmallett * select a specific core, a group of cores, or all available cores, for 49210284Sjmallett * initialization and differentiation of roles within a single shared binary 50210284Sjmallett * executable image. 51210284Sjmallett * 52210284Sjmallett * <hr>$Revision: 41586 $<hr> 53210284Sjmallett * 54210284Sjmallett */ 55210284Sjmallett 56210284Sjmallett#include "cvmx-config.h" 57210284Sjmallett#include "cvmx.h" 58210284Sjmallett#include "cvmx-spinlock.h" 59210284Sjmallett#include "cvmx-coremask.h" 60210284Sjmallett 61210284Sjmallett 62210284Sjmallett#define CVMX_COREMASK_MAX_SYNCS 20 /* maximum number of coremasks for barrier sync */ 63210284Sjmallett 64210284Sjmallett/** 65210284Sjmallett * This structure defines the private state maintained by coremask module. 66210284Sjmallett * 67210284Sjmallett */ 68210284SjmallettCVMX_SHARED static struct { 69210284Sjmallett 70210284Sjmallett cvmx_spinlock_t lock; /**< mutex spinlock */ 71210284Sjmallett 72210284Sjmallett struct { 73210284Sjmallett 74210284Sjmallett unsigned int coremask; /**< coremask specified for barrier */ 75210284Sjmallett unsigned int checkin; /**< bitmask of cores checking in */ 76210284Sjmallett volatile unsigned int exit; /**< variable to poll for exit condition */ 77210284Sjmallett 78210284Sjmallett } s[CVMX_COREMASK_MAX_SYNCS]; 79210284Sjmallett 80210284Sjmallett} state = { 81210284Sjmallett 82210284Sjmallett { CVMX_SPINLOCK_UNLOCKED_VAL }, 83210284Sjmallett 84210284Sjmallett { { 0, 0, 0 } }, 85210284Sjmallett}; 86210284Sjmallett 87210284Sjmallett 88210284Sjmallett/** 89210284Sjmallett * Wait (stall) until all cores in the given coremask has reached this point 90210284Sjmallett * in the program execution before proceeding. 91210284Sjmallett * 92210284Sjmallett * @param coremask the group of cores performing the barrier sync 93210284Sjmallett * 94210284Sjmallett */ 95210284Sjmallettvoid cvmx_coremask_barrier_sync(unsigned int coremask) 96210284Sjmallett{ 97210284Sjmallett int i; 98210284Sjmallett unsigned int target; 99210284Sjmallett 100210284Sjmallett assert(coremask != 0); 101210284Sjmallett 102210284Sjmallett cvmx_spinlock_lock(&state.lock); 103210284Sjmallett 104210284Sjmallett for (i = 0; i < CVMX_COREMASK_MAX_SYNCS; i++) { 105210284Sjmallett 106210284Sjmallett if (state.s[i].coremask == 0) { 107210284Sjmallett /* end of existing coremask list, create new entry, fall-thru */ 108210284Sjmallett state.s[i].coremask = coremask; 109210284Sjmallett } 110210284Sjmallett 111210284Sjmallett if (state.s[i].coremask == coremask) { 112210284Sjmallett 113210284Sjmallett target = state.s[i].exit + 1; /* wrap-around at 32b */ 114210284Sjmallett 115210284Sjmallett state.s[i].checkin |= cvmx_coremask_core(cvmx_get_core_num()); 116210284Sjmallett if (state.s[i].checkin == coremask) { 117210284Sjmallett state.s[i].checkin = 0; 118210284Sjmallett state.s[i].exit = target; /* signal exit condition */ 119210284Sjmallett } 120210284Sjmallett cvmx_spinlock_unlock(&state.lock); 121210284Sjmallett 122210284Sjmallett while (state.s[i].exit != target) 123210284Sjmallett ; 124210284Sjmallett 125210284Sjmallett return; 126210284Sjmallett } 127210284Sjmallett } 128210284Sjmallett 129210284Sjmallett /* error condition - coremask array overflowed */ 130210284Sjmallett cvmx_spinlock_unlock(&state.lock); 131210284Sjmallett assert(0); 132210284Sjmallett} 133