cvmx-clock.c revision 215976 
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44
45
46/**
47 * @file
48 *
49 * Interface to Core, IO and DDR Clock.
50 *
51 * <hr>$Revision: 45089 $<hr>
52*/
53
54#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
55#include <linux/module.h>
56#include <asm/octeon/octeon.h>
57#include <asm/octeon/cvmx-clock.h>
58#include <asm/octeon/cvmx-npei-defs.h>
59#include <asm/octeon/cvmx-pexp-defs.h>
60#include <asm/octeon/cvmx-dbg-defs.h>
61#else
62#include "executive-config.h"
63#include "cvmx.h"
64#endif
65
66#ifndef CVMX_BUILD_FOR_UBOOT
67static uint64_t rate_eclk = 0;
68static uint64_t rate_sclk = 0;
69static uint64_t rate_dclk = 0;
70#endif
71
72/**
73 * Get clock rate based on the clock type.
74 *
75 * @param clock - Enumeration of the clock type.
76 * @return      - return the clock rate.
77 */
78uint64_t cvmx_clock_get_rate(cvmx_clock_t clock)
79{
80    const uint64_t REF_CLOCK = 50000000;
81
82#ifdef CVMX_BUILD_FOR_UBOOT
83    uint64_t rate_eclk = 0;
84    uint64_t rate_sclk = 0;
85    uint64_t rate_dclk = 0;
86#endif
87
88    if (cvmx_unlikely(!rate_eclk))
89    {
90        if (octeon_has_feature(OCTEON_FEATURE_NPEI))
91        {
92            cvmx_npei_dbg_data_t npei_dbg_data;
93            npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
94            rate_eclk =  REF_CLOCK * npei_dbg_data.s.c_mul;
95            rate_sclk = rate_eclk;
96        }
97        else if (octeon_has_feature(OCTEON_FEATURE_PCIE))
98        {
99            cvmx_mio_rst_boot_t mio_rst_boot;
100            mio_rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
101            rate_eclk =  REF_CLOCK * mio_rst_boot.s.c_mul;
102            rate_sclk = REF_CLOCK * mio_rst_boot.s.pnr_mul;
103        }
104        else
105        {
106            cvmx_dbg_data_t dbg_data;
107            dbg_data.u64 = cvmx_read_csr(CVMX_DBG_DATA);
108            rate_eclk =  REF_CLOCK * dbg_data.s.c_mul;
109            rate_sclk = rate_eclk;
110        }
111    }
112
113    switch (clock)
114    {
115        case CVMX_CLOCK_SCLK:
116        case CVMX_CLOCK_TIM:
117        case CVMX_CLOCK_IPD:
118            return rate_sclk;
119
120        case CVMX_CLOCK_RCLK:
121        case CVMX_CLOCK_CORE:
122            return rate_eclk;
123
124        case CVMX_CLOCK_DDR:
125#if !defined(CVMX_BUILD_FOR_LINUX_HOST) && !defined(__OCTEON_NEWLIB__)
126            if (cvmx_unlikely(!rate_dclk))
127                rate_dclk = cvmx_sysinfo_get()->dram_data_rate_hz;
128#endif
129            return rate_dclk;
130    }
131
132    cvmx_dprintf("cvmx_clock_get_rate: Unknown clock type\n");
133    return 0;
134}
135#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
136EXPORT_SYMBOL(cvmx_clock_get_rate);
137#endif
138