ar9300eep.h revision 250007
167117Sdfr/* 267117Sdfr * Copyright (c) 2013 Qualcomm Atheros, Inc. 367117Sdfr * 467117Sdfr * Permission to use, copy, modify, and/or distribute this software for any 567117Sdfr * purpose with or without fee is hereby granted, provided that the above 667117Sdfr * copyright notice and this permission notice appear in all copies. 767117Sdfr * 867117Sdfr * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 967117Sdfr * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 1067117Sdfr * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 1167117Sdfr * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 1267117Sdfr * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 1367117Sdfr * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 1467117Sdfr * PERFORMANCE OF THIS SOFTWARE. 1567117Sdfr */ 1667117Sdfr 1767117Sdfr#ifndef _ATH_AR9300_EEP_H_ 1867117Sdfr#define _ATH_AR9300_EEP_H_ 1967117Sdfr 2067117Sdfr#include "opt_ah.h" 2167117Sdfr 2267117Sdfr#include "ah.h" 2367117Sdfr 2467117Sdfr#if defined(WIN32) || defined(WIN64) 2567117Sdfr#pragma pack (push, ar9300, 1) 2667117Sdfr#endif 2767117Sdfr 2867117Sdfr 2967117Sdfr#define MSTATE 100 3067117Sdfr#define MOUTPUT 2048 3167117Sdfr#define MDEFAULT 15 3267117Sdfr#define MVALUE 100 3367117Sdfr 3467117Sdfrenum CompressAlgorithm 35{ 36 _compress_none = 0, 37 _compress_lzma, 38 _compress_pairs, 39 _compress_block, 40 _compress4, 41 _compress5, 42 _compress6, 43 _compress7, 44}; 45 46 47enum 48{ 49 calibration_data_none = 0, 50 calibration_data_dram, 51 calibration_data_flash, 52 calibration_data_eeprom, 53 calibration_data_otp, 54#ifdef ATH_CAL_NAND_FLASH 55 calibration_data_nand, 56#endif 57 CalibrationDataDontLoad, 58}; 59#define HOST_CALDATA_SIZE (16*1024) 60 61// 62// DO NOT CHANGE THE DEFINTIONS OF THESE SYMBOLS. 63// Add additional definitions to the end. 64// Yes, the first one is 2. Do not use 0 or 1. 65// 66enum Ar9300EepromTemplate 67{ 68 ar9300_eeprom_template_generic = 2, 69 ar9300_eeprom_template_hb112 = 3, 70 ar9300_eeprom_template_hb116 = 4, 71 ar9300_eeprom_template_xb112 = 5, 72 ar9300_eeprom_template_xb113 = 6, 73 ar9300_eeprom_template_xb114 = 7, 74 ar9300_eeprom_template_tb417 = 8, 75 ar9300_eeprom_template_ap111 = 9, 76 ar9300_eeprom_template_ap121 = 10, 77 ar9300_eeprom_template_hornet_generic = 11, 78 ar9300_eeprom_template_wasp_2 = 12, 79 ar9300_eeprom_template_wasp_k31 = 13, 80 ar9300_eeprom_template_osprey_k31 = 14, 81 ar9300_eeprom_template_aphrodite = 15 82}; 83 84#define ar9300_eeprom_template_default ar9300_eeprom_template_generic 85#define Ar9300EepromFormatDefault 2 86 87#define reference_current 0 88#define compression_header_length 4 89#define compression_checksum_length 2 90 91#define OSPREY_EEP_VER 0xD000 92#define OSPREY_EEP_VER_MINOR_MASK 0xFFF 93#define OSPREY_EEP_MINOR_VER_1 0x1 94#define OSPREY_EEP_MINOR_VER OSPREY_EEP_MINOR_VER_1 95 96// 16-bit offset location start of calibration struct 97#define OSPREY_EEP_START_LOC 256 98#define OSPREY_NUM_5G_CAL_PIERS 8 99#define OSPREY_NUM_2G_CAL_PIERS 3 100#define OSPREY_NUM_5G_20_TARGET_POWERS 8 101#define OSPREY_NUM_5G_40_TARGET_POWERS 8 102#define OSPREY_NUM_2G_CCK_TARGET_POWERS 2 103#define OSPREY_NUM_2G_20_TARGET_POWERS 3 104#define OSPREY_NUM_2G_40_TARGET_POWERS 3 105//#define OSPREY_NUM_CTLS 21 106#define OSPREY_NUM_CTLS_5G 9 107#define OSPREY_NUM_CTLS_2G 12 108#define OSPREY_CTL_MODE_M 0xF 109#define OSPREY_NUM_BAND_EDGES_5G 8 110#define OSPREY_NUM_BAND_EDGES_2G 4 111#define OSPREY_NUM_PD_GAINS 4 112#define OSPREY_PD_GAINS_IN_MASK 4 113#define OSPREY_PD_GAIN_ICEPTS 5 114#define OSPREY_EEPROM_MODAL_SPURS 5 115#define OSPREY_MAX_RATE_POWER 63 116#define OSPREY_NUM_PDADC_VALUES 128 117#define OSPREY_NUM_RATES 16 118#define OSPREY_BCHAN_UNUSED 0xFF 119#define OSPREY_MAX_PWR_RANGE_IN_HALF_DB 64 120#define OSPREY_OPFLAGS_11A 0x01 121#define OSPREY_OPFLAGS_11G 0x02 122#define OSPREY_OPFLAGS_5G_HT40 0x04 123#define OSPREY_OPFLAGS_2G_HT40 0x08 124#define OSPREY_OPFLAGS_5G_HT20 0x10 125#define OSPREY_OPFLAGS_2G_HT20 0x20 126#define OSPREY_EEPMISC_BIG_ENDIAN 0x01 127#define OSPREY_EEPMISC_WOW 0x02 128#define OSPREY_CUSTOMER_DATA_SIZE 20 129 130#define FREQ2FBIN(x,y) \ 131 (((y) == HAL_FREQ_BAND_2GHZ) ? ((x) - 2300) : (((x) - 4800) / 5)) 132#define FBIN2FREQ(x,y) \ 133 (((y) == HAL_FREQ_BAND_2GHZ) ? (2300 + x) : (4800 + 5 * x)) 134#define OSPREY_MAX_CHAINS 3 135#define OSPREY_ANT_16S 25 136#define OSPREY_FUTURE_MODAL_SZ 6 137 138#define OSPREY_NUM_ANT_CHAIN_FIELDS 7 139#define OSPREY_NUM_ANT_COMMON_FIELDS 4 140#define OSPREY_SIZE_ANT_CHAIN_FIELD 3 141#define OSPREY_SIZE_ANT_COMMON_FIELD 4 142#define OSPREY_ANT_CHAIN_MASK 0x7 143#define OSPREY_ANT_COMMON_MASK 0xf 144#define OSPREY_CHAIN_0_IDX 0 145#define OSPREY_CHAIN_1_IDX 1 146#define OSPREY_CHAIN_2_IDX 2 147#define OSPREY_1_CHAINMASK 1 148#define OSPREY_2LOHI_CHAINMASK 5 149#define OSPREY_2LOMID_CHAINMASK 3 150#define OSPREY_3_CHAINMASK 7 151 152#define AR928X_NUM_ANT_CHAIN_FIELDS 6 153#define AR928X_SIZE_ANT_CHAIN_FIELD 2 154#define AR928X_ANT_CHAIN_MASK 0x3 155 156/* Delta from which to start power to pdadc table */ 157/* This offset is used in both open loop and closed loop power control 158 * schemes. In open loop power control, it is not really needed, but for 159 * the "sake of consistency" it was kept. 160 * For certain AP designs, this value is overwritten by the value in the flag 161 * "pwrTableOffset" just before writing the pdadc vs pwr into the chip registers. 162 */ 163#define OSPREY_PWR_TABLE_OFFSET 0 164 165//enable flags for voltage and temp compensation 166#define ENABLE_TEMP_COMPENSATION 0x01 167#define ENABLE_VOLT_COMPENSATION 0x02 168 169#define FLASH_BASE_CALDATA_OFFSET 0x1000 170#define AR9300_EEPROM_SIZE 16*1024 // byte addressable 171#define FIXED_CCA_THRESHOLD 15 172 173typedef struct eepFlags { 174 u_int8_t op_flags; 175 u_int8_t eepMisc; 176} __packed EEP_FLAGS; 177 178typedef enum targetPowerHTRates { 179 HT_TARGET_RATE_0_8_16, 180 HT_TARGET_RATE_1_3_9_11_17_19, 181 HT_TARGET_RATE_4, 182 HT_TARGET_RATE_5, 183 HT_TARGET_RATE_6, 184 HT_TARGET_RATE_7, 185 HT_TARGET_RATE_12, 186 HT_TARGET_RATE_13, 187 HT_TARGET_RATE_14, 188 HT_TARGET_RATE_15, 189 HT_TARGET_RATE_20, 190 HT_TARGET_RATE_21, 191 HT_TARGET_RATE_22, 192 HT_TARGET_RATE_23 193}TARGET_POWER_HT_RATES; 194 195const static int mapRate2Index[24]= 196{ 197 0,1,1,1,2, 198 3,4,5,0,1, 199 1,1,6,7,8, 200 9,0,1,1,1, 201 10,11,12,13 202}; 203 204typedef enum targetPowerLegacyRates { 205 LEGACY_TARGET_RATE_6_24, 206 LEGACY_TARGET_RATE_36, 207 LEGACY_TARGET_RATE_48, 208 LEGACY_TARGET_RATE_54 209}TARGET_POWER_LEGACY_RATES; 210 211typedef enum targetPowerCckRates { 212 LEGACY_TARGET_RATE_1L_5L, 213 LEGACY_TARGET_RATE_5S, 214 LEGACY_TARGET_RATE_11L, 215 LEGACY_TARGET_RATE_11S 216}TARGET_POWER_CCK_RATES; 217 218#define MAX_MODAL_RESERVED 11 219#define MAX_MODAL_FUTURE 5 220#define MAX_BASE_EXTENSION_FUTURE 2 221#define MAX_TEMP_SLOPE 8 222#define OSPREY_CHECKSUM_LOCATION (OSPREY_EEP_START_LOC + 1) 223 224typedef struct osprey_BaseEepHeader { 225 u_int16_t reg_dmn[2]; //Does this need to be outside of this structure, if it gets written after calibration 226 u_int8_t txrx_mask; //4 bits tx and 4 bits rx 227 EEP_FLAGS op_cap_flags; 228 u_int8_t rf_silent; 229 u_int8_t blue_tooth_options; 230 u_int8_t device_cap; 231 u_int8_t device_type; // takes lower byte in eeprom location 232 int8_t pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration 233 u_int8_t params_for_tuning_caps[2]; //placeholder, get more details from Don 234 u_int8_t feature_enable; //bit0 - enable tx temp comp 235 //bit1 - enable tx volt comp 236 //bit2 - enable fastClock - default to 1 237 //bit3 - enable doubling - default to 1 238 //bit4 - enable internal regulator - default to 1 239 //bit5 - enable paprd - default to 0 240 //bit6 - enable TuningCaps - default to 0 241 //bit7 - enable tx_frame_to_xpa_on - default to 0 242 u_int8_t misc_configuration; //misc flags: bit0 - turn down drivestrength 243 // bit 1:2 - 0=don't force, 1=force to thermometer 0, 2=force to thermometer 1, 3=force to thermometer 2 244 // bit 3 - reduce chain mask from 0x7 to 0x3 on 2 stream rates 245 // bit 4 - enable quick drop 246 // bit 5 - enable 8 temp slop 247 // bit 6; enable xLNA_bias_strength 248 // bit 7; enable rf_gain_cap 249 u_int8_t eeprom_write_enable_gpio; 250 u_int8_t wlan_disable_gpio; 251 u_int8_t wlan_led_gpio; 252 u_int8_t rx_band_select_gpio; 253 u_int8_t txrxgain; 254 u_int32_t swreg; // SW controlled internal regulator fields 255} __packed OSPREY_BASE_EEP_HEADER; 256 257typedef struct osprey_BaseExtension_1 { 258 u_int8_t ant_div_control; 259 u_int8_t future[MAX_BASE_EXTENSION_FUTURE]; 260 u_int8_t misc_enable; 261 int8_t tempslopextension[MAX_TEMP_SLOPE]; 262 int8_t quick_drop_low; 263 int8_t quick_drop_high; 264} __packed OSPREY_BASE_EXTENSION_1; 265 266typedef struct osprey_BaseExtension_2 { 267 int8_t temp_slope_low; 268 int8_t temp_slope_high; 269 u_int8_t xatten1_db_low[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 270 u_int8_t xatten1_margin_low[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 271 u_int8_t xatten1_db_high[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 272 u_int8_t xatten1_margin_high[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 273} __packed OSPREY_BASE_EXTENSION_2; 274 275typedef struct spurChanStruct { 276 u_int16_t spur_chan; 277 u_int8_t spurRangeLow; 278 u_int8_t spurRangeHigh; 279} __packed SPUR_CHAN; 280 281//Note the order of the fields in this structure has been optimized to put all fields likely to change together 282typedef struct ospreyModalEepHeader { 283 u_int32_t ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) 284 u_int32_t ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 285 u_int16_t ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) 286 u_int8_t xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 287 u_int8_t xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 288 int8_t temp_slope; 289 int8_t voltSlope; 290 u_int8_t spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format 291 int8_t noise_floor_thresh_ch[OSPREY_MAX_CHAINS];// 3 //Check if the register is per chain 292 u_int8_t reserved[MAX_MODAL_RESERVED]; 293 int8_t quick_drop; 294 u_int8_t xpa_bias_lvl; // 1 295 u_int8_t tx_frame_to_data_start; // 1 296 u_int8_t tx_frame_to_pa_on; // 1 297 u_int8_t txClip; // 4 bits tx_clip, 4 bits dac_scale_cck 298 int8_t antenna_gain; // 1 299 u_int8_t switchSettling; // 1 300 int8_t adcDesiredSize; // 1 301 u_int8_t tx_end_to_xpa_off; // 1 302 u_int8_t txEndToRxOn; // 1 303 u_int8_t tx_frame_to_xpa_on; // 1 304 u_int8_t thresh62; // 1 305 u_int32_t paprd_rate_mask_ht20; 306 u_int32_t paprd_rate_mask_ht40; 307 u_int16_t switchcomspdt; 308 u_int8_t xLNA_bias_strength; // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 309 u_int8_t rf_gain_cap; 310 u_int8_t tx_gain_cap; // bit0:4 txgain cap, txgain index for max_txgain + 20 (10dBm higher than max txgain) 311 u_int8_t futureModal[MAX_MODAL_FUTURE]; 312 // last 12 bytes stolen and moved to newly created base extension structure 313} __packed OSPREY_MODAL_EEP_HEADER; // == 100 B 314 315typedef struct ospCalDataPerFreqOpLoop { 316 int8_t ref_power; /* */ 317 u_int8_t volt_meas; /* pdadc voltage at power measurement */ 318 u_int8_t temp_meas; /* pcdac used for power measurement */ 319 int8_t rx_noisefloor_cal; /*range is -60 to -127 create a mapping equation 1db resolution */ 320 int8_t rx_noisefloor_power; /*range is same as noisefloor */ 321 u_int8_t rxTempMeas; /*temp measured when noisefloor cal was performed */ 322} __packed OSP_CAL_DATA_PER_FREQ_OP_LOOP; 323 324typedef struct CalTargetPowerLegacy { 325 u_int8_t t_pow2x[4]; 326} __packed CAL_TARGET_POWER_LEG; 327 328typedef struct ospCalTargetPowerHt { 329 u_int8_t t_pow2x[14]; 330} __packed OSP_CAL_TARGET_POWER_HT; 331 332#if AH_BYTE_ORDER == AH_BIG_ENDIAN 333typedef struct CalCtlEdgePwr { 334 u_int8_t flag :2, 335 t_power :6; 336} __packed CAL_CTL_EDGE_PWR; 337#else 338typedef struct CalCtlEdgePwr { 339 u_int8_t t_power :6, 340 flag :2; 341} __packed CAL_CTL_EDGE_PWR; 342#endif 343 344typedef struct ospCalCtlData_5G { 345 CAL_CTL_EDGE_PWR ctl_edges[OSPREY_NUM_BAND_EDGES_5G]; 346} __packed OSP_CAL_CTL_DATA_5G; 347 348typedef struct ospCalCtlData_2G { 349 CAL_CTL_EDGE_PWR ctl_edges[OSPREY_NUM_BAND_EDGES_2G]; 350} __packed OSP_CAL_CTL_DATA_2G; 351 352typedef struct ospreyEeprom { 353 u_int8_t eeprom_version; 354 u_int8_t template_version; 355 u_int8_t mac_addr[6]; 356 u_int8_t custData[OSPREY_CUSTOMER_DATA_SIZE]; 357 358 OSPREY_BASE_EEP_HEADER base_eep_header; 359 360 OSPREY_MODAL_EEP_HEADER modal_header_2g; 361 OSPREY_BASE_EXTENSION_1 base_ext1; 362 u_int8_t cal_freq_pier_2g[OSPREY_NUM_2G_CAL_PIERS]; 363 OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_2g[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]; 364 u_int8_t cal_target_freqbin_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]; 365 u_int8_t cal_target_freqbin_2g[OSPREY_NUM_2G_20_TARGET_POWERS]; 366 u_int8_t cal_target_freqbin_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS]; 367 u_int8_t cal_target_freqbin_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS]; 368 CAL_TARGET_POWER_LEG cal_target_power_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]; 369 CAL_TARGET_POWER_LEG cal_target_power_2g[OSPREY_NUM_2G_20_TARGET_POWERS]; 370 OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS]; 371 OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS]; 372 u_int8_t ctl_index_2g[OSPREY_NUM_CTLS_2G]; 373 u_int8_t ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G]; 374 OSP_CAL_CTL_DATA_2G ctl_power_data_2g[OSPREY_NUM_CTLS_2G]; 375 376 OSPREY_MODAL_EEP_HEADER modal_header_5g; 377 OSPREY_BASE_EXTENSION_2 base_ext2; 378 u_int8_t cal_freq_pier_5g[OSPREY_NUM_5G_CAL_PIERS]; 379 OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_5g[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]; 380 u_int8_t cal_target_freqbin_5g[OSPREY_NUM_5G_20_TARGET_POWERS]; 381 u_int8_t cal_target_freqbin_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]; 382 u_int8_t cal_target_freqbin_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]; 383 CAL_TARGET_POWER_LEG cal_target_power_5g[OSPREY_NUM_5G_20_TARGET_POWERS]; 384 OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]; 385 OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]; 386 u_int8_t ctl_index_5g[OSPREY_NUM_CTLS_5G]; 387 u_int8_t ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G]; 388 OSP_CAL_CTL_DATA_5G ctl_power_data_5g[OSPREY_NUM_CTLS_5G]; 389} __packed ar9300_eeprom_t; 390 391 392/* 393** SWAP Functions 394** used to read EEPROM data, which is apparently stored in little 395** endian form. We have included both forms of the swap functions, 396** one for big endian and one for little endian. The indices of the 397** array elements are the differences 398*/ 399#if AH_BYTE_ORDER == AH_BIG_ENDIAN 400 401#define AR9300_EEPROM_MAGIC 0x5aa5 402#define SWAP16(_x) ( (u_int16_t)( (((const u_int8_t *)(&_x))[0] ) |\ 403 ( ( (const u_int8_t *)( &_x ) )[1]<< 8) ) ) 404 405#define SWAP32(_x) ((u_int32_t)( \ 406 (((const u_int8_t *)(&_x))[0]) | \ 407 (((const u_int8_t *)(&_x))[1]<< 8) | \ 408 (((const u_int8_t *)(&_x))[2]<<16) | \ 409 (((const u_int8_t *)(&_x))[3]<<24))) 410 411#else // AH_BYTE_ORDER 412 413#define AR9300_EEPROM_MAGIC 0xa55a 414#define SWAP16(_x) ( (u_int16_t)( (((const u_int8_t *)(&_x))[1] ) |\ 415 ( ( (const u_int8_t *)( &_x ) )[0]<< 8) ) ) 416 417#define SWAP32(_x) ((u_int32_t)( \ 418 (((const u_int8_t *)(&_x))[3]) | \ 419 (((const u_int8_t *)(&_x))[2]<< 8) | \ 420 (((const u_int8_t *)(&_x))[1]<<16) | \ 421 (((const u_int8_t *)(&_x))[0]<<24))) 422 423#endif // AH_BYTE_ORDER 424 425// OTP registers for OSPREY 426 427#define AR_GPIO_IN_OUT 0x4048 // GPIO input / output register 428#define OTP_MEM_START_ADDRESS 0x14000 429#define OTP_STATUS0_OTP_SM_BUSY 0x00015f18 430#define OTP_STATUS1_EFUSE_READ_DATA 0x00015f1c 431 432#define OTP_LDO_CONTROL_ENABLE 0x00015f24 433#define OTP_LDO_STATUS_POWER_ON 0x00015f2c 434#define OTP_INTF0_EFUSE_WR_ENABLE_REG_V 0x00015f00 435// OTP register for Jupiter 436#define GLB_OTP_LDO_CONTROL_ENABLE 0x00020020 437#define GLB_OTP_LDO_STATUS_POWER_ON 0x00020028 438#define OTP_PGENB_SETUP_HOLD_TIME_DELAY 0x15f34 439 440// OTP register for Jupiter BT 441#define BTOTP_MEM_START_ADDRESS 0x64000 442#define BTOTP_STATUS0_OTP_SM_BUSY 0x00065f18 443#define BTOTP_STATUS1_EFUSE_READ_DATA 0x00065f1c 444#define BTOTP_INTF0_EFUSE_WR_ENABLE_REG_V 0x00065f00 445#define BTOTP_INTF2 0x00065f08 446#define BTOTP_PGENB_SETUP_HOLD_TIME_DELAY 0x65f34 447#define BT_RESET_CTL 0x44000 448#define BT_CLOCK_CONTROL 0x44028 449 450 451// OTP register for WASP 452#define OTP_MEM_START_ADDRESS_WASP 0x00030000 453#define OTP_STATUS0_OTP_SM_BUSY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1018) 454#define OTP_STATUS1_EFUSE_READ_DATA_WASP (OTP_MEM_START_ADDRESS_WASP + 0x101C) 455#define OTP_LDO_CONTROL_ENABLE_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1024) 456#define OTP_LDO_STATUS_POWER_ON_WASP (OTP_MEM_START_ADDRESS_WASP + 0x102C) 457#define OTP_INTF0_EFUSE_WR_ENABLE_REG_V_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1000) 458// Below control the access timing of OTP read/write 459#define OTP_PG_STROBE_PW_REG_V_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1008) 460#define OTP_RD_STROBE_PW_REG_V_WASP (OTP_MEM_START_ADDRESS_WASP + 0x100C) 461#define OTP_VDDQ_HOLD_TIME_DELAY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1030) 462#define OTP_PGENB_SETUP_HOLD_TIME_DELAY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1034) 463#define OTP_STROBE_PULSE_INTERVAL_DELAY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1038) 464#define OTP_CSB_ADDR_LOAD_SETUP_HOLD_DELAY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x103C) 465 466#define AR9300_EEPROM_MAGIC_OFFSET 0x0 467/* reg_off = 4 * (eep_off) */ 468#define AR9300_EEPROM_S 2 469#define AR9300_EEPROM_OFFSET 0x2000 470#ifdef AR9100 471#define AR9300_EEPROM_START_ADDR 0x1fff1000 472#else 473#define AR9300_EEPROM_START_ADDR 0x503f1200 474#endif 475#define AR9300_FLASH_CAL_START_OFFSET 0x1000 476#define AR9300_EEPROM_MAX 0xae0 477#define IS_EEP_MINOR_V3(_ahp) (ar9300_eeprom_get((_ahp), EEP_MINOR_REV) >= AR9300_EEP_MINOR_VER_3) 478 479#define ar9300_get_ntxchains(_txchainmask) \ 480 (((_txchainmask >> 2) & 1) + ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) 481 482/* RF silent fields in \ */ 483#define EEP_RFSILENT_ENABLED 0x0001 /* bit 0: enabled/disabled */ 484#define EEP_RFSILENT_ENABLED_S 0 /* bit 0: enabled/disabled */ 485#define EEP_RFSILENT_POLARITY 0x0002 /* bit 1: polarity */ 486#define EEP_RFSILENT_POLARITY_S 1 /* bit 1: polarity */ 487#define EEP_RFSILENT_GPIO_SEL 0x00fc /* bits 2..7: gpio PIN */ 488#define EEP_RFSILENT_GPIO_SEL_S 2 /* bits 2..7: gpio PIN */ 489#define AR9300_EEP_VER 0xE 490#define AR9300_BCHAN_UNUSED 0xFF 491#define AR9300_MAX_RATE_POWER 63 492 493typedef enum { 494 CALDATA_AUTO=0, 495 CALDATA_EEPROM, 496 CALDATA_FLASH, 497 CALDATA_OTP 498} CALDATA_TYPE; 499 500typedef enum { 501 EEP_NFTHRESH_5, 502 EEP_NFTHRESH_2, 503 EEP_MAC_MSW, 504 EEP_MAC_MID, 505 EEP_MAC_LSW, 506 EEP_REG_0, 507 EEP_REG_1, 508 EEP_OP_CAP, 509 EEP_OP_MODE, 510 EEP_RF_SILENT, 511 EEP_OB_5, 512 EEP_DB_5, 513 EEP_OB_2, 514 EEP_DB_2, 515 EEP_MINOR_REV, 516 EEP_TX_MASK, 517 EEP_RX_MASK, 518 EEP_FSTCLK_5G, 519 EEP_RXGAIN_TYPE, 520 EEP_OL_PWRCTRL, 521 EEP_TXGAIN_TYPE, 522 EEP_RC_CHAIN_MASK, 523 EEP_DAC_HPWR_5G, 524 EEP_FRAC_N_5G, 525 EEP_DEV_TYPE, 526 EEP_TEMPSENSE_SLOPE, 527 EEP_TEMPSENSE_SLOPE_PAL_ON, 528 EEP_PWR_TABLE_OFFSET, 529 EEP_DRIVE_STRENGTH, 530 EEP_INTERNAL_REGULATOR, 531 EEP_SWREG, 532 EEP_PAPRD_ENABLED, 533 EEP_ANTDIV_control, 534 EEP_CHAIN_MASK_REDUCE, 535} EEPROM_PARAM; 536 537#define AR9300_RATES_OFDM_OFFSET 0 538#define AR9300_RATES_CCK_OFFSET 4 539#define AR9300_RATES_HT20_OFFSET 8 540#define AR9300_RATES_HT40_OFFSET 22 541typedef enum ar9300_Rates { 542 ALL_TARGET_LEGACY_6_24, 543 ALL_TARGET_LEGACY_36, 544 ALL_TARGET_LEGACY_48, 545 ALL_TARGET_LEGACY_54, 546 ALL_TARGET_LEGACY_1L_5L, 547 ALL_TARGET_LEGACY_5S, 548 ALL_TARGET_LEGACY_11L, 549 ALL_TARGET_LEGACY_11S, 550 ALL_TARGET_HT20_0_8_16, 551 ALL_TARGET_HT20_1_3_9_11_17_19, 552 ALL_TARGET_HT20_4, 553 ALL_TARGET_HT20_5, 554 ALL_TARGET_HT20_6, 555 ALL_TARGET_HT20_7, 556 ALL_TARGET_HT20_12, 557 ALL_TARGET_HT20_13, 558 ALL_TARGET_HT20_14, 559 ALL_TARGET_HT20_15, 560 ALL_TARGET_HT20_20, 561 ALL_TARGET_HT20_21, 562 ALL_TARGET_HT20_22, 563 ALL_TARGET_HT20_23, 564 ALL_TARGET_HT40_0_8_16, 565 ALL_TARGET_HT40_1_3_9_11_17_19, 566 ALL_TARGET_HT40_4, 567 ALL_TARGET_HT40_5, 568 ALL_TARGET_HT40_6, 569 ALL_TARGET_HT40_7, 570 ALL_TARGET_HT40_12, 571 ALL_TARGET_HT40_13, 572 ALL_TARGET_HT40_14, 573 ALL_TARGET_HT40_15, 574 ALL_TARGET_HT40_20, 575 ALL_TARGET_HT40_21, 576 ALL_TARGET_HT40_22, 577 ALL_TARGET_HT40_23, 578 ar9300_rate_size 579} AR9300_RATES; 580 581 582/************************************************************************** 583 * fbin2freq 584 * 585 * Get channel value from binary representation held in eeprom 586 * RETURNS: the frequency in MHz 587 */ 588static inline u_int16_t 589fbin2freq(u_int8_t fbin, HAL_BOOL is_2ghz) 590{ 591 /* 592 * Reserved value 0xFF provides an empty definition both as 593 * an fbin and as a frequency - do not convert 594 */ 595 if (fbin == AR9300_BCHAN_UNUSED) 596 { 597 return fbin; 598 } 599 600 return (u_int16_t)((is_2ghz) ? (2300 + fbin) : (4800 + 5 * fbin)); 601} 602 603extern int CompressionHeaderUnpack(u_int8_t *best, int *code, int *reference, int *length, int *major, int *minor); 604extern void Ar9300EepromFormatConvert(ar9300_eeprom_t *mptr); 605extern HAL_BOOL ar9300_eeprom_restore(struct ath_hal *ah); 606extern int ar9300_eeprom_restore_internal(struct ath_hal *ah, ar9300_eeprom_t *mptr, int /*msize*/); 607extern int ar9300_eeprom_base_address(struct ath_hal *ah); 608extern int ar9300_eeprom_volatile(struct ath_hal *ah); 609extern int ar9300_eeprom_low_limit(struct ath_hal *ah); 610extern u_int16_t ar9300_compression_checksum(u_int8_t *data, int dsize); 611extern int ar9300_compression_header_unpack(u_int8_t *best, int *code, int *reference, int *length, int *major, int *minor); 612 613extern u_int16_t ar9300_eeprom_struct_size(void); 614extern ar9300_eeprom_t *ar9300EepromStructInit(int default_index); 615extern ar9300_eeprom_t *ar9300EepromStructGet(void); 616extern ar9300_eeprom_t *ar9300_eeprom_struct_default(int default_index); 617extern ar9300_eeprom_t *ar9300_eeprom_struct_default_find_by_id(int ver); 618extern int ar9300_eeprom_struct_default_many(void); 619extern int ar9300EepromUpdateCalPier(int pierIdx, int freq, int chain, 620 int pwrCorrection, int volt_meas, int temp_meas); 621extern int ar9300_power_control_override(struct ath_hal *ah, int frequency, int *correction, int *voltage, int *temperature); 622 623extern void ar9300EepromDisplayCalData(int for2GHz); 624extern void ar9300EepromDisplayAll(void); 625extern void ar9300_set_target_power_from_eeprom(struct ath_hal *ah, u_int16_t freq, 626 u_int8_t *target_power_val_t2); 627extern HAL_BOOL ar9300_eeprom_set_power_per_rate_table(struct ath_hal *ah, 628 ar9300_eeprom_t *p_eep_data, 629 HAL_CHANNEL_INTERNAL *chan, 630 u_int8_t *p_pwr_array, 631 u_int16_t cfg_ctl, 632 u_int16_t antenna_reduction, 633 u_int16_t twice_max_regulatory_power, 634 u_int16_t power_limit, 635 u_int8_t chainmask); 636extern int ar9300_transmit_power_reg_write(struct ath_hal *ah, u_int8_t *p_pwr_array); 637extern int ar9300_compression_header_unpack(u_int8_t *best, int *code, int *reference, int *length, int *major, int *minor); 638 639extern u_int8_t ar9300_eeprom_get_legacy_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, u_int16_t freq, HAL_BOOL is_2ghz); 640extern u_int8_t ar9300_eeprom_get_ht20_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, u_int16_t freq, HAL_BOOL is_2ghz); 641extern u_int8_t ar9300_eeprom_get_ht40_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, u_int16_t freq, HAL_BOOL is_2ghz); 642extern u_int8_t ar9300_eeprom_get_cck_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, u_int16_t freq); 643extern HAL_BOOL ar9300_internal_regulator_apply(struct ath_hal *ah); 644extern HAL_BOOL ar9300_drive_strength_apply(struct ath_hal *ah); 645extern HAL_BOOL ar9300_attenuation_apply(struct ath_hal *ah, u_int16_t channel); 646extern int32_t ar9300_thermometer_get(struct ath_hal *ah); 647extern HAL_BOOL ar9300_thermometer_apply(struct ath_hal *ah); 648extern HAL_BOOL ar9300_xpa_timing_control_apply(struct ath_hal *ah, HAL_BOOL is_2ghz); 649extern HAL_BOOL ar9300_x_lNA_bias_strength_apply(struct ath_hal *ah, HAL_BOOL is_2ghz); 650 651extern int32_t ar9300MacAdressGet(u_int8_t *mac); 652extern int32_t ar9300CustomerDataGet(u_int8_t *data, int32_t len); 653extern int32_t ar9300ReconfigDriveStrengthGet(void); 654extern int32_t ar9300EnableTempCompensationGet(void); 655extern int32_t ar9300EnableVoltCompensationGet(void); 656extern int32_t ar9300FastClockEnableGet(void); 657extern int32_t ar9300EnableDoublingGet(void); 658 659extern u_int16_t *ar9300_regulatory_domain_get(struct ath_hal *ah); 660extern int32_t ar9300_eeprom_write_enable_gpio_get(struct ath_hal *ah); 661extern int32_t ar9300_wlan_led_gpio_get(struct ath_hal *ah); 662extern int32_t ar9300_wlan_disable_gpio_get(struct ath_hal *ah); 663extern int32_t ar9300_rx_band_select_gpio_get(struct ath_hal *ah); 664extern int32_t ar9300_rx_gain_index_get(struct ath_hal *ah); 665extern int32_t ar9300_tx_gain_index_get(struct ath_hal *ah); 666extern int32_t ar9300_xpa_bias_level_get(struct ath_hal *ah, HAL_BOOL is_2ghz); 667extern HAL_BOOL ar9300_xpa_bias_level_apply(struct ath_hal *ah, HAL_BOOL is_2ghz); 668extern u_int32_t ar9300_ant_ctrl_common_get(struct ath_hal *ah, HAL_BOOL is_2ghz); 669extern u_int32_t ar9300_ant_ctrl_common2_get(struct ath_hal *ah, HAL_BOOL is_2ghz); 670extern u_int16_t ar9300_ant_ctrl_chain_get(struct ath_hal *ah, int chain, HAL_BOOL is_2ghz); 671extern HAL_BOOL ar9300_ant_ctrl_apply(struct ath_hal *ah, HAL_BOOL is_2ghz); 672/* since valid noise floor values are negative, returns 1 on error */ 673extern int32_t ar9300_noise_floor_cal_or_power_get( 674 struct ath_hal *ah, int32_t frequency, int32_t ichain, HAL_BOOL use_cal); 675#define ar9300NoiseFloorGet(ah, frequency, ichain) \ 676 ar9300_noise_floor_cal_or_power_get(ah, frequency, ichain, 1/*use_cal*/) 677#define ar9300NoiseFloorPowerGet(ah, frequency, ichain) \ 678 ar9300_noise_floor_cal_or_power_get(ah, frequency, ichain, 0/*use_cal*/) 679extern void ar9300_eeprom_template_preference(int32_t value); 680extern int32_t ar9300_eeprom_template_install(struct ath_hal *ah, int32_t value); 681extern void ar9300_calibration_data_set(struct ath_hal *ah, int32_t source); 682extern int32_t ar9300_calibration_data_get(struct ath_hal *ah); 683extern int32_t ar9300_calibration_data_address_get(struct ath_hal *ah); 684extern void ar9300_calibration_data_address_set(struct ath_hal *ah, int32_t source); 685extern HAL_BOOL ar9300_calibration_data_read_flash(struct ath_hal *ah, long address, u_int8_t *buffer, int many); 686extern HAL_BOOL ar9300_calibration_data_read_eeprom(struct ath_hal *ah, long address, u_int8_t *buffer, int many); 687extern HAL_BOOL ar9300_calibration_data_read_otp(struct ath_hal *ah, long address, u_int8_t *buffer, int many, HAL_BOOL is_wifi); 688extern HAL_BOOL ar9300_calibration_data_read(struct ath_hal *ah, long address, u_int8_t *buffer, int many); 689extern int32_t ar9300_eeprom_size(struct ath_hal *ah); 690extern int32_t ar9300_otp_size(struct ath_hal *ah); 691extern HAL_BOOL ar9300_calibration_data_read_array(struct ath_hal *ah, int address, u_int8_t *buffer, int many); 692 693 694 695#if defined(WIN32) || defined(WIN64) 696#pragma pack (pop, ar9300) 697#endif 698 699#endif /* _ATH_AR9300_EEP_H_ */ 700