db88f6281.dts revision 235609 
1/*
2 * Copyright (c) 2009-2010 The FreeBSD Foundation
3 * All rights reserved.
4 *
5 * This software was developed by Semihalf under sponsorship from
6 * the FreeBSD Foundation.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * Marvell DB-88F6281 Device Tree Source.
30 *
31 * $FreeBSD: head/sys/boot/fdt/dts/db88f6281.dts 235609 2012-05-18 14:41:14Z gber $
32 */
33
34/dts-v1/;
35
36/ {
37	model = "mrvl,DB-88F6281";
38	compatible = "DB-88F6281-BP", "DB-88F6281-BP-A";
39	#address-cells = <1>;
40	#size-cells = <1>;
41
42	aliases {
43		ethernet0 = &enet0;
44		mpp = &MPP;
45		pci0 = &pci0;
46		serial0 = &serial0;
47		serial1 = &serial1;
48		soc = &SOC;
49		sram = &SRAM;
50	};
51
52	cpus {
53		#address-cells = <1>;
54		#size-cells = <0>;
55
56		cpu@0 {
57			device_type = "cpu";
58			compatible = "ARM,88FR131";
59			reg = <0x0>;
60			d-cache-line-size = <32>;	// 32 bytes
61			i-cache-line-size = <32>;	// 32 bytes
62			d-cache-size = <0x4000>;	// L1, 16K
63			i-cache-size = <0x4000>;	// L1, 16K
64			timebase-frequency = <0>;
65			bus-frequency = <0>;
66			clock-frequency = <0>;
67		};
68	};
69
70	memory {
71		device_type = "memory";
72		reg = <0x0 0x20000000>;		// 512M at 0x0
73	};
74
75	localbus@0 {
76		#address-cells = <2>;
77		#size-cells = <1>;
78		compatible = "mrvl,lbc";
79		bank-count = <3>;
80
81		/* This reflects CPU decode windows setup. */
82		ranges = <0x0 0x2f 0xf9300000 0x00100000>;
83
84		nand@0,0 {
85			#address-cells = <1>;
86			#size-cells = <1>;
87			compatible = "mrvl,nfc";
88			reg = <0x0 0x0 0x00100000>;
89			bank-width = <2>;
90			device-width = <1>;
91
92
93		};
94	};
95
96	SOC: soc88f6281@f1000000 {
97		#address-cells = <1>;
98		#size-cells = <1>;
99		compatible = "simple-bus";
100		ranges = <0x0 0xf1000000 0x00100000>;
101		bus-frequency = <0>;
102
103		PIC: pic@20200 {
104			interrupt-controller;
105			#address-cells = <0>;
106			#interrupt-cells = <1>;
107			reg = <0x20200 0x3c>;
108			compatible = "mrvl,pic";
109		};
110
111		timer@20300 {
112			compatible = "mrvl,timer";
113			reg = <0x20300 0x30>;
114			interrupts = <1>;
115			interrupt-parent = <&PIC>;
116			mrvl,has-wdt;
117		};
118
119		MPP: mpp@10000 {
120			#pin-cells = <2>;
121			compatible = "mrvl,mpp";
122			reg = <0x10000 0x34>;
123			pin-count = <50>;
124			pin-map = <
125				0  1		/* MPP[0]:  NF_IO[2] */
126				1  1		/* MPP[1]:  NF_IO[3] */
127				2  1		/* MPP[2]:  NF_IO[4] */
128				3  1		/* MPP[3]:  NF_IO[5] */
129				4  1		/* MPP[4]:  NF_IO[6] */
130				5  1		/* MPP[5]:  NF_IO[7] */
131				6  1		/* MPP[6]:  SYSRST_OUTn */
132				7  2		/* MPP[7]:  SPI_SCn */
133				8  1		/* MPP[8]:  TW_SDA */
134				9  1		/* MPP[9]:  TW_SCK */
135				10 3		/* MPP[10]: UA0_TXD */
136				11 3		/* MPP[11]: UA0_RXD */
137				12 1		/* MPP[12]: SD_CLK */
138				13 1		/* MPP[13]: SD_CMD */
139				14 1		/* MPP[14]: SD_D[0] */
140				15 1		/* MPP[15]: SD_D[1] */
141				16 1		/* MPP[16]: SD_D[2] */
142				17 1		/* MPP[17]: SD_D[3] */
143				18 1		/* MPP[18]: NF_IO[0] */
144				19 1		/* MPP[19]: NF_IO[1] */
145				20 5		/* MPP[20]: SATA1_AC */
146				21 5 >;		/* MPP[21]: SATA0_AC */
147		};
148
149		GPIO: gpio@10100 {
150			#gpio-cells = <3>;
151			compatible = "mrvl,gpio";
152			reg = <0x10100 0x20>;
153			gpio-controller;
154			interrupts = <35 36 37 38 39 40 41>;
155			interrupt-parent = <&PIC>;
156		};
157
158		rtc@10300 {
159			compatible = "mrvl,rtc";
160			reg = <0x10300 0x08>;
161		};
162
163		twsi@11000 {
164			#address-cells = <1>;
165			#size-cells = <0>;
166			compatible = "mrvl,twsi";
167			reg = <0x11000 0x20>;
168			interrupts = <43>;
169			interrupt-parent = <&PIC>;
170		};
171
172		enet0: ethernet@72000 {
173			#address-cells = <1>;
174			#size-cells = <1>;
175			model = "V2";
176			compatible = "mrvl,ge";
177			reg = <0x72000 0x2000>;
178			ranges = <0x0 0x72000 0x2000>;
179			local-mac-address = [ 00 00 00 00 00 00 ];
180			interrupts = <12 13 14 11 46>;
181			interrupt-parent = <&PIC>;
182			phy-handle = <&phy0>;
183
184			mdio@0 {
185				#address-cells = <1>;
186				#size-cells = <0>;
187				compatible = "mrvl,mdio";
188
189				phy0: ethernet-phy@0 {
190					reg = <0x8>;
191				};
192			};
193		};
194
195		serial0: serial@12000 {
196			compatible = "ns16550";
197			reg = <0x12000 0x20>;
198			reg-shift = <2>;
199			clock-frequency = <0>;
200			interrupts = <33>;
201			interrupt-parent = <&PIC>;
202		};
203
204		serial1: serial@12100 {
205			compatible = "ns16550";
206			reg = <0x12100 0x20>;
207			reg-shift = <2>;
208			clock-frequency = <0>;
209			interrupts = <34>;
210			interrupt-parent = <&PIC>;
211		};
212
213		crypto@30000 {
214			compatible = "mrvl,cesa";
215			reg = <0x30000 0x10000>;
216			interrupts = <22>;
217			interrupt-parent = <&PIC>;
218
219			sram-handle = <&SRAM>;
220		};
221
222		usb@50000 {
223			compatible = "mrvl,usb-ehci", "usb-ehci";
224			reg = <0x50000 0x1000>;
225			interrupts = <48 19>;
226			interrupt-parent = <&PIC>;
227		};
228
229		xor@60000 {
230			compatible = "mrvl,xor";
231			reg = <0x60000 0x1000>;
232			interrupts = <5 6 7 8>;
233			interrupt-parent = <&PIC>;
234		};
235
236		sata@80000 {
237			compatible = "mrvl,sata";
238			reg = <0x80000 0x6000>;
239			interrupts = <21>;
240			interrupt-parent = <&PIC>;
241		};
242	};
243
244	SRAM: sram@fd000000 {
245		compatible = "mrvl,cesa-sram";
246		reg = <0xfd000000 0x00100000>;
247	};
248
249	pci0: pcie@f1040000 {
250		compatible = "mrvl,pcie";
251		device_type = "pci";
252		#interrupt-cells = <1>;
253		#size-cells = <2>;
254		#address-cells = <3>;
255		reg = <0xf1040000 0x2000>;
256		bus-range = <0 255>;
257		ranges = <0x02000000 0x0 0xf1300000 0xf1300000 0x0 0x04000000
258			  0x01000000 0x0 0x00000000 0xf1100000 0x0 0x00100000>;
259		clock-frequency = <33333333>;
260		interrupt-parent = <&PIC>;
261		interrupts = <44>;
262		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
263		interrupt-map = <
264			/* IDSEL 0x1 */
265			0x0800 0x0 0x0 0x1 &PIC 0x9
266			0x0800 0x0 0x0 0x2 &PIC 0x9
267			0x0800 0x0 0x0 0x3 &PIC 0x9
268			0x0800 0x0 0x0 0x4 &PIC 0x9
269			>;
270		pcie@0 {
271			reg = <0x0 0x0 0x0 0x0 0x0>;
272			#size-cells = <2>;
273			#address-cells = <3>;
274			device_type = "pci";
275			ranges = <0x02000000 0x0 0xf1300000
276				  0x02000000 0x0 0xf1300000
277				  0x0 0x04000000
278
279				  0x01000000 0x0 0x0
280				  0x01000000 0x0 0x0
281				  0x0 0x00100000>;
282		};
283	};
284
285      	chosen {
286		stdin = "serial0";
287		stdout = "serial0";
288	};
289};
290