db78100.dts revision 208561
156083Skris/* 2280297Sjkim * Copyright (c) 2010 The FreeBSD Foundation 3280297Sjkim * All rights reserved. 4280297Sjkim * 5280297Sjkim * This software was developed by Semihalf under sponsorship from 656083Skris * the FreeBSD Foundation. 789837Skris * 856083Skris * Redistribution and use in source and binary forms, with or without 9280297Sjkim * modification, are permitted provided that the following conditions 10280297Sjkim * are met: 11280297Sjkim * 1. Redistributions of source code must retain the above copyright 12280297Sjkim * notice, this list of conditions and the following disclaimer. 13280297Sjkim * 2. Redistributions in binary form must reproduce the above copyright 14280297Sjkim * notice, this list of conditions and the following disclaimer in the 15280297Sjkim * documentation and/or other materials provided with the distribution. 16280297Sjkim * 17280297Sjkim * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1889837Skris * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1989837Skris * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20273144Sjkim * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 2189837Skris * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22109998Smarkm * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23280297Sjkim * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24280297Sjkim * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25280297Sjkim * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26280297Sjkim * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27280297Sjkim * SUCH DAMAGE. 28280297Sjkim * 29280297Sjkim * Marvell DB-78100 Device Tree Source. 3056083Skris * 3156083Skris * $FreeBSD: head/sys/boot/fdt/dts/db78100.dts 208561 2010-05-26 09:50:09Z raj $ 32280297Sjkim */ 33280297Sjkim 34280297Sjkim/dts-v1/; 35290207Sjkim 36290207Sjkim/ { 37290207Sjkim model = "mrvl,DB-78100"; 38290207Sjkim compatible = "DB-78100-BP", "DB-78100-BP-A"; 39290207Sjkim #address-cells = <1>; 40290207Sjkim #size-cells = <1>; 41290207Sjkim 42290207Sjkim aliases { 43290207Sjkim ethernet0 = &enet0; 44280297Sjkim serial0 = &serial0; 45280297Sjkim serial1 = &serial1; 46290207Sjkim mpp = &MPP; 47290207Sjkim }; 4856083Skris 49290207Sjkim cpus { 50290207Sjkim #address-cells = <1>; 51290207Sjkim #size-cells = <0>; 52290207Sjkim 53290207Sjkim cpu@0 { 54290207Sjkim device_type = "cpu"; 55290207Sjkim compatible = "ARM,88FR571"; 56290207Sjkim reg = <0x0>; 57290207Sjkim d-cache-line-size = <32>; // 32 bytes 58280297Sjkim i-cache-line-size = <32>; // 32 bytes 59280297Sjkim d-cache-size = <0x4000>; // L1, 16K 60280297Sjkim i-cache-size = <0x4000>; // L1, 16K 6156083Skris timebase-frequency = <0>; 62290207Sjkim bus-frequency = <0>; 63290207Sjkim clock-frequency = <0>; 64290207Sjkim }; 65280297Sjkim }; 66280297Sjkim 6756083Skris memory { 68280297Sjkim device_type = "memory"; 69280297Sjkim reg = <0x0 0x20000000>; // 512M at 0x0 70290207Sjkim }; 7189837Skris 72290207Sjkim localbus@f1000000 { 73280297Sjkim #address-cells = <2>; 74290207Sjkim #size-cells = <1>; 75290207Sjkim compatible = "mrvl,lbc"; 76290207Sjkim win-count = <14>; 77290207Sjkim 78280297Sjkim /* This reflects CPU decode windows setup. */ 79280297Sjkim ranges = <0x0 0x0f 0xf9300000 0x00100000 80280297Sjkim 0x1 0x1e 0xfa000000 0x00100000 81280297Sjkim 0x2 0x1d 0xfa100000 0x02000000 82280297Sjkim 0x3 0x1b 0xfc100000 0x00000400>; 83280297Sjkim 8456083Skris nor@0,0 { 85290207Sjkim #address-cells = <1>; 86280297Sjkim #size-cells = <1>; 87290207Sjkim compatible = "cfi-flash"; 88280297Sjkim reg = <0x0 0x0 0x00100000>; 89280297Sjkim bank-width = <2>; 90205128Ssimon device-width = <1>; 91290207Sjkim }; 92314125Sdelphij 93290207Sjkim led@1,0 { 94280297Sjkim #address-cells = <1>; 9556083Skris #size-cells = <1>; 96290207Sjkim compatible = "led"; 97314125Sdelphij reg = <0x1 0x0 0x00100000>; 98290207Sjkim }; 99280297Sjkim 10056083Skris nor@2,0 { 101280297Sjkim #address-cells = <1>; 102280297Sjkim #size-cells = <1>; 103314125Sdelphij compatible = "cfi-flash"; 104314125Sdelphij reg = <0x2 0x0 0x02000000>; 105314125Sdelphij bank-width = <2>; 106314125Sdelphij device-width = <1>; 107280297Sjkim }; 10856083Skris 10956083Skris nand@3,0 { 110280297Sjkim #address-cells = <1>; 111280297Sjkim #size-cells = <1>; 112280297Sjkim reg = <0x3 0x0 0x00100000>; 113290207Sjkim bank-width = <2>; 114290207Sjkim device-width = <1>; 115290207Sjkim }; 116290207Sjkim }; 117290207Sjkim 118290207Sjkim soc78100@f1000000 { 119290207Sjkim #address-cells = <1>; 120290207Sjkim #size-cells = <1>; 121290207Sjkim compatible = "simple-bus"; 122290207Sjkim ranges = <0x0 0xf1000000 0x00100000>; 123280297Sjkim bus-frequency = <0>; 124280297Sjkim 125280297Sjkim PIC: pic@20200 { 126280297Sjkim interrupt-controller; 127280297Sjkim #address-cells = <0>; 128280297Sjkim #interrupt-cells = <1>; 129280297Sjkim reg = <0x20200 0x3c>; 130280297Sjkim compatible = "mrvl,pic"; 131280297Sjkim }; 132290207Sjkim 13356083Skris timer@20300 { 134290207Sjkim compatible = "mrvl,timer"; 135290207Sjkim reg = <0x20300 0x30>; 136290207Sjkim interrupts = <8>; 137290207Sjkim interrupt-parent = <&PIC>; 138290207Sjkim mrvl,has-wdt; 139290207Sjkim }; 140290207Sjkim 141280297Sjkim MPP: mpp@10000 { 142280297Sjkim #pin-cells = <2>; 143280297Sjkim compatible = "mrvl,mpp"; 144280297Sjkim reg = <0x10000 0x34>; 145280297Sjkim pin-count = <50>; 146280297Sjkim pin-map = < 147290207Sjkim 0 2 /* MPP[0]: GE1_TXCLK */ 148290207Sjkim 1 2 /* MPP[1]: GE1_TXCTL */ 149280297Sjkim 2 2 /* MPP[2]: GE1_RXCTL */ 150280297Sjkim 3 2 /* MPP[3]: GE1_RXCLK */ 151290207Sjkim 4 2 /* MPP[4]: GE1_TXD[0] */ 152280297Sjkim 5 2 /* MPP[5]: GE1_TXD[1] */ 15356083Skris 6 2 /* MPP[6]: GE1_TXD[2] */ 154290207Sjkim 7 2 /* MPP[7]: GE1_TXD[3] */ 155280297Sjkim 8 2 /* MPP[8]: GE1_RXD[0] */ 156280297Sjkim 9 2 /* MPP[9]: GE1_RXD[1] */ 157280297Sjkim 10 2 /* MPP[10]: GE1_RXD[2] */ 158290207Sjkim 11 2 /* MPP[11]: GE1_RXD[3] */ 159280297Sjkim 13 3 /* MPP[13]: SYSRST_OUTn */ 160280297Sjkim 14 3 /* MPP[14]: SATA1_ACTn */ 16156083Skris 15 3 /* MPP[15]: SATA0_ACTn */ 162280297Sjkim 16 4 /* MPP[16]: UA2_TXD */ 163280297Sjkim 17 4 /* MPP[17]: UA2_RXD */ 164280297Sjkim 18 3 /* MPP[18]: <UNKNOWN> */ 165280297Sjkim 19 3 /* MPP[19]: <UNKNOWN> */ 166280297Sjkim 20 3 /* MPP[20]: <UNKNOWN> */ 167280297Sjkim 21 3 /* MPP[21]: <UNKNOWN> */ 168280297Sjkim 22 4 /* MPP[22]: UA3_TXD */ 169280297Sjkim 23 4 >; /* MPP[21]: UA3_RXD */ 170280297Sjkim }; 171280297Sjkim 172194206Ssimon GPIO: gpio@10100 { 173280297Sjkim #gpio-cells = <3>; 174280297Sjkim compatible = "mrvl,gpio"; 175280297Sjkim reg = <0x10100 0x20>; 176280297Sjkim gpio-controller; 177280297Sjkim interrupts = <56 57 58 59>; 178280297Sjkim interrupt-parent = <&PIC>; 179194206Ssimon }; 180280297Sjkim 181290207Sjkim rtc@10300 { 182273144Sjkim compatible = "mrvl,rtc"; 183290207Sjkim reg = <0x10300 0x08>; 184280297Sjkim }; 185290207Sjkim 186280297Sjkim twsi@11000 { 187273144Sjkim #address-cells = <1>; 188290207Sjkim #size-cells = <0>; 189280297Sjkim compatible = "mrvl,twsi"; 190280297Sjkim reg = <0x11000 0x20>; 191280297Sjkim interrupts = <2>; 19289837Skris interrupt-parent = <&PIC>; 193290207Sjkim }; 194280297Sjkim 19589837Skris twsi@11100 { 196290207Sjkim #address-cells = <1>; 197273144Sjkim #size-cells = <0>; 198280297Sjkim compatible = "mrvl,twsi"; 199290207Sjkim reg = <0x11100 0x20>; 200280297Sjkim interrupts = <3>; 201280297Sjkim interrupt-parent = <&PIC>; 202280297Sjkim }; 203280297Sjkim 204280297Sjkim enet0: ethernet@72000 { 205280297Sjkim #address-cells = <1>; 206280297Sjkim #size-cells = <1>; 207280297Sjkim model = "V2"; 208280297Sjkim compatible = "mrvl,ge"; 209280297Sjkim reg = <0x72000 0x2000>; 210273144Sjkim ranges = <0x0 0x72000 0x2000>; 211280297Sjkim local-mac-address = [ 00 00 00 00 00 00 ]; 212273144Sjkim interrupts = <41 42 43 40 70>; 213280297Sjkim interrupt-parent = <&PIC>; 214280297Sjkim phy-handle = <&phy0>; 215280297Sjkim 216280297Sjkim mdio@0 { 217280297Sjkim #address-cells = <1>; 218280297Sjkim #size-cells = <0>; 219280297Sjkim compatible = "mrvl,mdio"; 220273144Sjkim 221280297Sjkim phy0: ethernet-phy@0 { 222280297Sjkim reg = <0x8>; 223273144Sjkim }; 224280297Sjkim }; 225290207Sjkim }; 226280297Sjkim 227280297Sjkim enet1: ethernet@76000 { 228280297Sjkim #address-cells = <1>; 229280297Sjkim #size-cells = <1>; 230280297Sjkim model = "V2"; 23179998Skris compatible = "mrvl,ge"; 232280297Sjkim reg = <0x76000 0x2000>; 233280297Sjkim ranges = <0x0 0x76000 0x2000>; 234280297Sjkim local-mac-address = [ 00 00 00 00 00 00 ]; 235280297Sjkim interrupts = <45 46 47 44 70>; 236280297Sjkim interrupt-parent = <&PIC>; 237290207Sjkim phy-handle = <&phy0>; 238290207Sjkim 239280297Sjkim mdio@0 { 240280297Sjkim #address-cells = <1>; 241280297Sjkim #size-cells = <0>; 242280297Sjkim compatible = "mrvl,mdio"; 243280297Sjkim 244280297Sjkim phy0: ethernet-phy@0 { 245280297Sjkim reg = <0x9>; 24656083Skris }; 247160814Ssimon }; 248280297Sjkim }; 249280297Sjkim 250280297Sjkim serial0: serial@12000 { 251280297Sjkim compatible = "ns16550"; 252280297Sjkim reg = <0x12000 0x20>; 253280297Sjkim reg-shift = <2>; 254280297Sjkim clock-frequency = <0>; 255280297Sjkim interrupts = <12>; 25656083Skris interrupt-parent = <&PIC>; 257280297Sjkim }; 258280297Sjkim 259280297Sjkim serial1: serial@12100 { 260280297Sjkim compatible = "ns16550"; 261280297Sjkim reg = <0x12100 0x20>; 262280297Sjkim reg-shift = <2>; 263280297Sjkim clock-frequency = <0>; 264280297Sjkim interrupts = <13>; 265280297Sjkim interrupt-parent = <&PIC>; 266280297Sjkim }; 267280297Sjkim 268280297Sjkim usb@50000 { 269280297Sjkim compatible = "mrvl,usb-ehci", "usb-ehci"; 270280297Sjkim reg = <0x50000 0x1000>; 271280297Sjkim interrupts = <72 16>; 272280297Sjkim interrupt-parent = <&PIC>; 273280297Sjkim }; 274280297Sjkim 275280297Sjkim usb@51000 { 276280297Sjkim compatible = "mrvl,usb-ehci", "usb-ehci"; 277280297Sjkim reg = <0x51000 0x1000>; 278280297Sjkim interrupts = <72 17>; 279280297Sjkim interrupt-parent = <&PIC>; 280280297Sjkim }; 281280297Sjkim 282280297Sjkim usb@52000 { 283280297Sjkim compatible = "mrvl,usb-ehci", "usb-ehci"; 284280297Sjkim reg = <0x52000 0x1000>; 285280297Sjkim interrupts = <72 18>; 286160814Ssimon interrupt-parent = <&PIC>; 28756083Skris }; 288 289 xor@60000 { 290 compatible = "mrvl,xor"; 291 reg = <0x60000 0x1000>; 292 interrupts = <22 23>; 293 interrupt-parent = <&PIC>; 294 }; 295 296 crypto@90000 { 297 compatible = "mrvl,cesa"; 298 reg = <0x90000 0x10000>; 299 interrupts = <19>; 300 interrupt-parent = <&PIC>; 301 }; 302 303 sata@a0000 { 304 compatible = "mrvl,sata"; 305 reg = <0xa0000 0x6000>; 306 interrupts = <26>; 307 interrupt-parent = <&PIC>; 308 }; 309 }; 310 311 sram@fd000000 { 312 compatible = "mrvl,cesa-sram"; 313 reg = <0xfd000000 0x00100000>; 314 }; 315}; 316