at91rm9200_lowlevel.c revision 163533
1157873Simp/*- 2157873Simp * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3157873Simp * 4157873Simp * Redistribution and use in source and binary forms, with or without 5157873Simp * modification, are permitted provided that the following conditions 6157873Simp * are met: 7157873Simp * 1. Redistributions of source code must retain the above copyright 8157873Simp * notice, this list of conditions and the following disclaimer. 9157873Simp * 2. Redistributions in binary form must reproduce the above copyright 10157873Simp * notice, this list of conditions and the following disclaimer in the 11157873Simp * documentation and/or other materials provided with the distribution. 12157873Simp * 13157873Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14157873Simp * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15157873Simp * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16157873Simp * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17157873Simp * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18157873Simp * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19157873Simp * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20157873Simp * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21157873Simp * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22157873Simp * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23157873Simp * 24157873Simp * This software is derived from software provide by Kwikbyte who specifically 25157873Simp * disclaimed copyright on the code. 26157873Simp * 27157873Simp * $FreeBSD: head/sys/boot/arm/at91/libat91/at91rm9200_lowlevel.c 163533 2006-10-20 09:12:05Z imp $ 28157873Simp */ 29157873Simp 30157873Simp#include "at91rm9200.h" 31157873Simp#include "at91rm9200_lowlevel.h" 32157873Simp 33163533Simpextern int __bss_start__[]; 34163533Simpextern int __bss_end__[]; 35163533Simp 36157873Simp#define BAUD 115200 37157873Simp#define AT91C_US_ASYNC_MODE (AT91C_US_USMODE_NORMAL | AT91C_US_NBSTOP_1_BIT | \ 38157873Simp AT91C_US_PAR_NONE | AT91C_US_CHRL_8_BITS | AT91C_US_CLKS_CLOCK) 39157873Simp 40157873Simp/* 41157873Simp * void DefaultSystemInit(void) 42157873Simp * Load the system with sane values based on how the system is configured. 43157873Simp * at91rm9200_lowlevel.h is expected to define the necessary parameters. 44157873Simp */ 45157873Simpvoid 46157873Simp_init(void) 47157873Simp{ 48163533Simp int *i; 49163533Simp 50157873Simp AT91PS_USART pUSART = (AT91PS_USART)AT91C_BASE_DBGU; 51157873Simp AT91PS_PDC pPDC = (AT91PS_PDC)&(pUSART->US_RPR); 52157873Simp 53157873Simp register unsigned value; 54157873Simp volatile sdram_size_t *p = (sdram_size_t *)SDRAM_BASE; 55157873Simp 56163533Simp#if 0 57157873Simp#ifdef BOOT_TSC 58157873Simp // For the TSC board, we turn ON the one LED we have while 59157873Simp // early in boot. 60157873Simp AT91C_BASE_PIOC->PIO_PER = AT91C_PIO_PC10; 61157873Simp AT91C_BASE_PIOC->PIO_OER = AT91C_PIO_PC10; 62157873Simp AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC10; 63157873Simp#endif 64163533Simp#endif 65157873Simp 66157873Simp // configure clocks 67157873Simp // assume: 68157873Simp // main osc = 10Mhz 69157873Simp // PLLB configured for 96MHz (48MHz after div) 70157873Simp // CSS = PLLB 71157873Simp // set PLLA = 180MHz 72157873Simp // assume main osc = 10Mhz 73157873Simp // div = 5 , out = 2 (150MHz = 240MHz) 74157873Simp value = AT91C_BASE_CKGR->CKGR_PLLAR; 75157873Simp value &= ~(AT91C_CKGR_DIVA | AT91C_CKGR_OUTA | AT91C_CKGR_MULA); 76157873Simp value |= OSC_MAIN_FREQ_DIV | AT91C_CKGR_OUTA_2 | AT91C_CKGR_SRCA | 77157873Simp ((OSC_MAIN_MULT - 1) << 16); 78157873Simp AT91C_BASE_CKGR->CKGR_PLLAR = value; 79157873Simp 80157873Simp // wait for lock 81157873Simp while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA)) 82157873Simp continue; 83157873Simp 84157873Simp // change divider = 3, pres = 1 85157873Simp value = AT91C_BASE_PMC->PMC_MCKR; 86157873Simp value &= ~(AT91C_PMC_MDIV | AT91C_PMC_PRES); 87157873Simp value |= AT91C_PMC_MDIV_3 | AT91C_PMC_PRES_CLK; 88157873Simp AT91C_BASE_PMC->PMC_MCKR = value; 89157873Simp 90157873Simp // wait for update 91157873Simp while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) 92157873Simp continue; 93157873Simp 94157873Simp // change CSS = PLLA 95157873Simp value &= ~AT91C_PMC_CSS; 96157873Simp value |= AT91C_PMC_CSS_PLLA_CLK; 97157873Simp AT91C_BASE_PMC->PMC_MCKR = value; 98157873Simp 99157873Simp // wait for update 100157873Simp while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) 101157873Simp continue; 102157873Simp 103157924Simp#ifdef BOOT_KB9202 104157924Simp // setup flash access (allow ample margin) 105157924Simp // 9 wait states, 1 setup, 1 hold, 1 float for 8-bit device 106157924Simp ((AT91PS_SMC2)AT91C_BASE_SMC2)->SMC2_CSR[0] = 107157924Simp AT91C_SMC2_WSEN | 108157924Simp (9 & AT91C_SMC2_NWS) | 109157924Simp ((1 << 8) & AT91C_SMC2_TDF) | 110157924Simp AT91C_SMC2_DBW_8 | 111157924Simp ((1 << 24) & AT91C_SMC2_RWSETUP) | 112157924Simp ((1 << 29) & AT91C_SMC2_RWHOLD); 113157924Simp#endif 114157924Simp 115157873Simp // setup SDRAM access 116157873Simp // EBI chip-select register (CS1 = SDRAM controller) 117157873Simp // 9 col, 13row, 4 bank, CAS2 118157873Simp // write recovery = 2 (Twr) 119157873Simp // row cycle = 5 (Trc) 120157873Simp // precharge delay = 2 (Trp) 121157873Simp // row to col delay 2 (Trcd) 122157873Simp // active to precharge = 4 (Tras) 123157873Simp // exit self refresh to active = 6 (Txsr) 124157873Simp value = ((AT91PS_EBI)AT91C_BASE_EBI)->EBI_CSA; 125157873Simp value &= ~AT91C_EBI_CS1A; 126157873Simp value |= AT91C_EBI_CS1A_SDRAMC; 127157873Simp AT91C_BASE_EBI->EBI_CSA = value; 128157873Simp 129157873Simp AT91C_BASE_SDRC->SDRC_CR = 130157873Simp AT91C_SDRC_NC_9 | 131157873Simp AT91C_SDRC_NR_13 | 132157873Simp AT91C_SDRC_NB_4_BANKS | 133157873Simp AT91C_SDRC_CAS_2 | 134157873Simp ((2 << 7) & AT91C_SDRC_TWR) | 135157873Simp ((5 << 11) & AT91C_SDRC_TRC) | 136157873Simp ((2 << 15) & AT91C_SDRC_TRP) | 137157873Simp ((2 << 19) & AT91C_SDRC_TRCD) | 138157873Simp ((4 << 23) & AT91C_SDRC_TRAS) | 139157873Simp ((6 << 27) & AT91C_SDRC_TXSR); 140157873Simp 141157873Simp // Step 1: We assume 200us of idle time. 142157873Simp // Step 2: Issue an all banks precharge command 143157873Simp AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_PRCGALL_CMD; 144157873Simp *p = 0; 145157873Simp 146157873Simp // Step 3: Issue 8 Auto-refresh (CBR) cycles 147157873Simp AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_RFSH_CMD; 148157873Simp *p = 0; 149157873Simp *p = 0; 150157873Simp *p = 0; 151157873Simp *p = 0; 152157873Simp *p = 0; 153157873Simp *p = 0; 154157873Simp *p = 0; 155157873Simp *p = 0; 156157873Simp 157157873Simp // Step 4: Issue an Mode Set Register (MRS) cycle to program in 158157873Simp // the parameters that we setup in the SDRC_CR register above. 159157873Simp AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_LMR_CMD; 160157873Simp *p = 0; 161157873Simp 162157873Simp // Step 5: set the refresh timer and access memory to start it 163157873Simp // running. We have to wait 3 clocks after the LMR_CMD above, 164157873Simp // and this fits the bill nicely. 165157873Simp AT91C_BASE_SDRC->SDRC_TR = 7 * AT91C_MASTER_CLOCK / 1000000; 166157873Simp *p = 0; 167157873Simp 168157873Simp // Step 6: Set normal mode. 169157873Simp AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_NORMAL_CMD; 170157873Simp *p = 0; 171157873Simp 172157873Simp#if SDRAM_WIDTH == AT91C_SDRC_DBW_32_BITS 173157873Simp // Turn on the upper 16 bits on the SDRAM bus. 174157873Simp AT91C_BASE_PIOC->PIO_ASR = 0xffff0000; 175157873Simp AT91C_BASE_PIOC->PIO_PDR = 0xffff0000; 176157873Simp#endif 177157873Simp // Configure DBGU -use local routine optimized for space 178157873Simp AT91C_BASE_PIOA->PIO_ASR = AT91C_PA31_DTXD | AT91C_PA30_DRXD; 179157873Simp AT91C_BASE_PIOA->PIO_PDR = AT91C_PA31_DTXD | AT91C_PA30_DRXD; 180157873Simp pUSART->US_IDR = (unsigned int) -1; 181157873Simp pUSART->US_CR = 182157924Simp AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS; 183157873Simp pUSART->US_BRGR = ((((AT91C_MASTER_CLOCK*10)/(BAUD*16))+5)/10); 184157873Simp pUSART->US_TTGR = 0; 185157873Simp pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; 186157873Simp pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; 187157873Simp pPDC->PDC_TNPR = 0; 188157873Simp pPDC->PDC_TNCR = 0; 189157873Simp 190157873Simp pPDC->PDC_RNPR = 0; 191157873Simp pPDC->PDC_RNCR = 0; 192157873Simp 193157873Simp pPDC->PDC_TPR = 0; 194157873Simp pPDC->PDC_TCR = 0; 195157873Simp 196157873Simp pPDC->PDC_RPR = 0; 197157873Simp pPDC->PDC_RCR = 0; 198157873Simp 199157873Simp pPDC->PDC_PTCR = AT91C_PDC_RXTEN; 200157873Simp pPDC->PDC_PTCR = AT91C_PDC_TXTEN; 201157873Simp 202157873Simp pUSART->US_MR = AT91C_US_ASYNC_MODE; 203157873Simp pUSART->US_CR = AT91C_US_TXEN; 204157873Simp pUSART->US_CR = AT91C_US_RXEN; 205163533Simp 206163533Simp /* Zero BSS now that we have memory setup */ 207163533Simp i = (int *)__bss_start__; 208163533Simp while (i < (int *)__bss_end__) 209163533Simp *i++ = 0; 210157873Simp} 211