at91rm9200_lowlevel.c revision 157873
1157873Simp/*- 2157873Simp * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3157873Simp * 4157873Simp * Redistribution and use in source and binary forms, with or without 5157873Simp * modification, are permitted provided that the following conditions 6157873Simp * are met: 7157873Simp * 1. Redistributions of source code must retain the above copyright 8157873Simp * notice, this list of conditions and the following disclaimer. 9157873Simp * 2. Redistributions in binary form must reproduce the above copyright 10157873Simp * notice, this list of conditions and the following disclaimer in the 11157873Simp * documentation and/or other materials provided with the distribution. 12157873Simp * 13157873Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14157873Simp * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15157873Simp * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16157873Simp * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17157873Simp * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18157873Simp * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19157873Simp * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20157873Simp * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21157873Simp * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22157873Simp * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23157873Simp * 24157873Simp * This software is derived from software provide by Kwikbyte who specifically 25157873Simp * disclaimed copyright on the code. 26157873Simp * 27157873Simp * $FreeBSD: head/sys/boot/arm/at91/libat91/at91rm9200_lowlevel.c 157873 2006-04-19 17:16:49Z imp $ 28157873Simp */ 29157873Simp 30157873Simp#include "at91rm9200.h" 31157873Simp#include "at91rm9200_lowlevel.h" 32157873Simp 33157873Simp#define BAUD 115200 34157873Simp#define AT91C_US_ASYNC_MODE (AT91C_US_USMODE_NORMAL | AT91C_US_NBSTOP_1_BIT | \ 35157873Simp AT91C_US_PAR_NONE | AT91C_US_CHRL_8_BITS | AT91C_US_CLKS_CLOCK) 36157873Simp 37157873Simp/* 38157873Simp * void DefaultSystemInit(void) 39157873Simp * Load the system with sane values based on how the system is configured. 40157873Simp * at91rm9200_lowlevel.h is expected to define the necessary parameters. 41157873Simp */ 42157873Simpvoid 43157873Simp_init(void) 44157873Simp{ 45157873Simp AT91PS_USART pUSART = (AT91PS_USART)AT91C_BASE_DBGU; 46157873Simp AT91PS_PDC pPDC = (AT91PS_PDC)&(pUSART->US_RPR); 47157873Simp 48157873Simp register unsigned value; 49157873Simp volatile sdram_size_t *p = (sdram_size_t *)SDRAM_BASE; 50157873Simp 51157873Simp#ifdef BOOT_TSC 52157873Simp // For the TSC board, we turn ON the one LED we have while 53157873Simp // early in boot. 54157873Simp AT91C_BASE_PIOC->PIO_PER = AT91C_PIO_PC10; 55157873Simp AT91C_BASE_PIOC->PIO_OER = AT91C_PIO_PC10; 56157873Simp AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC10; 57157873Simp#endif 58157873Simp 59157873Simp // configure clocks 60157873Simp // assume: 61157873Simp // main osc = 10Mhz 62157873Simp // PLLB configured for 96MHz (48MHz after div) 63157873Simp // CSS = PLLB 64157873Simp // set PLLA = 180MHz 65157873Simp // assume main osc = 10Mhz 66157873Simp // div = 5 , out = 2 (150MHz = 240MHz) 67157873Simp value = AT91C_BASE_CKGR->CKGR_PLLAR; 68157873Simp value &= ~(AT91C_CKGR_DIVA | AT91C_CKGR_OUTA | AT91C_CKGR_MULA); 69157873Simp value |= OSC_MAIN_FREQ_DIV | AT91C_CKGR_OUTA_2 | AT91C_CKGR_SRCA | 70157873Simp ((OSC_MAIN_MULT - 1) << 16); 71157873Simp AT91C_BASE_CKGR->CKGR_PLLAR = value; 72157873Simp 73157873Simp // wait for lock 74157873Simp while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA)) 75157873Simp continue; 76157873Simp 77157873Simp // change divider = 3, pres = 1 78157873Simp value = AT91C_BASE_PMC->PMC_MCKR; 79157873Simp value &= ~(AT91C_PMC_MDIV | AT91C_PMC_PRES); 80157873Simp value |= AT91C_PMC_MDIV_3 | AT91C_PMC_PRES_CLK; 81157873Simp AT91C_BASE_PMC->PMC_MCKR = value; 82157873Simp 83157873Simp // wait for update 84157873Simp while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) 85157873Simp continue; 86157873Simp 87157873Simp // change CSS = PLLA 88157873Simp value &= ~AT91C_PMC_CSS; 89157873Simp value |= AT91C_PMC_CSS_PLLA_CLK; 90157873Simp AT91C_BASE_PMC->PMC_MCKR = value; 91157873Simp 92157873Simp // wait for update 93157873Simp while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) 94157873Simp continue; 95157873Simp 96157873Simp // setup SDRAM access 97157873Simp // EBI chip-select register (CS1 = SDRAM controller) 98157873Simp // 9 col, 13row, 4 bank, CAS2 99157873Simp // write recovery = 2 (Twr) 100157873Simp // row cycle = 5 (Trc) 101157873Simp // precharge delay = 2 (Trp) 102157873Simp // row to col delay 2 (Trcd) 103157873Simp // active to precharge = 4 (Tras) 104157873Simp // exit self refresh to active = 6 (Txsr) 105157873Simp value = ((AT91PS_EBI)AT91C_BASE_EBI)->EBI_CSA; 106157873Simp value &= ~AT91C_EBI_CS1A; 107157873Simp value |= AT91C_EBI_CS1A_SDRAMC; 108157873Simp AT91C_BASE_EBI->EBI_CSA = value; 109157873Simp 110157873Simp AT91C_BASE_SDRC->SDRC_CR = 111157873Simp AT91C_SDRC_NC_9 | 112157873Simp AT91C_SDRC_NR_13 | 113157873Simp AT91C_SDRC_NB_4_BANKS | 114157873Simp AT91C_SDRC_CAS_2 | 115157873Simp ((2 << 7) & AT91C_SDRC_TWR) | 116157873Simp ((5 << 11) & AT91C_SDRC_TRC) | 117157873Simp ((2 << 15) & AT91C_SDRC_TRP) | 118157873Simp ((2 << 19) & AT91C_SDRC_TRCD) | 119157873Simp ((4 << 23) & AT91C_SDRC_TRAS) | 120157873Simp ((6 << 27) & AT91C_SDRC_TXSR); 121157873Simp 122157873Simp // Step 1: We assume 200us of idle time. 123157873Simp // Step 2: Issue an all banks precharge command 124157873Simp AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_PRCGALL_CMD; 125157873Simp *p = 0; 126157873Simp 127157873Simp // Step 3: Issue 8 Auto-refresh (CBR) cycles 128157873Simp AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_RFSH_CMD; 129157873Simp *p = 0; 130157873Simp *p = 0; 131157873Simp *p = 0; 132157873Simp *p = 0; 133157873Simp *p = 0; 134157873Simp *p = 0; 135157873Simp *p = 0; 136157873Simp *p = 0; 137157873Simp 138157873Simp // Step 4: Issue an Mode Set Register (MRS) cycle to program in 139157873Simp // the parameters that we setup in the SDRC_CR register above. 140157873Simp AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_LMR_CMD; 141157873Simp *p = 0; 142157873Simp 143157873Simp // Step 5: set the refresh timer and access memory to start it 144157873Simp // running. We have to wait 3 clocks after the LMR_CMD above, 145157873Simp // and this fits the bill nicely. 146157873Simp AT91C_BASE_SDRC->SDRC_TR = 7 * AT91C_MASTER_CLOCK / 1000000; 147157873Simp *p = 0; 148157873Simp 149157873Simp // Step 6: Set normal mode. 150157873Simp AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_NORMAL_CMD; 151157873Simp *p = 0; 152157873Simp 153157873Simp#if SDRAM_WIDTH == AT91C_SDRC_DBW_32_BITS 154157873Simp // Turn on the upper 16 bits on the SDRAM bus. 155157873Simp AT91C_BASE_PIOC->PIO_ASR = 0xffff0000; 156157873Simp AT91C_BASE_PIOC->PIO_PDR = 0xffff0000; 157157873Simp#endif 158157873Simp // Configure DBGU -use local routine optimized for space 159157873Simp AT91C_BASE_PIOA->PIO_ASR = AT91C_PA31_DTXD | AT91C_PA30_DRXD; 160157873Simp AT91C_BASE_PIOA->PIO_PDR = AT91C_PA31_DTXD | AT91C_PA30_DRXD; 161157873Simp pUSART->US_IDR = (unsigned int) -1; 162157873Simp pUSART->US_CR = 163157873Simp AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS; 164157873Simp pUSART->US_BRGR = ((((AT91C_MASTER_CLOCK*10)/(BAUD*16))+5)/10); 165157873Simp pUSART->US_TTGR = 0; 166157873Simp pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; 167157873Simp pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; 168157873Simp pPDC->PDC_TNPR = 0; 169157873Simp pPDC->PDC_TNCR = 0; 170157873Simp 171157873Simp pPDC->PDC_RNPR = 0; 172157873Simp pPDC->PDC_RNCR = 0; 173157873Simp 174157873Simp pPDC->PDC_TPR = 0; 175157873Simp pPDC->PDC_TCR = 0; 176157873Simp 177157873Simp pPDC->PDC_RPR = 0; 178157873Simp pPDC->PDC_RCR = 0; 179157873Simp 180157873Simp pPDC->PDC_PTCR = AT91C_PDC_RXTEN; 181157873Simp pPDC->PDC_PTCR = AT91C_PDC_TXTEN; 182157873Simp 183157873Simp pUSART->US_MR = AT91C_US_ASYNC_MODE; 184157873Simp pUSART->US_CR = AT91C_US_TXEN; 185157873Simp pUSART->US_CR = AT91C_US_RXEN; 186157873Simp} 187