1157873Simp/*- 2157873Simp * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3157873Simp * 4157873Simp * Redistribution and use in source and binary forms, with or without 5157873Simp * modification, are permitted provided that the following conditions 6157873Simp * are met: 7157873Simp * 1. Redistributions of source code must retain the above copyright 8157873Simp * notice, this list of conditions and the following disclaimer. 9157873Simp * 2. Redistributions in binary form must reproduce the above copyright 10157873Simp * notice, this list of conditions and the following disclaimer in the 11157873Simp * documentation and/or other materials provided with the distribution. 12157873Simp * 13157873Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14157873Simp * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15157873Simp * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16157873Simp * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17157873Simp * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18157873Simp * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19157873Simp * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20157873Simp * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21157873Simp * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22157873Simp * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23157873Simp * 24157873Simp * This software is derived from software provide by Kwikbyte who specifically 25157873Simp * disclaimed copyright on the code. 26157873Simp * 27157873Simp * $FreeBSD: releng/10.2/sys/boot/arm/at91/libat91/at91rm9200_lowlevel.c 238463 2012-07-15 05:35:14Z imp $ 28157873Simp */ 29157873Simp 30157873Simp#include "at91rm9200.h" 31157873Simp#include "at91rm9200_lowlevel.h" 32157873Simp 33163533Simpextern int __bss_start__[]; 34163533Simpextern int __bss_end__[]; 35163533Simp 36157873Simp#define BAUD 115200 37157873Simp#define AT91C_US_ASYNC_MODE (AT91C_US_USMODE_NORMAL | AT91C_US_NBSTOP_1_BIT | \ 38157873Simp AT91C_US_PAR_NONE | AT91C_US_CHRL_8_BITS | AT91C_US_CLKS_CLOCK) 39157873Simp 40157873Simp/* 41157873Simp * void DefaultSystemInit(void) 42157873Simp * Load the system with sane values based on how the system is configured. 43157873Simp * at91rm9200_lowlevel.h is expected to define the necessary parameters. 44157873Simp */ 45157873Simpvoid 46157873Simp_init(void) 47157873Simp{ 48163533Simp int *i; 49163533Simp 50157873Simp AT91PS_USART pUSART = (AT91PS_USART)AT91C_BASE_DBGU; 51157873Simp AT91PS_PDC pPDC = (AT91PS_PDC)&(pUSART->US_RPR); 52157873Simp 53157873Simp register unsigned value; 54157873Simp volatile sdram_size_t *p = (sdram_size_t *)SDRAM_BASE; 55157873Simp 56168013Simp AT91C_BASE_ST->ST_RTMR = 1; 57157873Simp#ifdef BOOT_TSC 58157873Simp // For the TSC board, we turn ON the one LED we have while 59157873Simp // early in boot. 60157873Simp AT91C_BASE_PIOC->PIO_PER = AT91C_PIO_PC10; 61157873Simp AT91C_BASE_PIOC->PIO_OER = AT91C_PIO_PC10; 62157873Simp AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC10; 63157873Simp#endif 64164137Simp 65171426Simp#if defined(BOOT_KB920X) 66164137Simp AT91C_BASE_PIOC->PIO_PER = AT91C_PIO_PC18 | AT91C_PIO_PC19 | 67164137Simp AT91C_PIO_PC20; 68164137Simp AT91C_BASE_PIOC->PIO_OER = AT91C_PIO_PC18 | AT91C_PIO_PC19 | 69164137Simp AT91C_PIO_PC20; 70164137Simp AT91C_BASE_PIOC->PIO_SODR = AT91C_PIO_PC18 | AT91C_PIO_PC19 | 71164137Simp AT91C_PIO_PC20; 72164137Simp AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC18; 73163533Simp#endif 74157873Simp 75157873Simp // configure clocks 76157873Simp // assume: 77157873Simp // main osc = 10Mhz 78157873Simp // PLLB configured for 96MHz (48MHz after div) 79157873Simp // CSS = PLLB 80157873Simp // set PLLA = 180MHz 81157873Simp // assume main osc = 10Mhz 82157873Simp // div = 5 , out = 2 (150MHz = 240MHz) 83157873Simp value = AT91C_BASE_CKGR->CKGR_PLLAR; 84157873Simp value &= ~(AT91C_CKGR_DIVA | AT91C_CKGR_OUTA | AT91C_CKGR_MULA); 85157873Simp value |= OSC_MAIN_FREQ_DIV | AT91C_CKGR_OUTA_2 | AT91C_CKGR_SRCA | 86157873Simp ((OSC_MAIN_MULT - 1) << 16); 87157873Simp AT91C_BASE_CKGR->CKGR_PLLAR = value; 88157873Simp 89157873Simp // wait for lock 90157873Simp while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA)) 91157873Simp continue; 92157873Simp 93157873Simp // change divider = 3, pres = 1 94157873Simp value = AT91C_BASE_PMC->PMC_MCKR; 95157873Simp value &= ~(AT91C_PMC_MDIV | AT91C_PMC_PRES); 96157873Simp value |= AT91C_PMC_MDIV_3 | AT91C_PMC_PRES_CLK; 97157873Simp AT91C_BASE_PMC->PMC_MCKR = value; 98157873Simp 99157873Simp // wait for update 100157873Simp while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) 101157873Simp continue; 102157873Simp 103157873Simp // change CSS = PLLA 104157873Simp value &= ~AT91C_PMC_CSS; 105157873Simp value |= AT91C_PMC_CSS_PLLA_CLK; 106157873Simp AT91C_BASE_PMC->PMC_MCKR = value; 107157873Simp 108157873Simp // wait for update 109157873Simp while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) 110157873Simp continue; 111157873Simp 112164137Simp#ifdef BOOT_KB920X 113157924Simp // setup flash access (allow ample margin) 114157924Simp // 9 wait states, 1 setup, 1 hold, 1 float for 8-bit device 115157924Simp ((AT91PS_SMC2)AT91C_BASE_SMC2)->SMC2_CSR[0] = 116157924Simp AT91C_SMC2_WSEN | 117157924Simp (9 & AT91C_SMC2_NWS) | 118157924Simp ((1 << 8) & AT91C_SMC2_TDF) | 119157924Simp AT91C_SMC2_DBW_8 | 120157924Simp ((1 << 24) & AT91C_SMC2_RWSETUP) | 121157924Simp ((1 << 29) & AT91C_SMC2_RWHOLD); 122157924Simp#endif 123157924Simp 124157873Simp // setup SDRAM access 125157873Simp // EBI chip-select register (CS1 = SDRAM controller) 126157873Simp // 9 col, 13row, 4 bank, CAS2 127157873Simp // write recovery = 2 (Twr) 128157873Simp // row cycle = 5 (Trc) 129157873Simp // precharge delay = 2 (Trp) 130157873Simp // row to col delay 2 (Trcd) 131157873Simp // active to precharge = 4 (Tras) 132157873Simp // exit self refresh to active = 6 (Txsr) 133157873Simp value = ((AT91PS_EBI)AT91C_BASE_EBI)->EBI_CSA; 134157873Simp value &= ~AT91C_EBI_CS1A; 135157873Simp value |= AT91C_EBI_CS1A_SDRAMC; 136157873Simp AT91C_BASE_EBI->EBI_CSA = value; 137157873Simp 138157873Simp AT91C_BASE_SDRC->SDRC_CR = 139204900Sticso#if defined(KB9202_B) || defined(SDRAM_128M) 140171426Simp AT91C_SDRC_NC_10 | 141171426Simp#else 142157873Simp AT91C_SDRC_NC_9 | 143171426Simp#endif 144157873Simp AT91C_SDRC_NR_13 | 145157873Simp AT91C_SDRC_NB_4_BANKS | 146157873Simp AT91C_SDRC_CAS_2 | 147157873Simp ((2 << 7) & AT91C_SDRC_TWR) | 148157873Simp ((5 << 11) & AT91C_SDRC_TRC) | 149157873Simp ((2 << 15) & AT91C_SDRC_TRP) | 150157873Simp ((2 << 19) & AT91C_SDRC_TRCD) | 151157873Simp ((4 << 23) & AT91C_SDRC_TRAS) | 152157873Simp ((6 << 27) & AT91C_SDRC_TXSR); 153157873Simp 154157873Simp // Step 1: We assume 200us of idle time. 155157873Simp // Step 2: Issue an all banks precharge command 156157873Simp AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_PRCGALL_CMD; 157157873Simp *p = 0; 158157873Simp 159157873Simp // Step 3: Issue 8 Auto-refresh (CBR) cycles 160157873Simp AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_RFSH_CMD; 161157873Simp *p = 0; 162157873Simp *p = 0; 163157873Simp *p = 0; 164157873Simp *p = 0; 165157873Simp *p = 0; 166157873Simp *p = 0; 167157873Simp *p = 0; 168157873Simp *p = 0; 169157873Simp 170157873Simp // Step 4: Issue an Mode Set Register (MRS) cycle to program in 171157873Simp // the parameters that we setup in the SDRC_CR register above. 172157873Simp AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_LMR_CMD; 173157873Simp *p = 0; 174157873Simp 175157873Simp // Step 5: set the refresh timer and access memory to start it 176157873Simp // running. We have to wait 3 clocks after the LMR_CMD above, 177157873Simp // and this fits the bill nicely. 178157873Simp AT91C_BASE_SDRC->SDRC_TR = 7 * AT91C_MASTER_CLOCK / 1000000; 179157873Simp *p = 0; 180157873Simp 181157873Simp // Step 6: Set normal mode. 182157873Simp AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_NORMAL_CMD; 183157873Simp *p = 0; 184157873Simp 185157873Simp#if SDRAM_WIDTH == AT91C_SDRC_DBW_32_BITS 186157873Simp // Turn on the upper 16 bits on the SDRAM bus. 187157873Simp AT91C_BASE_PIOC->PIO_ASR = 0xffff0000; 188157873Simp AT91C_BASE_PIOC->PIO_PDR = 0xffff0000; 189157873Simp#endif 190157873Simp // Configure DBGU -use local routine optimized for space 191238463Simp AT91C_BASE_PIOA->PIO_ASR = AT91C_PIO_PA31 | AT91C_PIO_PA30; 192238463Simp AT91C_BASE_PIOA->PIO_PDR = AT91C_PIO_PA31 | AT91C_PIO_PA30; 193157873Simp pUSART->US_IDR = (unsigned int) -1; 194157873Simp pUSART->US_CR = 195157924Simp AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS; 196157873Simp pUSART->US_BRGR = ((((AT91C_MASTER_CLOCK*10)/(BAUD*16))+5)/10); 197157873Simp pUSART->US_TTGR = 0; 198157873Simp pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; 199157873Simp pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; 200157873Simp pPDC->PDC_TNPR = 0; 201157873Simp pPDC->PDC_TNCR = 0; 202157873Simp 203157873Simp pPDC->PDC_RNPR = 0; 204157873Simp pPDC->PDC_RNCR = 0; 205157873Simp 206157873Simp pPDC->PDC_TPR = 0; 207157873Simp pPDC->PDC_TCR = 0; 208157873Simp 209157873Simp pPDC->PDC_RPR = 0; 210157873Simp pPDC->PDC_RCR = 0; 211157873Simp 212157873Simp pPDC->PDC_PTCR = AT91C_PDC_RXTEN; 213157873Simp pPDC->PDC_PTCR = AT91C_PDC_TXTEN; 214157873Simp 215157873Simp pUSART->US_MR = AT91C_US_ASYNC_MODE; 216157873Simp pUSART->US_CR = AT91C_US_TXEN; 217157873Simp pUSART->US_CR = AT91C_US_RXEN; 218163533Simp 219163533Simp /* Zero BSS now that we have memory setup */ 220163533Simp i = (int *)__bss_start__; 221163533Simp while (i < (int *)__bss_end__) 222163533Simp *i++ = 0; 223157873Simp} 224