pxareg.h revision 236987
1179595Sbenno/* $NetBSD: pxa2x0reg.h,v 1.9 2006/04/10 04:13:58 simonb Exp $ */ 2179595Sbenno 3179595Sbenno/* 4179595Sbenno * Copyright (c) 2002 Genetec Corporation. All rights reserved. 5179595Sbenno * Written by Hiroyuki Bessho for Genetec Corporation. 6179595Sbenno * 7179595Sbenno * Redistribution and use in source and binary forms, with or without 8179595Sbenno * modification, are permitted provided that the following conditions 9179595Sbenno * are met: 10179595Sbenno * 1. Redistributions of source code must retain the above copyright 11179595Sbenno * notice, this list of conditions and the following disclaimer. 12179595Sbenno * 2. Redistributions in binary form must reproduce the above copyright 13179595Sbenno * notice, this list of conditions and the following disclaimer in the 14179595Sbenno * documentation and/or other materials provided with the distribution. 15179595Sbenno * 3. All advertising materials mentioning features or use of this software 16179595Sbenno * must display the following acknowledgement: 17179595Sbenno * This product includes software developed for the NetBSD Project by 18179595Sbenno * Genetec Corporation. 19236987Simp * 4. The name of Genetec Corporation may not be used to endorse or 20179595Sbenno * promote products derived from this software without specific prior 21179595Sbenno * written permission. 22179595Sbenno * 23179595Sbenno * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 24179595Sbenno * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25179595Sbenno * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26179595Sbenno * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 27179595Sbenno * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28179595Sbenno * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29179595Sbenno * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30179595Sbenno * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31179595Sbenno * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32179595Sbenno * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33179595Sbenno * POSSIBILITY OF SUCH DAMAGE. 34179595Sbenno * 35179595Sbenno * $FreeBSD: head/sys/arm/xscale/pxa/pxareg.h 236987 2012-06-13 04:38:09Z imp $ 36179595Sbenno */ 37179595Sbenno 38179595Sbenno 39179595Sbenno/* 40179595Sbenno * Intel PXA2[15]0 processor is XScale based integrated CPU 41179595Sbenno * 42179595Sbenno * Reference: 43179595Sbenno * Intel(r) PXA250 and PXA210 Application Processors 44179595Sbenno * Developer's Manual 45179595Sbenno * (278522-001.pdf) 46179595Sbenno */ 47179595Sbenno#ifndef _ARM_XSCALE_PXAREG_H_ 48179595Sbenno#define _ARM_XSCALE_PXAREG_H_ 49179595Sbenno 50179595Sbenno/* Borrow some register definitions from sa11x0 */ 51179595Sbenno#include <arm/sa11x0/sa11x0_reg.h> 52179595Sbenno 53179595Sbenno#ifndef _LOCORE 54179595Sbenno#include <sys/types.h> /* for uint32_t */ 55179595Sbenno#endif 56179595Sbenno 57179595Sbenno/* 58179595Sbenno * Chip select domains 59179595Sbenno */ 60179595Sbenno#define PXA2X0_CS0_START 0x00000000 61179595Sbenno#define PXA2X0_CS1_START 0x04000000 62179595Sbenno#define PXA2X0_CS2_START 0x08000000 63179595Sbenno#define PXA2X0_CS3_START 0x0c000000 64179595Sbenno#define PXA2X0_CS4_START 0x10000000 65179595Sbenno#define PXA2X0_CS5_START 0x14000000 66179595Sbenno#define PXA2X0_CS_SIZE 0x04000000 67179595Sbenno 68179595Sbenno#define PXA2X0_PCMCIA_SLOT0 0x20000000 69179595Sbenno#define PXA2X0_PCMCIA_SLOT1 0x30000000 70179595Sbenno 71179595Sbenno#define PXA2X0_PERIPH_START 0x40000000 72179595Sbenno/* #define PXA2X0_MEMCTL_START 0x48000000 */ 73179595Sbenno#define PXA270_PERIPH_END 0x530fffff 74179595Sbenno#define PXA250_PERIPH_END 0x480fffff 75179595Sbenno#define PXA2X0_PERIPH_OFFSET 0xa8000000 76179595Sbenno 77179595Sbenno#define PXA2X0_SDRAM0_START 0xa0000000 78179595Sbenno#define PXA2X0_SDRAM1_START 0xa4000000 79179595Sbenno#define PXA2X0_SDRAM2_START 0xa8000000 80179595Sbenno#define PXA2X0_SDRAM3_START 0xac000000 81179595Sbenno#define PXA2X0_SDRAM_BANKS 4 82179595Sbenno#define PXA2X0_SDRAM_BANK_SIZE 0x04000000 83179595Sbenno 84179595Sbenno/* 85179595Sbenno * Physical address of integrated peripherals 86179595Sbenno */ 87179595Sbenno 88179595Sbenno#define PXA2X0_DMAC_BASE 0x40000000 89179595Sbenno#define PXA2X0_DMAC_SIZE 0x300 90179595Sbenno#define PXA2X0_FFUART_BASE 0x40100000 /* Full Function UART */ 91179595Sbenno#define PXA2X0_FFUART_SIZE 0x20 92179595Sbenno#define PXA2X0_BTUART_BASE 0x40200000 /* Bluetooth UART */ 93179595Sbenno#define PXA2X0_BTUART_SIZE 0x24 94179595Sbenno#define PXA2X0_I2C_BASE 0x40300000 95179595Sbenno#define PXA2X0_I2C_SIZE 0x000016a4 96179595Sbenno#define PXA2X0_I2S_BASE 0x40400000 97179595Sbenno#define PXA2X0_AC97_BASE 0x40500000 98179595Sbenno#define PXA2X0_AC97_SIZE 0x600 99179595Sbenno#define PXA2X0_USBDC_BASE 0x40600000 /* USB Client */ 100179595Sbenno#define PXA2X0_USBDC_SIZE 0x0e04 101179595Sbenno#define PXA2X0_STUART_BASE 0x40700000 /* Standard UART */ 102179595Sbenno#define PXA2X0_STUART_SIZE 0x24 103179595Sbenno#define PXA2X0_ICP_BASE 0x40800000 104179595Sbenno#define PXA2X0_RTC_BASE 0x40900000 105179595Sbenno#define PXA2X0_RTC_SIZE 0x10 106179595Sbenno#define PXA2X0_OST_BASE 0x40a00000 /* OS Timer */ 107179595Sbenno#define PXA2X0_OST_SIZE 0x20 108179595Sbenno#define PXA2X0_PWM0_BASE 0x40b00000 109179595Sbenno#define PXA2X0_PWM1_BASE 0x40c00000 110179595Sbenno#define PXA2X0_INTCTL_BASE 0x40d00000 /* Interrupt controller */ 111179595Sbenno#define PXA2X0_INTCTL_SIZE 0x20 112179595Sbenno#define PXA2X0_GPIO_BASE 0x40e00000 113179595Sbenno 114179595Sbenno#define PXA270_GPIO_SIZE 0x150 115179595Sbenno#define PXA250_GPIO_SIZE 0x70 116179595Sbenno#define PXA2X0_POWMAN_BASE 0x40f00000 /* Power management */ 117179595Sbenno#define PXA2X0_SSP_BASE 0x41000000 118179595Sbenno#define PXA2X0_MMC_BASE 0x41100000 /* MultiMediaCard */ 119179595Sbenno#define PXA2X0_MMC_SIZE 0x48 120179595Sbenno#define PXA2X0_CLKMAN_BASE 0x41300000 /* Clock Manager */ 121179595Sbenno#define PXA2X0_CLKMAN_SIZE 12 122179595Sbenno#define PXA2X0_HWUART_BASE 0x41600000 /* Hardware UART */ 123179595Sbenno#define PXA2X0_HWUART_SIZE 0x30 124179595Sbenno#define PXA2X0_LCDC_BASE 0x44000000 /* LCD Controller */ 125179595Sbenno#define PXA2X0_LCDC_SIZE 0x220 126179595Sbenno#define PXA2X0_MEMCTL_BASE 0x48000000 /* Memory Controller */ 127179595Sbenno#define PXA2X0_MEMCTL_SIZE 0x48 128179595Sbenno#define PXA2X0_USBH_BASE 0x4c000000 /* USB Host controller */ 129179595Sbenno#define PXA2X0_USBH_SIZE 0x70 130179595Sbenno 131179595Sbenno/* Internal SRAM storage. PXA27x only */ 132179595Sbenno#define PXA270_SRAM0_START 0x5c000000 133179595Sbenno#define PXA270_SRAM1_START 0x5c010000 134179595Sbenno#define PXA270_SRAM2_START 0x5c020000 135179595Sbenno#define PXA270_SRAM3_START 0x5c030000 136179595Sbenno#define PXA270_SRAM_BANKS 4 137179595Sbenno#define PXA270_SRAM_BANK_SIZE 0x00010000 138179595Sbenno 139179595Sbenno/* width of interrupt controller */ 140179595Sbenno#define ICU_LEN 32 /* but [0..7,15,16] is not used */ 141179595Sbenno#define ICU_INT_HWMASK 0xffffff00 142236987Simp#define PXA250_IRQ_MIN 8 /* 0..7 are not used by integrated 143179595Sbenno peripherals */ 144179595Sbenno#define PXA270_IRQ_MIN 0 145179595Sbenno 146179595Sbenno#define PXA2X0_INT_USBH1 3 /* USB host (OHCI) */ 147179595Sbenno 148179595Sbenno#define PXA2X0_INT_HWUART 7 149179595Sbenno#define PXA2X0_INT_GPIO0 8 150179595Sbenno#define PXA2X0_INT_GPIO1 9 151179595Sbenno#define PXA2X0_INT_GPION 10 /* irq from GPIO[2..80] */ 152179595Sbenno#define PXA2X0_INT_USB 11 153179595Sbenno#define PXA2X0_INT_PMU 12 154179595Sbenno#define PXA2X0_INT_I2S 13 155179595Sbenno#define PXA2X0_INT_AC97 14 156179595Sbenno#define PXA2X0_INT_LCD 17 157179595Sbenno#define PXA2X0_INT_I2C 18 158179595Sbenno#define PXA2X0_INT_ICP 19 159179595Sbenno#define PXA2X0_INT_STUART 20 160179595Sbenno#define PXA2X0_INT_BTUART 21 161179595Sbenno#define PXA2X0_INT_FFUART 22 162179595Sbenno#define PXA2X0_INT_MMC 23 163179595Sbenno#define PXA2X0_INT_SSP 24 164179595Sbenno#define PXA2X0_INT_DMA 25 165179595Sbenno#define PXA2X0_INT_OST0 26 166179595Sbenno#define PXA2X0_INT_OST1 27 167179595Sbenno#define PXA2X0_INT_OST2 28 168179595Sbenno#define PXA2X0_INT_OST3 29 169179595Sbenno#define PXA2X0_INT_RTCHZ 30 170179595Sbenno#define PXA2X0_INT_ALARM 31 /* RTC Alarm interrupt */ 171179595Sbenno 172179595Sbenno/* DMAC */ 173179595Sbenno#define DMAC_N_CHANNELS 16 174179595Sbenno#define DMAC_N_PRIORITIES 3 175179595Sbenno 176179595Sbenno#define DMAC_DCSR(n) ((n)*4) 177179595Sbenno#define DCSR_BUSERRINTR (1<<0) /* bus error interrupt */ 178179595Sbenno#define DCSR_STARTINTR (1<<1) /* start interrupt */ 179179595Sbenno#define DCSR_ENDINTR (1<<2) /* end interrupt */ 180179595Sbenno#define DCSR_STOPSTATE (1<<3) /* channel is not running */ 181179595Sbenno#define DCSR_REQPEND (1<<8) /* request pending */ 182179595Sbenno#define DCSR_STOPIRQEN (1<<29) /* stop interrupt enable */ 183179595Sbenno#define DCSR_NODESCFETCH (1<<30) /* no-descriptor fetch mode */ 184179595Sbenno#define DCSR_RUN (1<<31) 185179595Sbenno#define DMAC_DINT 0x00f0 /* DAM interrupt */ 186179595Sbenno#define DMAC_DINT_MASK 0xffffu 187179595Sbenno#define DMAC_DRCMR(n) (0x100+(n)*4) /* Channel map register */ 188179595Sbenno#define DRCMR_CHLNUM 0x0f /* channel number */ 189179595Sbenno#define DRCMR_MAPVLD (1<<7) /* map valid */ 190179595Sbenno#define DMAC_DDADR(n) (0x0200+(n)*16) 191179595Sbenno#define DDADR_STOP (1<<0) 192179595Sbenno#define DMAC_DSADR(n) (0x0204+(n)*16) 193179595Sbenno#define DMAC_DTADR(n) (0x0208+(n)*16) 194179595Sbenno#define DMAC_DCMD(n) (0x020c+(n)*16) 195179595Sbenno#define DCMD_LENGTH_MASK 0x1fff 196179595Sbenno#define DCMD_WIDTH_SHIFT 14 197179595Sbenno#define DCMD_WIDTH_0 (0<<DCMD_WIDTH_SHIFT) /* for mem-to-mem transfer*/ 198179595Sbenno#define DCMD_WIDTH_1 (1<<DCMD_WIDTH_SHIFT) 199179595Sbenno#define DCMD_WIDTH_2 (2<<DCMD_WIDTH_SHIFT) 200179595Sbenno#define DCMD_WIDTH_4 (3<<DCMD_WIDTH_SHIFT) 201179595Sbenno#define DCMD_SIZE_SHIFT 16 202179595Sbenno#define DCMD_SIZE_8 (1<<DCMD_SIZE_SHIFT) 203179595Sbenno#define DCMD_SIZE_16 (2<<DCMD_SIZE_SHIFT) 204179595Sbenno#define DCMD_SIZE_32 (3<<DCMD_SIZE_SHIFT) 205179595Sbenno#define DCMD_LITTLE_ENDIEN (0<<18) 206179595Sbenno#define DCMD_ENDIRQEN (1<<21) 207179595Sbenno#define DCMD_STARTIRQEN (1<<22) 208179595Sbenno#define DCMD_FLOWTRG (1<<28) /* flow control by target */ 209179595Sbenno#define DCMD_FLOWSRC (1<<29) /* flow control by source */ 210179595Sbenno#define DCMD_INCTRGADDR (1<<30) /* increment target address */ 211179595Sbenno#define DCMD_INCSRCADDR (1<<31) /* increment source address */ 212179595Sbenno 213179595Sbenno#ifndef __ASSEMBLER__ 214179595Sbenno/* DMA descriptor */ 215179595Sbennostruct pxa_dma_desc { 216179595Sbenno volatile uint32_t dd_ddadr; 217179595Sbenno#define DMAC_DESC_LAST 0x1 218179595Sbenno volatile uint32_t dd_dsadr; 219179595Sbenno volatile uint32_t dd_dtadr; 220179595Sbenno volatile uint32_t dd_dcmd; /* command and length */ 221179595Sbenno}; 222179595Sbenno#endif 223179595Sbenno 224179595Sbenno/* UART */ 225179595Sbenno#define PXA2X0_COM_FREQ 14745600L 226179595Sbenno 227179595Sbenno/* I2C */ 228179595Sbenno#define I2C_IBMR 0x1680 /* Bus monitor register */ 229179595Sbenno#define I2C_IDBR 0x1688 /* Data buffer */ 230179595Sbenno#define I2C_ICR 0x1690 /* Control register */ 231179595Sbenno#define ICR_START (1<<0) 232179595Sbenno#define ICR_STOP (1<<1) 233179595Sbenno#define ICR_ACKNAK (1<<2) 234179595Sbenno#define ICR_TB (1<<3) 235179595Sbenno#define ICR_MA (1<<4) 236179595Sbenno#define I2C_ISR 0x1698 /* Status register */ 237179595Sbenno#define I2C_ISAR 0x16a0 /* Slave address */ 238179595Sbenno 239179595Sbenno/* Clock Manager */ 240179595Sbenno#define CLKMAN_CCCR 0x00 /* Core Clock Configuration */ 241179595Sbenno#define CCCR_TURBO_X1 (2<<7) 242179595Sbenno#define CCCR_TURBO_X15 (3<<7) /* x 1.5 */ 243179595Sbenno#define CCCR_TURBO_X2 (4<<7) 244179595Sbenno#define CCCR_TURBO_X25 (5<<7) /* x 2.5 */ 245179595Sbenno#define CCCR_TURBO_X3 (6<<7) /* x 3.0 */ 246179595Sbenno#define CCCR_RUN_X1 (1<<5) 247179595Sbenno#define CCCR_RUN_X2 (2<<5) 248179595Sbenno#define CCCR_RUN_X4 (3<<5) 249179595Sbenno#define CCCR_MEM_X27 (1<<0) /* x27, 99.53MHz */ 250179595Sbenno#define CCCR_MEM_X32 (2<<0) /* x32, 117,96MHz */ 251179595Sbenno#define CCCR_MEM_X36 (3<<0) /* x26, 132.71MHz */ 252179595Sbenno#define CCCR_MEM_X40 (4<<0) /* x27, 99.53MHz */ 253179595Sbenno#define CCCR_MEM_X45 (5<<0) /* x27, 99.53MHz */ 254179595Sbenno#define CCCR_MEM_X9 (0x1f<<0) /* x9, 33.2MHz */ 255179595Sbenno 256179595Sbenno#define CLKMAN_CKEN 0x04 /* Clock Enable Register */ 257179595Sbenno#define CLKMAN_OSCC 0x08 /* Osillcator Configuration Register */ 258179595Sbenno 259179595Sbenno#define CCCR_N_SHIFT 7 260179595Sbenno#define CCCR_N_MASK (0x07<<CCCR_N_SHIFT) 261179595Sbenno#define CCCR_M_SHIFT 5 262179595Sbenno#define CCCR_M_MASK (0x03<<CCCR_M_SHIFT) 263179595Sbenno#define CCCR_L_MASK 0x1f 264179595Sbenno 265179595Sbenno#define CKEN_PWM0 (1<<0) 266179595Sbenno#define CKEN_PWM1 (1<<1) 267179595Sbenno#define CKEN_AC97 (1<<2) 268179595Sbenno#define CKEN_SSP (1<<3) 269179595Sbenno#define CKEN_STUART (1<<5) 270179595Sbenno#define CKEN_FFUART (1<<6) 271179595Sbenno#define CKEN_BTUART (1<<7) 272179595Sbenno#define CKEN_I2S (1<<8) 273179595Sbenno#define CKEN_USBH (1<<10) 274179595Sbenno#define CKEN_USB (1<<11) 275179595Sbenno#define CKEN_MMC (1<<12) 276179595Sbenno#define CKEN_FICP (1<<13) 277179595Sbenno#define CKEN_I2C (1<<14) 278179595Sbenno#define CKEN_LCD (1<<16) 279179595Sbenno 280179595Sbenno#define OSCC_OOK (1<<0) /* 32.768 kHz oscillator status */ 281179595Sbenno#define OSCC_OON (1<<1) /* 32.768 kHz oscillator */ 282179595Sbenno 283179595Sbenno/* 284179595Sbenno * RTC 285179595Sbenno */ 286179595Sbenno#define RTC_RCNR 0x0000 /* count register */ 287179595Sbenno#define RTC_RTAR 0x0004 /* alarm register */ 288179595Sbenno#define RTC_RTSR 0x0008 /* status register */ 289179595Sbenno#define RTC_RTTR 0x000c /* trim register */ 290179595Sbenno/* 291179595Sbenno * GPIO 292179595Sbenno */ 293179595Sbenno#define GPIO_GPLR0 0x00 /* Level reg [31:0] */ 294179595Sbenno#define GPIO_GPLR1 0x04 /* Level reg [63:32] */ 295179595Sbenno#define GPIO_GPLR2 0x08 /* Level reg [80:64] */ 296179595Sbenno 297179595Sbenno#define GPIO_GPDR0 0x0c /* dir reg [31:0] */ 298179595Sbenno#define GPIO_GPDR1 0x10 /* dir reg [63:32] */ 299179595Sbenno#define GPIO_GPDR2 0x14 /* dir reg [80:64] */ 300179595Sbenno 301179595Sbenno#define GPIO_GPSR0 0x18 /* set reg [31:0] */ 302179595Sbenno#define GPIO_GPSR1 0x1c /* set reg [63:32] */ 303179595Sbenno#define GPIO_GPSR2 0x20 /* set reg [80:64] */ 304179595Sbenno 305179595Sbenno#define GPIO_GPCR0 0x24 /* clear reg [31:0] */ 306179595Sbenno#define GPIO_GPCR1 0x28 /* clear reg [63:32] */ 307179595Sbenno#define GPIO_GPCR2 0x2c /* clear reg [80:64] */ 308179595Sbenno 309179595Sbenno#define GPIO_GPER0 0x30 /* rising edge [31:0] */ 310179595Sbenno#define GPIO_GPER1 0x34 /* rising edge [63:32] */ 311179595Sbenno#define GPIO_GPER2 0x38 /* rising edge [80:64] */ 312179595Sbenno 313179595Sbenno#define GPIO_GRER0 0x30 /* rising edge [31:0] */ 314179595Sbenno#define GPIO_GRER1 0x34 /* rising edge [63:32] */ 315179595Sbenno#define GPIO_GRER2 0x38 /* rising edge [80:64] */ 316179595Sbenno 317179595Sbenno#define GPIO_GFER0 0x3c /* falling edge [31:0] */ 318179595Sbenno#define GPIO_GFER1 0x40 /* falling edge [63:32] */ 319179595Sbenno#define GPIO_GFER2 0x44 /* falling edge [80:64] */ 320179595Sbenno 321179595Sbenno#define GPIO_GEDR0 0x48 /* edge detect [31:0] */ 322179595Sbenno#define GPIO_GEDR1 0x4c /* edge detect [63:32] */ 323179595Sbenno#define GPIO_GEDR2 0x50 /* edge detect [80:64] */ 324179595Sbenno 325179595Sbenno#define GPIO_GAFR0_L 0x54 /* alternate function [15:0] */ 326179595Sbenno#define GPIO_GAFR0_U 0x58 /* alternate function [31:16] */ 327179595Sbenno#define GPIO_GAFR1_L 0x5c /* alternate function [47:32] */ 328179595Sbenno#define GPIO_GAFR1_U 0x60 /* alternate function [63:48] */ 329179595Sbenno#define GPIO_GAFR2_L 0x64 /* alternate function [79:64] */ 330179595Sbenno#define GPIO_GAFR2_U 0x68 /* alternate function [80] */ 331179595Sbenno 332179595Sbenno/* Only for PXA270 */ 333179595Sbenno#define GPIO_GAFR3_L 0x6c /* alternate function [111:96] */ 334179595Sbenno#define GPIO_GAFR3_U 0x70 /* alternate function [120:112] */ 335179595Sbenno 336179595Sbenno#define GPIO_GPLR3 0x100 /* Level reg [120:96] */ 337179595Sbenno#define GPIO_GPDR3 0x10c /* dir reg [120:96] */ 338179595Sbenno#define GPIO_GPSR3 0x118 /* set reg [120:96] */ 339179595Sbenno#define GPIO_GPCR3 0x124 /* clear reg [120:96] */ 340179595Sbenno#define GPIO_GRER3 0x130 /* rising edge [120:96] */ 341179595Sbenno#define GPIO_GFER3 0x13c /* falling edge [120:96] */ 342179595Sbenno#define GPIO_GEDR3 0x148 /* edge detect [120:96] */ 343179595Sbenno 344179595Sbenno/* a bit simpler if we don't support PXA270 */ 345179595Sbenno#define PXA250_GPIO_REG(r, pin) ((r) + (((pin) / 32) * 4)) 346179595Sbenno#define PXA250_GPIO_NPINS 85 347179595Sbenno 348179595Sbenno#define PXA270_GPIO_REG(r, pin) \ 349179595Sbenno(pin < 96 ? PXA250_GPIO_REG(r,pin) : ((r) + 0x100 + ((((pin)-96) / 32) * 4))) 350179595Sbenno#define PXA270_GPIO_NPINS 121 351179595Sbenno 352179595Sbenno 353179595Sbenno#define GPIO_BANK(pin) ((pin) / 32) 354179595Sbenno#define GPIO_BIT(pin) (1u << ((pin) & 0x1f)) 355179595Sbenno#define GPIO_FN_REG(pin) (GPIO_GAFR0_L + (((pin) / 16) * 4)) 356179595Sbenno#define GPIO_FN_SHIFT(pin) ((pin & 0xf) * 2) 357179595Sbenno 358179595Sbenno#define GPIO_IN 0x00 /* Regular GPIO input pin */ 359179595Sbenno#define GPIO_OUT 0x10 /* Regular GPIO output pin */ 360179595Sbenno#define GPIO_ALT_FN_1_IN 0x01 /* Alternate function 1 input */ 361179595Sbenno#define GPIO_ALT_FN_1_OUT 0x11 /* Alternate function 1 output */ 362179595Sbenno#define GPIO_ALT_FN_2_IN 0x02 /* Alternate function 2 input */ 363179595Sbenno#define GPIO_ALT_FN_2_OUT 0x12 /* Alternate function 2 output */ 364179595Sbenno#define GPIO_ALT_FN_3_IN 0x03 /* Alternate function 3 input */ 365179595Sbenno#define GPIO_ALT_FN_3_OUT 0x13 /* Alternate function 3 output */ 366179595Sbenno#define GPIO_SET 0x20 /* Initial state is Set */ 367179595Sbenno#define GPIO_CLR 0x00 /* Initial state is Clear */ 368179595Sbenno 369179595Sbenno#define GPIO_FN_MASK 0x03 370179595Sbenno#define GPIO_FN_IS_OUT(n) ((n) & GPIO_OUT) 371179595Sbenno#define GPIO_FN_IS_SET(n) ((n) & GPIO_SET) 372179595Sbenno#define GPIO_FN(n) ((n) & GPIO_FN_MASK) 373179595Sbenno#define GPIO_IS_GPIO(n) (GPIO_FN(n) == 0) 374179595Sbenno#define GPIO_IS_GPIO_IN(n) (((n) & (GPIO_FN_MASK|GPIO_OUT)) == GPIO_IN) 375179595Sbenno#define GPIO_IS_GPIO_OUT(n) (((n) & (GPIO_FN_MASK|GPIO_OUT)) == GPIO_OUT) 376179595Sbenno 377179595Sbenno#define IRQ_GPIO0 64 378179595Sbenno#define IRQ_NGPIO 128 379179595Sbenno#define IRQ_GPIO_MAX IRQ_GPIO0 + IRQ_NGPIO 380179595Sbenno#define IRQ_TO_GPIO(x) (x - IRQ_GPIO0) 381179595Sbenno#define GPIO_TO_IRQ(x) (x + IRQ_GPIO0) 382179595Sbenno 383179595Sbenno/* 384179595Sbenno * memory controller 385179595Sbenno */ 386179595Sbenno 387179595Sbenno#define MEMCTL_MDCNFG 0x0000 388179595Sbenno#define MDCNFG_DE0 (1<<0) 389179595Sbenno#define MDCNFG_DE1 (1<<1) 390179595Sbenno#define MDCNFD_DWID01_SHIFT 2 391179595Sbenno#define MDCNFD_DCAC01_SHIFT 3 392179595Sbenno#define MDCNFD_DRAC01_SHIFT 5 393179595Sbenno#define MDCNFD_DNB01_SHIFT 7 394179595Sbenno#define MDCNFG_DE2 (1<<16) 395179595Sbenno#define MDCNFG_DE3 (1<<17) 396179595Sbenno#define MDCNFD_DWID23_SHIFT 18 397179595Sbenno#define MDCNFD_DCAC23_SHIFT 19 398179595Sbenno#define MDCNFD_DRAC23_SHIFT 21 399179595Sbenno#define MDCNFD_DNB23_SHIFT 23 400179595Sbenno 401179595Sbenno#define MDCNFD_DWID_MASK 0x1 402179595Sbenno#define MDCNFD_DCAC_MASK 0x3 403179595Sbenno#define MDCNFD_DRAC_MASK 0x3 404179595Sbenno#define MDCNFD_DNB_MASK 0x1 405179595Sbenno 406179595Sbenno#define MEMCTL_MDREFR 0x04 /* refresh control register */ 407179595Sbenno#define MDREFR_DRI 0xfff 408179595Sbenno#define MDREFR_E0PIN (1<<12) 409179595Sbenno#define MDREFR_K0RUN (1<<13) /* SDCLK0 enable */ 410179595Sbenno#define MDREFR_K0DB2 (1<<14) /* SDCLK0 1/2 freq */ 411179595Sbenno#define MDREFR_E1PIN (1<<15) 412179595Sbenno#define MDREFR_K1RUN (1<<16) /* SDCLK1 enable */ 413179595Sbenno#define MDREFR_K1DB2 (1<<17) /* SDCLK1 1/2 freq */ 414179595Sbenno#define MDREFR_K2RUN (1<<18) /* SDCLK2 enable */ 415179595Sbenno#define MDREFR_K2DB2 (1<<19) /* SDCLK2 1/2 freq */ 416179595Sbenno#define MDREFR_APD (1<<20) /* Auto Power Down */ 417179595Sbenno#define MDREFR_SLFRSH (1<<22) /* Self Refresh */ 418179595Sbenno#define MDREFR_K0FREE (1<<23) /* SDCLK0 free run */ 419179595Sbenno#define MDREFR_K1FREE (1<<24) /* SDCLK1 free run */ 420179595Sbenno#define MDREFR_K2FREE (1<<25) /* SDCLK2 free run */ 421179595Sbenno 422179595Sbenno#define MEMCTL_MSC0 0x08 /* Asychronous Statis memory Control CS[01] */ 423179595Sbenno#define MEMCTL_MSC1 0x0c /* Asychronous Statis memory Control CS[23] */ 424179595Sbenno#define MEMCTL_MSC2 0x10 /* Asychronous Statis memory Control CS[45] */ 425179595Sbenno#define MSC_RBUFF_SHIFT 15 /* return data buffer */ 426179595Sbenno#define MSC_RBUFF (1<<MSC_RBUFF_SHIFT) 427179595Sbenno#define MSC_RRR_SHIFT 12 /* recovery time */ 428179595Sbenno#define MSC_RRR (7<<MSC_RRR_SHIFT) 429179595Sbenno#define MSC_RDN_SHIFT 8 /* ROM delay next access */ 430179595Sbenno#define MSC_RDN (0x0f<<MSC_RDN_SHIFT) 431179595Sbenno#define MSC_RDF_SHIFT 4 /* ROM delay first access*/ 432179595Sbenno#define MSC_RDF (0x0f<<MSC_RDF_SHIFT) 433179595Sbenno#define MSC_RBW_SHIFT 3 /* 32/16 bit bus */ 434179595Sbenno#define MSC_RBW (1<<MSC_RBW_SHIFT) 435179595Sbenno#define MSC_RT_SHIFT 0 /* type */ 436179595Sbenno#define MSC_RT (7<<MSC_RT_SHIFT) 437179595Sbenno#define MSC_RT_NONBURST 0 438179595Sbenno#define MSC_RT_SRAM 1 439179595Sbenno#define MSC_RT_BURST4 2 440179595Sbenno#define MSC_RT_BURST8 3 441179595Sbenno#define MSC_RT_VLIO 4 442179595Sbenno 443179595Sbenno/* expansion memory timing configuration */ 444179595Sbenno#define MEMCTL_MCMEM(n) (0x28+4*(n)) 445179595Sbenno#define MEMCTL_MCATT(n) (0x30+4*(n)) 446179595Sbenno#define MEMCTL_MCIO(n) (0x38+4*(n)) 447179595Sbenno 448179595Sbenno#define MC_HOLD_SHIFT 14 449179595Sbenno#define MC_ASST_SHIFT 7 450179595Sbenno#define MC_SET_SHIFT 0 451179595Sbenno#define MC_TIMING_VAL(hold,asst,set) (((hold)<<MC_HOLD_SHIFT)| \ 452179595Sbenno ((asst)<<MC_ASST_SHIFT)|((set)<<MC_SET_SHIFT)) 453179595Sbenno 454179595Sbenno#define MEMCTL_MECR 0x14 /* Expansion memory configuration */ 455179595Sbenno#define MECR_NOS (1<<0) /* Number of sockets */ 456179595Sbenno#define MECR_CIT (1<<1) /* Card-is-there */ 457179595Sbenno 458179595Sbenno#define MEMCTL_MDMRS 0x0040 459179595Sbenno 460179595Sbenno/* 461179595Sbenno * LCD Controller 462179595Sbenno */ 463179595Sbenno#define LCDC_LCCR0 0x000 /* Controller Control Register 0 */ 464179595Sbenno#define LCCR0_ENB (1U<<0) /* LCD Controller Enable */ 465179595Sbenno#define LCCR0_CMS (1U<<1) /* Color/Mono select */ 466179595Sbenno#define LCCR0_SDS (1U<<2) /* Single/Dual -panel */ 467179595Sbenno#define LCCR0_LDM (1U<<3) /* LCD Disable Done Mask */ 468179595Sbenno#define LCCR0_SFM (1U<<4) /* Start of Frame Mask */ 469179595Sbenno#define LCCR0_IUM (1U<<5) /* Input FIFO Underrun Mask */ 470179595Sbenno#define LCCR0_EFM (1U<<6) /* End of Frame Mask */ 471179595Sbenno#define LCCR0_PAS (1U<<7) /* Passive/Active Display select */ 472179595Sbenno#define LCCR0_DPD (1U<<9) /* Double-Pixel Data pin mode */ 473179595Sbenno#define LCCR0_DIS (1U<<10) /* LCD Disable */ 474179595Sbenno#define LCCR0_QDM (1U<<11) /* LCD Quick Disable Mask */ 475179595Sbenno#define LCCR0_BM (1U<<20) /* Branch Mask */ 476179595Sbenno#define LCCR0_OUM (1U<<21) /* Output FIFO Underrun Mask */ 477179595Sbenno 478179595Sbenno#define LCCR0_IMASK (LCCR0_LDM|LCCR0_SFM|LCCR0_IUM|LCCR0_EFM|LCCR0_QDM|LCCR0_BM|LCCR0_OUM) 479179595Sbenno 480179595Sbenno 481179595Sbenno#define LCDC_LCCR1 0x004 /* Controller Control Register 1 */ 482179595Sbenno#define LCDC_LCCR2 0x008 /* Controller Control Register 2 */ 483179595Sbenno#define LCDC_LCCR3 0x00c /* Controller Control Register 2 */ 484179595Sbenno#define LCCR3_BPP_SHIFT 24 /* Bits per pixel */ 485179595Sbenno#define LCCR3_BPP (0x07<<LCCR3_BPP_SHIFT) 486179595Sbenno#define LCDC_LCCR4 0x010 /* Controller Control Register 4 */ 487179595Sbenno#define LCDC_LCCR5 0x014 /* Controller Control Register 5 */ 488179595Sbenno#define LCDC_FBR0 0x020 /* DMA ch0 frame branch register */ 489179595Sbenno#define LCDC_FBR1 0x024 /* DMA ch1 frame branch register */ 490179595Sbenno#define LCDC_FBR2 0x028 /* DMA ch2 frame branch register */ 491179595Sbenno#define LCDC_FBR3 0x02c /* DMA ch3 frame branch register */ 492179595Sbenno#define LCDC_FBR4 0x030 /* DMA ch4 frame branch register */ 493179595Sbenno#define LCDC_LCSR1 0x034 /* controller status register 1 PXA27x only */ 494179595Sbenno#define LCDC_LCSR 0x038 /* controller status register */ 495179595Sbenno#define LCSR_LDD (1U<<0) /* LCD disable done */ 496179595Sbenno#define LCSR_SOF (1U<<1) /* Start of frame */ 497179595Sbenno#define LCDC_LIIDR 0x03c /* controller interrupt ID Register */ 498179595Sbenno#define LCDC_TRGBR 0x040 /* TMED RGB Speed Register */ 499179595Sbenno#define LCDC_TCR 0x044 /* TMED Control Register */ 500179595Sbenno#define LCDC_OVL1C1 0x050 /* Overlay 1 control register 1 */ 501179595Sbenno#define LCDC_OVL1C2 0x060 /* Overlay 1 control register 2 */ 502179595Sbenno#define LCDC_OVL2C1 0x070 /* Overlay 1 control register 1 */ 503179595Sbenno#define LCDC_OVL2C2 0x080 /* Overlay 1 control register 2 */ 504179595Sbenno#define LCDC_CCR 0x090 /* Cursor control register */ 505179595Sbenno#define LCDC_CMDCR 0x100 /* Command control register */ 506179595Sbenno#define LCDC_PRSR 0x104 /* Panel read status register */ 507179595Sbenno#define LCDC_FBR5 0x110 /* DMA ch5 frame branch register */ 508179595Sbenno#define LCDC_FBR6 0x114 /* DMA ch6 frame branch register */ 509179595Sbenno#define LCDC_FDADR0 0x200 /* DMA ch0 frame descriptor address */ 510179595Sbenno#define LCDC_FSADR0 0x204 /* DMA ch0 frame source address */ 511179595Sbenno#define LCDC_FIDR0 0x208 /* DMA ch0 frame ID register */ 512179595Sbenno#define LCDC_LDCMD0 0x20c /* DMA ch0 command register */ 513179595Sbenno#define LCDC_FDADR1 0x210 /* DMA ch1 frame descriptor address */ 514179595Sbenno#define LCDC_FSADR1 0x214 /* DMA ch1 frame source address */ 515179595Sbenno#define LCDC_FIDR1 0x218 /* DMA ch1 frame ID register */ 516179595Sbenno#define LCDC_LDCMD1 0x21c /* DMA ch1 command register */ 517179595Sbenno#define LCDC_FDADR2 0x220 /* DMA ch2 frame descriptor address */ 518179595Sbenno#define LCDC_FSADR2 0x224 /* DMA ch2 frame source address */ 519179595Sbenno#define LCDC_FIDR2 0x228 /* DMA ch2 frame ID register */ 520179595Sbenno#define LCDC_LDCMD2 0x22c /* DMA ch2 command register */ 521179595Sbenno#define LCDC_FDADR3 0x230 /* DMA ch3 frame descriptor address */ 522179595Sbenno#define LCDC_FSADR3 0x234 /* DMA ch3 frame source address */ 523179595Sbenno#define LCDC_FIDR3 0x238 /* DMA ch3 frame ID register */ 524179595Sbenno#define LCDC_LDCMD3 0x23c /* DMA ch3 command register */ 525179595Sbenno#define LCDC_FDADR4 0x240 /* DMA ch4 frame descriptor address */ 526179595Sbenno#define LCDC_FSADR4 0x244 /* DMA ch4 frame source address */ 527179595Sbenno#define LCDC_FIDR4 0x248 /* DMA ch4 frame ID register */ 528179595Sbenno#define LCDC_LDCMD4 0x24c /* DMA ch4 command register */ 529179595Sbenno#define LCDC_FDADR5 0x250 /* DMA ch5 frame descriptor address */ 530179595Sbenno#define LCDC_FSADR5 0x254 /* DMA ch5 frame source address */ 531179595Sbenno#define LCDC_FIDR5 0x258 /* DMA ch5 frame ID register */ 532179595Sbenno#define LCDC_LDCMD5 0x25c /* DMA ch5 command register */ 533179595Sbenno#define LCDC_FDADR6 0x260 /* DMA ch6 frame descriptor address */ 534179595Sbenno#define LCDC_FSADR6 0x264 /* DMA ch6 frame source address */ 535179595Sbenno#define LCDC_FIDR6 0x268 /* DMA ch6 frame ID register */ 536179595Sbenno#define LCDC_LDCMD6 0x26c /* DMA ch6 command register */ 537179595Sbenno#define LCDC_LCDBSCNTR 0x054 /* LCD buffer strength control register */ 538179595Sbenno 539179595Sbenno/* 540179595Sbenno * MMC/SD controller 541179595Sbenno */ 542179595Sbenno#define MMC_STRPCL 0x00 /* start/stop MMC clock */ 543179595Sbenno#define STRPCL_NOOP 0 544179595Sbenno#define STRPCL_STOP 1 /* stop MMC clock */ 545179595Sbenno#define STRPCL_START 2 /* start MMC clock */ 546179595Sbenno#define MMC_STAT 0x04 /* status register */ 547179595Sbenno#define STAT_READ_TIME_OUT (1<<0) 548179595Sbenno#define STAT_TIMEOUT_RESPONSE (1<<1) 549179595Sbenno#define STAT_CRC_WRITE_ERROR (1<<2) 550179595Sbenno#define STAT_CRC_READ_ERROR (1<<3) 551179595Sbenno#define STAT_SPI_READ_ERROR_TOKEN (1<<4) 552179595Sbenno#define STAT_RES_CRC_ERR (1<<5) 553179595Sbenno#define STAT_XMIT_FIFO_EMPTY (1<<6) 554179595Sbenno#define STAT_RECV_FIFO_FULL (1<<7) 555179595Sbenno#define STAT_CLK_EN (1<<8) 556179595Sbenno#define STAT_DATA_TRAN_DONE (1<<11) 557179595Sbenno#define STAT_PRG_DONE (1<<12) 558179595Sbenno#define STAT_END_CMD_RES (1<<13) 559179595Sbenno#define MMC_CLKRT 0x08 /* MMC clock rate */ 560179595Sbenno#define CLKRT_20M 0 561179595Sbenno#define CLKRT_10M 1 562179595Sbenno#define CLKRT_5M 2 563179595Sbenno#define CLKRT_2_5M 3 564179595Sbenno#define CLKRT_1_25M 4 565179595Sbenno#define CLKRT_625K 5 566179595Sbenno#define CLKRT_312K 6 567179595Sbenno#define MMC_SPI 0x0c /* SPI mode control */ 568179595Sbenno#define SPI_EN (1<<0) /* enable SPI mode */ 569179595Sbenno#define SPI_CRC_ON (1<<1) /* enable CRC generation */ 570179595Sbenno#define SPI_CS_EN (1<<2) /* Enable CS[01] */ 571179595Sbenno#define SPI_CS_ADDRESS (1<<3) /* CS0/CS1 */ 572179595Sbenno#define MMC_CMDAT 0x10 /* command/response/data */ 573179595Sbenno#define CMDAT_RESPONSE_FORMAT 0x03 574179595Sbenno#define CMDAT_RESPONSE_FORMAT_NO 0 /* no response */ 575179595Sbenno#define CMDAT_RESPONSE_FORMAT_R1 1 /* R1, R1b, R4, R5 */ 576179595Sbenno#define CMDAT_RESPONSE_FORMAT_R2 2 577179595Sbenno#define CMDAT_RESPONSE_FORMAT_R3 3 578179595Sbenno#define CMDAT_DATA_EN (1<<2) 579179595Sbenno#define CMDAT_WRITE (1<<3) /* 1=write 0=read operation */ 580179595Sbenno#define CMDAT_STREAM_BLOCK (1<<4) /* stream mode */ 581179595Sbenno#define CMDAT_BUSY (1<<5) /* busy signal is expected */ 582179595Sbenno#define CMDAT_INIT (1<<6) /* preceede command with 80 clocks */ 583179595Sbenno#define CMDAT_MMC_DMA_EN (1<<7) /* DMA enable */ 584179595Sbenno#define MMC_RESTO 0x14 /* expected response time out */ 585179595Sbenno#define MMC_RDTO 0x18 /* expected data read time out */ 586179595Sbenno#define MMC_BLKLEN 0x1c /* block length of data transaction */ 587179595Sbenno#define MMC_NOB 0x20 /* number of blocks (block mode) */ 588179595Sbenno#define MMC_PRTBUF 0x24 /* partial MMC_TXFIFO written */ 589179595Sbenno#define PRTBUF_BUF_PART_FULL (1<<0) /* buffer partially full */ 590179595Sbenno#define MMC_I_MASK 0x28 /* interrupt mask */ 591179595Sbenno#define MMC_I_REG 0x2c /* interrupt register */ 592179595Sbenno#define MMC_I_DATA_TRAN_DONE (1<<0) 593179595Sbenno#define MMC_I_PRG_DONE (1<<1) 594179595Sbenno#define MMC_I_END_CMD_RES (1<<2) 595179595Sbenno#define MMC_I_STOP_CMD (1<<3) 596179595Sbenno#define MMC_I_CLK_IS_OFF (1<<4) 597179595Sbenno#define MMC_I_RXFIFO_RD_REQ (1<<5) 598179595Sbenno#define MMC_I_TXFIFO_WR_REQ (1<<6) 599179595Sbenno#define MMC_CMD 0x30 /* index of current command */ 600179595Sbenno#define MMC_ARGH 0x34 /* MSW part of the current command arg */ 601179595Sbenno#define MMC_ARGL 0x38 /* LSW part of the current command arg */ 602179595Sbenno#define MMC_RES 0x3c /* response FIFO */ 603179595Sbenno#define MMC_RXFIFO 0x40 /* receive FIFO */ 604179595Sbenno#define MMC_TXFIFO 0x44 /* transmit FIFO */ 605179595Sbenno 606179595Sbenno/* 607179595Sbenno * AC97 608179595Sbenno */ 609179595Sbenno#define AC97_N_CODECS 2 610179595Sbenno#define AC97_GCR 0x000c /* Global control register */ 611179595Sbenno#define GCR_GIE (1<<0) /* interrupt enable */ 612179595Sbenno#define GCR_COLD_RST (1<<1) 613179595Sbenno#define GCR_WARM_RST (1<<2) 614179595Sbenno#define GCR_ACLINK_OFF (1<<3) 615179595Sbenno#define GCR_PRIRES_IEN (1<<4) /* Primary resume interrupt enable */ 616179595Sbenno#define GCR_SECRES_IEN (1<<5) /* Secondary resume interrupt enable */ 617179595Sbenno#define GCR_PRIRDY_IEN (1<<8) /* Primary ready interrupt enable */ 618179595Sbenno#define GCR_SECRDY_IEN (1<<9) /* Primary ready interrupt enable */ 619179595Sbenno#define GCR_SDONE_IE (1<<18) /* Status done interrupt enable */ 620179595Sbenno#define GCR_CDONE_IE (1<<19) /* Command done interrupt enable */ 621179595Sbenno 622179595Sbenno#define AC97_GSR 0x001c /* Global status register */ 623179595Sbenno#define GSR_GSCI (1<<0) /* codec GPI status change interrupt */ 624179595Sbenno#define GSR_MIINT (1<<1) /* modem in interrupt */ 625179595Sbenno#define GSR_MOINT (1<<2) /* modem out interrupt */ 626179595Sbenno#define GSR_PIINT (1<<5) /* PCM in interrupt */ 627179595Sbenno#define GSR_POINT (1<<6) /* PCM out interrupt */ 628179595Sbenno#define GSR_MINT (1<<7) /* Mic in interrupt */ 629179595Sbenno#define GSR_PCR (1<<8) /* primary code ready */ 630179595Sbenno#define GSR_SCR (1<<9) /* secondary code ready */ 631179595Sbenno#define GSR_PRIRES (1<<10) /* primary resume interrupt */ 632179595Sbenno#define GSR_SECRES (1<<11) /* secondary resume interrupt */ 633179595Sbenno#define GSR_BIT1SLT12 (1<<12) /* Bit 1 of slot 12 */ 634179595Sbenno#define GSR_BIT2SLT12 (1<<13) /* Bit 2 of slot 12 */ 635179595Sbenno#define GSR_BIT3SLT12 (1<<14) /* Bit 3 of slot 12 */ 636179595Sbenno#define GSR_RDCS (1<<15) /* Read completion status */ 637179595Sbenno#define GSR_SDONE (1<<18) /* status done */ 638179595Sbenno#define GSR_CDONE (1<<19) /* command done */ 639179595Sbenno 640179595Sbenno#define AC97_POCR 0x0000 /* PCM-out control */ 641179595Sbenno#define AC97_PICR 0x0004 /* PCM-in control */ 642179595Sbenno#define AC97_POSR 0x0010 /* PCM-out status */ 643179595Sbenno#define AC97_PISR 0x0014 /* PCM-out status */ 644179595Sbenno#define AC97_MCCR 0x0008 /* MIC-in control register */ 645179595Sbenno#define AC97_MCSR 0x0018 /* MIC-in status register */ 646179595Sbenno#define AC97_MICR 0x0100 /* Modem-in control register */ 647179595Sbenno#define AC97_MISR 0x0108 /* Modem-in status register */ 648179595Sbenno#define AC97_MOCR 0x0110 /* Modem-out control register */ 649179595Sbenno#define AC97_MOSR 0x0118 /* Modem-out status register */ 650179595Sbenno#define AC97_FEFIE (1<<3) /* fifo error interrupt enable */ 651179595Sbenno#define AC97_FIFOE (1<<4) /* fifo error */ 652179595Sbenno 653179595Sbenno#define AC97_CAR 0x0020 /* Codec access register */ 654179595Sbenno#define CAR_CAIP (1<<0) /* Codec access in progress */ 655179595Sbenno 656179595Sbenno#define AC97_PCDR 0x0040 /* PCM data register */ 657179595Sbenno#define AC97_MCDR 0x0060 /* MIC-in data register */ 658179595Sbenno#define AC97_MODR 0x0140 /* Modem data register */ 659179595Sbenno 660179595Sbenno/* address to access codec registers */ 661179595Sbenno#define AC97_PRIAUDIO 0x0200 /* Primary audio codec */ 662179595Sbenno#define AC97_SECAUDIO 0x0300 /* Secondary autio codec */ 663179595Sbenno#define AC97_PRIMODEM 0x0400 /* Primary modem codec */ 664179595Sbenno#define AC97_SECMODEM 0x0500 /* Secondary modem codec */ 665179595Sbenno#define AC97_CODEC_BASE(c) (AC97_PRIAUDIO + ((c) * 0x100)) 666179595Sbenno 667179595Sbenno/* 668179595Sbenno * USB device controller 669179595Sbenno */ 670179595Sbenno#define USBDC_UDCCR 0x0000 /* UDC control register */ 671179595Sbenno#define USBDC_UDCCS(n) (0x0010+4*(n)) /* Endpoint Control/Status Registers */ 672179595Sbenno#define USBDC_UICR0 0x0050 /* UDC Interrupt Control Register 0 */ 673179595Sbenno#define USBDC_UICR1 0x0054 /* UDC Interrupt Control Register 1 */ 674179595Sbenno#define USBDC_USIR0 0x0058 /* UDC Status Interrupt Register 0 */ 675179595Sbenno#define USBDC_USIR1 0x005C /* UDC Status Interrupt Register 1 */ 676179595Sbenno#define USBDC_UFNHR 0x0060 /* UDC Frame Number Register High */ 677179595Sbenno#define USBDC_UFNLR 0x0064 /* UDC Frame Number Register Low */ 678179595Sbenno#define USBDC_UBCR2 0x0068 /* UDC Byte Count Register 2 */ 679179595Sbenno#define USBDC_UBCR4 0x006C /* UDC Byte Count Register 4 */ 680179595Sbenno#define USBDC_UBCR7 0x0070 /* UDC Byte Count Register 7 */ 681179595Sbenno#define USBDC_UBCR9 0x0074 /* UDC Byte Count Register 9 */ 682179595Sbenno#define USBDC_UBCR12 0x0078 /* UDC Byte Count Register 12 */ 683179595Sbenno#define USBDC_UBCR14 0x007C /* UDC Byte Count Register 14 */ 684179595Sbenno#define USBDC_UDDR0 0x0080 /* UDC Endpoint 0 Data Register */ 685179595Sbenno#define USBDC_UDDR1 0x0100 /* UDC Endpoint 1 Data Register */ 686179595Sbenno#define USBDC_UDDR2 0x0180 /* UDC Endpoint 2 Data Register */ 687179595Sbenno#define USBDC_UDDR3 0x0200 /* UDC Endpoint 3 Data Register */ 688179595Sbenno#define USBDC_UDDR4 0x0400 /* UDC Endpoint 4 Data Register */ 689179595Sbenno#define USBDC_UDDR5 0x00A0 /* UDC Endpoint 5 Data Register */ 690179595Sbenno#define USBDC_UDDR6 0x0600 /* UDC Endpoint 6 Data Register */ 691179595Sbenno#define USBDC_UDDR7 0x0680 /* UDC Endpoint 7 Data Register */ 692179595Sbenno#define USBDC_UDDR8 0x0700 /* UDC Endpoint 8 Data Register */ 693179595Sbenno#define USBDC_UDDR9 0x0900 /* UDC Endpoint 9 Data Register */ 694179595Sbenno#define USBDC_UDDR10 0x00C0 /* UDC Endpoint 10 Data Register */ 695179595Sbenno#define USBDC_UDDR11 0x0B00 /* UDC Endpoint 11 Data Register */ 696179595Sbenno#define USBDC_UDDR12 0x0B80 /* UDC Endpoint 12 Data Register */ 697179595Sbenno#define USBDC_UDDR13 0x0C00 /* UDC Endpoint 13 Data Register */ 698179595Sbenno#define USBDC_UDDR14 0x0E00 /* UDC Endpoint 14 Data Register */ 699179595Sbenno#define USBDC_UDDR15 0x00E0 /* UDC Endpoint 15 Data Register */ 700179595Sbenno 701179595Sbenno#define USBHC_UHCRHDA 0x0048 /* UHC Root Hub Descriptor A */ 702179595Sbenno#define UHCRHDA_POTPGT_SHIFT 24 /* Power on to power good time */ 703179595Sbenno#define UHCRHDA_NOCP (1<<12) /* No over current protection */ 704179595Sbenno#define UHCRHDA_OCPM (1<<11) /* Over current protection mode */ 705179595Sbenno#define UHCRHDA_DT (1<<10) /* Device type */ 706179595Sbenno#define UHCRHDA_NPS (1<<9) /* No power switching */ 707179595Sbenno#define UHCRHDA_PSM (1<<8) /* Power switching mode */ 708179595Sbenno#define UHCRHDA_NDP_MASK 0xff /* Number downstream ports */ 709179595Sbenno#define USBHC_UHCRHDB 0x004c /* UHC Root Hub Descriptor B */ 710179595Sbenno#define USBHC_UHCRHS 0x0050 /* UHC Root Hub Stauts */ 711179595Sbenno#define USBHC_UHCHR 0x0064 /* UHC Reset Register */ 712179595Sbenno#define UHCHR_SSEP3 (1<<11) /* Sleep standby enable for port3 */ 713179595Sbenno#define UHCHR_SSEP2 (1<<10) /* Sleep standby enable for port2 */ 714179595Sbenno#define UHCHR_SSEP1 (1<<9) /* Sleep standby enable for port1 */ 715179595Sbenno#define UHCHR_PCPL (1<<7) /* Power control polarity low */ 716179595Sbenno#define UHCHR_PSPL (1<<6) /* Power sense polarity low */ 717179595Sbenno#define UHCHR_SSE (1<<5) /* Sleep standby enable */ 718179595Sbenno#define UHCHR_UIT (1<<4) /* USB interrupt test */ 719179595Sbenno#define UHCHR_SSDC (1<<3) /* Simulation scale down clock */ 720179595Sbenno#define UHCHR_CGR (1<<2) /* Clock generation reset */ 721179595Sbenno#define UHCHR_FHR (1<<1) /* Force host controller reset */ 722179595Sbenno#define UHCHR_FSBIR (1<<0) /* Force system bus interface reset */ 723179595Sbenno#define UHCHR_MASK 0xeff 724179595Sbenno 725179595Sbenno/* 726179595Sbenno * PWM controller 727179595Sbenno */ 728179595Sbenno#define PWM_PWMCR 0x0000 /* Control register */ 729179595Sbenno#define PWM_PWMDCR 0x0004 /* Duty cycle register */ 730179595Sbenno#define PWM_FD (1<<10) /* Full duty */ 731179595Sbenno#define PWM_PWMPCR 0x0008 /* Period register */ 732179595Sbenno 733179595Sbenno/* 734179595Sbenno * OS timer 735179595Sbenno */ 736179595Sbenno#define OST_MR0 0x00 /* Match register 0 */ 737179595Sbenno#define OST_MR1 0x04 /* Match register 1 */ 738179595Sbenno#define OST_MR2 0x08 /* Match register 2 */ 739179595Sbenno#define OST_MR3 0x0c /* Match register 3 */ 740179595Sbenno#define OST_CR 0x10 /* Count register */ 741179595Sbenno#define OST_SR 0x14 /* Status register */ 742179595Sbenno#define OST_SR_CH0 (1<<0) 743179595Sbenno#define OST_SR_CH1 (1<<1) 744179595Sbenno#define OST_SR_CH2 (1<<2) 745179595Sbenno#define OST_SR_CH3 (1<<3) 746179595Sbenno#define OST_WR 0x18 /* Watchdog enable register */ 747179595Sbenno#define OST_IR 0x1c /* Interrupt enable register */ 748179595Sbenno 749179595Sbenno/* 750179595Sbenno * Interrupt controller 751179595Sbenno */ 752179595Sbenno#define ICU_IP 0x00 /* IRQ pending register */ 753179595Sbenno#define ICU_MR 0x04 /* Mask register */ 754179595Sbenno#define ICU_LR 0x08 /* Level register */ 755179595Sbenno#define ICU_FP 0x0c /* FIQ pending register */ 756179595Sbenno#define ICU_PR 0x10 /* Pending register */ 757179595Sbenno#define ICU_CR 0x14 /* Control register */ 758179595Sbenno 759179595Sbenno#endif /* _ARM_XSCALE_PXAREG_H_ */ 760