1164426Ssam/*- 2164426Ssam * Copyright (c) 2006 Sam Leffler, Errno Consulting 3164426Ssam * All rights reserved. 4164426Ssam * 5164426Ssam * Redistribution and use in source and binary forms, with or without 6164426Ssam * modification, are permitted provided that the following conditions 7164426Ssam * are met: 8164426Ssam * 1. Redistributions of source code must retain the above copyright 9164426Ssam * notice, this list of conditions and the following disclaimer, 10164426Ssam * without modification. 11164426Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12164426Ssam * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13164426Ssam * redistribution must be conditioned upon including a substantially 14164426Ssam * similar Disclaimer requirement for further binary redistribution. 15164426Ssam * 16164426Ssam * NO WARRANTY 17164426Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18164426Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19164426Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20164426Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21164426Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22164426Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23164426Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24164426Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25164426Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26164426Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27164426Ssam * THE POSSIBILITY OF SUCH DAMAGES. 28164426Ssam * 29164426Ssam * $FreeBSD: releng/10.2/sys/arm/xscale/ixp425/if_npereg.h 236987 2012-06-13 04:38:09Z imp $ 30164426Ssam */ 31164426Ssam 32164426Ssam/* 33164426Ssam * Copyright (c) 2001-2005, Intel Corporation. 34164426Ssam * All rights reserved. 35236987Simp * 36164426Ssam * Redistribution and use in source and binary forms, with or without 37164426Ssam * modification, are permitted provided that the following conditions 38164426Ssam * are met: 39164426Ssam * 1. Redistributions of source code must retain the above copyright 40164426Ssam * notice, this list of conditions and the following disclaimer. 41164426Ssam * 2. Redistributions in binary form must reproduce the above copyright 42164426Ssam * notice, this list of conditions and the following disclaimer in the 43164426Ssam * documentation and/or other materials provided with the distribution. 44164426Ssam * 3. Neither the name of the Intel Corporation nor the names of its contributors 45164426Ssam * may be used to endorse or promote products derived from this software 46164426Ssam * without specific prior written permission. 47236987Simp * 48236987Simp * 49164426Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' 50164426Ssam * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 51164426Ssam * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 52164426Ssam * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 53164426Ssam * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 54164426Ssam * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 55164426Ssam * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 56164426Ssam * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 57164426Ssam * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 58164426Ssam * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 59164426Ssam * SUCH DAMAGE. 60164426Ssam */ 61164426Ssam 62164426Ssam#ifndef ARM_XSCALE_IF_NPEREG_H 63164426Ssam#define ARM_XSCALE_IF_NPEREG_H 64164426Ssam 65164426Ssam/* 66164426Ssam * NPE/NPE tx/rx descriptor format. This is just the area 67164426Ssam * shared with ucode running in the NPE; the driver-specific 68164426Ssam * state is defined in the driver. The shared area must be 69164426Ssam * cacheline-aligned. We allocate NPE_MAXSEG "descriptors" 70164426Ssam * per buffer; this allows us to do minimal s/g. The number 71164426Ssam * of descriptors can be expanded but doing so uses memory 72164426Ssam * so should be done with care. 73164426Ssam * 74164426Ssam * The driver sets up buffers in uncached memory. 75164426Ssam */ 76164426Ssam#define NPE_MAXSEG 3 /* empirically selected */ 77164426Ssam 78164426Ssamstruct npehwbuf { 79164426Ssam struct { /* NPE shared area, cacheline aligned */ 80164426Ssam uint32_t next; /* phys addr of next segment */ 81164426Ssam uint32_t len; /* buffer/segment length (bytes) */ 82164426Ssam uint32_t data; /* phys addr of data segment */ 83164426Ssam uint32_t pad[5]; /* pad to cacheline */ 84164426Ssam } ix_ne[NPE_MAXSEG]; 85164426Ssam}; 86164426Ssam 87164426Ssam#define NPE_FRAME_SIZE_DEFAULT 1536 88164426Ssam#define NPE_FRAME_SIZE_MAX (65536-64) 89164426Ssam#define NPE_FRAME_SIZE_MIN 64 90164426Ssam 91164426Ssam/* 92164426Ssam * Queue Manager-related definitions. 93164426Ssam * 94164426Ssam * These define the layout of 32-bit Q entries passed 95164426Ssam * between the host cpu and the NPE's. 96164426Ssam */ 97164426Ssam#define NPE_QM_Q_NPE(e) (((e)>>0)&0x3) /* NPE ID */ 98164426Ssam#define NPE_QM_Q_PORT(e) (((e)>>3)&0x1) /* Port ID */ 99164426Ssam#define NPE_QM_Q_PRIO(e) (((e)>>0)&0x3) /* 802.1d priority */ 100164426Ssam#define NPE_QM_Q_ADDR(e) ((e)&0xfffffffe0) /* phys address */ 101164426Ssam 102164426Ssam/* 103164426Ssam * Host->NPE requests written to the shared mailbox. 104164426Ssam * The NPE writes the same value back as an ACK. 105164426Ssam */ 106164426Ssam#define NPE_GETSTATUS 0x00 /* get firmware revision */ 107164426Ssam#define NPE_SETPORTADDRESS 0x01 /* set port id and mac address */ 108164426Ssam#define NPE_GETMACADDRDB 0x02 /* upload filter database */ 109164426Ssam#define NPE_SETMACADDRDB 0x03 /* download filter database */ 110164426Ssam#define NPE_GETSTATS 0x04 /* get statistics */ 111164426Ssam#define NPE_RESETSTATS 0x05 /* reset stats + return result */ 112164426Ssam#define NPE_SETMAXFRAME 0x06 /* configure max tx/rx frame lengths */ 113164426Ssam#define NPE_SETRXTAGMODE 0x07 /* configure VLAN rx operating mode */ 114164426Ssam#define NPE_SETDEFRXVID 0x08 /* set def VLAN tag + traffic class */ 115164426Ssam#define NPE_SETRXQOSENTRY 0x0b /* map user pri -> QoS class+rx qid */ 116164426Ssam#define NPE_SETFIREWALLMODE 0x0e /* config firewall services */ 117164426Ssam#define NPE_SETLOOPBACK 0x12 /* enable/disable loopback */ 118164426Ssam/* ... XXX more */ 119164426Ssam 120164426Ssam#define NPE_MAC_MSGID_SHL 24 121164426Ssam#define NPE_MAC_PORTID_SHL 16 122164426Ssam 123164426Ssam/* 124164426Ssam * MAC register definitions; see section 125164426Ssam * 15.2 of the Intel Developers Manual. 126164426Ssam */ 127164426Ssam#define NPE_MAC_TX_CNTRL1 0x000 128164426Ssam#define NPE_MAC_TX_CNTRL2 0x004 129164426Ssam#define NPE_MAC_RX_CNTRL1 0x010 130164426Ssam#define NPE_MAC_RX_CNTRL2 0x014 131164426Ssam#define NPE_MAC_RANDOM_SEED 0x020 132164426Ssam#define NPE_MAC_THRESH_P_EMPTY 0x030 133164426Ssam#define NPE_MAC_THRESH_P_FULL 0x038 134164426Ssam#define NPE_MAC_BUF_SIZE_TX 0x040 135164426Ssam#define NPE_MAC_TX_DEFER 0x050 136164426Ssam#define NPE_MAC_RX_DEFER 0x054 137164426Ssam#define NPE_MAC_TX_TWO_DEFER_1 0x060 138164426Ssam#define NPE_MAC_TX_TWO_DEFER_2 0x064 139164426Ssam#define NPE_MAC_SLOT_TIME 0x070 140164426Ssam#define NPE_MAC_MDIO_CMD_1 0x080 141164426Ssam#define NPE_MAC_MDIO_CMD_2 0x084 142164426Ssam#define NPE_MAC_MDIO_CMD_3 0x088 143164426Ssam#define NPE_MAC_MDIO_CMD_4 0x08c 144164426Ssam#define NPE_MAC_MDIO_STS_1 0x090 145164426Ssam#define NPE_MAC_MDIO_STS_2 0x094 146164426Ssam#define NPE_MAC_MDIO_STS_3 0x098 147164426Ssam#define NPE_MAC_MDIO_STS_4 0x09c 148164426Ssam#define NPE_MAC_ADDR_MASK_1 0x0A0 149164426Ssam#define NPE_MAC_ADDR_MASK_2 0x0A4 150164426Ssam#define NPE_MAC_ADDR_MASK_3 0x0A8 151164426Ssam#define NPE_MAC_ADDR_MASK_4 0x0AC 152164426Ssam#define NPE_MAC_ADDR_MASK_5 0x0B0 153164426Ssam#define NPE_MAC_ADDR_MASK_6 0x0B4 154164426Ssam#define NPE_MAC_ADDR_1 0x0C0 155164426Ssam#define NPE_MAC_ADDR_2 0x0C4 156164426Ssam#define NPE_MAC_ADDR_3 0x0C8 157164426Ssam#define NPE_MAC_ADDR_4 0x0CC 158164426Ssam#define NPE_MAC_ADDR_5 0x0D0 159164426Ssam#define NPE_MAC_ADDR_6 0x0D4 160164426Ssam#define NPE_MAC_INT_CLK_THRESH 0x0E0 161164426Ssam#define NPE_MAC_UNI_ADDR_1 0x0F0 162164426Ssam#define NPE_MAC_UNI_ADDR_2 0x0F4 163164426Ssam#define NPE_MAC_UNI_ADDR_3 0x0F8 164164426Ssam#define NPE_MAC_UNI_ADDR_4 0x0FC 165164426Ssam#define NPE_MAC_UNI_ADDR_5 0x100 166164426Ssam#define NPE_MAC_UNI_ADDR_6 0x104 167164426Ssam#define NPE_MAC_CORE_CNTRL 0x1FC 168164426Ssam 169164426Ssam#define NPE_MAC_ADDR_MASK(i) (NPE_MAC_ADDR_MASK_1 + ((i)<<2)) 170164426Ssam#define NPE_MAC_ADDR(i) (NPE_MAC_ADDR_1 + ((i)<<2)) 171164426Ssam#define NPE_MAC_UNI_ADDR(i) (NPE_MAC_UNI_ADDR_1 + ((i)<<2)) 172164426Ssam 173164426Ssam/* 174164426Ssam * Bit definitions 175164426Ssam */ 176164426Ssam 177164426Ssam/* TX Control Register 1*/ 178164426Ssam#define NPE_TX_CNTRL1_TX_EN 0x01 /* enable TX engine */ 179164426Ssam#define NPE_TX_CNTRL1_DUPLEX 0x02 /* select half duplex */ 180164426Ssam#define NPE_TX_CNTRL1_RETRY 0x04 /* auto-retry on collision */ 181164426Ssam#define NPE_TX_CNTRL1_PAD_EN 0x08 /* pad frames <64 bytes */ 182164426Ssam#define NPE_TX_CNTRL1_FCS_EN 0x10 /* append FCS */ 183164426Ssam#define NPE_TX_CNTRL1_2DEFER 0x20 /* select 2-part deferral */ 184164426Ssam#define NPE_TX_CNTRL1_RMII 0x40 185164426Ssam 186164426Ssam/* TX Control Register 2 */ 187164426Ssam#define NPE_TX_CNTRL2_RETRIES_MASK 0xf /* max retry count */ 188164426Ssam 189164426Ssam/* RX Control Register 1 */ 190164426Ssam#define NPE_RX_CNTRL1_RX_EN 0x01 /* enable RX engine */ 191164426Ssam#define NPE_RX_CNTRL1_PADSTRIP_EN 0x02 /* strip frame padding */ 192164426Ssam#define NPE_RX_CNTRL1_CRC_EN 0x04 /* include CRC in RX frame */ 193164426Ssam#define NPE_RX_CNTRL1_PAUSE_EN 0x08 /* detect Pause frames */ 194164426Ssam#define NPE_RX_CNTRL1_LOOP_EN 0x10 /* loopback tx/rx */ 195164426Ssam#define NPE_RX_CNTRL1_ADDR_FLTR_EN 0x20 /* enable address filtering */ 196164426Ssam#define NPE_RX_CNTRL1_RX_RUNT_EN 0x40 /* enable RX of runt frames */ 197164426Ssam#define NPE_RX_CNTRL1_BCAST_DIS 0x80 /* discard broadcast frames */ 198164426Ssam 199164426Ssam/* RX Control Register 2 */ 200164426Ssam#define NPE_RX_CNTRL2_DEFER_EN 0x01 201164426Ssam 202164426Ssam/* Core Control Register */ 203164426Ssam#define NPE_CORE_RESET 0x01 /* MAC reset state */ 204164426Ssam#define NPE_CORE_RX_FIFO_FLUSH 0x02 /* flush RX FIFO */ 205164426Ssam#define NPE_CORE_TX_FIFO_FLUSH 0x04 /* flush TX FIFO */ 206164426Ssam#define NPE_CORE_SEND_JAM 0x08 /* send JAM on packet RX */ 207164426Ssam#define NPE_CORE_MDC_EN 0x10 /* IXP42X drives MDC clock */ 208164426Ssam 209164426Ssam/* 210164426Ssam * Stat block returned by NPE with NPE_GETSTATS msg. 211164426Ssam */ 212164426Ssamstruct npestats { 213164426Ssam uint32_t dot3StatsAlignmentErrors; 214164426Ssam uint32_t dot3StatsFCSErrors; 215164426Ssam uint32_t dot3StatsInternalMacReceiveErrors; 216164426Ssam uint32_t RxOverrunDiscards; 217164426Ssam uint32_t RxLearnedEntryDiscards; 218164426Ssam uint32_t RxLargeFramesDiscards; 219164426Ssam uint32_t RxSTPBlockedDiscards; 220164426Ssam uint32_t RxVLANTypeFilterDiscards; 221164426Ssam uint32_t RxVLANIdFilterDiscards; 222164426Ssam uint32_t RxInvalidSourceDiscards; 223164426Ssam uint32_t RxBlackListDiscards; 224164426Ssam uint32_t RxWhiteListDiscards; 225164426Ssam uint32_t RxUnderflowEntryDiscards; 226164426Ssam uint32_t dot3StatsSingleCollisionFrames; 227164426Ssam uint32_t dot3StatsMultipleCollisionFrames; 228164426Ssam uint32_t dot3StatsDeferredTransmissions; 229164426Ssam uint32_t dot3StatsLateCollisions; 230164426Ssam uint32_t dot3StatsExcessiveCollisions; 231164426Ssam uint32_t dot3StatsInternalMacTransmitErrors; 232164426Ssam uint32_t dot3StatsCarrierSenseErrors; 233164426Ssam uint32_t TxLargeFrameDiscards; 234164426Ssam uint32_t TxVLANIdFilterDiscards; 235164426Ssam}; 236164426Ssam 237164426Ssam/* 238164426Ssam * Default values 239164426Ssam */ 240164426Ssam#define NPE_MAC_INT_CLK_THRESH_DEFAULT 0x1 241164426Ssam 242164426Ssam#define NPE_MAC_RESET_DELAY 1 243164426Ssam 244164426Ssam/* This value applies to RMII */ 245164426Ssam#define NPE_MAC_SLOT_TIME_RMII_DEFAULT 0xFF 246164426Ssam 247164426Ssam/* 248164426Ssam * MII definitions - these have been verified against the LXT971 and LXT972 PHYs 249164426Ssam */ 250164426Ssam#define NPE_MII_REG_SHL 16 251164426Ssam#define NPE_MII_ADDR_SHL 21 252164426Ssam 253164426Ssam/* NB: shorthands for mii bus mdio routines */ 254164426Ssam#define NPE_MAC_MDIO_CMD NPE_MAC_MDIO_CMD_1 255164426Ssam#define NPE_MAC_MDIO_STS NPE_MAC_MDIO_STS_1 256236987Simp 257164426Ssam#define NPE_MII_GO (1<<31) 258164426Ssam#define NPE_MII_WRITE (1<<26) 259236987Simp#define NPE_MII_TIMEOUT_10TH_SECS 5 260164426Ssam#define NPE_MII_10TH_SEC_IN_MILLIS 100 261164426Ssam#define NPE_MII_READ_FAIL (1<<31) 262236987Simp 263164426Ssam#define NPE_MII_PHY_DEF_DELAY 300 /* max delay before link up, etc. */ 264164426Ssam#define NPE_MII_PHY_NO_DELAY 0x0 /* do not delay */ 265164426Ssam#define NPE_MII_PHY_NULL 0xff /* PHY is not present */ 266164426Ssam#define NPE_MII_PHY_DEF_ADDR 0x0 /* default PHY's logical address */ 267164426Ssam 268236987Simp/* Register definition */ 269164426Ssam#define NPE_MII_CTRL_REG 0x0 /* Control Register */ 270164426Ssam#define NPE_MII_STAT_REG 0x1 /* Status Register */ 271164426Ssam#define NPE_MII_PHY_ID1_REG 0x2 /* PHY identifier 1 Register */ 272164426Ssam#define NPE_MII_PHY_ID2_REG 0x3 /* PHY identifier 2 Register */ 273164426Ssam#define NPE_MII_AN_ADS_REG 0x4 /* Auto-Negotiation */ 274164426Ssam /* Advertisement Register */ 275164426Ssam#define NPE_MII_AN_PRTN_REG 0x5 /* Auto-Negotiation */ 276164426Ssam /* partner ability Register */ 277164426Ssam#define NPE_MII_AN_EXP_REG 0x6 /* Auto-Negotiation */ 278164426Ssam /* Expansion Register */ 279164426Ssam#define NPE_MII_AN_NEXT_REG 0x7 /* Auto-Negotiation */ 280164426Ssam /* next-page transmit Register */ 281164426Ssam#endif /* ARM_XSCALE_IF_NPEREG_H */ 282