sp804.c revision 259329
1/* 2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * Copyright (c) 2012 Damjan Marion <dmarion@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: stable/10/sys/arm/versatile/sp804.c 259329 2013-12-13 20:43:11Z ian $"); 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/bus.h> 34#include <sys/kernel.h> 35#include <sys/module.h> 36#include <sys/malloc.h> 37#include <sys/rman.h> 38#include <sys/timeet.h> 39#include <sys/timetc.h> 40#include <sys/watchdog.h> 41#include <machine/bus.h> 42#include <machine/cpu.h> 43#include <machine/intr.h> 44 45#include <dev/fdt/fdt_common.h> 46#include <dev/ofw/openfirm.h> 47#include <dev/ofw/ofw_bus.h> 48#include <dev/ofw/ofw_bus_subr.h> 49 50#include <machine/bus.h> 51#include <machine/fdt.h> 52 53#define SP804_TIMER1_LOAD 0x00 54#define SP804_TIMER1_VALUE 0x04 55#define SP804_TIMER1_CONTROL 0x08 56#define TIMER_CONTROL_EN (1 << 7) 57#define TIMER_CONTROL_FREERUN (0 << 6) 58#define TIMER_CONTROL_PERIODIC (1 << 6) 59#define TIMER_CONTROL_INTREN (1 << 5) 60#define TIMER_CONTROL_DIV1 (0 << 2) 61#define TIMER_CONTROL_DIV16 (1 << 2) 62#define TIMER_CONTROL_DIV256 (2 << 2) 63#define TIMER_CONTROL_32BIT (1 << 1) 64#define TIMER_CONTROL_ONESHOT (1 << 0) 65#define SP804_TIMER1_INTCLR 0x0C 66#define SP804_TIMER1_RIS 0x10 67#define SP804_TIMER1_MIS 0x14 68#define SP804_TIMER1_BGLOAD 0x18 69#define SP804_TIMER2_LOAD 0x20 70#define SP804_TIMER2_VALUE 0x24 71#define SP804_TIMER2_CONTROL 0x28 72#define SP804_TIMER2_INTCLR 0x2C 73#define SP804_TIMER2_RIS 0x30 74#define SP804_TIMER2_MIS 0x34 75#define SP804_TIMER2_BGLOAD 0x38 76 77#define SP804_PERIPH_ID0 0xFE0 78#define SP804_PERIPH_ID1 0xFE4 79#define SP804_PERIPH_ID2 0xFE8 80#define SP804_PERIPH_ID3 0xFEC 81#define SP804_PRIMECELL_ID0 0xFF0 82#define SP804_PRIMECELL_ID1 0xFF4 83#define SP804_PRIMECELL_ID2 0xFF8 84#define SP804_PRIMECELL_ID3 0xFFC 85 86#define DEFAULT_FREQUENCY 1000000 87/* 88 * QEMU seems to have problem with full frequency 89 */ 90#define DEFAULT_DIVISOR 16 91#define DEFAULT_CONTROL_DIV TIMER_CONTROL_DIV16 92 93struct sp804_timer_softc { 94 struct resource* mem_res; 95 struct resource* irq_res; 96 void* intr_hl; 97 uint32_t sysclk_freq; 98 bus_space_tag_t bst; 99 bus_space_handle_t bsh; 100 struct timecounter tc; 101 bool et_enabled; 102 struct eventtimer et; 103}; 104 105/* Read/Write macros for Timer used as timecounter */ 106#define sp804_timer_tc_read_4(reg) \ 107 bus_space_read_4(sc->bst, sc->bsh, reg) 108 109#define sp804_timer_tc_write_4(reg, val) \ 110 bus_space_write_4(sc->bst, sc->bsh, reg, val) 111 112static unsigned sp804_timer_tc_get_timecount(struct timecounter *); 113 114static unsigned 115sp804_timer_tc_get_timecount(struct timecounter *tc) 116{ 117 struct sp804_timer_softc *sc = tc->tc_priv; 118 return 0xffffffff - sp804_timer_tc_read_4(SP804_TIMER1_VALUE); 119} 120 121static int 122sp804_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 123{ 124 struct sp804_timer_softc *sc = et->et_priv; 125 uint32_t count, reg; 126 127 if (first != 0) { 128 sc->et_enabled = 1; 129 130 count = ((uint32_t)et->et_frequency * first) >> 32; 131 132 sp804_timer_tc_write_4(SP804_TIMER2_LOAD, count); 133 reg = TIMER_CONTROL_32BIT | TIMER_CONTROL_INTREN | 134 TIMER_CONTROL_PERIODIC | DEFAULT_CONTROL_DIV | 135 TIMER_CONTROL_EN; 136 sp804_timer_tc_write_4(SP804_TIMER2_CONTROL, reg); 137 138 return (0); 139 } 140 141 if (period != 0) { 142 panic("period"); 143 } 144 145 return (EINVAL); 146} 147 148static int 149sp804_timer_stop(struct eventtimer *et) 150{ 151 struct sp804_timer_softc *sc = et->et_priv; 152 uint32_t reg; 153 154 sc->et_enabled = 0; 155 reg = sp804_timer_tc_read_4(SP804_TIMER2_CONTROL); 156 reg &= ~(TIMER_CONTROL_EN); 157 sp804_timer_tc_write_4(SP804_TIMER2_CONTROL, reg); 158 159 return (0); 160} 161 162static int 163sp804_timer_intr(void *arg) 164{ 165 struct sp804_timer_softc *sc = arg; 166 static uint32_t prev = 0; 167 uint32_t x = 0; 168 169 x = sp804_timer_tc_read_4(SP804_TIMER1_VALUE); 170 171 prev =x ; 172 sp804_timer_tc_write_4(SP804_TIMER2_INTCLR, 1); 173 if (sc->et_enabled) { 174 if (sc->et.et_active) { 175 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 176 } 177 } 178 179 return (FILTER_HANDLED); 180} 181 182static int 183sp804_timer_probe(device_t dev) 184{ 185 186 if (ofw_bus_is_compatible(dev, "arm,sp804")) { 187 device_set_desc(dev, "SP804 System Timer"); 188 return (BUS_PROBE_DEFAULT); 189 } 190 191 return (ENXIO); 192} 193 194static int 195sp804_timer_attach(device_t dev) 196{ 197 struct sp804_timer_softc *sc = device_get_softc(dev); 198 int rid = 0; 199 int i; 200 uint32_t id, reg; 201 202 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 203 if (sc->mem_res == NULL) { 204 device_printf(dev, "could not allocate memory resource\n"); 205 return (ENXIO); 206 } 207 208 sc->bst = rman_get_bustag(sc->mem_res); 209 sc->bsh = rman_get_bushandle(sc->mem_res); 210 211 /* Request the IRQ resources */ 212 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); 213 if (sc->irq_res == NULL) { 214 device_printf(dev, "Error: could not allocate irq resources\n"); 215 return (ENXIO); 216 } 217 218 /* TODO: get frequency from FDT */ 219 sc->sysclk_freq = DEFAULT_FREQUENCY; 220 221 /* Setup and enable the timer */ 222 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_CLK, 223 sp804_timer_intr, NULL, sc, 224 &sc->intr_hl) != 0) { 225 bus_release_resource(dev, SYS_RES_IRQ, rid, 226 sc->irq_res); 227 device_printf(dev, "Unable to setup the clock irq handler.\n"); 228 return (ENXIO); 229 } 230 231 sp804_timer_tc_write_4(SP804_TIMER1_CONTROL, 0); 232 sp804_timer_tc_write_4(SP804_TIMER2_CONTROL, 0); 233 234 /* 235 * Timer 1, timecounter 236 */ 237 sc->tc.tc_frequency = DEFAULT_FREQUENCY; 238 sc->tc.tc_name = "SP804 Timecouter"; 239 sc->tc.tc_get_timecount = sp804_timer_tc_get_timecount; 240 sc->tc.tc_poll_pps = NULL; 241 sc->tc.tc_counter_mask = ~0u; 242 sc->tc.tc_quality = 1000; 243 sc->tc.tc_priv = sc; 244 245 sp804_timer_tc_write_4(SP804_TIMER1_VALUE, 0xffffffff); 246 sp804_timer_tc_write_4(SP804_TIMER1_LOAD, 0xffffffff); 247 reg = TIMER_CONTROL_PERIODIC | TIMER_CONTROL_32BIT; 248 sp804_timer_tc_write_4(SP804_TIMER1_CONTROL, reg); 249 reg |= TIMER_CONTROL_EN; 250 sp804_timer_tc_write_4(SP804_TIMER1_CONTROL, reg); 251 tc_init(&sc->tc); 252 253 /* 254 * Timer 2, event timer 255 */ 256 sc->et_enabled = 0; 257 sc->et.et_name = malloc(64, M_DEVBUF, M_NOWAIT | M_ZERO); 258 sprintf(sc->et.et_name, "SP804 Event Timer %d", 259 device_get_unit(dev)); 260 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 261 sc->et.et_quality = 1000; 262 sc->et.et_frequency = sc->sysclk_freq / DEFAULT_DIVISOR; 263 sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency; 264 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; 265 sc->et.et_start = sp804_timer_start; 266 sc->et.et_stop = sp804_timer_stop; 267 sc->et.et_priv = sc; 268 et_register(&sc->et); 269 270 id = 0; 271 for (i = 3; i >= 0; i--) { 272 id = (id << 8) | 273 (sp804_timer_tc_read_4(SP804_PERIPH_ID0 + i*4) & 0xff); 274 } 275 276 device_printf(dev, "peripheral ID: %08x\n", id); 277 278 id = 0; 279 for (i = 3; i >= 0; i--) { 280 id = (id << 8) | 281 (sp804_timer_tc_read_4(SP804_PRIMECELL_ID0 + i*4) & 0xff); 282 } 283 284 device_printf(dev, "PrimeCell ID: %08x\n", id); 285 286 return (0); 287} 288 289static device_method_t sp804_timer_methods[] = { 290 DEVMETHOD(device_probe, sp804_timer_probe), 291 DEVMETHOD(device_attach, sp804_timer_attach), 292 { 0, 0 } 293}; 294 295static driver_t sp804_timer_driver = { 296 "timer", 297 sp804_timer_methods, 298 sizeof(struct sp804_timer_softc), 299}; 300 301static devclass_t sp804_timer_devclass; 302 303DRIVER_MODULE(sp804_timer, simplebus, sp804_timer_driver, sp804_timer_devclass, 0, 0); 304 305void 306DELAY(int usec) 307{ 308 int32_t counts; 309 uint32_t first, last; 310 device_t timer_dev; 311 struct sp804_timer_softc *sc; 312 313 timer_dev = devclass_get_device(sp804_timer_devclass, 0); 314 315 if (timer_dev == NULL) { 316 /* 317 * Timer is not initialized yet 318 */ 319 for (; usec > 0; usec--) 320 for (counts = 200; counts > 0; counts--) 321 /* Prevent gcc from optimizing out the loop */ 322 cpufunc_nullop(); 323 return; 324 } 325 326 sc = device_get_softc(timer_dev); 327 328 /* Get the number of times to count */ 329 counts = usec * ((sc->tc.tc_frequency / 1000000) + 1); 330 331 first = sp804_timer_tc_get_timecount(&sc->tc); 332 333 while (counts > 0) { 334 last = sp804_timer_tc_get_timecount(&sc->tc); 335 if (last == first) 336 continue; 337 if (last>first) { 338 counts -= (int32_t)(last - first); 339 } else { 340 counts -= (int32_t)((0xFFFFFFFF - first) + last); 341 } 342 first = last; 343 } 344} 345