sp804.c revision 247463
1/* 2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * Copyright (c) 2012 Damjan Marion <dmarion@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/arm/versatile/sp804.c 247463 2013-02-28 13:46:03Z mav $"); 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/bus.h> 34#include <sys/kernel.h> 35#include <sys/module.h> 36#include <sys/malloc.h> 37#include <sys/rman.h> 38#include <sys/timeet.h> 39#include <sys/timetc.h> 40#include <sys/watchdog.h> 41#include <machine/bus.h> 42#include <machine/cpu.h> 43#include <machine/frame.h> 44#include <machine/intr.h> 45 46#include <dev/fdt/fdt_common.h> 47#include <dev/ofw/openfirm.h> 48#include <dev/ofw/ofw_bus.h> 49#include <dev/ofw/ofw_bus_subr.h> 50 51#include <machine/bus.h> 52#include <machine/fdt.h> 53 54#define SP804_TIMER1_LOAD 0x00 55#define SP804_TIMER1_VALUE 0x04 56#define SP804_TIMER1_CONTROL 0x08 57#define TIMER_CONTROL_EN (1 << 7) 58#define TIMER_CONTROL_FREERUN (0 << 6) 59#define TIMER_CONTROL_PERIODIC (1 << 6) 60#define TIMER_CONTROL_INTREN (1 << 5) 61#define TIMER_CONTROL_DIV1 (0 << 2) 62#define TIMER_CONTROL_DIV16 (1 << 2) 63#define TIMER_CONTROL_DIV256 (2 << 2) 64#define TIMER_CONTROL_32BIT (1 << 1) 65#define TIMER_CONTROL_ONESHOT (1 << 0) 66#define SP804_TIMER1_INTCLR 0x0C 67#define SP804_TIMER1_RIS 0x10 68#define SP804_TIMER1_MIS 0x14 69#define SP804_TIMER1_BGLOAD 0x18 70#define SP804_TIMER2_LOAD 0x20 71#define SP804_TIMER2_VALUE 0x24 72#define SP804_TIMER2_CONTROL 0x28 73#define SP804_TIMER2_INTCLR 0x2C 74#define SP804_TIMER2_RIS 0x30 75#define SP804_TIMER2_MIS 0x34 76#define SP804_TIMER2_BGLOAD 0x38 77 78#define SP804_PERIPH_ID0 0xFE0 79#define SP804_PERIPH_ID1 0xFE4 80#define SP804_PERIPH_ID2 0xFE8 81#define SP804_PERIPH_ID3 0xFEC 82#define SP804_PRIMECELL_ID0 0xFF0 83#define SP804_PRIMECELL_ID1 0xFF4 84#define SP804_PRIMECELL_ID2 0xFF8 85#define SP804_PRIMECELL_ID3 0xFFC 86 87#define DEFAULT_FREQUENCY 1000000 88/* 89 * QEMU seems to have problem with full frequency 90 */ 91#define DEFAULT_DIVISOR 16 92#define DEFAULT_CONTROL_DIV TIMER_CONTROL_DIV16 93 94struct sp804_timer_softc { 95 struct resource* mem_res; 96 struct resource* irq_res; 97 void* intr_hl; 98 uint32_t sysclk_freq; 99 bus_space_tag_t bst; 100 bus_space_handle_t bsh; 101 struct timecounter tc; 102 bool et_enabled; 103 struct eventtimer et; 104}; 105 106/* Read/Write macros for Timer used as timecounter */ 107#define sp804_timer_tc_read_4(reg) \ 108 bus_space_read_4(sc->bst, sc->bsh, reg) 109 110#define sp804_timer_tc_write_4(reg, val) \ 111 bus_space_write_4(sc->bst, sc->bsh, reg, val) 112 113static unsigned sp804_timer_tc_get_timecount(struct timecounter *); 114 115static unsigned 116sp804_timer_tc_get_timecount(struct timecounter *tc) 117{ 118 struct sp804_timer_softc *sc = tc->tc_priv; 119 return 0xffffffff - sp804_timer_tc_read_4(SP804_TIMER1_VALUE); 120} 121 122static int 123sp804_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 124{ 125 struct sp804_timer_softc *sc = et->et_priv; 126 uint32_t count, reg; 127 128 if (first != 0) { 129 sc->et_enabled = 1; 130 131 count = ((uint32_t)et->et_frequency * first) >> 32; 132 133 sp804_timer_tc_write_4(SP804_TIMER2_LOAD, count); 134 reg = TIMER_CONTROL_32BIT | TIMER_CONTROL_INTREN | 135 TIMER_CONTROL_PERIODIC | DEFAULT_CONTROL_DIV | 136 TIMER_CONTROL_EN; 137 sp804_timer_tc_write_4(SP804_TIMER2_CONTROL, reg); 138 139 return (0); 140 } 141 142 if (period != 0) { 143 panic("period"); 144 } 145 146 return (EINVAL); 147} 148 149static int 150sp804_timer_stop(struct eventtimer *et) 151{ 152 struct sp804_timer_softc *sc = et->et_priv; 153 uint32_t reg; 154 155 sc->et_enabled = 0; 156 reg = sp804_timer_tc_read_4(SP804_TIMER2_CONTROL); 157 reg &= ~(TIMER_CONTROL_EN); 158 sp804_timer_tc_write_4(SP804_TIMER2_CONTROL, reg); 159 160 return (0); 161} 162 163static int 164sp804_timer_intr(void *arg) 165{ 166 struct sp804_timer_softc *sc = arg; 167 static uint32_t prev = 0; 168 uint32_t x = 0; 169 170 x = sp804_timer_tc_read_4(SP804_TIMER1_VALUE); 171 172 prev =x ; 173 sp804_timer_tc_write_4(SP804_TIMER2_INTCLR, 1); 174 if (sc->et_enabled) { 175 if (sc->et.et_active) { 176 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 177 } 178 } 179 180 return (FILTER_HANDLED); 181} 182 183static int 184sp804_timer_probe(device_t dev) 185{ 186 187 if (ofw_bus_is_compatible(dev, "arm,sp804")) { 188 device_set_desc(dev, "SP804 System Timer"); 189 return (BUS_PROBE_DEFAULT); 190 } 191 192 return (ENXIO); 193} 194 195static int 196sp804_timer_attach(device_t dev) 197{ 198 struct sp804_timer_softc *sc = device_get_softc(dev); 199 int rid = 0; 200 int i; 201 uint32_t id, reg; 202 203 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 204 if (sc->mem_res == NULL) { 205 device_printf(dev, "could not allocate memory resource\n"); 206 return (ENXIO); 207 } 208 209 sc->bst = rman_get_bustag(sc->mem_res); 210 sc->bsh = rman_get_bushandle(sc->mem_res); 211 212 /* Request the IRQ resources */ 213 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); 214 if (sc->irq_res == NULL) { 215 device_printf(dev, "Error: could not allocate irq resources\n"); 216 return (ENXIO); 217 } 218 219 /* TODO: get frequency from FDT */ 220 sc->sysclk_freq = DEFAULT_FREQUENCY; 221 222 /* Setup and enable the timer */ 223 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_CLK, 224 sp804_timer_intr, NULL, sc, 225 &sc->intr_hl) != 0) { 226 bus_release_resource(dev, SYS_RES_IRQ, rid, 227 sc->irq_res); 228 device_printf(dev, "Unable to setup the clock irq handler.\n"); 229 return (ENXIO); 230 } 231 232 sp804_timer_tc_write_4(SP804_TIMER1_CONTROL, 0); 233 sp804_timer_tc_write_4(SP804_TIMER2_CONTROL, 0); 234 235 /* 236 * Timer 1, timecounter 237 */ 238 sc->tc.tc_frequency = DEFAULT_FREQUENCY; 239 sc->tc.tc_name = "SP804 Timecouter"; 240 sc->tc.tc_get_timecount = sp804_timer_tc_get_timecount; 241 sc->tc.tc_poll_pps = NULL; 242 sc->tc.tc_counter_mask = ~0u; 243 sc->tc.tc_quality = 1000; 244 sc->tc.tc_priv = sc; 245 246 sp804_timer_tc_write_4(SP804_TIMER1_VALUE, 0xffffffff); 247 sp804_timer_tc_write_4(SP804_TIMER1_LOAD, 0xffffffff); 248 reg = TIMER_CONTROL_PERIODIC | TIMER_CONTROL_32BIT; 249 sp804_timer_tc_write_4(SP804_TIMER1_CONTROL, reg); 250 reg |= TIMER_CONTROL_EN; 251 sp804_timer_tc_write_4(SP804_TIMER1_CONTROL, reg); 252 tc_init(&sc->tc); 253 254 /* 255 * Timer 2, event timer 256 */ 257 sc->et_enabled = 0; 258 sc->et.et_name = malloc(64, M_DEVBUF, M_NOWAIT | M_ZERO); 259 sprintf(sc->et.et_name, "SP804 Event Timer %d", 260 device_get_unit(dev)); 261 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 262 sc->et.et_quality = 1000; 263 sc->et.et_frequency = sc->sysclk_freq / DEFAULT_DIVISOR; 264 sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency; 265 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; 266 sc->et.et_start = sp804_timer_start; 267 sc->et.et_stop = sp804_timer_stop; 268 sc->et.et_priv = sc; 269 et_register(&sc->et); 270 271 id = 0; 272 for (i = 3; i >= 0; i--) { 273 id = (id << 8) | 274 (sp804_timer_tc_read_4(SP804_PERIPH_ID0 + i*4) & 0xff); 275 } 276 277 device_printf(dev, "peripheral ID: %08x\n", id); 278 279 id = 0; 280 for (i = 3; i >= 0; i--) { 281 id = (id << 8) | 282 (sp804_timer_tc_read_4(SP804_PRIMECELL_ID0 + i*4) & 0xff); 283 } 284 285 device_printf(dev, "PrimeCell ID: %08x\n", id); 286 287 return (0); 288} 289 290static device_method_t sp804_timer_methods[] = { 291 DEVMETHOD(device_probe, sp804_timer_probe), 292 DEVMETHOD(device_attach, sp804_timer_attach), 293 { 0, 0 } 294}; 295 296static driver_t sp804_timer_driver = { 297 "timer", 298 sp804_timer_methods, 299 sizeof(struct sp804_timer_softc), 300}; 301 302static devclass_t sp804_timer_devclass; 303 304DRIVER_MODULE(sp804_timer, simplebus, sp804_timer_driver, sp804_timer_devclass, 0, 0); 305 306void 307DELAY(int usec) 308{ 309 int32_t counts; 310 uint32_t first, last; 311 device_t timer_dev; 312 struct sp804_timer_softc *sc; 313 314 timer_dev = devclass_get_device(sp804_timer_devclass, 0); 315 316 if (timer_dev == NULL) { 317 /* 318 * Timer is not initialized yet 319 */ 320 for (; usec > 0; usec--) 321 for (counts = 200; counts > 0; counts--) 322 /* Prevent gcc from optimizing out the loop */ 323 cpufunc_nullop(); 324 return; 325 } 326 327 sc = device_get_softc(timer_dev); 328 329 /* Get the number of times to count */ 330 counts = usec * ((sc->tc.tc_frequency / 1000000) + 1); 331 332 first = sp804_timer_tc_get_timecount(&sc->tc); 333 334 while (counts > 0) { 335 last = sp804_timer_tc_get_timecount(&sc->tc); 336 if (last == first) 337 continue; 338 if (last>first) { 339 counts -= (int32_t)(last - first); 340 } else { 341 counts -= (int32_t)((0xFFFFFFFF - first) + last); 342 } 343 first = last; 344 } 345} 346