1273257Srpaulo/*- 2273257Srpaulo * Copyright (c) 2014 Rui Paulo <rpaulo@FreeBSD.org> 3273257Srpaulo * All rights reserved. 4273257Srpaulo * 5273257Srpaulo * Redistribution and use in source and binary forms, with or without 6273257Srpaulo * modification, are permitted provided that the following conditions 7273257Srpaulo * are met: 8273257Srpaulo * 1. Redistributions of source code must retain the above copyright 9273257Srpaulo * notice, this list of conditions and the following disclaimer. 10273257Srpaulo * 2. Redistributions in binary form must reproduce the above copyright 11273257Srpaulo * notice, this list of conditions and the following disclaimer in the 12273257Srpaulo * documentation and/or other materials provided with the distribution. 13273257Srpaulo * 14273257Srpaulo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15273257Srpaulo * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16273257Srpaulo * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17273257Srpaulo * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 18273257Srpaulo * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19273257Srpaulo * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 20273257Srpaulo * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21273257Srpaulo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 22273257Srpaulo * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 23273257Srpaulo * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24273257Srpaulo * POSSIBILITY OF SUCH DAMAGE. 25273257Srpaulo * 26273257Srpaulo * $FreeBSD: releng/10.2/sys/arm/ti/ti_wdt.h 273624 2014-10-25 02:05:21Z rpaulo $ 27273257Srpaulo */ 28273257Srpaulo#ifndef _TI_WDT_H_ 29273257Srpaulo#define _TI_WDT_H_ 30273257Srpaulo 31273257Srpaulo/* TI WDT registers */ 32273257Srpaulo#define TI_WDT_WIDR 0x00 /* Watchdog Identification Register */ 33273257Srpaulo#define TI_WDT_WDSC 0x10 /* Watchdog System Control Register */ 34273257Srpaulo#define TI_WDT_WDST 0x14 /* Watchdog Status Register */ 35273257Srpaulo#define TI_WDT_WISR 0x18 /* Watchdog Interrupt Status Register */ 36273257Srpaulo#define TI_WDT_WIER 0x1c /* Watchdog Interrupt Enable Register */ 37273257Srpaulo#define TI_WDT_WCLR 0x24 /* Watchdog Control Register */ 38273257Srpaulo#define TI_WDT_WCRR 0x28 /* Watchdog Counter Register */ 39273257Srpaulo#define TI_WDT_WLDR 0x2c /* Watchdog Load Register */ 40273257Srpaulo#define TI_WDT_WTGR 0x30 /* Watchdog Trigger Register */ 41273257Srpaulo#define TI_WDT_WWPS 0x34 /* Watchdog Write Posting Register */ 42273257Srpaulo#define TI_WDT_WDLY 0x44 /* Watchdog Delay Configuration Reg */ 43273257Srpaulo#define TI_WDT_WSPR 0x48 /* Watchdog Start/Stop Register */ 44273257Srpaulo#define TI_WDT_WIRQSTATRAW 0x54 /* Watchdog Raw Interrupt Status Reg. */ 45273257Srpaulo#define TI_WDT_WIRQSTAT 0x58 /* Watchdog Int. Status Register */ 46273257Srpaulo#define TI_WDT_WIRQENSET 0x5c /* Watchdog Int. Enable Set Register */ 47273257Srpaulo#define TI_WDT_WIRQENCLR 0x60 /* Watchdog Int. Enable Clear Reg. */ 48273257Srpaulo 49273257Srpaulo/* WDT_WDSC Register */ 50273257Srpaulo#define TI_WDSC_SR (1 << 1) /* Soft reset */ 51273257Srpaulo 52273257Srpaulo/* 53273257Srpaulo * WDT_WWPS Register 54273257Srpaulo * 55273257Srpaulo * Writes to some registers require synchronisation with a different clock 56273257Srpaulo * domain. The WDT_WWPS register is the place where this synchronisation 57273257Srpaulo * happens. 58273257Srpaulo */ 59273257Srpaulo#define TI_W_PEND_WCLR (1 << 0) 60273257Srpaulo#define TI_W_PEND_WCRR (1 << 1) 61273257Srpaulo#define TI_W_PEND_WLDR (1 << 2) 62273257Srpaulo#define TI_W_PEND_WTGR (1 << 3) 63273257Srpaulo#define TI_W_PEND_WSPR (1 << 4) 64273257Srpaulo#define TI_W_PEND_WDLY (1 << 5) 65273257Srpaulo 66273257Srpaulo/* WDT_WIRQENSET Register */ 67273257Srpaulo#define TI_IRQ_EN_OVF (1 << 0) /* Overflow interrupt */ 68273257Srpaulo#define TI_IRQ_EN_DLY (1 << 1) /* Delay interrupt */ 69273257Srpaulo 70273257Srpaulo/* WDT_WIRQSTAT Register */ 71273257Srpaulo#define TI_IRQ_EV_OVF (1 << 0) /* Overflow event */ 72273257Srpaulo#define TI_IRQ_EV_DLY (1 << 1) /* Delay event */ 73273257Srpaulo 74273257Srpaulo#endif /* _TI_WDT_H_ */ 75