1263693Sloos/*- 2263693Sloos * Copyright 2014 Luiz Otavio O Souza <loos@freebsd.org> 3263693Sloos * All rights reserved. 4263693Sloos * 5263693Sloos * Redistribution and use in source and binary forms, with or without 6263693Sloos * modification, are permitted provided that the following conditions 7263693Sloos * are met: 8263693Sloos * 1. Redistributions of source code must retain the above copyright 9263693Sloos * notice, this list of conditions and the following disclaimer. 10263693Sloos * 2. Redistributions in binary form must reproduce the above copyright 11263693Sloos * notice, this list of conditions and the following disclaimer in the 12263693Sloos * documentation and/or other materials provided with the distribution. 13263693Sloos * 14263693Sloos * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15263693Sloos * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16263693Sloos * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17263693Sloos * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18263693Sloos * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19263693Sloos * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20263693Sloos * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21263693Sloos * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22263693Sloos * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23263693Sloos * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24263693Sloos * SUCH DAMAGE. 25263693Sloos * 26263693Sloos * $FreeBSD: releng/10.2/sys/arm/ti/ti_adcreg.h 270238 2014-08-20 18:10:12Z loos $ 27263693Sloos */ 28263693Sloos 29263693Sloos#ifndef _TI_ADCREG_H_ 30263693Sloos#define _TI_ADCREG_H_ 31263693Sloos 32263693Sloos#define ADC_REVISION 0x000 33263693Sloos#define ADC_REV_SCHEME_MSK 0xc0000000 34263693Sloos#define ADC_REV_SCHEME_SHIFT 30 35263693Sloos#define ADC_REV_FUNC_MSK 0x0fff0000 36263693Sloos#define ADC_REV_FUNC_SHIFT 16 37263693Sloos#define ADC_REV_RTL_MSK 0x0000f800 38263693Sloos#define ADC_REV_RTL_SHIFT 11 39263693Sloos#define ADC_REV_MAJOR_MSK 0x00000700 40263693Sloos#define ADC_REV_MAJOR_SHIFT 8 41263693Sloos#define ADC_REV_CUSTOM_MSK 0x000000c0 42263693Sloos#define ADC_REV_CUSTOM_SHIFT 6 43263693Sloos#define ADC_REV_MINOR_MSK 0x0000003f 44263693Sloos#define ADC_SYSCFG 0x010 45263693Sloos#define ADC_SYSCFG_IDLE_MSK 0x000000c0 46263693Sloos#define ADC_SYSCFG_IDLE_SHIFT 2 47263693Sloos#define ADC_IRQSTATUS_RAW 0x024 48263693Sloos#define ADC_IRQSTATUS 0x028 49263693Sloos#define ADC_IRQENABLE_SET 0x02c 50263693Sloos#define ADC_IRQENABLE_CLR 0x030 51263693Sloos#define ADC_IRQ_HW_PEN_SYNC (1 << 10) 52263693Sloos#define ADC_IRQ_PEN_UP (1 << 9) 53263693Sloos#define ADC_IRQ_OUT_RANGE (1 << 8) 54263693Sloos#define ADC_IRQ_FIFO1_UNDR (1 << 7) 55263693Sloos#define ADC_IRQ_FIFO1_OVERR (1 << 6) 56263693Sloos#define ADC_IRQ_FIFO1_THRES (1 << 5) 57263693Sloos#define ADC_IRQ_FIFO0_UNDR (1 << 4) 58263693Sloos#define ADC_IRQ_FIFO0_OVERR (1 << 3) 59263693Sloos#define ADC_IRQ_FIFO0_THRES (1 << 2) 60263693Sloos#define ADC_IRQ_END_OF_SEQ (1 << 1) 61263693Sloos#define ADC_IRQ_HW_PEN_ASYNC (1 << 0) 62263693Sloos#define ADC_CTRL 0x040 63263693Sloos#define ADC_CTRL_STEP_WP (1 << 2) 64263693Sloos#define ADC_CTRL_STEP_ID (1 << 1) 65263693Sloos#define ADC_CTRL_ENABLE (1 << 0) 66263693Sloos#define ADC_STAT 0x044 67263693Sloos#define ADC_CLKDIV 0x04c 68263693Sloos#define ADC_STEPENABLE 0x054 69263693Sloos#define ADC_IDLECONFIG 0x058 70263693Sloos#define ADC_STEPCFG1 0x064 71263693Sloos#define ADC_STEPDLY1 0x068 72263693Sloos#define ADC_STEPCFG2 0x06c 73263693Sloos#define ADC_STEPDLY2 0x070 74263693Sloos#define ADC_STEPCFG3 0x074 75263693Sloos#define ADC_STEPDLY3 0x078 76263693Sloos#define ADC_STEPCFG4 0x07c 77263693Sloos#define ADC_STEPDLY4 0x080 78263693Sloos#define ADC_STEPCFG5 0x084 79263693Sloos#define ADC_STEPDLY5 0x088 80263693Sloos#define ADC_STEPCFG6 0x08c 81263693Sloos#define ADC_STEPDLY6 0x090 82263693Sloos#define ADC_STEPCFG7 0x094 83263693Sloos#define ADC_STEPDLY7 0x098 84270238Sloos#define ADC_STEPCFG8 0x09c 85270238Sloos#define ADC_STEPDLY8 0x0a0 86263693Sloos#define ADC_STEP_DIFF_CNTRL (1 << 25) 87263693Sloos#define ADC_STEP_RFM_MSK 0x01800000 88263693Sloos#define ADC_STEP_RFM_SHIFT 23 89263693Sloos#define ADC_STEP_RFM_VSSA 0 90263693Sloos#define ADC_STEP_RFM_XNUR 1 91263693Sloos#define ADC_STEP_RFM_YNLR 2 92263693Sloos#define ADC_STEP_RFM_VREFN 3 93263693Sloos#define ADC_STEP_INP_MSK 0x00780000 94263693Sloos#define ADC_STEP_INP_SHIFT 19 95263693Sloos#define ADC_STEP_INM_MSK 0x00078000 96263693Sloos#define ADC_STEP_INM_SHIFT 15 97263693Sloos#define ADC_STEP_IN_VREFN 8 98263693Sloos#define ADC_STEP_RFP_MSK 0x00007000 99263693Sloos#define ADC_STEP_RFP_SHIFT 12 100263693Sloos#define ADC_STEP_RFP_VDDA 0 101263693Sloos#define ADC_STEP_RFP_XPUL 1 102263693Sloos#define ADC_STEP_RFP_YPLL 2 103263693Sloos#define ADC_STEP_RFP_VREFP 3 104263693Sloos#define ADC_STEP_RFP_INTREF 4 105263693Sloos#define ADC_STEP_AVG_MSK 0x0000001c 106263693Sloos#define ADC_STEP_AVG_SHIFT 2 107263693Sloos#define ADC_STEP_MODE_MSK 0x00000003 108263693Sloos#define ADC_STEP_MODE_ONESHOT 0x00000000 109263693Sloos#define ADC_STEP_MODE_CONTINUOUS 0x00000001 110263693Sloos#define ADC_STEP_SAMPLE_DELAY 0xff000000 111263693Sloos#define ADC_STEP_OPEN_DELAY 0x0003ffff 112263693Sloos#define ADC_FIFO0COUNT 0x0e4 113263693Sloos#define ADC_FIFO0THRESHOLD 0x0e8 114263693Sloos#define ADC_FIFO0DATA 0x100 115263693Sloos#define ADC_FIFO_COUNT_MSK 0x0000007f 116263693Sloos#define ADC_FIFO_STEP_ID_MSK 0x000f0000 117263693Sloos#define ADC_FIFO_STEP_ID_SHIFT 16 118263693Sloos#define ADC_FIFO_DATA_MSK 0x00000fff 119263693Sloos 120263693Sloos#endif /* _TI_ADCREG_H_ */ 121