152284Sobrien/*- 250397Sobrien * Copyright (c) 2011 350397Sobrien * Ben Gray <ben.r.gray@gmail.com>. 450397Sobrien * All rights reserved. 550397Sobrien * 650397Sobrien * Redistribution and use in source and binary forms, with or without 750397Sobrien * modification, are permitted provided that the following conditions 850397Sobrien * are met: 950397Sobrien * 1. Redistributions of source code must retain the above copyright 1050397Sobrien * notice, this list of conditions and the following disclaimer. 1150397Sobrien * 2. Redistributions in binary form must reproduce the above copyright 1250397Sobrien * notice, this list of conditions and the following disclaimer in the 1350397Sobrien * documentation and/or other materials provided with the distribution. 1450397Sobrien * 1550397Sobrien * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1650397Sobrien * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1750397Sobrien * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1850397Sobrien * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 1950397Sobrien * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2050397Sobrien * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2150397Sobrien * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2250397Sobrien * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2350397Sobrien * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2450397Sobrien * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2550397Sobrien * SUCH DAMAGE. 26169689Skan * 27169689Skan * $FreeBSD: releng/10.2/sys/arm/ti/omap3/omap3_reg.h 239281 2012-08-15 06:31:32Z gonzo $ 2850397Sobrien */ 2950397Sobrien 3050397Sobrien/* 3150397Sobrien * Texas Instruments - OMAP3xxx series processors 3250397Sobrien * 3350397Sobrien * Reference: 3450397Sobrien * OMAP35x Applications Processor 3550397Sobrien * Technical Reference Manual 3650397Sobrien * (omap35xx_techref.pdf) 3750397Sobrien * 3850397Sobrien * 3950397Sobrien * Note: 4052284Sobrien * The devices are mapped into address above 0xD000_0000 as the kernel space 4152284Sobrien * memory is at 0xC000_0000 and above. The first 256MB after this is reserved 4252284Sobrien * for the size of the kernel, everything above that is reserved for SoC 4352284Sobrien * devices. 4452284Sobrien * 4552284Sobrien */ 4652284Sobrien#ifndef _OMAP35XX_REG_H_ 4752284Sobrien#define _OMAP35XX_REG_H_ 4852284Sobrien 4952284Sobrien#ifndef _LOCORE 5052284Sobrien#include <sys/types.h> /* for uint32_t */ 5152284Sobrien#endif 5252284Sobrien 5352284Sobrien 5452284Sobrien 5552284Sobrien 5650397Sobrien#define OMAP35XX_SDRAM0_START 0x80000000UL 5750397Sobrien#define OMAP35XX_SDRAM1_START 0xA0000000UL 5850397Sobrien#define OMAP35XX_SDRAM_BANKS 2 5950397Sobrien#define OMAP35XX_SDRAM_BANK_SIZE 0x20000000UL 6050397Sobrien 6150397Sobrien 6252284Sobrien/* Physical/Virtual address for SDRAM controller */ 6352284Sobrien 6450397Sobrien#define OMAP35XX_SMS_VBASE 0x6C000000UL 6550397Sobrien#define OMAP35XX_SMS_HWBASE 0x6C000000UL 6650397Sobrien#define OMAP35XX_SMS_SIZE 0x01000000UL 6752284Sobrien 6852284Sobrien#define OMAP35XX_SDRC_VBASE 0x6D000000UL 6952284Sobrien#define OMAP35XX_SDRC_HWBASE 0x6D000000UL 7050397Sobrien#define OMAP35XX_SDRC_SIZE 0x01000000UL 7152284Sobrien 7250397Sobrien 7350397Sobrien 7450397Sobrien/* Physical/Virtual address for I/O space */ 7552284Sobrien 7652284Sobrien#define OMAP35XX_L3_VBASE 0xD0000000UL 7752284Sobrien#define OMAP35XX_L3_HWBASE 0x68000000UL 7850397Sobrien#define OMAP35XX_L3_SIZE 0x01000000UL 7952284Sobrien 8050397Sobrien#define OMAP35XX_L4_CORE_VBASE 0xE8000000UL 8150397Sobrien#define OMAP35XX_L4_CORE_HWBASE 0x48000000UL 8250397Sobrien#define OMAP35XX_L4_CORE_SIZE 0x01000000UL 8350397Sobrien 8450397Sobrien#define OMAP35XX_L4_WAKEUP_VBASE 0xE8300000UL 8552284Sobrien#define OMAP35XX_L4_WAKEUP_HWBASE 0x48300000UL 8650397Sobrien#define OMAP35XX_L4_WAKEUP_SIZE 0x00040000UL 8750397Sobrien 8850397Sobrien#define OMAP35XX_L4_PERIPH_VBASE 0xE9000000UL 8950397Sobrien#define OMAP35XX_L4_PERIPH_HWBASE 0x49000000UL 9050397Sobrien#define OMAP35XX_L4_PERIPH_SIZE 0x00100000UL 9152284Sobrien 9250397Sobrien 9350397Sobrien/* 9450397Sobrien * L4-CORE Physical/Virtual addresss offsets 95122180Skan */ 96122180Skan#define OMAP35XX_SCM_OFFSET 0x00002000UL 97122180Skan#define OMAP35XX_CM_OFFSET 0x00004000UL 98122180Skan#define OMAP35XX_SDMA_OFFSET 0x00056000UL 9950397Sobrien#define OMAP35XX_I2C3_OFFSET 0x00060000UL 10052284Sobrien#define OMAP35XX_USB_TLL_OFFSET 0x00062000UL 10152284Sobrien#define OMAP35XX_USB_UHH_OFFSET 0x00064000UL 10250397Sobrien#define OMAP35XX_USB_EHCI_OFFSET 0x00064800UL 10352284Sobrien 10452284Sobrien 10550397Sobrien#define OMAP35XX_UART1_OFFSET 0x0006A000UL 10650397Sobrien#define OMAP35XX_UART2_OFFSET 0x0006C000UL 10750397Sobrien#define OMAP35XX_I2C1_OFFSET 0x00070000UL 10850397Sobrien#define OMAP35XX_I2C2_OFFSET 0x00072000UL 10950397Sobrien#define OMAP35XX_MCBSP1_OFFSET 0x00074000UL 11050397Sobrien#define OMAP35XX_GPTIMER10_OFFSET 0x00086000UL 11150397Sobrien#define OMAP35XX_GPTIMER11_OFFSET 0x00088000UL 11250397Sobrien#define OMAP35XX_MCBSP5_OFFSET 0x00096000UL 11350397Sobrien#define OMAP35XX_MMU1_OFFSET 0x000BD400UL 11450397Sobrien#define OMAP35XX_INTCPS_OFFSET 0x00200000UL 115 116 117/* 118 * L4-WAKEUP Physical/Virtual addresss offsets 119 */ 120#define OMAP35XX_PRM_OFFSET 0x00006000UL 121#define OMAP35XX_GPIO1_OFFSET 0x00010000UL 122#define OMAP35XX_GPTIMER1_OFFSET 0x00018000UL 123 124 125 126/* 127 * L4-PERIPH Physical/Virtual addresss offsets 128 */ 129#define OMAP35XX_UART3_OFFSET 0x00020000UL 130#define OMAP35XX_MCBSP2_OFFSET 0x00022000UL 131#define OMAP35XX_MCBSP3_OFFSET 0x00024000UL 132#define OMAP35XX_MCBSP4_OFFSET 0x00026000UL 133#define OMAP35XX_SIDETONE_MCBSP2_OFFSET 0x00028000UL 134#define OMAP35XX_SIDETONE_MCBSP3_OFFSET 0x0002A000UL 135#define OMAP35XX_GPTIMER2_OFFSET 0x00032000UL 136#define OMAP35XX_GPTIMER3_OFFSET 0x00034000UL 137#define OMAP35XX_GPTIMER4_OFFSET 0x00036000UL 138#define OMAP35XX_GPTIMER5_OFFSET 0x00038000UL 139#define OMAP35XX_GPTIMER6_OFFSET 0x0003A000UL 140#define OMAP35XX_GPTIMER7_OFFSET 0x0003C000UL 141#define OMAP35XX_GPTIMER8_OFFSET 0x0003E000UL 142#define OMAP35XX_GPTIMER9_OFFSET 0x00040000UL 143#define OMAP35XX_GPIO2_OFFSET 0x00050000UL 144#define OMAP35XX_GPIO3_OFFSET 0x00052000UL 145#define OMAP35XX_GPIO4_OFFSET 0x00054000UL 146#define OMAP35XX_GPIO5_OFFSET 0x00056000UL 147#define OMAP35XX_GPIO6_OFFSET 0x00058000UL 148 149 150 151 152 153 154/* 155 * System Control Module 156 */ 157#define OMAP35XX_SCM_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_SCM_OFFSET) 158#define OMAP35XX_SCM_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_SCM_OFFSET) 159#define OMAP35XX_SCM_SIZE 0x00001000UL 160 161#define OMAP35XX_SCM_REVISION 0x00000000UL 162#define OMAP35XX_SCM_SYSCONFIG 0x00000010UL 163#define OMAP35XX_SCM_PADCONFS_BASE 0x00000030UL 164#define OMAP35XX_SCM_DEVCONF0 0x00000274UL 165#define OMAP35XX_SCM_MEM_DFTRW0 0x00000278UL 166 167 168 169 170/* 171 * 172 */ 173#define OMAP35XX_CM_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_CM_OFFSET) 174#define OMAP35XX_CM_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_CM_OFFSET) 175#define OMAP35XX_CM_SIZE 0x00001500UL 176 177#define OMAP35XX_CM_CORE_OFFSET 0x00000A00UL 178#define OMAP35XX_CM_CORE_SIZE 0x00000100UL 179#define OMAP35XX_CM_FCLKEN1_CORE (OMAP35XX_CM_CORE_OFFSET + 0x0000UL) 180#define OMAP35XX_CM_FCLKEN3_CORE (OMAP35XX_CM_CORE_OFFSET + 0x0008UL) 181#define OMAP35XX_CM_ICLKEN1_CORE (OMAP35XX_CM_CORE_OFFSET + 0x0010UL) 182#define OMAP35XX_CM_ICLKEN2_CORE (OMAP35XX_CM_CORE_OFFSET + 0x0014UL) 183#define OMAP35XX_CM_ICLKEN3_CORE (OMAP35XX_CM_CORE_OFFSET + 0x0018UL) 184#define OMAP35XX_CM_IDLEST1_CORE (OMAP35XX_CM_CORE_OFFSET + 0x0020UL) 185#define OMAP35XX_CM_IDLEST2_CORE (OMAP35XX_CM_CORE_OFFSET + 0x0024UL) 186#define OMAP35XX_CM_IDLEST3_CORE (OMAP35XX_CM_CORE_OFFSET + 0x0028UL) 187#define OMAP35XX_CM_AUTOIDLE1_CORE (OMAP35XX_CM_CORE_OFFSET + 0x0030UL) 188#define OMAP35XX_CM_AUTOIDLE2_CORE (OMAP35XX_CM_CORE_OFFSET + 0x0034UL) 189#define OMAP35XX_CM_AUTOIDLE3_CORE (OMAP35XX_CM_CORE_OFFSET + 0x0038UL) 190#define OMAP35XX_CM_CLKSEL_CORE (OMAP35XX_CM_CORE_OFFSET + 0x0040UL) 191#define OMAP35XX_CM_CLKSTCTRL_CORE (OMAP35XX_CM_CORE_OFFSET + 0x0048UL) 192#define OMAP35XX_CM_CLKSTST_CORE (OMAP35XX_CM_CORE_OFFSET + 0x004CUL) 193 194#define OMAP35XX_CM_WKUP_OFFSET 0x00000C00UL 195#define OMAP35XX_CM_WKUP_SIZE 0x00000100UL 196#define OMAP35XX_CM_FCLKEN_WKUP (OMAP35XX_CM_WKUP_OFFSET + 0x0000UL) 197#define OMAP35XX_CM_ICLKEN_WKUP (OMAP35XX_CM_WKUP_OFFSET + 0x0010UL) 198#define OMAP35XX_CM_IDLEST_WKUP (OMAP35XX_CM_WKUP_OFFSET + 0x0020UL) 199#define OMAP35XX_CM_AUTOIDLE_WKUP (OMAP35XX_CM_WKUP_OFFSET + 0x0030UL) 200#define OMAP35XX_CM_CLKSEL_WKUP (OMAP35XX_CM_WKUP_OFFSET + 0x0040UL) 201 202#define OMAP35XX_CM_PLL_OFFSET 0x00000D00UL 203#define OMAP35XX_CM_PLL_SIZE 0x00000100UL 204#define OMAP35XX_CM_CLKEN_PLL (OMAP35XX_CM_PLL_OFFSET + 0x0000UL) 205#define OMAP35XX_CM_CLKEN2_PLL (OMAP35XX_CM_PLL_OFFSET + 0x0004UL) 206#define OMAP35XX_CM_IDLEST_CKGEN (OMAP35XX_CM_PLL_OFFSET + 0x0020UL) 207#define OMAP35XX_CM_IDLEST2_CKGEN (OMAP35XX_CM_PLL_OFFSET + 0x0024UL) 208#define OMAP35XX_CM_AUTOIDLE_PLL (OMAP35XX_CM_PLL_OFFSET + 0x0030UL) 209#define OMAP35XX_CM_AUTOIDLE2_PLL (OMAP35XX_CM_PLL_OFFSET + 0x0034UL) 210#define OMAP35XX_CM_CLKSEL1_PLL (OMAP35XX_CM_PLL_OFFSET + 0x0040UL) 211#define OMAP35XX_CM_CLKSEL2_PLL (OMAP35XX_CM_PLL_OFFSET + 0x0044UL) 212#define OMAP35XX_CM_CLKSEL3_PLL (OMAP35XX_CM_PLL_OFFSET + 0x0048UL) 213#define OMAP35XX_CM_CLKSEL4_PLL (OMAP35XX_CM_PLL_OFFSET + 0x004CUL) 214#define OMAP35XX_CM_CLKSEL5_PLL (OMAP35XX_CM_PLL_OFFSET + 0x0050UL) 215#define OMAP35XX_CM_CLKOUT_CTRL (OMAP35XX_CM_PLL_OFFSET + 0x0070UL) 216 217#define OMAP35XX_CM_PER_OFFSET 0x00001000UL 218#define OMAP35XX_CM_PER_SIZE 0x00000100UL 219#define OMAP35XX_CM_FCLKEN_PER (OMAP35XX_CM_PER_OFFSET + 0x0000UL) 220#define OMAP35XX_CM_ICLKEN_PER (OMAP35XX_CM_PER_OFFSET + 0x0010UL) 221#define OMAP35XX_CM_IDLEST_PER (OMAP35XX_CM_PER_OFFSET + 0x0020UL) 222#define OMAP35XX_CM_AUTOIDLE_PER (OMAP35XX_CM_PER_OFFSET + 0x0030UL) 223#define OMAP35XX_CM_CLKSEL_PER (OMAP35XX_CM_PER_OFFSET + 0x0040UL) 224#define OMAP35XX_CM_SLEEPDEP_PER (OMAP35XX_CM_PER_OFFSET + 0x0044UL) 225#define OMAP35XX_CM_CLKSTCTRL_PER (OMAP35XX_CM_PER_OFFSET + 0x0048UL) 226#define OMAP35XX_CM_CLKSTST_PER (OMAP35XX_CM_PER_OFFSET + 0x004CUL) 227 228#define OMAP35XX_CM_USBHOST_OFFSET 0x00001400UL 229#define OMAP35XX_CM_USBHOST_SIZE 0x00000100UL 230#define OMAP35XX_CM_FCLKEN_USBHOST (OMAP35XX_CM_USBHOST_OFFSET + 0x0000UL) 231#define OMAP35XX_CM_ICLKEN_USBHOST (OMAP35XX_CM_USBHOST_OFFSET + 0x0010UL) 232#define OMAP35XX_CM_IDLEST_USBHOST (OMAP35XX_CM_USBHOST_OFFSET + 0x0020UL) 233#define OMAP35XX_CM_AUTOIDLE_USBHOST (OMAP35XX_CM_USBHOST_OFFSET + 0x0030UL) 234#define OMAP35XX_CM_SLEEPDEP_USBHOST (OMAP35XX_CM_USBHOST_OFFSET + 0x0044UL) 235#define OMAP35XX_CM_CLKSTCTRL_USBHOST (OMAP35XX_CM_USBHOST_OFFSET + 0x0048UL) 236#define OMAP35XX_CM_CLKSTST_USBHOST (OMAP35XX_CM_USBHOST_OFFSET + 0x004CUL) 237 238 239 240 241/* 242 * 243 */ 244#define OMAP35XX_PRM_HWBASE (OMAP35XX_L4_WAKEUP_HWBASE + OMAP35XX_PRM_OFFSET) 245#define OMAP35XX_PRM_VBASE (OMAP35XX_L4_WAKEUP_VBASE + OMAP35XX_PRM_OFFSET) 246#define OMAP35XX_PRM_SIZE 0x00001600UL 247 248#define OMAP35XX_PRM_CLKCTRL_OFFSET 0x00000D00UL 249#define OMAP35XX_PRM_CLKCTRL_SIZE 0x00000100UL 250#define OMAP35XX_PRM_CLKSEL (OMAP35XX_PRM_CLKCTRL_OFFSET + 0x0040UL) 251#define OMAP35XX_PRM_CLKOUT_CTRL (OMAP35XX_PRM_CLKCTRL_OFFSET + 0x0070UL) 252 253#define OMAP35XX_PRM_GLOBAL_OFFSET 0x00001200UL 254#define OMAP35XX_PRM_GLOBAL_SIZE 0x00000100UL 255#define OMAP35XX_PRM_CLKSRC_CTRL (OMAP35XX_PRM_GLOBAL_OFFSET + 0x0070UL) 256 257 258 259 260 261/* 262 * Uarts 263 */ 264#define OMAP35XX_UART1_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_UART1_OFFSET) 265#define OMAP35XX_UART1_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_UART1_OFFSET) 266#define OMAP35XX_UART1_SIZE 0x00001000UL 267 268#define OMAP35XX_UART2_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_UART2_OFFSET) 269#define OMAP35XX_UART2_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_UART2_OFFSET) 270#define OMAP35XX_UART2_SIZE 0x00001000UL 271 272#define OMAP35XX_UART3_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_UART3_OFFSET) 273#define OMAP35XX_UART3_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_UART3_OFFSET) 274#define OMAP35XX_UART3_SIZE 0x00001000UL 275 276 277 278 279/* 280 * I2C Modules 281 */ 282#define OMAP35XX_I2C1_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_I2C1_OFFSET) 283#define OMAP35XX_I2C1_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_I2C1_OFFSET) 284#define OMAP35XX_I2C1_SIZE 0x00000080UL 285 286#define OMAP35XX_I2C2_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_I2C2_OFFSET) 287#define OMAP35XX_I2C2_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_I2C2_OFFSET) 288#define OMAP35XX_I2C2_SIZE 0x00000080UL 289 290#define OMAP35XX_I2C3_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_I2C3_OFFSET) 291#define OMAP35XX_I2C3_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_I2C3_OFFSET) 292#define OMAP35XX_I2C3_SIZE 0x00000080UL 293 294#define OMAP35XX_I2C_IE 0x04 295#define OMAP35XX_I2C_STAT 0x08 296#define OMAP35XX_I2C_WE 0x0C 297#define OMAP35XX_I2C_SYSS 0x10 298#define OMAP35XX_I2C_BUF 0x14 299#define OMAP35XX_I2C_CNT 0x18 300#define OMAP35XX_I2C_DATA 0x1C 301#define OMAP35XX_I2C_SYSC 0x20 302#define OMAP35XX_I2C_CON 0x24 303#define OMAP35XX_I2C_OA0 0x28 304#define OMAP35XX_I2C_SA 0x2C 305#define OMAP35XX_I2C_PSC 0x30 306#define OMAP35XX_I2C_SCLL 0x34 307#define OMAP35XX_I2C_SCLH 0x38 308#define OMAP35XX_I2C_SYSTEST 0x3C 309#define OMAP35XX_I2C_BUFSTAT 0x40 310#define OMAP35XX_I2C_OA1 0x44 311#define OMAP35XX_I2C_OA2 0x48 312#define OMAP35XX_I2C_OA3 0x4C 313#define OMAP35XX_I2C_ACTOA 0x50 314#define OMAP35XX_I2C_SBLOCK 0x54 315 316 317 318/* 319 * McBSP Modules 320 */ 321#define OMAP35XX_MCBSP1_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_MCBSP1_OFFSET) 322#define OMAP35XX_MCBSP1_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_MCBSP1_OFFSET) 323#define OMAP35XX_MCBSP1_SIZE 0x00001000UL 324 325#define OMAP35XX_MCBSP2_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_MCBSP2_OFFSET) 326#define OMAP35XX_MCBSP2_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_MCBSP2_OFFSET) 327#define OMAP35XX_MCBSP2_SIZE 0x00001000UL 328 329#define OMAP35XX_MCBSP3_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_MCBSP3_OFFSET) 330#define OMAP35XX_MCBSP3_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_MCBSP3_OFFSET) 331#define OMAP35XX_MCBSP3_SIZE 0x00001000UL 332 333#define OMAP35XX_MCBSP4_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_MCBSP4_OFFSET) 334#define OMAP35XX_MCBSP4_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_MCBSP4_OFFSET) 335#define OMAP35XX_MCBSP4_SIZE 0x00001000UL 336 337#define OMAP35XX_MCBSP5_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_MCBSP5_OFFSET) 338#define OMAP35XX_MCBSP5_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_MCBSP5_OFFSET) 339#define OMAP35XX_MCBSP5_SIZE 0x00001000UL 340 341#define OMAP35XX_MCBSP_DRR 0x0000 342#define OMAP35XX_MCBSP_DXR 0x0008 343#define OMAP35XX_MCBSP_SPCR2 0x0010 344#define OMAP35XX_MCBSP_SPCR1 0x0014 345#define OMAP35XX_MCBSP_RCR2 0x0018 346#define OMAP35XX_MCBSP_RCR1 0x001C 347#define OMAP35XX_MCBSP_XCR2 0x0020 348#define OMAP35XX_MCBSP_XCR1 0x0024 349#define OMAP35XX_MCBSP_SRGR2 0x0028 350#define OMAP35XX_MCBSP_SRGR1 0x002C 351#define OMAP35XX_MCBSP_MCR2 0x0030 352#define OMAP35XX_MCBSP_MCR1 0x0034 353#define OMAP35XX_MCBSP_RCERA 0x0038 354#define OMAP35XX_MCBSP_RCERB 0x003C 355#define OMAP35XX_MCBSP_XCERA 0x0040 356#define OMAP35XX_MCBSP_XCERB 0x0044 357#define OMAP35XX_MCBSP_PCR 0x0048 358#define OMAP35XX_MCBSP_RCERC 0x004C 359#define OMAP35XX_MCBSP_RCERD 0x0050 360#define OMAP35XX_MCBSP_XCERC 0x0054 361#define OMAP35XX_MCBSP_XCERD 0x0058 362#define OMAP35XX_MCBSP_RCERE 0x005C 363#define OMAP35XX_MCBSP_RCERF 0x0060 364#define OMAP35XX_MCBSP_XCERE 0x0064 365#define OMAP35XX_MCBSP_XCERF 0x0068 366#define OMAP35XX_MCBSP_RCERG 0x006C 367#define OMAP35XX_MCBSP_RCERH 0x0070 368#define OMAP35XX_MCBSP_XCERG 0x0074 369#define OMAP35XX_MCBSP_XCERH 0x0078 370#define OMAP35XX_MCBSP_RINTCLR 0x0080 371#define OMAP35XX_MCBSP_XINTCLR 0x0084 372#define OMAP35XX_MCBSP_ROVFLCLR 0x0088 373#define OMAP35XX_MCBSP_SYSCONFIG 0x008C 374#define OMAP35XX_MCBSP_THRSH2 0x0090 375#define OMAP35XX_MCBSP_THRSH1 0x0094 376#define OMAP35XX_MCBSP_IRQSTATUS 0x00A0 377#define OMAP35XX_MCBSP_IRQENABLE 0x00A4 378#define OMAP35XX_MCBSP_WAKEUPEN 0x00A8 379#define OMAP35XX_MCBSP_XCCR 0x00AC 380#define OMAP35XX_MCBSP_RCCR 0x00B0 381#define OMAP35XX_MCBSP_XBUFFSTAT 0x00B4 382#define OMAP35XX_MCBSP_RBUFFSTAT 0x00B8 383#define OMAP35XX_MCBSP_SSELCR 0x00BC 384#define OMAP35XX_MCBSP_STATUS 0x00C0 385 386 387 388/* 389 * USB TTL Module 390 */ 391#define OMAP35XX_USBTLL_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_USBTLL_OFFSET) 392#define OMAP35XX_USBTLL_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_USBTLL_OFFSET) 393#define OMAP35XX_USBTLL_SIZE 0x00001000UL 394 395#define OMAP35XX_USBTLL_REVISION 0x0000 396#define OMAP35XX_USBTLL_SYSCONFIG 0x0010 397#define OMAP35XX_USBTLL_SYSSTATUS 0x0014 398#define OMAP35XX_USBTLL_IRQSTATUS 0x0018 399#define OMAP35XX_USBTLL_IRQENABLE 0x001C 400#define OMAP35XX_USBTLL_TLL_SHARED_CONF 0x0030 401#define OMAP35XX_USBTLL_TLL_CHANNEL_CONF(i) (0x0040 + (0x04 * (i))) 402#define OMAP35XX_USBTLL_ULPI_VENDOR_ID_LO(i) (0x0800 + (0x100 * (i))) 403#define OMAP35XX_USBTLL_ULPI_VENDOR_ID_HI(i) (0x0801 + (0x100 * (i))) 404#define OMAP35XX_USBTLL_ULPI_PRODUCT_ID_LO(i) (0x0802 + (0x100 * (i))) 405#define OMAP35XX_USBTLL_ULPI_PRODUCT_ID_HI(i) (0x0803 + (0x100 * (i))) 406#define OMAP35XX_USBTLL_ULPI_FUNCTION_CTRL(i) (0x0804 + (0x100 * (i))) 407#define OMAP35XX_USBTLL_ULPI_FUNCTION_CTRL_SET(i) (0x0805 + (0x100 * (i))) 408#define OMAP35XX_USBTLL_ULPI_FUNCTION_CTRL_CLR(i) (0x0806 + (0x100 * (i))) 409#define OMAP35XX_USBTLL_ULPI_INTERFACE_CTRL(i) (0x0807 + (0x100 * (i))) 410#define OMAP35XX_USBTLL_ULPI_INTERFACE_CTRL_SET(i) (0x0808 + (0x100 * (i))) 411#define OMAP35XX_USBTLL_ULPI_INTERFACE_CTRL_CLR(i) (0x0809 + (0x100 * (i))) 412#define OMAP35XX_USBTLL_ULPI_OTG_CTRL(i) (0x080A + (0x100 * (i))) 413#define OMAP35XX_USBTLL_ULPI_OTG_CTRL_SET(i) (0x080B + (0x100 * (i))) 414#define OMAP35XX_USBTLL_ULPI_OTG_CTRL_CLR(i) (0x080C + (0x100 * (i))) 415#define OMAP35XX_USBTLL_ULPI_USB_INT_EN_RISE(i) (0x080D + (0x100 * (i))) 416#define OMAP35XX_USBTLL_ULPI_USB_INT_EN_RISE_SET(i) (0x080E + (0x100 * (i))) 417#define OMAP35XX_USBTLL_ULPI_USB_INT_EN_RISE_CLR(i) (0x080F + (0x100 * (i))) 418#define OMAP35XX_USBTLL_ULPI_USB_INT_EN_FALL(i) (0x0810 + (0x100 * (i))) 419#define OMAP35XX_USBTLL_ULPI_USB_INT_EN_FALL_SET(i) (0x0811 + (0x100 * (i))) 420#define OMAP35XX_USBTLL_ULPI_USB_INT_EN_FALL_CLR(i) (0x0812 + (0x100 * (i))) 421#define OMAP35XX_USBTLL_ULPI_USB_INT_STATUS(i) (0x0813 + (0x100 * (i))) 422#define OMAP35XX_USBTLL_ULPI_USB_INT_LATCH(i) (0x0814 + (0x100 * (i))) 423#define OMAP35XX_USBTLL_ULPI_DEBUG(i) (0x0815 + (0x100 * (i))) 424#define OMAP35XX_USBTLL_ULPI_SCRATCH_REGISTER(i) (0x0816 + (0x100 * (i))) 425#define OMAP35XX_USBTLL_ULPI_SCRATCH_REGISTER_SET(i) (0x0817 + (0x100 * (i))) 426#define OMAP35XX_USBTLL_ULPI_SCRATCH_REGISTER_CLR(i) (0x0818 + (0x100 * (i))) 427#define OMAP35XX_USBTLL_ULPI_EXTENDED_SET_ACCESS(i) (0x082F + (0x100 * (i))) 428#define OMAP35XX_USBTLL_ULPI_UTMI_VCONTROL_EN(i) (0x0830 + (0x100 * (i))) 429#define OMAP35XX_USBTLL_ULPI_UTMI_VCONTROL_EN_SET(i) (0x0831 + (0x100 * (i))) 430#define OMAP35XX_USBTLL_ULPI_UTMI_VCONTROL_EN_CLR(i) (0x0832 + (0x100 * (i))) 431#define OMAP35XX_USBTLL_ULPI_UTMI_VCONTROL_STATUS(i) (0x0833 + (0x100 * (i))) 432#define OMAP35XX_USBTLL_ULPI_UTMI_VCONTROL_LATCH(i) (0x0834 + (0x100 * (i))) 433#define OMAP35XX_USBTLL_ULPI_UTMI_VSTATUS(i) (0x0835 + (0x100 * (i))) 434#define OMAP35XX_USBTLL_ULPI_UTMI_VSTATUS_SET(i) (0x0836 + (0x100 * (i))) 435#define OMAP35XX_USBTLL_ULPI_UTMI_VSTATUS_CLR(i) (0x0837 + (0x100 * (i))) 436#define OMAP35XX_USBTLL_ULPI_USB_INT_LATCH_NOCLR(i) (0x0838 + (0x100 * (i))) 437#define OMAP35XX_USBTLL_ULPI_VENDOR_INT_EN(i) (0x083B + (0x100 * (i))) 438#define OMAP35XX_USBTLL_ULPI_VENDOR_INT_EN_SET(i) (0x083C + (0x100 * (i))) 439#define OMAP35XX_USBTLL_ULPI_VENDOR_INT_EN_CLR(i) (0x083D + (0x100 * (i))) 440#define OMAP35XX_USBTLL_ULPI_VENDOR_INT_STATUS(i) (0x083E + (0x100 * (i))) 441#define OMAP35XX_USBTLL_ULPI_VENDOR_INT_LATCH(i) (0x083F + (0x100 * (i))) 442 443 444/* 445 * USB Host Module 446 */ 447#define OMAP35XX_USB_TLL_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_USB_TLL_OFFSET) 448#define OMAP35XX_USB_TLL_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_USB_TLL_OFFSET) 449#define OMAP35XX_USB_TLL_SIZE 0x00001000UL 450 451#define OMAP35XX_USB_EHCI_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_USB_EHCI_OFFSET) 452#define OMAP35XX_USB_EHCI_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_USB_EHCI_OFFSET) 453#define OMAP35XX_USB_EHCI_SIZE 0x00000400UL 454 455#define OMAP35XX_USB_UHH_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_USB_UHH_OFFSET) 456#define OMAP35XX_USB_UHH_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_USB_UHH_OFFSET) 457#define OMAP35XX_USB_UHH_SIZE 0x00000400UL 458 459 460 461 462 463/* 464 * SDRAM Controler (SDRC) 465 * PA 0x6D00_0000 466 */ 467 468#define OMAP35XX_SDRC_SYSCONFIG (OMAP35XX_SDRC_VBASE + 0x10) 469#define OMAP35XX_SDRC_SYSSTATUS (OMAP35XX_SDRC_VBASE + 0x14) 470#define OMAP35XX_SDRC_CS_CFG (OMAP35XX_SDRC_VBASE + 0x40) 471#define OMAP35XX_SDRC_SHARING (OMAP35XX_SDRC_VBASE + 0x44) 472#define OMAP35XX_SDRC_ERR_ADDR (OMAP35XX_SDRC_VBASE + 0x48) 473#define OMAP35XX_SDRC_ERR_TYPE (OMAP35XX_SDRC_VBASE + 0x4C) 474#define OMAP35XX_SDRC_DLLA_CTRL (OMAP35XX_SDRC_VBASE + 0x60) 475#define OMAP35XX_SDRC_DLLA_STATUS (OMAP35XX_SDRC_VBASE + 0x64) 476#define OMAP35XX_SDRC_POWER_REG (OMAP35XX_SDRC_VBASE + 0x70) 477#define OMAP35XX_SDRC_MCFG(p) (OMAP35XX_SDRC_VBASE + 0x80 + (0x30 * (p))) 478#define OMAP35XX_SDRC_MR(p) (OMAP35XX_SDRC_VBASE + 0x84 + (0x30 * (p))) 479#define OMAP35XX_SDRC_EMR2(p) (OMAP35XX_SDRC_VBASE + 0x8C + (0x30 * (p))) 480#define OMAP35XX_SDRC_ACTIM_CTRLA(p) (OMAP35XX_SDRC_VBASE + 0x9C + (0x28 * (p))) 481#define OMAP35XX_SDRC_ACTIM_CTRLB(p) (OMAP35XX_SDRC_VBASE + 0xA0 + (0x28 * (p))) 482#define OMAP35XX_SDRC_RFR_CTRL(p) (OMAP35XX_SDRC_VBASE + 0xA4 + (0x30 * (p))) 483#define OMAP35XX_SDRC_MANUAL(p) (OMAP35XX_SDRC_VBASE + 0xA8 + (0x30 * (p))) 484 485 486/* 487 * SDMA Offset 488 * PA 0x4805 6000 489 */ 490 491#define OMAP35XX_SDMA_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_SDMA_OFFSET) 492#define OMAP35XX_SDMA_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_SDMA_OFFSET) 493#define OMAP35XX_SDMA_SIZE 0x00001000UL 494 495 496 497/* 498 * Interrupt Controller Unit. 499 * PA 0x4820_0000 500 */ 501 502#define OMAP35XX_INTCPS_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_INTCPS_OFFSET) 503#define OMAP35XX_INTCPS_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_INTCPS_OFFSET) 504#define OMAP35XX_INTCPS_SIZE 0x00001000UL 505 506#define OMAP35XX_INTCPS_SYSCONFIG (OMAP35XX_INTCPS_VBASE + 0x10) 507#define OMAP35XX_INTCPS_SYSSTATUS (OMAP35XX_INTCPS_VBASE + 0x14) 508#define OMAP35XX_INTCPS_SIR_IRQ (OMAP35XX_INTCPS_VBASE + 0x40) 509#define OMAP35XX_INTCPS_SIR_FIQ (OMAP35XX_INTCPS_VBASE + 0x44) 510#define OMAP35XX_INTCPS_CONTROL (OMAP35XX_INTCPS_VBASE + 0x48) 511#define OMAP35XX_INTCPS_PROTECTION (OMAP35XX_INTCPS_VBASE + 0x4C) 512#define OMAP35XX_INTCPS_IDLE (OMAP35XX_INTCPS_VBASE + 0x50) 513#define OMAP35XX_INTCPS_IRQ_PRIORITY (OMAP35XX_INTCPS_VBASE + 0x60) 514#define OMAP35XX_INTCPS_FIQ_PRIORITY (OMAP35XX_INTCPS_VBASE + 0x64) 515#define OMAP35XX_INTCPS_THRESHOLD (OMAP35XX_INTCPS_VBASE + 0x68) 516#define OMAP35XX_INTCPS_ITR(n) (OMAP35XX_INTCPS_VBASE + 0x80 + (0x20 * (n))) 517#define OMAP35XX_INTCPS_MIR(n) (OMAP35XX_INTCPS_VBASE + 0x84 + (0x20 * (n))) 518#define OMAP35XX_INTCPS_MIR_CLEAR(n) (OMAP35XX_INTCPS_VBASE + 0x88 + (0x20 * (n))) 519#define OMAP35XX_INTCPS_MIR_SET(n) (OMAP35XX_INTCPS_VBASE + 0x8C + (0x20 * (n))) 520#define OMAP35XX_INTCPS_ISR_SET(n) (OMAP35XX_INTCPS_VBASE + 0x90 + (0x20 * (n))) 521#define OMAP35XX_INTCPS_ISR_CLEAR(n) (OMAP35XX_INTCPS_VBASE + 0x94 + (0x20 * (n))) 522#define OMAP35XX_INTCPS_PENDING_IRQ(n) (OMAP35XX_INTCPS_VBASE + 0x98 + (0x20 * (n))) 523#define OMAP35XX_INTCPS_PENDING_FIQ(n) (OMAP35XX_INTCPS_VBASE + 0x9C + (0x20 * (n))) 524#define OMAP35XX_INTCPS_ILR(m) (OMAP35XX_INTCPS_VBASE + 0x100 + (0x4 * (m))) 525 526 527#define OMAP35XX_IRQ_EMUINT 0 /* MPU emulation(2) */ 528#define OMAP35XX_IRQ_COMMTX 1 /* MPU emulation(2) */ 529#define OMAP35XX_IRQ_COMMRX 2 /* MPU emulation(2) */ 530#define OMAP35XX_IRQ_BENCH 3 /* MPU emulation(2) */ 531#define OMAP35XX_IRQ_MCBSP2_ST 4 /* Sidetone MCBSP2 overflow */ 532#define OMAP35XX_IRQ_MCBSP3_ST 5 /* Sidetone MCBSP3 overflow */ 533#define OMAP35XX_IRQ_SSM_ABORT 6 /* MPU subsystem secure state-machine abort (2) */ 534#define OMAP35XX_IRQ_SYS_NIRQ 7 /* External source (active low) */ 535#define OMAP35XX_IRQ_RESERVED8 8 /* RESERVED */ 536#define OMAP35XX_IRQ_SMX_DBG 9 /* SMX error for debug */ 537#define OMAP35XX_IRQ_SMX_APP 10 /* SMX error for application */ 538#define OMAP35XX_IRQ_PRCM_MPU 11 /* PRCM module IRQ */ 539#define OMAP35XX_IRQ_SDMA0 12 /* System DMA request 0(3) */ 540#define OMAP35XX_IRQ_SDMA1 13 /* System DMA request 1(3) */ 541#define OMAP35XX_IRQ_SDMA2 14 /* System DMA request 2 */ 542#define OMAP35XX_IRQ_SDMA3 15 /* System DMA request 3 */ 543#define OMAP35XX_IRQ_MCBSP1 16 /* McBSP module 1 IRQ (3) */ 544#define OMAP35XX_IRQ_MCBSP2 17 /* McBSP module 2 IRQ (3) */ 545#define OMAP35XX_IRQ_SR1 18 /* SmartReflex��� 1 */ 546#define OMAP35XX_IRQ_SR2 19 /* SmartReflex��� 2 */ 547#define OMAP35XX_IRQ_GPMC 20 /* General-purpose memory controller module */ 548#define OMAP35XX_IRQ_SGX 21 /* 2D/3D graphics module */ 549#define OMAP35XX_IRQ_MCBSP3 22 /* McBSP module 3(3) */ 550#define OMAP35XX_IRQ_MCBSP4 23 /* McBSP module 4(3) */ 551#define OMAP35XX_IRQ_CAM0 24 /* Camera interface request 0 */ 552#define OMAP35XX_IRQ_DSS 25 /* Display subsystem module(3) */ 553#define OMAP35XX_IRQ_MAIL_U0 26 /* Mailbox user 0 request */ 554#define OMAP35XX_IRQ_MCBSP5_IRQ1 27 /* McBSP module 5 (3) */ 555#define OMAP35XX_IRQ_IVA2_MMU 28 /* IVA2 MMU */ 556#define OMAP35XX_IRQ_GPIO1_MPU 29 /* GPIO module 1(3) */ 557#define OMAP35XX_IRQ_GPIO2_MPU 30 /* GPIO module 2(3) */ 558#define OMAP35XX_IRQ_GPIO3_MPU 31 /* GPIO module 3(3) */ 559#define OMAP35XX_IRQ_GPIO4_MPU 32 /* GPIO module 4(3) */ 560#define OMAP35XX_IRQ_GPIO5_MPU 33 /* GPIO module 5(3) */ 561#define OMAP35XX_IRQ_GPIO6_MPU 34 /* GPIO module 6(3) */ 562#define OMAP35XX_IRQ_USIM 35 /* USIM interrupt (HS devices only) (4) */ 563#define OMAP35XX_IRQ_WDT3 36 /* Watchdog timer module 3 overflow */ 564#define OMAP35XX_IRQ_GPT1 37 /* General-purpose timer module 1 */ 565#define OMAP35XX_IRQ_GPT2 38 /* General-purpose timer module 2 */ 566#define OMAP35XX_IRQ_GPT3 39 /* General-purpose timer module 3 */ 567#define OMAP35XX_IRQ_GPT4 40 /* General-purpose timer module 4 */ 568#define OMAP35XX_IRQ_GPT5 41 /* General-purpose timer module 5(3) */ 569#define OMAP35XX_IRQ_GPT6 42 /* General-purpose timer module 6(3) */ 570#define OMAP35XX_IRQ_GPT7 43 /* General-purpose timer module 7(3) */ 571#define OMAP35XX_IRQ_GPT8 44 /* General-purpose timer module 8(3) */ 572#define OMAP35XX_IRQ_GPT9 45 /* General-purpose timer module 9 */ 573#define OMAP35XX_IRQ_GPT10 46 /* General-purpose timer module 10 */ 574#define OMAP35XX_IRQ_GPT11 47 /* General-purpose timer module 11 */ 575#define OMAP35XX_IRQ_SPI4 48 /* McSPI module 4 */ 576#define OMAP35XX_IRQ_SHA1MD5_2 49 /* SHA-1/MD5 crypto-accelerator 2 (HS devices only)(4) */ 577#define OMAP35XX_IRQ_FPKA_IRQREADY_N 50 /* PKA crypto-accelerator (HS devices only) (4) */ 578#define OMAP35XX_IRQ_SHA2MD5 51 /* SHA-2/MD5 crypto-accelerator 1 (HS devices only) (4) */ 579#define OMAP35XX_IRQ_RNG 52 /* RNG module (HS devices only) (4) */ 580#define OMAP35XX_IRQ_MG 53 /* MG function (3) */ 581#define OMAP35XX_IRQ_MCBSP4_TX 54 /* McBSP module 4 transmit(3) */ 582#define OMAP35XX_IRQ_MCBSP4_RX 55 /* McBSP module 4 receive(3) */ 583#define OMAP35XX_IRQ_I2C1 56 /* I2C module 1 */ 584#define OMAP35XX_IRQ_I2C2 57 /* I2C module 2 */ 585#define OMAP35XX_IRQ_HDQ 58 /* HDQ / One-wire */ 586#define OMAP35XX_IRQ_MCBSP1_TX 59 /* McBSP module 1 transmit(3) */ 587#define OMAP35XX_IRQ_MCBSP1_RX 60 /* McBSP module 1 receive(3) */ 588#define OMAP35XX_IRQ_I2C3 61 /* I2C module 3 */ 589#define OMAP35XX_IRQ_McBSP2_TX 62 /* McBSP module 2 transmit(3) */ 590#define OMAP35XX_IRQ_McBSP2_RX 63 /* McBSP module 2 receive(3) */ 591#define OMAP35XX_IRQ_FPKA_IRQRERROR_N 64 /* PKA crypto-accelerator (HS devices only) (4) */ 592#define OMAP35XX_IRQ_SPI1 65 /* McSPI module 1 */ 593#define OMAP35XX_IRQ_SPI2 66 /* McSPI module 2 */ 594#define OMAP35XX_IRQ_RESERVED67 67 /* RESERVED */ 595#define OMAP35XX_IRQ_RESERVED68 68 /* RESERVED */ 596#define OMAP35XX_IRQ_RESERVED69 69 /* RESERVED */ 597#define OMAP35XX_IRQ_RESERVED70 70 /* RESERVED */ 598#define OMAP35XX_IRQ_RESERVED71 71 /* RESERVED */ 599#define OMAP35XX_IRQ_UART1 72 /* UART module 1 */ 600#define OMAP35XX_IRQ_UART2 73 /* UART module 2 */ 601#define OMAP35XX_IRQ_UART3 74 /* UART module 3 (also infrared)(3) */ 602#define OMAP35XX_IRQ_PBIAS 75 /* Merged interrupt for PBIASlite1 and 2 */ 603#define OMAP35XX_IRQ_OHCI 76 /* OHCI controller HSUSB MP Host Interrupt */ 604#define OMAP35XX_IRQ_EHCI 77 /* EHCI controller HSUSB MP Host Interrupt */ 605#define OMAP35XX_IRQ_TLL 78 /* HSUSB MP TLL Interrupt */ 606#define OMAP35XX_IRQ_PARTHASH 79 /* SHA2/MD5 crypto-accelerator 1 (HS devices only) (4) */ 607#define OMAP35XX_IRQ_RESERVED80 80 /* Reserved */ 608#define OMAP35XX_IRQ_MCBSP5_TX 81 /* McBSP module 5 transmit(3) */ 609#define OMAP35XX_IRQ_MCBSP5_RX 82 /* McBSP module 5 receive(3) */ 610#define OMAP35XX_IRQ_MMC1 83 /* MMC/SD module 1 */ 611#define OMAP35XX_IRQ_MS 84 /* MS-PRO��� module */ 612#define OMAP35XX_IRQ_RESERVED85 85 /* Reserved */ 613#define OMAP35XX_IRQ_MMC2 86 /* MMC/SD module 2 */ 614#define OMAP35XX_IRQ_MPU_ICR 87 /* MPU ICR */ 615#define OMAP35XX_IRQ_RESERVED 88 /* RESERVED */ 616#define OMAP35XX_IRQ_MCBSP3_TX 89 /* McBSP module 3 transmit(3) */ 617#define OMAP35XX_IRQ_MCBSP3_RX 90 /* McBSP module 3 receive(3) */ 618#define OMAP35XX_IRQ_SPI3 91 /* McSPI module 3 */ 619#define OMAP35XX_IRQ_HSUSB_MC_NINT 92 /* High-Speed USB OTG controller */ 620#define OMAP35XX_IRQ_HSUSB_DMA_NINT 93 /* High-Speed USB OTG DMA controller */ 621#define OMAP35XX_IRQ_MMC3 94 /* MMC/SD module 3 */ 622#define OMAP35XX_IRQ_GPT12 95 /* General-purpose timer module 12 */ 623 624 625 626 627/* 628 * General Purpose Timers 629 */ 630#define OMAP35XX_GPTIMER1_VBASE (OMAP35XX_L4_WAKEUP_VBASE + OMAP35XX_GPTIMER1_OFFSET) 631#define OMAP35XX_GPTIMER1_HWBASE (OMAP35XX_L4_WAKEUP_HWBASE + OMAP35XX_GPTIMER1_OFFSET) 632#define OMAP35XX_GPTIMER2_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_GPTIMER2_OFFSET) 633#define OMAP35XX_GPTIMER2_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_GPTIMER2_OFFSET) 634#define OMAP35XX_GPTIMER3_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_GPTIMER3_OFFSET) 635#define OMAP35XX_GPTIMER3_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_GPTIMER3_OFFSET) 636#define OMAP35XX_GPTIMER4_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_GPTIMER4_OFFSET) 637#define OMAP35XX_GPTIMER4_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_GPTIMER4_OFFSET) 638#define OMAP35XX_GPTIMER5_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_GPTIMER5_OFFSET) 639#define OMAP35XX_GPTIMER5_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_GPTIMER5_OFFSET) 640#define OMAP35XX_GPTIMER6_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_GPTIMER6_OFFSET) 641#define OMAP35XX_GPTIMER6_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_GPTIMER6_OFFSET) 642#define OMAP35XX_GPTIMER7_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_GPTIMER7_OFFSET) 643#define OMAP35XX_GPTIMER7_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_GPTIMER7_OFFSET) 644#define OMAP35XX_GPTIMER8_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_GPTIMER8_OFFSET) 645#define OMAP35XX_GPTIMER8_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_GPTIMER8_OFFSET) 646#define OMAP35XX_GPTIMER9_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_GPTIMER9_OFFSET) 647#define OMAP35XX_GPTIMER9_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_GPTIMER9_OFFSET) 648#define OMAP35XX_GPTIMER10_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_GPTIMER10_OFFSET) 649#define OMAP35XX_GPTIMER10_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_GPTIMER10_OFFSET) 650#define OMAP35XX_GPTIMER11_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_GPTIMER11_OFFSET) 651#define OMAP35XX_GPTIMER11_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_GPTIMER11_OFFSET) 652#define OMAP35XX_GPTIMER12_VBASE 0x48304000UL /* GPTIMER12 */ 653#define OMAP35XX_GPTIMER_SIZE 0x00001000UL 654 655 656 657/* Timer register offsets */ 658#define OMAP35XX_GPTIMER_TIOCP_CFG 0x010 659#define OMAP35XX_GPTIMER_TISTAT 0x014 660#define OMAP35XX_GPTIMER_TISR 0x018 661#define OMAP35XX_GPTIMER_TIER 0x01C 662#define OMAP35XX_GPTIMER_TWER 0x020 663#define OMAP35XX_GPTIMER_TCLR 0x024 664#define OMAP35XX_GPTIMER_TCRR 0x028 665#define OMAP35XX_GPTIMER_TLDR 0x02C 666#define OMAP35XX_GPTIMER_TTGR 0x030 667#define OMAP35XX_GPTIMER_TWPS 0x034 668#define OMAP35XX_GPTIMER_TMAR 0x038 669#define OMAP35XX_GPTIMER_TCAR1 0x03C 670#define OMAP35XX_GPTIMER_TSICR 0x040 671#define OMAP35XX_GPTIMER_TCAR2 0x044 672#define OMAP35XX_GPTIMER_TPIR 0x048 673#define OMAP35XX_GPTIMER_TNIR 0x04C 674#define OMAP35XX_GPTIMER_TCVR 0x050 675#define OMAP35XX_GPTIMER_TOCR 0x054 676#define OMAP35XX_GPTIMER_TOWR 0x058 677 678/* Bit values */ 679#define MAT_IT_FLAG 0x01 680#define OVF_IT_FLAG 0x02 681#define TCAR_IT_FLAG 0x04 682 683 684 685/* 686 * GPIO - General Purpose IO 687 */ 688 689/* Base addresses for the GPIO modules */ 690#define OMAP35XX_GPIO1_HWBASE (OMAP35XX_L4_WAKEUP_HWBASE + OMAP35XX_GPIO1_OFFSET) 691#define OMAP35XX_GPIO1_VBASE (OMAP35XX_L4_WAKEUP_VBASE + OMAP35XX_GPIO1_OFFSET) 692#define OMAP35XX_GPIO1_SIZE 0x00001000UL 693#define OMAP35XX_GPIO2_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_GPIO2_OFFSET) 694#define OMAP35XX_GPIO2_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_GPIO2_OFFSET) 695#define OMAP35XX_GPIO2_SIZE 0x00001000UL 696#define OMAP35XX_GPIO3_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_GPIO3_OFFSET) 697#define OMAP35XX_GPIO3_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_GPIO3_OFFSET) 698#define OMAP35XX_GPIO3_SIZE 0x00001000UL 699#define OMAP35XX_GPIO4_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_GPIO4_OFFSET) 700#define OMAP35XX_GPIO4_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_GPIO4_OFFSET) 701#define OMAP35XX_GPIO4_SIZE 0x00001000UL 702#define OMAP35XX_GPIO5_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_GPIO5_OFFSET) 703#define OMAP35XX_GPIO5_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_GPIO5_OFFSET) 704#define OMAP35XX_GPIO5_SIZE 0x00001000UL 705#define OMAP35XX_GPIO6_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_GPIO6_OFFSET) 706#define OMAP35XX_GPIO6_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_GPIO6_OFFSET) 707#define OMAP35XX_GPIO6_SIZE 0x00001000UL 708 709 710 711/* Register offsets within the banks above */ 712#define OMAP35XX_GPIO_SYSCONFIG 0x010 713#define OMAP35XX_GPIO_SYSSTATUS 0x014 714#define OMAP35XX_GPIO_IRQSTATUS1 0x018 715#define OMAP35XX_GPIO_IRQENABLE1 0x01C 716#define OMAP35XX_GPIO_WAKEUPENABLE 0x020 717#define OMAP35XX_GPIO_IRQSTATUS2 0x028 718#define OMAP35XX_GPIO_IRQENABLE2 0x02C 719#define OMAP35XX_GPIO_CTRL 0x030 720#define OMAP35XX_GPIO_OE 0x034 721#define OMAP35XX_GPIO_DATAIN 0x038 722#define OMAP35XX_GPIO_DATAOUT 0x03C 723#define OMAP35XX_GPIO_LEVELDETECT0 0x040 724#define OMAP35XX_GPIO_LEVELDETECT1 0x044 725#define OMAP35XX_GPIO_RISINGDETECT 0x048 726#define OMAP35XX_GPIO_FALLINGDETECT 0x04C 727#define OMAP35XX_GPIO_DEBOUNCENABLE 0x050 728#define OMAP35XX_GPIO_DEBOUNCINGTIME 0x054 729#define OMAP35XX_GPIO_CLEARIRQENABLE1 0x060 730#define OMAP35XX_GPIO_SETIRQENABLE1 0x064 731#define OMAP35XX_GPIO_CLEARIRQENABLE2 0x070 732#define OMAP35XX_GPIO_SETIRQENABLE2 0x074 733#define OMAP35XX_GPIO_CLEARWKUENA 0x080 734#define OMAP35XX_GPIO_SETWKUENA 0x084 735#define OMAP35XX_GPIO_CLEARDATAOUT 0x090 736#define OMAP35XX_GPIO_SETDATAOUT 0x094 737 738 739/* 740 * MMC/SD/SDIO 741 */ 742 743/* Base addresses for the MMC/SD/SDIO modules */ 744#define OMAP35XX_MMCHS1_HWBASE (OMAP35XX_L4_CORE_HWBASE + 0x0009C000) 745#define OMAP35XX_MMCHS1_VBASE (OMAP35XX_L4_CORE_VBASE + 0x0009C000) 746#define OMAP35XX_MMCHS2_HWBASE (OMAP35XX_L4_CORE_HWBASE + 0x000B4000) 747#define OMAP35XX_MMCHS2_VBASE (OMAP35XX_L4_CORE_VBASE + 0x000B4000) 748#define OMAP35XX_MMCHS3_HWBASE (OMAP35XX_L4_CORE_HWBASE + 0x000AD000) 749#define OMAP35XX_MMCHS3_VBASE (OMAP35XX_L4_CORE_VBASE + 0x000AD000) 750#define OMAP35XX_MMCHS_SIZE 0x00000200UL 751 752/* Register offsets within each of the MMC/SD/SDIO controllers */ 753#define OMAP35XX_MMCHS_SYSCONFIG 0x010 754#define OMAP35XX_MMCHS_SYSSTATUS 0x014 755#define OMAP35XX_MMCHS_CSRE 0x024 756#define OMAP35XX_MMCHS_SYSTEST 0x028 757#define OMAP35XX_MMCHS_CON 0x02C 758#define OMAP35XX_MMCHS_PWCNT 0x030 759#define OMAP35XX_MMCHS_BLK 0x104 760#define OMAP35XX_MMCHS_ARG 0x108 761#define OMAP35XX_MMCHS_CMD 0x10C 762#define OMAP35XX_MMCHS_RSP10 0x110 763#define OMAP35XX_MMCHS_RSP32 0x114 764#define OMAP35XX_MMCHS_RSP54 0x118 765#define OMAP35XX_MMCHS_RSP76 0x11C 766#define OMAP35XX_MMCHS_DATA 0x120 767#define OMAP35XX_MMCHS_PSTATE 0x124 768#define OMAP35XX_MMCHS_HCTL 0x128 769#define OMAP35XX_MMCHS_SYSCTL 0x12C 770#define OMAP35XX_MMCHS_STAT 0x130 771#define OMAP35XX_MMCHS_IE 0x134 772#define OMAP35XX_MMCHS_ISE 0x138 773#define OMAP35XX_MMCHS_AC12 0x13C 774#define OMAP35XX_MMCHS_CAPA 0x140 775#define OMAP35XX_MMCHS_CUR_CAPA 0x148 776#define OMAP35XX_MMCHS_REV 0x1FC 777 778 779 780#endif /* _OMAP35XX_REG_H_ */ 781