1183840Sraj/*- 2183840Sraj * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. 3183840Sraj * All rights reserved. 4183840Sraj * 5183840Sraj * Developed by Semihalf. 6183840Sraj * 7183840Sraj * Redistribution and use in source and binary forms, with or without 8183840Sraj * modification, are permitted provided that the following conditions 9183840Sraj * are met: 10183840Sraj * 1. Redistributions of source code must retain the above copyright 11183840Sraj * notice, this list of conditions and the following disclaimer. 12183840Sraj * 2. Redistributions in binary form must reproduce the above copyright 13183840Sraj * notice, this list of conditions and the following disclaimer in the 14183840Sraj * documentation and/or other materials provided with the distribution. 15183840Sraj * 3. Neither the name of MARVELL nor the names of contributors 16183840Sraj * may be used to endorse or promote products derived from this software 17183840Sraj * without specific prior written permission. 18183840Sraj * 19183840Sraj * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20183840Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21183840Sraj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22183840Sraj * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23183840Sraj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24183840Sraj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25183840Sraj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26183840Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27183840Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28183840Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29183840Sraj * SUCH DAMAGE. 30183840Sraj */ 31183840Sraj 32183840Sraj#include <sys/cdefs.h> 33183840Sraj__FBSDID("$FreeBSD: releng/10.2/sys/arm/mv/orion/db88f5xxx.c 266386 2014-05-18 00:32:35Z ian $"); 34183840Sraj 35183840Sraj#include <sys/param.h> 36183840Sraj#include <sys/systm.h> 37183840Sraj#include <sys/bus.h> 38183840Sraj#include <sys/kernel.h> 39183840Sraj 40183840Sraj#include <vm/vm.h> 41183840Sraj#include <vm/pmap.h> 42183840Sraj 43186909Sraj#include <machine/bus.h> 44194072Smarcel#include <machine/intr.h> 45183840Sraj#include <machine/pte.h> 46183840Sraj#include <machine/vmparam.h> 47183840Sraj 48183840Sraj#include <arm/mv/mvreg.h> 49183840Sraj#include <arm/mv/mvvar.h> 50194072Smarcel#include <arm/mv/mvwin.h> 51183840Sraj 52183840Sraj/* 53183840Sraj * Virtual address space layout: 54183840Sraj * ----------------------------- 55183840Sraj * 0x0000_0000 - 0xbfff_ffff : user process 56183840Sraj * 57183840Sraj * 0xc040_0000 - virtual_avail : kernel reserved (text, data, page tables 58183840Sraj * : structures, ARM stacks etc.) 59183840Sraj * virtual_avail - 0xefff_ffff : KVA (virtual_avail is typically < 0xc0a0_0000) 60183840Sraj * 0xf000_0000 - 0xf0ff_ffff : no-cache allocation area (16MB) 61183840Sraj * 0xf100_0000 - 0xf10f_ffff : SoC integrated devices registers range (1MB) 62185089Sraj * 0xf110_0000 - 0xf11f_ffff : PCI-Express I/O space (1MB) 63185089Sraj * 0xf120_0000 - 0xf12f_ffff : PCI I/O space (1MB) 64185089Sraj * 0xf130_0000 - 0xf52f_ffff : PCI-Express memory space (64MB) 65185089Sraj * 0xf530_0000 - 0xf92f_ffff : PCI memory space (64MB) 66185089Sraj * 0xf930_0000 - 0xfffe_ffff : unused (~108MB) 67183840Sraj * 0xffff_0000 - 0xffff_0fff : 'high' vectors page (4KB) 68183840Sraj * 0xffff_1000 - 0xffff_1fff : ARM_TP_ADDRESS/RAS page (4KB) 69183840Sraj * 0xffff_2000 - 0xffff_ffff : unused (~55KB) 70183840Sraj */ 71183840Sraj 72209131Sraj 73209131Sraj#if 0 74185089Srajint platform_pci_get_irq(u_int bus, u_int slot, u_int func, u_int pin); 75183840Sraj 76183840Sraj/* Static device mappings. */ 77196531Srajconst struct pmap_devmap pmap_devmap[] = { 78183840Sraj /* 79183840Sraj * Map the on-board devices VA == PA so that we can access them 80183840Sraj * with the MMU on or off. 81183840Sraj */ 82183840Sraj { /* SoC integrated peripherals registers range */ 83183840Sraj MV_BASE, 84183840Sraj MV_PHYS_BASE, 85183840Sraj MV_SIZE, 86183840Sraj VM_PROT_READ | VM_PROT_WRITE, 87266386Sian PTE_DEVICE, 88183840Sraj }, 89183840Sraj { /* PCIE I/O */ 90183840Sraj MV_PCIE_IO_BASE, 91183840Sraj MV_PCIE_IO_PHYS_BASE, 92183840Sraj MV_PCIE_IO_SIZE, 93183840Sraj VM_PROT_READ | VM_PROT_WRITE, 94266386Sian PTE_DEVICE, 95183840Sraj }, 96183840Sraj { /* PCIE Memory */ 97183840Sraj MV_PCIE_MEM_BASE, 98183840Sraj MV_PCIE_MEM_PHYS_BASE, 99183840Sraj MV_PCIE_MEM_SIZE, 100183840Sraj VM_PROT_READ | VM_PROT_WRITE, 101266386Sian PTE_DEVICE, 102183840Sraj }, 103183840Sraj { /* PCI I/O */ 104183840Sraj MV_PCI_IO_BASE, 105183840Sraj MV_PCI_IO_PHYS_BASE, 106183840Sraj MV_PCI_IO_SIZE, 107183840Sraj VM_PROT_READ | VM_PROT_WRITE, 108266386Sian PTE_DEVICE, 109183840Sraj }, 110183840Sraj { /* PCI Memory */ 111183840Sraj MV_PCI_MEM_BASE, 112183840Sraj MV_PCI_MEM_PHYS_BASE, 113183840Sraj MV_PCI_MEM_SIZE, 114183840Sraj VM_PROT_READ | VM_PROT_WRITE, 115266386Sian PTE_DEVICE, 116183840Sraj }, 117183840Sraj { /* 7-seg LED */ 118183840Sraj MV_DEV_CS0_BASE, 119183840Sraj MV_DEV_CS0_PHYS_BASE, 120183840Sraj MV_DEV_CS0_SIZE, 121183840Sraj VM_PROT_READ | VM_PROT_WRITE, 122266386Sian PTE_DEVICE, 123183840Sraj }, 124183840Sraj { 0, 0, 0, 0, 0, } 125183840Sraj}; 126183840Sraj 127186932Sraj/* 128186932Sraj * The pci_irq_map table consists of 3 columns: 129186932Sraj * - PCI slot number (less than zero means ANY). 130186932Sraj * - PCI IRQ pin (less than zero means ANY). 131186932Sraj * - PCI IRQ (less than zero marks end of table). 132186932Sraj * 133186932Sraj * IRQ number from the first matching entry is used to configure PCI device 134186932Sraj */ 135183840Sraj 136186932Sraj/* PCI IRQ Map for DB-88F5281 */ 137186932Srajconst struct obio_pci_irq_map pci_irq_map[] = { 138186932Sraj { 7, -1, GPIO2IRQ(12) }, 139186932Sraj { 8, -1, GPIO2IRQ(13) }, 140186932Sraj { 9, -1, GPIO2IRQ(13) }, 141186932Sraj { -1, -1, -1 } 142186932Sraj}; 143183840Sraj 144186932Sraj/* PCI IRQ Map for DB-88F5182 */ 145186932Srajconst struct obio_pci_irq_map pci_irq_map[] = { 146186932Sraj { 7, -1, GPIO2IRQ(0) }, 147186932Sraj { 8, -1, GPIO2IRQ(1) }, 148186932Sraj { 9, -1, GPIO2IRQ(1) }, 149186932Sraj { -1, -1, -1 } 150186932Sraj}; 151186932Sraj#endif 152183840Sraj 153209131Sraj#if 0 154186909Sraj/* 155186909Sraj * mv_gpio_config row structure: 156186909Sraj * <GPIO number>, <GPIO flags>, <GPIO mode> 157186909Sraj * 158186909Sraj * - GPIO pin number (less than zero marks end of table) 159186909Sraj * - GPIO flags: 160186909Sraj * MV_GPIO_BLINK 161186909Sraj * MV_GPIO_POLAR_LOW 162186909Sraj * MV_GPIO_EDGE 163186909Sraj * MV_GPIO_LEVEL 164186909Sraj * - GPIO mode: 165186909Sraj * 1 - Output, set to HIGH. 166186909Sraj * 0 - Output, set to LOW. 167186909Sraj * -1 - Input. 168186909Sraj */ 169186909Sraj 170186909Sraj/* GPIO Configuration for DB-88F5281 */ 171186909Srajconst struct gpio_config mv_gpio_config[] = { 172186909Sraj { 12, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 }, 173186909Sraj { 13, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 }, 174186909Sraj { -1, -1, -1 } 175186909Sraj}; 176186909Sraj 177186909Sraj#if 0 178186909Sraj/* GPIO Configuration for DB-88F5182 */ 179186909Srajconst struct gpio_config mv_gpio_config[] = { 180186909Sraj { 0, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 }, 181186909Sraj { 1, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 }, 182186909Sraj { -1, -1, -1 } 183186909Sraj}; 184186909Sraj#endif 185186909Sraj 186186909Sraj#endif 187