mvreg.h revision 186899
1/*- 2 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: head/sys/arm/mv/mvreg.h 186899 2009-01-08 13:20:28Z raj $ 32 */ 33 34#ifndef _MVREG_H_ 35#define _MVREG_H_ 36 37#include <machine/intr.h> 38 39/* 40 * Physical addresses of integrated SoC peripherals 41 */ 42#define MV_PHYS_BASE 0xF1000000 43#define MV_SIZE 0x100000 44 45/* 46 * Decode windows addresses (physical) 47 */ 48#define MV_PCIE_IO_PHYS_BASE (MV_PHYS_BASE + MV_SIZE) 49#define MV_PCIE_IO_BASE MV_PCIE_IO_PHYS_BASE 50#define MV_PCIE_IO_SIZE (1024 * 1024) 51#define MV_PCI_IO_PHYS_BASE (MV_PCIE_IO_PHYS_BASE + MV_PCIE_IO_SIZE) 52#define MV_PCI_IO_BASE MV_PCI_IO_PHYS_BASE 53#define MV_PCI_IO_SIZE (1024 * 1024) 54 55#define MV_PCIE_MEM_PHYS_BASE (MV_PCI_IO_PHYS_BASE + MV_PCI_IO_SIZE) 56#define MV_PCIE_MEM_BASE MV_PCIE_MEM_PHYS_BASE 57#define MV_PCIE_MEM_SIZE (64 * 1024 * 1024) 58#define MV_PCI_MEM_PHYS_BASE (MV_PCIE_MEM_PHYS_BASE + MV_PCIE_MEM_SIZE) 59#define MV_PCI_MEM_BASE MV_PCI_MEM_PHYS_BASE 60#define MV_PCI_MEM_SIZE (64 * 1024 * 1024) 61 62/* XXX DEV_BOOT, CSx are board specific, should be defined per platform */ 63 64/* 512KB NOR FLASH */ 65#define MV_DEV_BOOT_PHYS_BASE (MV_PCI_MEM_PHYS_BASE + MV_PCI_MEM_SIZE) 66#define MV_DEV_BOOT_SIZE (512 * 1024) 67/* CS0: 7-seg LED */ 68#define MV_DEV_CS0_PHYS_BASE 0xFA000000 69#define MV_DEV_CS0_SIZE (1024 * 1024) /* XXX u-boot has 2MB */ 70/* CS1: 32MB NOR FLASH */ 71#define MV_DEV_CS1_PHYS_BASE (MV_DEV_CS0_PHYS_BASE + MV_DEV_CS0_SIZE) 72#define MV_DEV_CS1_SIZE (32 * 1024 * 1024) 73/* CS2: 32MB NAND FLASH */ 74#define MV_DEV_CS2_PHYS_BASE (MV_DEV_CS1_PHYS_BASE + MV_DEV_CS1_SIZE) 75#define MV_DEV_CS2_SIZE 1024 /* XXX u-boot has 1MB */ 76 77/* XXX this is probably not robust against wraparounds... */ 78#if ((MV_DEV_CS2_PHYS_BASE + MV_DEV_CS2_SIZE) > 0xFFFEFFFF) 79#error Devices memory layout overlaps reset vectors range! 80#endif 81 82/* 83 * Integrated SoC peripherals addresses 84 */ 85#define MV_BASE MV_PHYS_BASE /* VA == PA mapping */ 86#define MV_DDR_CADR_BASE (MV_BASE + 0x1500) 87#define MV_MPP_BASE (MV_BASE + 0x10000) 88#define MV_GPIO_BASE (MV_BASE + 0x10100) 89#define MV_GPIO_SIZE 0x20 90#define MV_RTC_BASE (MV_BASE + 0x10300) 91#define MV_RTC_SIZE 0x08 92#define MV_TWSI_BASE (MV_BASE + 0x11000) 93#define MV_TWSI_SIZE 0x20 94#define MV_UART0_BASE (MV_BASE + 0x12000) 95#define MV_UART1_BASE (MV_BASE + 0x12100) 96#define MV_UART_SIZE 0x20 97#define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000) 98#define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80) 99#define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x100) 100#define MV_IC_BASE (MV_MBUS_BRIDGE_BASE + 0x200) 101#define MV_IC_SIZE 0x3C 102#define MV_TIMERS_BASE (MV_MBUS_BRIDGE_BASE + 0x300) 103#define MV_TIMERS_SIZE 0x30 104#define MV_PCI_BASE (MV_BASE + 0x30000) 105#define MV_PCI_SIZE 0x2000 106#define MV_PCIE_BASE (MV_BASE + 0x40000) 107#define MV_PCIE_SIZE 0x2000 108 109#define MV_PCIE00_BASE (MV_PCIE_BASE + 0x00000) 110#define MV_PCIE01_BASE (MV_PCIE_BASE + 0x04000) 111#define MV_PCIE02_BASE (MV_PCIE_BASE + 0x08000) 112#define MV_PCIE03_BASE (MV_PCIE_BASE + 0x0C000) 113#define MV_PCIE10_BASE (MV_PCIE_BASE + 0x40000) 114#define MV_PCIE11_BASE (MV_PCIE_BASE + 0x44000) 115#define MV_PCIE12_BASE (MV_PCIE_BASE + 0x48000) 116#define MV_PCIE13_BASE (MV_PCIE_BASE + 0x4C000) 117 118#define MV_USB0_BASE (MV_BASE + 0x50000) 119#define MV_USB1_BASE (MV_USB0_BASE + 0x1000) 120#define MV_USB2_BASE (MV_USB0_BASE + 0x2000) 121#define MV_USB_SIZE 0x1000 122#define MV_USB_HOST_OFST 0x0100 /* EHCI HC regs start at this offset within USB range */ 123#define MV_USB_AWR_BASE (MV_USB0_BASE + 0x320) 124#define MV_IDMA_BASE (MV_BASE + 0x60000) 125#define MV_IDMA_SIZE 0x1000 126#define MV_XOR_BASE (MV_BASE + 0x60000) 127#define MV_XOR_SIZE 0x1000 128#define MV_ETH0_BASE (MV_BASE + 0x72000) 129#define MV_ETH1_BASE (MV_BASE + 0x76000) 130#define MV_ETH_SIZE 0x2000 131 132#define MV_DEV_CS0_BASE MV_DEV_CS0_PHYS_BASE 133 134/* 135 * Interrupt sources 136 */ 137#if defined(SOC_MV_ORION) 138 139#define MV_INT_BRIDGE 0 /* AHB-MBus Bridge Interrupt */ 140#define MV_INT_UART0 3 /* UART0 Interrupt */ 141#define MV_INT_UART1 4 142#define MV_INT_GPIO7_0 6 /* GPIO[7:0] Interrupt */ 143#define MV_INT_GPIO15_8 7 /* GPIO[15:8] Interrupt */ 144#define MV_INT_GPIO23_16 8 /* GPIO[23:16] Interrupt */ 145#define MV_INT_GPIO31_24 9 /* GPIO[31:24] Interrupt */ 146#define MV_INT_PEX0_ERR 10 /* PCI Express Error */ 147#define MV_INT_PEX0 11 /* PCI Express INTA,B,C,D Message */ 148#define MV_INT_PCI_ERR 15 /* PCI Error */ 149#define MV_INT_USB_BERR 16 /* USB Bridge Error */ 150#define MV_INT_USB_CI 17 /* USB Controller interrupt */ 151#define MV_INT_GBERX 18 /* GbE receive interrupt */ 152#define MV_INT_GBETX 19 /* GbE transmit interrupt */ 153#define MV_INT_GBEMISC 20 /* GbE misc. interrupt */ 154#define MV_INT_GBESUM 21 /* GbE summary interrupt */ 155#define MV_INT_GBEERR 22 /* GbE error interrupt */ 156#define MV_INT_IDMA_ERR 23 /* DMA error interrupt */ 157#define MV_INT_IDMA0 24 /* IDMA chan. 0 completion interrupt */ 158#define MV_INT_IDMA1 25 /* IDMA chan. 1 completion interrupt */ 159#define MV_INT_IDMA2 26 /* IDMA chan. 2 completion interrupt */ 160#define MV_INT_IDMA3 27 /* IDMA chan. 3 completion interrupt */ 161#define MV_INT_SATA 29 /* Serial-ATA Interrupt */ 162 163#elif defined(SOC_MV_KIRKWOOD) 164 165#define MV_INT_BRIDGE 1 /* AHB-MBus Bridge Interrupt */ 166#define MV_INT_XOR0_CHAN0 5 /* XOR engine 0 channel 0 Interrupt */ 167#define MV_INT_XOR0_CHAN1 6 /* XOR engine 0 channel 1 Interrupt */ 168#define MV_INT_XOR1_CHAN0 7 /* XOR engine 1 channel 0 Interrupt */ 169#define MV_INT_XOR1_CHAN1 8 /* XOR engine 1 channel 1 Interrupt */ 170#define MV_INT_PEX0 9 /* PCI Express INTA,B,C,D Message */ 171#define MV_INT_GBESUM 11 /* GbE0 summary interrupt */ 172#define MV_INT_GBERX 12 /* GbE0 receive interrupt */ 173#define MV_INT_GBETX 13 /* GbE0 transmit interrupt */ 174#define MV_INT_GBEMISC 14 /* GbE0 misc. interrupt */ 175#define MV_INT_GBE1SUM 15 /* GbE1 summary interrupt */ 176#define MV_INT_GBE1RX 16 /* GbE1 receive interrupt */ 177#define MV_INT_GBE1TX 17 /* GbE1 transmit interrupt */ 178#define MV_INT_GBE1MISC 18 /* GbE1 misc. interrupt */ 179#define MV_INT_USB_CI 19 /* USB Controller interrupt */ 180#define MV_INT_SATA 21 /* Serial-ATA Interrupt */ 181#define MV_INT_IDMA_ERR 23 /* DMA error interrupt */ 182#define MV_INT_UART0 33 /* UART0 Interrupt */ 183#define MV_INT_UART1 34 184#define MV_INT_GPIO7_0 35 /* GPIO[7:0] Interrupt */ 185#define MV_INT_GPIO15_8 36 /* GPIO[15:8] Interrupt */ 186#define MV_INT_GPIO23_16 37 /* GPIO[23:16] Interrupt */ 187#define MV_INT_GPIO31_24 38 /* GPIO[31:24] Interrupt */ 188#define MV_INT_GPIOHI7_0 39 /* GPIOHI[7:0] Interrupt */ 189#define MV_INT_GPIOHI15_8 40 /* GPIOHI[15:8] Interrupt */ 190#define MV_INT_GPIOHI23_16 41 /* GPIOHI[23:16] Interrupt */ 191#define MV_INT_XOR0_ERR 42 /* XOR engine 0 error Interrupt */ 192#define MV_INT_XOR1_ERR 43 /* XOR engine 1 error Interrupt */ 193#define MV_INT_PEX0_ERR 44 /* PCI Express Error */ 194#define MV_INT_GBEERR 46 /* GbE0 error interrupt */ 195#define MV_INT_GBE1ERR 47 /* GbE1 error interrupt */ 196#define MV_INT_USB_BERR 48 /* USB Bridge Error */ 197 198#elif defined(SOC_MV_DISCOVERY) 199 200#define MV_INT_ERRSUM 0 /* Summary of error interrupts */ 201#define MV_INT_SPI 1 /* SPI interrupt */ 202#define MV_INT_TWSI0 2 /* TWSI0 interrupt */ 203#define MV_INT_TWSI1 3 /* TWSI1 interrupt */ 204#define MV_INT_IDMA0 4 /* IDMA Channel0 completion */ 205#define MV_INT_IDMA1 5 /* IDMA Channel0 completion */ 206#define MV_INT_IDMA2 6 /* IDMA Channel0 completion */ 207#define MV_INT_IDMA3 7 /* IDMA Channel0 completion */ 208#define MV_INT_TIMER0 8 /* Timer0 interrupt */ 209#define MV_INT_TIMER1 9 /* Timer1 interrupt */ 210#define MV_INT_TIMER2 10 /* Timer2 interrupt */ 211#define MV_INT_TIMER3 11 /* Timer3 interrupt */ 212#define MV_INT_UART0 12 /* UART0 interrupt */ 213#define MV_INT_UART1 13 /* UART1 interrupt */ 214#define MV_INT_UART2 14 /* UART2 interrupt */ 215#define MV_INT_UART3 15 /* UART3 interrupt */ 216#define MV_INT_USB0 16 /* USB0 interrupt */ 217#define MV_INT_USB1 17 /* USB1 interrupt */ 218#define MV_INT_USB2 18 /* USB2 interrupt */ 219#define MV_INT_CRYPTO 19 /* Crypto engine completion interrupt */ 220#define MV_INT_XOR0 22 /* XOR engine 0 completion interrupt */ 221#define MV_INT_XOR1 23 /* XOR engine 1 completion interrupt */ 222#define MV_INT_SATA 26 /* SATA interrupt */ 223#define MV_INT_PEX00 32 /* PCI Express port 0.0 INTA/B/C/D */ 224#define MV_INT_PEX01 33 /* PCI Express port 0.1 INTA/B/C/D */ 225#define MV_INT_PEX02 34 /* PCI Express port 0.2 INTA/B/C/D */ 226#define MV_INT_PEX03 35 /* PCI Express port 0.3 INTA/B/C/D */ 227#define MV_INT_PEX10 36 /* PCI Express port 1.0 INTA/B/C/D */ 228#define MV_INT_PEX11 37 /* PCI Express port 1.1 INTA/B/C/D */ 229#define MV_INT_PEX12 38 /* PCI Express port 1.2 INTA/B/C/D */ 230#define MV_INT_PEX13 39 /* PCI Express port 1.3 INTA/B/C/D */ 231#define MV_INT_GBESUM 40 /* Gigabit Ethernet Port 0 summary */ 232#define MV_INT_GBERX 41 /* Gigabit Ethernet Port 0 Rx summary */ 233#define MV_INT_GBETX 42 /* Gigabit Ethernet Port 0 Tx summary */ 234#define MV_INT_GBEMISC 43 /* Gigabit Ethernet Port 0 Misc summ. */ 235#define MV_INT_GBE1SUM 44 /* Gigabit Ethernet Port 1 summary */ 236#define MV_INT_GBE1RX 45 /* Gigabit Ethernet Port 1 Rx summary */ 237#define MV_INT_GBE1TX 46 /* Gigabit Ethernet Port 1 Tx summary */ 238#define MV_INT_GBE1MISC 47 /* Gigabit Ethernet Port 1 Misc summ. */ 239#define MV_INT_GPIO7_0 56 /* GPIO[7:0] Interrupt */ 240#define MV_INT_GPIO15_8 57 /* GPIO[15:8] Interrupt */ 241#define MV_INT_GPIO23_16 58 /* GPIO[23:16] Interrupt */ 242#define MV_INT_GPIO31_24 59 /* GPIO[31:24] Interrupt */ 243#define MV_INT_DB_IN 60 /* Inbound Doorbell Cause reg Summary */ 244#define MV_INT_DB_OUT 61 /* Outbound Doorbell Cause reg Summ. */ 245#define MV_INT_CRYPT_ERR 64 /* Crypto engine error */ 246#define MV_INT_DEV_ERR 65 /* Device bus error */ 247#define MV_INT_IDMA_ERR 66 /* DMA error */ 248#define MV_INT_CPU_ERR 67 /* CPU error */ 249#define MV_INT_PEX0_ERR 68 /* PCI-Express port0 error */ 250#define MV_INT_PEX1_ERR 69 /* PCI-Express port1 error */ 251#define MV_INT_GBE_ERR 70 /* Gigabit Ethernet error */ 252#define MV_INT_USB_ERR 72 /* USB error */ 253#define MV_INT_DRAM_ERR 73 /* DRAM ECC error */ 254#define MV_INT_XOR_ERR 74 /* XOR engine error */ 255#define MV_INT_WD 79 /* WD Timer interrupt */ 256 257#endif /* SOC_MV_ORION */ 258 259#define BRIDGE_IRQ_CAUSE 0x10 260#define BRIGDE_IRQ_MASK 0x14 261 262#if defined(SOC_MV_DISCOVERY) 263#define IRQ_CAUSE_ERROR 0x0 264#define IRQ_CAUSE 0x4 265#define IRQ_CAUSE_HI 0x8 266#define IRQ_MASK_ERROR 0xC 267#define IRQ_MASK 0x10 268#define IRQ_MASK_HI 0x14 269#define IRQ_CAUSE_SELECT 0x18 270#define FIQ_MASK_ERROR 0x1C 271#define FIQ_MASK 0x20 272#define FIQ_MASK_HI 0x24 273#define FIQ_CAUSE_SELECT 0x28 274#define ENDPOINT_IRQ_MASK_ERROR 0x2C 275#define ENDPOINT_IRQ_MASK 0x30 276#define ENDPOINT_IRQ_MASK_HI 0x34 277#define ENDPOINT_IRQ_CAUSE_SELECT 0x38 278#else /* !SOC_MV_DISCOVERY */ 279#define IRQ_CAUSE 0x0 280#define IRQ_MASK 0x4 281#define FIQ_MASK 0x8 282#define ENDPOINT_IRQ_MASK 0xC 283#define IRQ_CAUSE_HI 0x10 284#define IRQ_MASK_HI 0x14 285#define FIQ_MASK_HI 0x18 286#define ENDPOINT_IRQ_MASK_HI 0x1C 287#define IRQ_CAUSE_ERROR (-1) /* Fake defines for unified */ 288#define IRQ_MASK_ERROR (-1) /* interrupt controller code */ 289#endif 290 291#define BRIDGE_IRQ_CAUSE 0x10 292#define IRQ_CPU_SELF 0x00000001 293#define IRQ_TIMER0 0x00000002 294#define IRQ_TIMER1 0x00000004 295#define IRQ_TIMER_WD 0x00000008 296 297#define BRIDGE_IRQ_MASK 0x14 298#define IRQ_CPU_MASK 0x00000001 299#define IRQ_TIMER0_MASK 0x00000002 300#define IRQ_TIMER1_MASK 0x00000004 301#define IRQ_TIMER_WD_MASK 0x00000008 302 303/* 304 * System reset 305 */ 306#define RSTOUTn_MASK 0x8 307#define WD_RST_OUT_EN 0x00000002 308#define SOFT_RST_OUT_EN 0x00000004 309#define SYSTEM_SOFT_RESET 0xc 310#define SYS_SOFT_RST 0x00000001 311 312/* 313 * Power Control 314 */ 315#define CPU_PM_CTRL 0x1C 316#define CPU_PM_CTRL_NONE 0 317 318#if defined(SOC_MV_KIRKWOOD) 319#define CPU_PM_CTRL_GE0 (1 << 0) 320#define CPU_PM_CTRL_PEX0_PHY (1 << 1) 321#define CPU_PM_CTRL_PEX0 (1 << 2) 322#define CPU_PM_CTRL_USB0 (1 << 3) 323#define CPU_PM_CTRL_SDIO (1 << 4) 324#define CPU_PM_CTRL_TSU (1 << 5) 325#define CPU_PM_CTRL_DUNIT (1 << 6) 326#define CPU_PM_CTRL_RUNIT (1 << 7) 327#define CPU_PM_CTRL_XOR0 (1 << 8) 328#define CPU_PM_CTRL_AUDIO (1 << 9) 329#define CPU_PM_CTRL_SATA0 (1 << 14) 330#define CPU_PM_CTRL_SATA1 (1 << 15) 331#define CPU_PM_CTRL_XOR1 (1 << 16) 332#define CPU_PM_CTRL_CRYPTO (1 << 17) 333#define CPU_PM_CTRL_GE1 (1 << 18) 334#define CPU_PM_CTRL_TDM (1 << 19) 335#elif defined(SOC_MV_DISCOVERY) 336#define CPU_PM_CTRL_GE0 (1 << 1) 337#define CPU_PM_CTRL_GE1 (1 << 2) 338#define CPU_PM_CTRL_PEX00 (1 << 5) 339#define CPU_PM_CTRL_PEX01 (1 << 6) 340#define CPU_PM_CTRL_PEX02 (1 << 7) 341#define CPU_PM_CTRL_PEX03 (1 << 8) 342#define CPU_PM_CTRL_PEX10 (1 << 9) 343#define CPU_PM_CTRL_PEX11 (1 << 10) 344#define CPU_PM_CTRL_PEX12 (1 << 11) 345#define CPU_PM_CTRL_PEX13 (1 << 12) 346#define CPU_PM_CTRL_SATA0_PHY (1 << 13) 347#define CPU_PM_CTRL_SATA0 (1 << 14) 348#define CPU_PM_CTRL_SATA1_PHY (1 << 15) 349#define CPU_PM_CTRL_SATA1 (1 << 16) 350#define CPU_PM_CTRL_USB0 (1 << 17) 351#define CPU_PM_CTRL_USB1 (1 << 18) 352#define CPU_PM_CTRL_USB2 (1 << 19) 353#define CPU_PM_CTRL_IDMA (1 << 20) 354#define CPU_PM_CTRL_XOR (1 << 21) 355#define CPU_PM_CTRL_CRYPTO (1 << 22) 356#define CPU_PM_CTRL_DEVICE (1 << 23) 357#endif 358 359/* 360 * Timers 361 */ 362#define CPU_TIMER_CONTROL 0x0 363#define CPU_TIMER0_EN 0x00000001 364#define CPU_TIMER0_AUTO 0x00000002 365#define CPU_TIMER1_EN 0x00000004 366#define CPU_TIMER1_AUTO 0x00000008 367#define CPU_TIMER_WD_EN 0x00000010 368#define CPU_TIMER_WD_AUTO 0x00000020 369#define CPU_TIMER0_REL 0x10 370#define CPU_TIMER0 0x14 371 372/* 373 * GPIO 374 */ 375#define GPIO_DATA_OUT 0x00 376#define GPIO_DATA_OUT_EN_CTRL 0x04 377#define GPIO_BLINK_EN 0x08 378#define GPIO_DATA_IN_POLAR 0x0c 379#define GPIO_DATA_IN 0x10 380#define GPIO_INT_CAUSE 0x14 381#define GPIO_INT_EDGE_MASK 0x18 382#define GPIO_INT_LEV_MASK 0x1c 383 384#define GPIO_HI_DATA_OUT 0x40 385#define GPIO_HI_DATA_OUT_EN_CTRL 0x44 386#define GPIO_HI_BLINK_EN 0x48 387#define GPIO_HI_DATA_IN_POLAR 0x4c 388#define GPIO_HI_DATA_IN 0x50 389#define GPIO_HI_INT_CAUSE 0x54 390#define GPIO_HI_INT_EDGE_MASK 0x58 391#define GPIO_HI_INT_LEV_MASK 0x5c 392 393#define GPIO(n) (1 << (n)) 394#define MV_GPIO_MAX_NPINS 64 395 396#define MV_GPIO_BLINK 0x1 397#define MV_GPIO_POLARITY 0x2 398#define MV_GPIO_EDGE 0x4 399#define MV_GPIO_LEVEL 0x8 400 401#define IS_GPIO_IRQ(irq) ((irq) >= NIRQ && (irq) < NIRQ + MV_GPIO_MAX_NPINS) 402#define GPIO2IRQ(gpio) ((gpio) + NIRQ) 403#define IRQ2GPIO(irq) ((irq) - NIRQ) 404 405/* 406 * MPP 407 */ 408#if defined(SOC_MV_ORION) 409#define MPP_CONTROL0 0x00 410#define MPP_CONTROL1 0x04 411#define MPP_CONTROL2 0x50 412#elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) 413#define MPP_CONTROL0 0x00 414#define MPP_CONTROL1 0x04 415#define MPP_CONTROL2 0x08 416#define MPP_CONTROL3 0x0C 417#define MPP_CONTROL4 0x10 418#define MPP_CONTROL5 0x14 419#define MPP_CONTROL6 0x18 420#else 421#error SOC_MV_XX not defined 422#endif 423 424#if defined(SOC_MV_ORION) 425#define SAMPLE_AT_RESET 0x10 426#elif defined(SOC_MV_KIRKWOOD) 427#define SAMPLE_AT_RESET 0x30 428#elif defined(SOC_MV_DISCOVERY) 429#define SAMPLE_AT_RESET_LO 0x30 430#define SAMPLE_AT_RESET_HI 0x34 431#else 432#error SOC_MV_XX not defined 433#endif 434 435/* 436 * Clocks 437 */ 438#if defined(SOC_MV_ORION) 439#define TCLK_MASK 0x00000300 440#define TCLK_SHIFT 0x08 441#elif defined(SOC_MV_DISCOVERY) 442#define TCLK_MASK 0x00000180 443#define TCLK_SHIFT 0x07 444#endif 445 446#define TCLK_100MHZ 100000000 447#define TCLK_125MHZ 125000000 448#define TCLK_133MHZ 133333333 449#define TCLK_150MHZ 150000000 450#define TCLK_166MHZ 166666667 451#define TCLK_200MHZ 200000000 452 453/* 454 * Chip ID 455 */ 456#define MV_DEV_88F5181 0x5181 457#define MV_DEV_88F5182 0x5182 458#define MV_DEV_88F5281 0x5281 459#define MV_DEV_88F6281 0x6281 460#define MV_DEV_MV78100 0x6381 461 462/* 463 * Decode windows definitions and macros 464 */ 465#define MV_WIN_CPU_CTRL(n) (0x10 * (n) + (((n) < 8) ? 0x000 : 0x880)) 466#define MV_WIN_CPU_BASE(n) (0x10 * (n) + (((n) < 8) ? 0x004 : 0x884)) 467#define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888)) 468#define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C)) 469#if defined(SOC_MV_DISCOVERY) 470#define MV_WIN_CPU_MAX 14 471#else 472#define MV_WIN_CPU_MAX 8 473#endif 474 475#define MV_WIN_DDR_BASE(n) (0x8 * (n) + 0x0) 476#define MV_WIN_DDR_SIZE(n) (0x8 * (n) + 0x4) 477#define MV_WIN_DDR_MAX 4 478 479#define MV_WIN_USB_CTRL(n) (0x10 * (n) + 0x0) 480#define MV_WIN_USB_BASE(n) (0x10 * (n) + 0x4) 481#define MV_WIN_USB_MAX 4 482 483#define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200) 484#define MV_WIN_ETH_SIZE(n) (0x8 * (n) + 0x204) 485#define MV_WIN_ETH_REMAP(n) (0x4 * (n) + 0x280) 486#define MV_WIN_ETH_MAX 6 487 488#define MV_WIN_IDMA_BASE(n) (0x8 * (n) + 0xa00) 489#define MV_WIN_IDMA_SIZE(n) (0x8 * (n) + 0xa04) 490#define MV_WIN_IDMA_REMAP(n) (0x4 * (n) + 0xa60) 491#define MV_WIN_IDMA_CAP(n) (0x4 * (n) + 0xa70) 492#define MV_WIN_IDMA_MAX 8 493#define MV_IDMA_CHAN_MAX 4 494 495#define MV_WIN_PCIE_CTRL(n) (0x10 * (((n) < 5) ? (n) : \ 496 (n) + 1) + 0x1820) 497#define MV_WIN_PCIE_BASE(n) (0x10 * (((n) < 5) ? (n) : \ 498 (n) + 1) + 0x1824) 499#define MV_WIN_PCIE_REMAP(n) (0x10 * (((n) < 5) ? (n) : \ 500 (n) + 1) + 0x182C) 501#define MV_WIN_PCIE_MAX 6 502 503#define MV_PCIE_BAR(n) (0x04 * (n) + 0x1804) 504#define MV_PCIE_BAR_MAX 3 505 506#define WIN_REG_IDX_RD(pre,reg,off,base) \ 507 static __inline uint32_t \ 508 pre ## _ ## reg ## _read(int i) \ 509 { \ 510 return (bus_space_read_4(obio_tag, base, off(i))); \ 511 } 512 513#define WIN_REG_BASE_IDX_RD(pre,reg,off) \ 514 static __inline uint32_t \ 515 pre ## _ ## reg ## _read(uint32_t base, int i) \ 516 { \ 517 return (bus_space_read_4(obio_tag, base, off(i))); \ 518 } 519 520#define WIN_REG_IDX_WR(pre,reg,off,base) \ 521 static __inline void \ 522 pre ## _ ## reg ## _write(int i, uint32_t val) \ 523 { \ 524 bus_space_write_4(obio_tag, base, off(i), val); \ 525 } 526 527#define WIN_REG_BASE_IDX_WR(pre,reg,off) \ 528 static __inline void \ 529 pre ## _ ## reg ## _write(uint32_t base, int i, uint32_t val) \ 530 { \ 531 bus_space_write_4(obio_tag, base, off(i), val); \ 532 } 533 534#define WIN_REG_RD(pre,reg,off,base) \ 535 static __inline uint32_t \ 536 pre ## _ ## reg ## _read(void) \ 537 { \ 538 return (bus_space_read_4(obio_tag, base, off)); \ 539 } 540 541#define WIN_REG_BASE_RD(pre,reg,off) \ 542 static __inline uint32_t \ 543 pre ## _ ## reg ## _read(uint32_t base) \ 544 { \ 545 return (bus_space_read_4(obio_tag, base, off)); \ 546 } 547 548#define WIN_REG_WR(pre,reg,off,base) \ 549 static __inline void \ 550 pre ## _ ## reg ## _write(uint32_t val) \ 551 { \ 552 bus_space_write_4(obio_tag, base, off, val); \ 553 } 554 555#define WIN_REG_BASE_WR(pre,reg,off) \ 556 static __inline void \ 557 pre ## _ ## reg ## _write(uint32_t base, uint32_t val) \ 558 { \ 559 bus_space_write_4(obio_tag, base, off, val); \ 560 } 561 562#endif /* _MVREG_H_ */ 563