mvreg.h revision 183840
1183840Sraj/*- 2183840Sraj * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD. 3183840Sraj * All rights reserved. 4183840Sraj * 5183840Sraj * Developed by Semihalf. 6183840Sraj * 7183840Sraj * Redistribution and use in source and binary forms, with or without 8183840Sraj * modification, are permitted provided that the following conditions 9183840Sraj * are met: 10183840Sraj * 1. Redistributions of source code must retain the above copyright 11183840Sraj * notice, this list of conditions and the following disclaimer. 12183840Sraj * 2. Redistributions in binary form must reproduce the above copyright 13183840Sraj * notice, this list of conditions and the following disclaimer in the 14183840Sraj * documentation and/or other materials provided with the distribution. 15183840Sraj * 3. Neither the name of MARVELL nor the names of contributors 16183840Sraj * may be used to endorse or promote products derived from this software 17183840Sraj * without specific prior written permission. 18183840Sraj * 19183840Sraj * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20183840Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21183840Sraj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22183840Sraj * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23183840Sraj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24183840Sraj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25183840Sraj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26183840Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27183840Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28183840Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29183840Sraj * SUCH DAMAGE. 30183840Sraj * 31183840Sraj * $FreeBSD: head/sys/arm/mv/mvreg.h 183840 2008-10-13 20:07:13Z raj $ 32183840Sraj */ 33183840Sraj 34183840Sraj#ifndef _MVREG_H_ 35183840Sraj#define _MVREG_H_ 36183840Sraj 37183840Sraj#include <machine/intr.h> 38183840Sraj 39183840Sraj/* 40183840Sraj * Physical addresses of integrated SoC peripherals 41183840Sraj */ 42183840Sraj#define MV_PHYS_BASE 0xF1000000 43183840Sraj#define MV_SIZE 0x100000 44183840Sraj 45183840Sraj/* 46183840Sraj * Decode windows addresses (physical) 47183840Sraj */ 48183840Sraj#define MV_PCIE_IO_PHYS_BASE (MV_PHYS_BASE + MV_SIZE) 49183840Sraj#define MV_PCIE_IO_BASE MV_PCIE_IO_PHYS_BASE 50183840Sraj#define MV_PCIE_IO_SIZE (1024 * 1024) 51183840Sraj#define MV_PCI_IO_PHYS_BASE (MV_PCIE_IO_PHYS_BASE + MV_PCIE_IO_SIZE) 52183840Sraj#define MV_PCI_IO_BASE MV_PCI_IO_PHYS_BASE 53183840Sraj#define MV_PCI_IO_SIZE (1024 * 1024) 54183840Sraj 55183840Sraj#define MV_PCIE_MEM_PHYS_BASE (MV_PCI_IO_PHYS_BASE + MV_PCI_IO_SIZE) 56183840Sraj#define MV_PCIE_MEM_BASE MV_PCIE_MEM_PHYS_BASE 57183840Sraj#define MV_PCIE_MEM_SIZE (64 * 1024 * 1024) 58183840Sraj#define MV_PCI_MEM_PHYS_BASE (MV_PCIE_MEM_PHYS_BASE + MV_PCIE_MEM_SIZE) 59183840Sraj#define MV_PCI_MEM_BASE MV_PCI_MEM_PHYS_BASE 60183840Sraj#define MV_PCI_MEM_SIZE (64 * 1024 * 1024) 61183840Sraj 62183840Sraj/* XXX DEV_BOOT, CSx are board specific, should be defined per platform */ 63183840Sraj 64183840Sraj/* 512KB NOR FLASH */ 65183840Sraj#define MV_DEV_BOOT_PHYS_BASE (MV_PCI_MEM_PHYS_BASE + MV_PCI_MEM_SIZE) 66183840Sraj#define MV_DEV_BOOT_SIZE (512 * 1024) 67183840Sraj/* CS0: 7-seg LED */ 68183840Sraj#define MV_DEV_CS0_PHYS_BASE 0xFA000000 69183840Sraj#define MV_DEV_CS0_SIZE (1024 * 1024) /* XXX u-boot has 2MB */ 70183840Sraj/* CS1: 32MB NOR FLASH */ 71183840Sraj#define MV_DEV_CS1_PHYS_BASE (MV_DEV_CS0_PHYS_BASE + MV_DEV_CS0_SIZE) 72183840Sraj#define MV_DEV_CS1_SIZE (32 * 1024 * 1024) 73183840Sraj/* CS2: 32MB NAND FLASH */ 74183840Sraj#define MV_DEV_CS2_PHYS_BASE (MV_DEV_CS1_PHYS_BASE + MV_DEV_CS1_SIZE) 75183840Sraj#define MV_DEV_CS2_SIZE 1024 /* XXX u-boot has 1MB */ 76183840Sraj 77183840Sraj/* XXX this is probably not robust against wraparounds... */ 78183840Sraj#if ((MV_DEV_CS2_PHYS_BASE + MV_DEV_CS2_SIZE) > 0xFFFEFFFF) 79183840Sraj#error Devices memory layout overlaps reset vectors range! 80183840Sraj#endif 81183840Sraj 82183840Sraj/* 83183840Sraj * Integrated SoC peripherals addresses 84183840Sraj */ 85183840Sraj#define MV_BASE MV_PHYS_BASE /* VA == PA mapping */ 86183840Sraj#define MV_DDR_CADR_BASE (MV_BASE + 0x1500) 87183840Sraj#define MV_MPP_BASE (MV_BASE + 0x10000) 88183840Sraj#define MV_GPIO_BASE (MV_BASE + 0x10100) 89183840Sraj#define MV_GPIO_SIZE 0x20 90183840Sraj#define MV_RTC_BASE (MV_BASE + 0x10300) 91183840Sraj#define MV_RTC_SIZE 0x08 92183840Sraj#define MV_TWSI_BASE (MV_BASE + 0x11000) 93183840Sraj#define MV_TWSI_SIZE 0x20 94183840Sraj#define MV_UART0_BASE (MV_BASE + 0x12000) 95183840Sraj#define MV_UART1_BASE (MV_BASE + 0x12100) 96183840Sraj#define MV_UART_SIZE 0x20 97183840Sraj#define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000) 98183840Sraj#define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80) 99183840Sraj#define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x100) 100183840Sraj#define MV_IC_BASE (MV_MBUS_BRIDGE_BASE + 0x200) 101183840Sraj#define MV_IC_SIZE 0x3C 102183840Sraj#define MV_TIMERS_BASE (MV_MBUS_BRIDGE_BASE + 0x300) 103183840Sraj#define MV_TIMERS_SIZE 0x30 104183840Sraj#define MV_PCI_BASE (MV_BASE + 0x30000) 105183840Sraj#define MV_PCI_SIZE 0x2000 106183840Sraj#define MV_PCIE_BASE (MV_BASE + 0x40000) 107183840Sraj#define MV_PCIE_SIZE 0x2000 108183840Sraj#define MV_USB0_BASE (MV_BASE + 0x50000) 109183840Sraj#define MV_USB1_BASE (MV_USB0_BASE + 0x1000) 110183840Sraj#define MV_USB2_BASE (MV_USB0_BASE + 0x2000) 111183840Sraj#define MV_USB_SIZE 0x1000 112183840Sraj#define MV_USB_HOST_OFST 0x0100 /* EHCI HC regs start at this offset within USB range */ 113183840Sraj#define MV_USB_AWR_BASE (MV_USB0_BASE + 0x320) 114183840Sraj#define MV_IDMA_BASE (MV_BASE + 0x60000) 115183840Sraj#define MV_IDMA_SIZE 0x1000 116183840Sraj#define MV_XOR_BASE (MV_BASE + 0x60000) 117183840Sraj#define MV_XOR_SIZE 0x1000 118183840Sraj#define MV_ETH0_BASE (MV_BASE + 0x72000) 119183840Sraj#define MV_ETH1_BASE (MV_BASE + 0x76000) 120183840Sraj#define MV_ETH_SIZE 0x2000 121183840Sraj 122183840Sraj#define MV_DEV_CS0_BASE MV_DEV_CS0_PHYS_BASE 123183840Sraj 124183840Sraj/* 125183840Sraj * Interrupt sources 126183840Sraj */ 127183840Sraj#if defined(SOC_MV_ORION) 128183840Sraj 129183840Sraj#define MV_INT_BRIDGE 0 /* AHB-MBus Bridge Interrupt */ 130183840Sraj#define MV_INT_UART0 3 /* UART0 Interrupt */ 131183840Sraj#define MV_INT_UART1 4 132183840Sraj#define MV_INT_GPIO7_0 6 /* GPIO[7:0] Interrupt */ 133183840Sraj#define MV_INT_GPIO15_8 7 /* GPIO[15:8] Interrupt */ 134183840Sraj#define MV_INT_GPIO23_16 8 /* GPIO[23:16] Interrupt */ 135183840Sraj#define MV_INT_GPIO31_24 9 /* GPIO[31:24] Interrupt */ 136183840Sraj#define MV_INT_PEX0_ERR 10 /* PCI Express Error */ 137183840Sraj#define MV_INT_PEX0 11 /* PCI Express INTA,B,C,D Message */ 138183840Sraj#define MV_INT_PCI_ERR 15 /* PCI Error */ 139183840Sraj#define MV_INT_USB_BERR 16 /* USB Bridge Error */ 140183840Sraj#define MV_INT_USB_CI 17 /* USB Controller interrupt */ 141183840Sraj#define MV_INT_GBERX 18 /* GbE receive interrupt */ 142183840Sraj#define MV_INT_GBETX 19 /* GbE transmit interrupt */ 143183840Sraj#define MV_INT_GBEMISC 20 /* GbE misc. interrupt */ 144183840Sraj#define MV_INT_GBESUM 21 /* GbE summary interrupt */ 145183840Sraj#define MV_INT_GBEERR 22 /* GbE error interrupt */ 146183840Sraj#define MV_INT_IDMA_ERR 23 /* DMA error interrupt */ 147183840Sraj#define MV_INT_IDMA0 24 /* IDMA chan. 0 completion interrupt */ 148183840Sraj#define MV_INT_IDMA1 25 /* IDMA chan. 1 completion interrupt */ 149183840Sraj#define MV_INT_IDMA2 26 /* IDMA chan. 2 completion interrupt */ 150183840Sraj#define MV_INT_IDMA3 27 /* IDMA chan. 3 completion interrupt */ 151183840Sraj#define MV_INT_SATA 29 /* Serial-ATA Interrupt */ 152183840Sraj 153183840Sraj#elif defined(SOC_MV_KIRKWOOD) 154183840Sraj 155183840Sraj#define MV_INT_BRIDGE 1 /* AHB-MBus Bridge Interrupt */ 156183840Sraj#define MV_INT_XOR0_CHAN0 5 /* XOR engine 0 channel 0 Interrupt */ 157183840Sraj#define MV_INT_XOR0_CHAN1 6 /* XOR engine 0 channel 1 Interrupt */ 158183840Sraj#define MV_INT_XOR1_CHAN0 7 /* XOR engine 1 channel 0 Interrupt */ 159183840Sraj#define MV_INT_XOR1_CHAN1 8 /* XOR engine 1 channel 1 Interrupt */ 160183840Sraj#define MV_INT_PEX0 9 /* PCI Express INTA,B,C,D Message */ 161183840Sraj#define MV_INT_GBESUM 11 /* GbE0 summary interrupt */ 162183840Sraj#define MV_INT_GBERX 12 /* GbE0 receive interrupt */ 163183840Sraj#define MV_INT_GBETX 13 /* GbE0 transmit interrupt */ 164183840Sraj#define MV_INT_GBEMISC 14 /* GbE0 misc. interrupt */ 165183840Sraj#define MV_INT_GBE1SUM 15 /* GbE1 summary interrupt */ 166183840Sraj#define MV_INT_GBE1RX 16 /* GbE1 receive interrupt */ 167183840Sraj#define MV_INT_GBE1TX 17 /* GbE1 transmit interrupt */ 168183840Sraj#define MV_INT_GBE1MISC 18 /* GbE1 misc. interrupt */ 169183840Sraj#define MV_INT_USB_CI 19 /* USB Controller interrupt */ 170183840Sraj#define MV_INT_SATA 21 /* Serial-ATA Interrupt */ 171183840Sraj#define MV_INT_IDMA_ERR 23 /* DMA error interrupt */ 172183840Sraj#define MV_INT_UART0 33 /* UART0 Interrupt */ 173183840Sraj#define MV_INT_UART1 34 174183840Sraj#define MV_INT_GPIO7_0 35 /* GPIO[7:0] Interrupt */ 175183840Sraj#define MV_INT_GPIO15_8 36 /* GPIO[15:8] Interrupt */ 176183840Sraj#define MV_INT_GPIO23_16 37 /* GPIO[23:16] Interrupt */ 177183840Sraj#define MV_INT_GPIO31_24 38 /* GPIO[31:24] Interrupt */ 178183840Sraj#define MV_INT_GPIOHI7_0 39 /* GPIOHI[7:0] Interrupt */ 179183840Sraj#define MV_INT_GPIOHI15_8 40 /* GPIOHI[15:8] Interrupt */ 180183840Sraj#define MV_INT_GPIOHI23_16 41 /* GPIOHI[23:16] Interrupt */ 181183840Sraj#define MV_INT_XOR0_ERR 42 /* XOR engine 0 error Interrupt */ 182183840Sraj#define MV_INT_XOR1_ERR 43 /* XOR engine 1 error Interrupt */ 183183840Sraj#define MV_INT_PEX0_ERR 44 /* PCI Express Error */ 184183840Sraj#define MV_INT_GBEERR 46 /* GbE0 error interrupt */ 185183840Sraj#define MV_INT_GBE1ERR 47 /* GbE1 error interrupt */ 186183840Sraj#define MV_INT_USB_BERR 48 /* USB Bridge Error */ 187183840Sraj 188183840Sraj#elif defined(SOC_MV_DISCOVERY) 189183840Sraj 190183840Sraj#define MV_INT_ERRSUM 0 /* Summary of error interrupts */ 191183840Sraj#define MV_INT_SPI 1 /* SPI interrupt */ 192183840Sraj#define MV_INT_TWSI0 2 /* TWSI0 interrupt */ 193183840Sraj#define MV_INT_TWSI1 3 /* TWSI1 interrupt */ 194183840Sraj#define MV_INT_IDMA0 4 /* IDMA Channel0 completion */ 195183840Sraj#define MV_INT_IDMA1 5 /* IDMA Channel0 completion */ 196183840Sraj#define MV_INT_IDMA2 6 /* IDMA Channel0 completion */ 197183840Sraj#define MV_INT_IDMA3 7 /* IDMA Channel0 completion */ 198183840Sraj#define MV_INT_TIMER0 8 /* Timer0 interrupt */ 199183840Sraj#define MV_INT_TIMER1 9 /* Timer1 interrupt */ 200183840Sraj#define MV_INT_TIMER2 10 /* Timer2 interrupt */ 201183840Sraj#define MV_INT_TIMER3 11 /* Timer3 interrupt */ 202183840Sraj#define MV_INT_UART0 12 /* UART0 interrupt */ 203183840Sraj#define MV_INT_UART1 13 /* UART1 interrupt */ 204183840Sraj#define MV_INT_UART2 14 /* UART2 interrupt */ 205183840Sraj#define MV_INT_UART3 15 /* UART3 interrupt */ 206183840Sraj#define MV_INT_USB0 16 /* USB0 interrupt */ 207183840Sraj#define MV_INT_USB1 17 /* USB1 interrupt */ 208183840Sraj#define MV_INT_USB2 18 /* USB2 interrupt */ 209183840Sraj#define MV_INT_CRYPTO 19 /* Crypto engine completion interrupt */ 210183840Sraj#define MV_INT_XOR0 22 /* XOR engine 0 completion interrupt */ 211183840Sraj#define MV_INT_XOR1 23 /* XOR engine 1 completion interrupt */ 212183840Sraj#define MV_INT_SATA 26 /* SATA interrupt */ 213183840Sraj#define MV_INT_PEX00 32 /* PCI Express port 0.0 INTA/B/C/D */ 214183840Sraj#define MV_INT_PEX01 33 /* PCI Express port 0.1 INTA/B/C/D */ 215183840Sraj#define MV_INT_PEX02 34 /* PCI Express port 0.2 INTA/B/C/D */ 216183840Sraj#define MV_INT_PEX03 35 /* PCI Express port 0.3 INTA/B/C/D */ 217183840Sraj#define MV_INT_PEX10 36 /* PCI Express port 1.0 INTA/B/C/D */ 218183840Sraj#define MV_INT_PEX11 37 /* PCI Express port 1.1 INTA/B/C/D */ 219183840Sraj#define MV_INT_PEX12 38 /* PCI Express port 1.2 INTA/B/C/D */ 220183840Sraj#define MV_INT_PEX13 39 /* PCI Express port 1.3 INTA/B/C/D */ 221183840Sraj#define MV_INT_GBESUM 40 /* Gigabit Ethernet Port 0 summary */ 222183840Sraj#define MV_INT_GBERX 41 /* Gigabit Ethernet Port 0 Rx summary */ 223183840Sraj#define MV_INT_GBETX 42 /* Gigabit Ethernet Port 0 Tx summary */ 224183840Sraj#define MV_INT_GBEMISC 43 /* Gigabit Ethernet Port 0 Misc summ. */ 225183840Sraj#define MV_INT_GBE1SUM 44 /* Gigabit Ethernet Port 1 summary */ 226183840Sraj#define MV_INT_GBE1RX 45 /* Gigabit Ethernet Port 1 Rx summary */ 227183840Sraj#define MV_INT_GBE1TX 46 /* Gigabit Ethernet Port 1 Tx summary */ 228183840Sraj#define MV_INT_GBE1MISC 47 /* Gigabit Ethernet Port 1 Misc summ. */ 229183840Sraj#define MV_INT_GPIO7_0 56 /* GPIO[7:0] Interrupt */ 230183840Sraj#define MV_INT_GPIO15_8 57 /* GPIO[15:8] Interrupt */ 231183840Sraj#define MV_INT_GPIO23_16 58 /* GPIO[23:16] Interrupt */ 232183840Sraj#define MV_INT_GPIO31_24 59 /* GPIO[31:24] Interrupt */ 233183840Sraj#define MV_INT_DB_IN 60 /* Inbound Doorbell Cause reg Summary */ 234183840Sraj#define MV_INT_DB_OUT 61 /* Outbound Doorbell Cause reg Summ. */ 235183840Sraj#define MV_INT_CRYPT_ERR 64 /* Crypto engine error */ 236183840Sraj#define MV_INT_DEV_ERR 65 /* Device bus error */ 237183840Sraj#define MV_INT_IDMA_ERR 66 /* DMA error */ 238183840Sraj#define MV_INT_CPU_ERR 67 /* CPU error */ 239183840Sraj#define MV_INT_PEX0_ERR 68 /* PCI-Express port0 error */ 240183840Sraj#define MV_INT_PEX1_ERR 69 /* PCI-Express port1 error */ 241183840Sraj#define MV_INT_GBE_ERR 70 /* Gigabit Ethernet error */ 242183840Sraj#define MV_INT_USB_ERR 72 /* USB error */ 243183840Sraj#define MV_INT_DRAM_ERR 73 /* DRAM ECC error */ 244183840Sraj#define MV_INT_XOR_ERR 74 /* XOR engine error */ 245183840Sraj#define MV_INT_WD 79 /* WD Timer interrupt */ 246183840Sraj 247183840Sraj#endif /* SOC_MV_ORION */ 248183840Sraj 249183840Sraj#define BRIDGE_IRQ_CAUSE 0x10 250183840Sraj#define BRIGDE_IRQ_MASK 0x14 251183840Sraj 252183840Sraj#if defined(SOC_MV_DISCOVERY) 253183840Sraj#define IRQ_CAUSE_ERROR 0x0 254183840Sraj#define IRQ_CAUSE 0x4 255183840Sraj#define IRQ_CAUSE_HI 0x8 256183840Sraj#define IRQ_MASK_ERROR 0xC 257183840Sraj#define IRQ_MASK 0x10 258183840Sraj#define IRQ_MASK_HI 0x14 259183840Sraj#define IRQ_CAUSE_SELECT 0x18 260183840Sraj#define FIQ_MASK_ERROR 0x1C 261183840Sraj#define FIQ_MASK 0x20 262183840Sraj#define FIQ_MASK_HI 0x24 263183840Sraj#define FIQ_CAUSE_SELECT 0x28 264183840Sraj#define ENDPOINT_IRQ_MASK_ERROR 0x2C 265183840Sraj#define ENDPOINT_IRQ_MASK 0x30 266183840Sraj#define ENDPOINT_IRQ_MASK_HI 0x34 267183840Sraj#define ENDPOINT_IRQ_CAUSE_SELECT 0x38 268183840Sraj#else /* !SOC_MV_DISCOVERY */ 269183840Sraj#define IRQ_CAUSE 0x0 270183840Sraj#define IRQ_MASK 0x4 271183840Sraj#define FIQ_MASK 0x8 272183840Sraj#define ENDPOINT_IRQ_MASK 0xC 273183840Sraj#define IRQ_CAUSE_HI 0x10 274183840Sraj#define IRQ_MASK_HI 0x14 275183840Sraj#define FIQ_MASK_HI 0x18 276183840Sraj#define ENDPOINT_IRQ_MASK_HI 0x1C 277183840Sraj#define IRQ_CAUSE_ERROR (-1) /* Fake defines for unified */ 278183840Sraj#define IRQ_MASK_ERROR (-1) /* interrupt controller code */ 279183840Sraj#endif 280183840Sraj 281183840Sraj#define BRIDGE_IRQ_CAUSE 0x10 282183840Sraj#define IRQ_CPU_SELF 0x00000001 283183840Sraj#define IRQ_TIMER0 0x00000002 284183840Sraj#define IRQ_TIMER1 0x00000004 285183840Sraj#define IRQ_TIMER_WD 0x00000008 286183840Sraj 287183840Sraj#define BRIDGE_IRQ_MASK 0x14 288183840Sraj#define IRQ_CPU_MASK 0x00000001 289183840Sraj#define IRQ_TIMER0_MASK 0x00000002 290183840Sraj#define IRQ_TIMER1_MASK 0x00000004 291183840Sraj#define IRQ_TIMER_WD_MASK 0x00000008 292183840Sraj 293183840Sraj/* 294183840Sraj * System reset 295183840Sraj */ 296183840Sraj#define RSTOUTn_MASK 0x8 297183840Sraj#define WD_RST_OUT_EN 0x00000002 298183840Sraj#define SOFT_RST_OUT_EN 0x00000004 299183840Sraj#define SYSTEM_SOFT_RESET 0xc 300183840Sraj#define SYS_SOFT_RST 0x00000001 301183840Sraj 302183840Sraj/* 303183840Sraj * Power Control 304183840Sraj */ 305183840Sraj#define CPU_PM_CTRL 0x1C 306183840Sraj#define CPU_PM_CTRL_NONE 0 307183840Sraj 308183840Sraj#if defined(SOC_MV_KIRKWOOD) 309183840Sraj#define CPU_PM_CTRL_GE0 (1 << 0) 310183840Sraj#define CPU_PM_CTRL_PEX0_PHY (1 << 1) 311183840Sraj#define CPU_PM_CTRL_PEX0 (1 << 2) 312183840Sraj#define CPU_PM_CTRL_USB0 (1 << 3) 313183840Sraj#define CPU_PM_CTRL_SDIO (1 << 4) 314183840Sraj#define CPU_PM_CTRL_TSU (1 << 5) 315183840Sraj#define CPU_PM_CTRL_DUNIT (1 << 6) 316183840Sraj#define CPU_PM_CTRL_RUNIT (1 << 7) 317183840Sraj#define CPU_PM_CTRL_XOR0 (1 << 8) 318183840Sraj#define CPU_PM_CTRL_AUDIO (1 << 9) 319183840Sraj#define CPU_PM_CTRL_SATA0 (1 << 14) 320183840Sraj#define CPU_PM_CTRL_SATA1 (1 << 15) 321183840Sraj#define CPU_PM_CTRL_XOR1 (1 << 16) 322183840Sraj#define CPU_PM_CTRL_CRYPTO (1 << 17) 323183840Sraj#define CPU_PM_CTRL_GE1 (1 << 18) 324183840Sraj#define CPU_PM_CTRL_TDM (1 << 19) 325183840Sraj#elif defined(SOC_MV_DISCOVERY) 326183840Sraj#define CPU_PM_CTRL_GE0 (1 << 1) 327183840Sraj#define CPU_PM_CTRL_GE1 (1 << 2) 328183840Sraj#define CPU_PM_CTRL_PEX00 (1 << 5) 329183840Sraj#define CPU_PM_CTRL_PEX01 (1 << 6) 330183840Sraj#define CPU_PM_CTRL_PEX02 (1 << 7) 331183840Sraj#define CPU_PM_CTRL_PEX03 (1 << 8) 332183840Sraj#define CPU_PM_CTRL_PEX10 (1 << 9) 333183840Sraj#define CPU_PM_CTRL_PEX11 (1 << 10) 334183840Sraj#define CPU_PM_CTRL_PEX12 (1 << 11) 335183840Sraj#define CPU_PM_CTRL_PEX13 (1 << 12) 336183840Sraj#define CPU_PM_CTRL_SATA0_PHY (1 << 13) 337183840Sraj#define CPU_PM_CTRL_SATA0 (1 << 14) 338183840Sraj#define CPU_PM_CTRL_SATA1_PHY (1 << 15) 339183840Sraj#define CPU_PM_CTRL_SATA1 (1 << 16) 340183840Sraj#define CPU_PM_CTRL_USB0 (1 << 17) 341183840Sraj#define CPU_PM_CTRL_USB1 (1 << 18) 342183840Sraj#define CPU_PM_CTRL_USB2 (1 << 19) 343183840Sraj#define CPU_PM_CTRL_IDMA (1 << 20) 344183840Sraj#define CPU_PM_CTRL_XOR (1 << 21) 345183840Sraj#define CPU_PM_CTRL_CRYPTO (1 << 22) 346183840Sraj#define CPU_PM_CTRL_DEVICE (1 << 23) 347183840Sraj#endif 348183840Sraj 349183840Sraj/* 350183840Sraj * Timers 351183840Sraj */ 352183840Sraj#define CPU_TIMER_CONTROL 0x0 353183840Sraj#define CPU_TIMER0_EN 0x00000001 354183840Sraj#define CPU_TIMER0_AUTO 0x00000002 355183840Sraj#define CPU_TIMER1_EN 0x00000004 356183840Sraj#define CPU_TIMER1_AUTO 0x00000008 357183840Sraj#define CPU_TIMER_WD_EN 0x00000010 358183840Sraj#define CPU_TIMER_WD_AUTO 0x00000020 359183840Sraj#define CPU_TIMER0_REL 0x10 360183840Sraj#define CPU_TIMER0 0x14 361183840Sraj 362183840Sraj/* 363183840Sraj * GPIO 364183840Sraj */ 365183840Sraj#define GPIO_DATA_OUT 0x00 366183840Sraj#define GPIO_DATA_OUT_EN_CTRL 0x04 367183840Sraj#define GPIO_BLINK_EN 0x08 368183840Sraj#define GPIO_DATA_IN_POLAR 0x0c 369183840Sraj#define GPIO_DATA_IN 0x10 370183840Sraj#define GPIO_INT_CAUSE 0x14 371183840Sraj#define GPIO_INT_EDGE_MASK 0x18 372183840Sraj#define GPIO_INT_LEV_MASK 0x1c 373183840Sraj 374183840Sraj#define GPIO_HI_DATA_OUT 0x40 375183840Sraj#define GPIO_HI_DATA_OUT_EN_CTRL 0x44 376183840Sraj#define GPIO_HI_BLINK_EN 0x48 377183840Sraj#define GPIO_HI_DATA_IN_POLAR 0x4c 378183840Sraj#define GPIO_HI_DATA_IN 0x50 379183840Sraj#define GPIO_HI_INT_CAUSE 0x54 380183840Sraj#define GPIO_HI_INT_EDGE_MASK 0x58 381183840Sraj#define GPIO_HI_INT_LEV_MASK 0x5c 382183840Sraj 383183840Sraj#define GPIO(n) (1 << (n)) 384183840Sraj#define MV_GPIO_MAX_NPINS 64 385183840Sraj 386183840Sraj#define MV_GPIO_BLINK 0x1 387183840Sraj#define MV_GPIO_POLARITY 0x2 388183840Sraj#define MV_GPIO_EDGE 0x4 389183840Sraj#define MV_GPIO_LEVEL 0x8 390183840Sraj 391183840Sraj#define IS_GPIO_IRQ(irq) ((irq) >= NIRQ && (irq) < NIRQ + MV_GPIO_MAX_NPINS) 392183840Sraj#define GPIO2IRQ(gpio) ((gpio) + NIRQ) 393183840Sraj#define IRQ2GPIO(irq) ((irq) - NIRQ) 394183840Sraj 395183840Sraj/* 396183840Sraj * MPP 397183840Sraj */ 398183840Sraj#define MPP_CONTROL0 0x00 399183840Sraj#define MPP_CONTROL1 0x04 400183840Sraj#define MPP_CONTROL2 0x50 401183840Sraj#define DEVICE_MULTIPLEX 0x08 402183840Sraj 403183840Sraj#if defined(SOC_MV_ORION) 404183840Sraj#define SAMPLE_AT_RESET 0x10 405183840Sraj#elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) 406183840Sraj#define SAMPLE_AT_RESET 0x30 407183840Sraj#else 408183840Sraj#error SOC_MV_XX not defined 409183840Sraj#endif 410183840Sraj 411183840Sraj/* 412183840Sraj * Clocks 413183840Sraj */ 414183840Sraj#ifdef SOC_MV_ORION 415183840Sraj#define TCLK_MASK 0x300 416183840Sraj#define TCLK_SHIFT 0x8 417183840Sraj#elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) 418183840Sraj#define TCLK_MASK 0x30000 419183840Sraj#define TCLK_SHIFT 0x10 420183840Sraj#else 421183840Sraj#error SOC_MV_XX not defined 422183840Sraj#endif 423183840Sraj 424183840Sraj#define TCLK_100MHZ 100000000 425183840Sraj#define TCLK_125MHZ 125000000 426183840Sraj#define TCLK_133MHZ 133333333 427183840Sraj#define TCLK_150MHZ 150000000 428183840Sraj#define TCLK_166MHZ 166666667 429183840Sraj#define TCLK_200MHZ 200000000 430183840Sraj 431183840Sraj/* 432183840Sraj * Chip ID 433183840Sraj */ 434183840Sraj#define MV_DEV_88F5181 0x5181 435183840Sraj#define MV_DEV_88F5182 0x5182 436183840Sraj#define MV_DEV_88F5281 0x5281 437183840Sraj#define MV_DEV_88F6281 0x6281 438183840Sraj#define MV_DEV_MV78100 0x6381 439183840Sraj 440183840Sraj/* 441183840Sraj * Decode windows definitions and macros 442183840Sraj */ 443183840Sraj#define MV_WIN_CPU_CTRL(n) (0x10 * (n) + (((n) < 8) ? 0x000 : 0x880)) 444183840Sraj#define MV_WIN_CPU_BASE(n) (0x10 * (n) + (((n) < 8) ? 0x004 : 0x884)) 445183840Sraj#define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888)) 446183840Sraj#define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C)) 447183840Sraj#if defined(SOC_MV_DISCOVERY) 448183840Sraj#define MV_WIN_CPU_MAX 14 449183840Sraj#else 450183840Sraj#define MV_WIN_CPU_MAX 8 451183840Sraj#endif 452183840Sraj 453183840Sraj#define MV_WIN_DDR_BASE(n) (0x8 * (n) + 0x0) 454183840Sraj#define MV_WIN_DDR_SIZE(n) (0x8 * (n) + 0x4) 455183840Sraj#define MV_WIN_DDR_MAX 4 456183840Sraj 457183840Sraj#define MV_WIN_USB_CTRL(n) (0x10 * (n) + 0x0) 458183840Sraj#define MV_WIN_USB_BASE(n) (0x10 * (n) + 0x4) 459183840Sraj#define MV_WIN_USB_MAX 4 460183840Sraj 461183840Sraj#define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200) 462183840Sraj#define MV_WIN_ETH_SIZE(n) (0x8 * (n) + 0x204) 463183840Sraj#define MV_WIN_ETH_REMAP(n) (0x4 * (n) + 0x280) 464183840Sraj#define MV_WIN_ETH_MAX 6 465183840Sraj 466183840Sraj#define MV_WIN_IDMA_BASE(n) (0x8 * (n) + 0xa00) 467183840Sraj#define MV_WIN_IDMA_SIZE(n) (0x8 * (n) + 0xa04) 468183840Sraj#define MV_WIN_IDMA_REMAP(n) (0x4 * (n) + 0xa60) 469183840Sraj#define MV_WIN_IDMA_CAP(n) (0x4 * (n) + 0xa70) 470183840Sraj#define MV_WIN_IDMA_MAX 8 471183840Sraj#define MV_IDMA_CHAN_MAX 4 472183840Sraj 473183840Sraj#define MV_WIN_PCIE_CTRL(n) (0x10 * (((n) < 5) ? (n) : \ 474183840Sraj (n) + 1) + 0x1820) 475183840Sraj#define MV_WIN_PCIE_BASE(n) (0x10 * (((n) < 5) ? (n) : \ 476183840Sraj (n) + 1) + 0x1824) 477183840Sraj#define MV_WIN_PCIE_REMAP(n) (0x10 * (((n) < 5) ? (n) : \ 478183840Sraj (n) + 1) + 0x182C) 479183840Sraj#define MV_WIN_PCIE_MAX 6 480183840Sraj 481183840Sraj#define MV_PCIE_BAR(n) (0x04 * (n) + 0x1804) 482183840Sraj#define MV_PCIE_BAR_MAX 3 483183840Sraj 484183840Sraj#define WIN_REG_IDX_RD(pre,reg,off,base) \ 485183840Sraj static __inline uint32_t \ 486183840Sraj pre ## _ ## reg ## _read(int i) \ 487183840Sraj { \ 488183840Sraj return (bus_space_read_4(obio_tag, base, off(i))); \ 489183840Sraj } 490183840Sraj 491183840Sraj#define WIN_REG_BASE_IDX_RD(pre,reg,off) \ 492183840Sraj static __inline uint32_t \ 493183840Sraj pre ## _ ## reg ## _read(uint32_t base, int i) \ 494183840Sraj { \ 495183840Sraj return (bus_space_read_4(obio_tag, base, off(i))); \ 496183840Sraj } 497183840Sraj 498183840Sraj#define WIN_REG_IDX_WR(pre,reg,off,base) \ 499183840Sraj static __inline void \ 500183840Sraj pre ## _ ## reg ## _write(int i, uint32_t val) \ 501183840Sraj { \ 502183840Sraj bus_space_write_4(obio_tag, base, off(i), val); \ 503183840Sraj } 504183840Sraj 505183840Sraj#define WIN_REG_BASE_IDX_WR(pre,reg,off) \ 506183840Sraj static __inline void \ 507183840Sraj pre ## _ ## reg ## _write(uint32_t base, int i, uint32_t val) \ 508183840Sraj { \ 509183840Sraj bus_space_write_4(obio_tag, base, off(i), val); \ 510183840Sraj } 511183840Sraj 512183840Sraj#define WIN_REG_RD(pre,reg,off,base) \ 513183840Sraj static __inline uint32_t \ 514183840Sraj pre ## _ ## reg ## _read(void) \ 515183840Sraj { \ 516183840Sraj return (bus_space_read_4(obio_tag, base, off)); \ 517183840Sraj } 518183840Sraj 519183840Sraj#define WIN_REG_BASE_RD(pre,reg,off) \ 520183840Sraj static __inline uint32_t \ 521183840Sraj pre ## _ ## reg ## _read(uint32_t base) \ 522183840Sraj { \ 523183840Sraj return (bus_space_read_4(obio_tag, base, off)); \ 524183840Sraj } 525183840Sraj 526183840Sraj#define WIN_REG_WR(pre,reg,off,base) \ 527183840Sraj static __inline void \ 528183840Sraj pre ## _ ## reg ## _write(uint32_t val) \ 529183840Sraj { \ 530183840Sraj bus_space_write_4(obio_tag, base, off, val); \ 531183840Sraj } 532183840Sraj 533183840Sraj#define WIN_REG_BASE_WR(pre,reg,off) \ 534183840Sraj static __inline void \ 535183840Sraj pre ## _ ## reg ## _write(uint32_t base, uint32_t val) \ 536183840Sraj { \ 537183840Sraj bus_space_write_4(obio_tag, base, off, val); \ 538183840Sraj } 539183840Sraj 540183840Sraj#endif /* _MVREG_H_ */ 541