mv_pci.c revision 266128
1185089Sraj/*- 2209131Sraj * Copyright (c) 2008 MARVELL INTERNATIONAL LTD. 3209131Sraj * Copyright (c) 2010 The FreeBSD Foundation 4240489Sgber * Copyright (c) 2010-2012 Semihalf 5185089Sraj * All rights reserved. 6185089Sraj * 7185089Sraj * Developed by Semihalf. 8185089Sraj * 9209131Sraj * Portions of this software were developed by Semihalf 10209131Sraj * under sponsorship from the FreeBSD Foundation. 11209131Sraj * 12185089Sraj * Redistribution and use in source and binary forms, with or without 13185089Sraj * modification, are permitted provided that the following conditions 14185089Sraj * are met: 15185089Sraj * 1. Redistributions of source code must retain the above copyright 16185089Sraj * notice, this list of conditions and the following disclaimer. 17185089Sraj * 2. Redistributions in binary form must reproduce the above copyright 18185089Sraj * notice, this list of conditions and the following disclaimer in the 19185089Sraj * documentation and/or other materials provided with the distribution. 20185089Sraj * 3. Neither the name of MARVELL nor the names of contributors 21185089Sraj * may be used to endorse or promote products derived from this software 22185089Sraj * without specific prior written permission. 23185089Sraj * 24185089Sraj * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 25185089Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26185089Sraj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27185089Sraj * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 28185089Sraj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29185089Sraj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30185089Sraj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31185089Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32185089Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33185089Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34185089Sraj * SUCH DAMAGE. 35185089Sraj */ 36185089Sraj 37185089Sraj/* 38185089Sraj * Marvell integrated PCI/PCI-Express controller driver. 39185089Sraj */ 40185089Sraj 41185089Sraj#include <sys/cdefs.h> 42185089Sraj__FBSDID("$FreeBSD: stable/10/sys/arm/mv/mv_pci.c 266128 2014-05-15 14:26:11Z ian $"); 43185089Sraj 44185089Sraj#include <sys/param.h> 45185089Sraj#include <sys/systm.h> 46185089Sraj#include <sys/kernel.h> 47185089Sraj#include <sys/lock.h> 48185089Sraj#include <sys/malloc.h> 49185089Sraj#include <sys/module.h> 50185089Sraj#include <sys/mutex.h> 51185089Sraj#include <sys/queue.h> 52185089Sraj#include <sys/bus.h> 53185089Sraj#include <sys/rman.h> 54185089Sraj#include <sys/endian.h> 55185089Sraj 56266084Sian#include <machine/fdt.h> 57240493Sgber#include <machine/intr.h> 58240493Sgber 59185089Sraj#include <vm/vm.h> 60185089Sraj#include <vm/pmap.h> 61185089Sraj 62209131Sraj#include <dev/fdt/fdt_common.h> 63209131Sraj#include <dev/ofw/ofw_bus.h> 64266020Sian#include <dev/ofw/ofw_pci.h> 65209131Sraj#include <dev/ofw/ofw_bus_subr.h> 66185089Sraj#include <dev/pci/pcivar.h> 67185089Sraj#include <dev/pci/pcireg.h> 68185089Sraj#include <dev/pci/pcib_private.h> 69185089Sraj 70209131Sraj#include "ofw_bus_if.h" 71185089Sraj#include "pcib_if.h" 72185089Sraj 73266084Sian#include <machine/devmap.h> 74185089Sraj#include <machine/resource.h> 75185089Sraj#include <machine/bus.h> 76185089Sraj 77185089Sraj#include <arm/mv/mvreg.h> 78185089Sraj#include <arm/mv/mvvar.h> 79209131Sraj#include <arm/mv/mvwin.h> 80185089Sraj 81240493Sgber#ifdef DEBUG 82240493Sgber#define debugf(fmt, args...) do { printf(fmt,##args); } while (0) 83240493Sgber#else 84240493Sgber#define debugf(fmt, args...) 85240493Sgber#endif 86240493Sgber 87266084Sian/* 88266084Sian * Code and data related to fdt-based PCI configuration. 89266084Sian * 90266084Sian * This stuff used to be in dev/fdt/fdt_pci.c and fdt_common.h, but it was 91266084Sian * always Marvell-specific so that was deleted and the code now lives here. 92266084Sian */ 93266084Sian 94266084Sianstruct mv_pci_range { 95266084Sian u_long base_pci; 96266084Sian u_long base_parent; 97266084Sian u_long len; 98266084Sian}; 99266084Sian 100266084Sian#define FDT_RANGES_CELLS ((3 + 3 + 2) * 2) 101266084Sian 102266084Sianstatic void 103266084Sianmv_pci_range_dump(struct mv_pci_range *range) 104266084Sian{ 105266084Sian#ifdef DEBUG 106266084Sian printf("\n"); 107266084Sian printf(" base_pci = 0x%08lx\n", range->base_pci); 108266084Sian printf(" base_par = 0x%08lx\n", range->base_parent); 109266084Sian printf(" len = 0x%08lx\n", range->len); 110266084Sian#endif 111266084Sian} 112266084Sian 113266084Sianstatic int 114266084Sianmv_pci_ranges_decode(phandle_t node, struct mv_pci_range *io_space, 115266084Sian struct mv_pci_range *mem_space) 116266084Sian{ 117266084Sian pcell_t ranges[FDT_RANGES_CELLS]; 118266084Sian struct mv_pci_range *pci_space; 119266084Sian pcell_t addr_cells, size_cells, par_addr_cells; 120266084Sian pcell_t *rangesptr; 121266084Sian pcell_t cell0, cell1, cell2; 122266084Sian int tuple_size, tuples, i, rv, offset_cells, len; 123266084Sian 124266084Sian /* 125266084Sian * Retrieve 'ranges' property. 126266084Sian */ 127266084Sian if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0) 128266084Sian return (EINVAL); 129266084Sian if (addr_cells != 3 || size_cells != 2) 130266084Sian return (ERANGE); 131266084Sian 132266084Sian par_addr_cells = fdt_parent_addr_cells(node); 133266084Sian if (par_addr_cells > 3) 134266084Sian return (ERANGE); 135266084Sian 136266084Sian len = OF_getproplen(node, "ranges"); 137266084Sian if (len > sizeof(ranges)) 138266084Sian return (ENOMEM); 139266084Sian 140266084Sian if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0) 141266084Sian return (EINVAL); 142266084Sian 143266084Sian tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells + 144266084Sian size_cells); 145266084Sian tuples = len / tuple_size; 146266084Sian 147266084Sian /* 148266084Sian * Initialize the ranges so that we don't have to worry about 149266084Sian * having them all defined in the FDT. In particular, it is 150266084Sian * perfectly fine not to want I/O space on PCI busses. 151266084Sian */ 152266084Sian bzero(io_space, sizeof(*io_space)); 153266084Sian bzero(mem_space, sizeof(*mem_space)); 154266084Sian 155266084Sian rangesptr = &ranges[0]; 156266084Sian offset_cells = 0; 157266084Sian for (i = 0; i < tuples; i++) { 158266084Sian cell0 = fdt_data_get((void *)rangesptr, 1); 159266084Sian rangesptr++; 160266084Sian cell1 = fdt_data_get((void *)rangesptr, 1); 161266084Sian rangesptr++; 162266084Sian cell2 = fdt_data_get((void *)rangesptr, 1); 163266084Sian rangesptr++; 164266084Sian 165266084Sian if (cell0 & 0x02000000) { 166266084Sian pci_space = mem_space; 167266084Sian } else if (cell0 & 0x01000000) { 168266084Sian pci_space = io_space; 169266084Sian } else { 170266084Sian rv = ERANGE; 171266084Sian goto out; 172266084Sian } 173266084Sian 174266084Sian if (par_addr_cells == 3) { 175266084Sian /* 176266084Sian * This is a PCI subnode 'ranges'. Skip cell0 and 177266084Sian * cell1 of this entry and only use cell2. 178266084Sian */ 179266084Sian offset_cells = 2; 180266084Sian rangesptr += offset_cells; 181266084Sian } 182266084Sian 183266084Sian if (fdt_data_verify((void *)rangesptr, par_addr_cells - 184266084Sian offset_cells)) { 185266084Sian rv = ERANGE; 186266084Sian goto out; 187266084Sian } 188266084Sian pci_space->base_parent = fdt_data_get((void *)rangesptr, 189266084Sian par_addr_cells - offset_cells); 190266084Sian rangesptr += par_addr_cells - offset_cells; 191266084Sian 192266084Sian if (fdt_data_verify((void *)rangesptr, size_cells)) { 193266084Sian rv = ERANGE; 194266084Sian goto out; 195266084Sian } 196266084Sian pci_space->len = fdt_data_get((void *)rangesptr, size_cells); 197266084Sian rangesptr += size_cells; 198266084Sian 199266084Sian pci_space->base_pci = cell2; 200266084Sian } 201266084Sian rv = 0; 202266084Sianout: 203266084Sian return (rv); 204266084Sian} 205266084Sian 206266084Sianstatic int 207266084Sianmv_pci_ranges(phandle_t node, struct mv_pci_range *io_space, 208266084Sian struct mv_pci_range *mem_space) 209266084Sian{ 210266084Sian int err; 211266084Sian 212266084Sian debugf("Processing PCI node: %x\n", node); 213266084Sian if ((err = mv_pci_ranges_decode(node, io_space, mem_space)) != 0) { 214266084Sian debugf("could not decode parent PCI node 'ranges'\n"); 215266084Sian return (err); 216266084Sian } 217266084Sian 218266084Sian debugf("Post fixup dump:\n"); 219266084Sian mv_pci_range_dump(io_space); 220266084Sian mv_pci_range_dump(mem_space); 221266084Sian return (0); 222266084Sian} 223266084Sian 224266084Sianint 225266084Sianmv_pci_devmap(phandle_t node, struct arm_devmap_entry *devmap, vm_offset_t io_va, 226266084Sian vm_offset_t mem_va) 227266084Sian{ 228266084Sian struct mv_pci_range io_space, mem_space; 229266084Sian int error; 230266084Sian 231266084Sian if ((error = mv_pci_ranges_decode(node, &io_space, &mem_space)) != 0) 232266084Sian return (error); 233266084Sian 234266084Sian devmap->pd_va = (io_va ? io_va : io_space.base_parent); 235266084Sian devmap->pd_pa = io_space.base_parent; 236266084Sian devmap->pd_size = io_space.len; 237266084Sian devmap->pd_prot = VM_PROT_READ | VM_PROT_WRITE; 238266084Sian devmap->pd_cache = PTE_NOCACHE; 239266084Sian devmap++; 240266084Sian 241266084Sian devmap->pd_va = (mem_va ? mem_va : mem_space.base_parent); 242266084Sian devmap->pd_pa = mem_space.base_parent; 243266084Sian devmap->pd_size = mem_space.len; 244266084Sian devmap->pd_prot = VM_PROT_READ | VM_PROT_WRITE; 245266084Sian devmap->pd_cache = PTE_NOCACHE; 246266084Sian return (0); 247266084Sian} 248266084Sian 249266084Sian/* 250266084Sian * Code and data related to the Marvell pcib driver. 251266084Sian */ 252266084Sian 253261455Seadler#define PCI_CFG_ENA (1U << 31) 254185089Sraj#define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16) 255185089Sraj#define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11) 256185089Sraj#define PCI_CFG_FUN(fun) (((fun) & 0x7) << 8) 257185089Sraj#define PCI_CFG_PCIE_REG(reg) ((reg) & 0xfc) 258185089Sraj 259185089Sraj#define PCI_REG_CFG_ADDR 0x0C78 260185089Sraj#define PCI_REG_CFG_DATA 0x0C7C 261185089Sraj 262185089Sraj#define PCIE_REG_CFG_ADDR 0x18F8 263185089Sraj#define PCIE_REG_CFG_DATA 0x18FC 264185089Sraj#define PCIE_REG_CONTROL 0x1A00 265185089Sraj#define PCIE_CTRL_LINK1X 0x00000001 266185089Sraj#define PCIE_REG_STATUS 0x1A04 267185089Sraj#define PCIE_REG_IRQ_MASK 0x1910 268185089Sraj 269240489Sgber#define PCIE_CONTROL_ROOT_CMPLX (1 << 1) 270240489Sgber#define PCIE_CONTROL_HOT_RESET (1 << 24) 271185089Sraj 272240489Sgber#define PCIE_LINK_TIMEOUT 1000000 273185089Sraj 274240489Sgber#define PCIE_STATUS_LINK_DOWN 1 275240489Sgber#define PCIE_STATUS_DEV_OFFS 16 276185089Sraj 277240489Sgber/* Minimum PCI Memory and I/O allocations taken from PCI spec (in bytes) */ 278240489Sgber#define PCI_MIN_IO_ALLOC 4 279240489Sgber#define PCI_MIN_MEM_ALLOC 16 280240489Sgber 281240489Sgber#define BITS_PER_UINT32 (NBBY * sizeof(uint32_t)) 282240489Sgber 283209131Srajstruct mv_pcib_softc { 284185089Sraj device_t sc_dev; 285185089Sraj 286209131Sraj struct rman sc_mem_rman; 287209131Sraj bus_addr_t sc_mem_base; 288209131Sraj bus_addr_t sc_mem_size; 289240489Sgber uint32_t sc_mem_map[MV_PCI_MEM_SLICE_SIZE / 290240489Sgber (PCI_MIN_MEM_ALLOC * BITS_PER_UINT32)]; 291240489Sgber int sc_win_target; 292209131Sraj int sc_mem_win_attr; 293185089Sraj 294209131Sraj struct rman sc_io_rman; 295209131Sraj bus_addr_t sc_io_base; 296209131Sraj bus_addr_t sc_io_size; 297240489Sgber uint32_t sc_io_map[MV_PCI_IO_SLICE_SIZE / 298240489Sgber (PCI_MIN_IO_ALLOC * BITS_PER_UINT32)]; 299209131Sraj int sc_io_win_attr; 300185089Sraj 301185089Sraj struct resource *sc_res; 302185089Sraj bus_space_handle_t sc_bsh; 303185089Sraj bus_space_tag_t sc_bst; 304185089Sraj int sc_rid; 305185089Sraj 306240493Sgber struct mtx sc_msi_mtx; 307240493Sgber uint32_t sc_msi_bitmap; 308240493Sgber 309185089Sraj int sc_busnr; /* Host bridge bus number */ 310185089Sraj int sc_devnr; /* Host bridge device number */ 311209131Sraj int sc_type; 312240489Sgber int sc_mode; /* Endpoint / Root Complex */ 313185089Sraj 314266020Sian struct ofw_bus_iinfo sc_pci_iinfo; 315185089Sraj}; 316185089Sraj 317209131Sraj/* Local forward prototypes */ 318209131Srajstatic int mv_pcib_decode_win(phandle_t, struct mv_pcib_softc *); 319209131Srajstatic void mv_pcib_hw_cfginit(void); 320209131Srajstatic uint32_t mv_pcib_hw_cfgread(struct mv_pcib_softc *, u_int, u_int, 321209131Sraj u_int, u_int, int); 322209131Srajstatic void mv_pcib_hw_cfgwrite(struct mv_pcib_softc *, u_int, u_int, 323209131Sraj u_int, u_int, uint32_t, int); 324209131Srajstatic int mv_pcib_init(struct mv_pcib_softc *, int, int); 325209131Srajstatic int mv_pcib_init_all_bars(struct mv_pcib_softc *, int, int, int, int); 326209131Srajstatic void mv_pcib_init_bridge(struct mv_pcib_softc *, int, int, int); 327209131Srajstatic inline void pcib_write_irq_mask(struct mv_pcib_softc *, uint32_t); 328240489Sgberstatic void mv_pcib_enable(struct mv_pcib_softc *, uint32_t); 329240489Sgberstatic int mv_pcib_mem_init(struct mv_pcib_softc *); 330185089Sraj 331209131Sraj/* Forward prototypes */ 332209131Srajstatic int mv_pcib_probe(device_t); 333209131Srajstatic int mv_pcib_attach(device_t); 334209131Sraj 335209131Srajstatic struct resource *mv_pcib_alloc_resource(device_t, device_t, int, int *, 336185089Sraj u_long, u_long, u_long, u_int); 337209131Srajstatic int mv_pcib_release_resource(device_t, device_t, int, int, 338185089Sraj struct resource *); 339209131Srajstatic int mv_pcib_read_ivar(device_t, device_t, int, uintptr_t *); 340209131Srajstatic int mv_pcib_write_ivar(device_t, device_t, int, uintptr_t); 341185089Sraj 342209131Srajstatic int mv_pcib_maxslots(device_t); 343209131Srajstatic uint32_t mv_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int); 344209131Srajstatic void mv_pcib_write_config(device_t, u_int, u_int, u_int, u_int, 345185089Sraj uint32_t, int); 346209131Srajstatic int mv_pcib_route_interrupt(device_t, device_t, int); 347240493Sgber#if defined(SOC_MV_ARMADAXP) 348240493Sgberstatic int mv_pcib_alloc_msi(device_t, device_t, int, int, int *); 349240493Sgberstatic int mv_pcib_map_msi(device_t, device_t, int, uint64_t *, uint32_t *); 350240493Sgberstatic int mv_pcib_release_msi(device_t, device_t, int, int *); 351240493Sgber#endif 352185089Sraj 353185089Sraj/* 354185089Sraj * Bus interface definitions. 355185089Sraj */ 356209131Srajstatic device_method_t mv_pcib_methods[] = { 357185089Sraj /* Device interface */ 358209131Sraj DEVMETHOD(device_probe, mv_pcib_probe), 359209131Sraj DEVMETHOD(device_attach, mv_pcib_attach), 360185089Sraj 361185089Sraj /* Bus interface */ 362209131Sraj DEVMETHOD(bus_read_ivar, mv_pcib_read_ivar), 363209131Sraj DEVMETHOD(bus_write_ivar, mv_pcib_write_ivar), 364209131Sraj DEVMETHOD(bus_alloc_resource, mv_pcib_alloc_resource), 365209131Sraj DEVMETHOD(bus_release_resource, mv_pcib_release_resource), 366185089Sraj DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 367185089Sraj DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 368185089Sraj DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 369185089Sraj DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 370185089Sraj 371185089Sraj /* pcib interface */ 372209131Sraj DEVMETHOD(pcib_maxslots, mv_pcib_maxslots), 373209131Sraj DEVMETHOD(pcib_read_config, mv_pcib_read_config), 374209131Sraj DEVMETHOD(pcib_write_config, mv_pcib_write_config), 375209131Sraj DEVMETHOD(pcib_route_interrupt, mv_pcib_route_interrupt), 376240493Sgber 377240493Sgber#if defined(SOC_MV_ARMADAXP) 378240493Sgber DEVMETHOD(pcib_alloc_msi, mv_pcib_alloc_msi), 379240493Sgber DEVMETHOD(pcib_release_msi, mv_pcib_release_msi), 380240493Sgber DEVMETHOD(pcib_map_msi, mv_pcib_map_msi), 381240493Sgber#endif 382240493Sgber 383209131Sraj /* OFW bus interface */ 384209131Sraj DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 385209131Sraj DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 386209131Sraj DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 387209131Sraj DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 388209131Sraj DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 389209131Sraj 390227843Smarius DEVMETHOD_END 391185089Sraj}; 392185089Sraj 393209131Srajstatic driver_t mv_pcib_driver = { 394185089Sraj "pcib", 395209131Sraj mv_pcib_methods, 396209131Sraj sizeof(struct mv_pcib_softc), 397185089Sraj}; 398185089Sraj 399185089Srajdevclass_t pcib_devclass; 400185089Sraj 401266000SianDRIVER_MODULE(pcib, nexus, mv_pcib_driver, pcib_devclass, 0, 0); 402185089Sraj 403185089Srajstatic struct mtx pcicfg_mtx; 404185089Sraj 405185089Srajstatic int 406209131Srajmv_pcib_probe(device_t self) 407185089Sraj{ 408218228Smarcel phandle_t node; 409185089Sraj 410218228Smarcel node = ofw_bus_get_node(self); 411218228Smarcel if (!fdt_is_type(node, "pci")) 412209131Sraj return (ENXIO); 413218228Smarcel 414266020Sian if (!(ofw_bus_is_compatible(self, "mrvl,pcie") || 415266020Sian ofw_bus_is_compatible(self, "mrvl,pci"))) 416209131Sraj return (ENXIO); 417185089Sraj 418209131Sraj device_set_desc(self, "Marvell Integrated PCI/PCI-E Controller"); 419209131Sraj return (BUS_PROBE_DEFAULT); 420185089Sraj} 421185089Sraj 422185089Srajstatic int 423209131Srajmv_pcib_attach(device_t self) 424185089Sraj{ 425209131Sraj struct mv_pcib_softc *sc; 426209131Sraj phandle_t node, parnode; 427240489Sgber uint32_t val, unit; 428209131Sraj int err; 429185089Sraj 430185089Sraj sc = device_get_softc(self); 431209131Sraj sc->sc_dev = self; 432240489Sgber unit = fdt_get_unit(self); 433185089Sraj 434240489Sgber 435218228Smarcel node = ofw_bus_get_node(self); 436218228Smarcel parnode = OF_parent(node); 437218228Smarcel if (fdt_is_compatible(node, "mrvl,pcie")) { 438209131Sraj sc->sc_type = MV_TYPE_PCIE; 439240489Sgber sc->sc_win_target = MV_WIN_PCIE_TARGET(unit); 440240489Sgber sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(unit); 441240489Sgber sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(unit); 442218228Smarcel } else if (fdt_is_compatible(node, "mrvl,pci")) { 443209131Sraj sc->sc_type = MV_TYPE_PCI; 444240489Sgber sc->sc_win_target = MV_WIN_PCI_TARGET; 445209131Sraj sc->sc_mem_win_attr = MV_WIN_PCI_MEM_ATTR; 446209131Sraj sc->sc_io_win_attr = MV_WIN_PCI_IO_ATTR; 447209131Sraj } else 448185089Sraj return (ENXIO); 449185089Sraj 450209131Sraj /* 451209131Sraj * Retrieve our mem-mapped registers range. 452209131Sraj */ 453185089Sraj sc->sc_rid = 0; 454185089Sraj sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid, 455185089Sraj RF_ACTIVE); 456185089Sraj if (sc->sc_res == NULL) { 457209131Sraj device_printf(self, "could not map memory\n"); 458185089Sraj return (ENXIO); 459185089Sraj } 460185089Sraj sc->sc_bst = rman_get_bustag(sc->sc_res); 461185089Sraj sc->sc_bsh = rman_get_bushandle(sc->sc_res); 462185089Sraj 463240489Sgber val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_CONTROL); 464240489Sgber sc->sc_mode = (val & PCIE_CONTROL_ROOT_CMPLX ? MV_MODE_ROOT : 465240489Sgber MV_MODE_ENDPOINT); 466240489Sgber 467209131Sraj /* 468240489Sgber * Get PCI interrupt info. 469240489Sgber */ 470266020Sian if (sc->sc_mode == MV_MODE_ROOT) 471266020Sian ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(pcell_t)); 472240489Sgber 473240489Sgber /* 474209131Sraj * Configure decode windows for PCI(E) access. 475209131Sraj */ 476209131Sraj if (mv_pcib_decode_win(node, sc) != 0) 477209131Sraj return (ENXIO); 478209131Sraj 479209131Sraj mv_pcib_hw_cfginit(); 480209131Sraj 481209131Sraj /* 482240489Sgber * Enable PCIE device. 483209131Sraj */ 484240489Sgber mv_pcib_enable(sc, unit); 485185089Sraj 486240489Sgber /* 487240489Sgber * Memory management. 488240489Sgber */ 489240489Sgber err = mv_pcib_mem_init(sc); 490240489Sgber if (err) 491240489Sgber return (err); 492185089Sraj 493240489Sgber if (sc->sc_mode == MV_MODE_ROOT) { 494240489Sgber err = mv_pcib_init(sc, sc->sc_busnr, 495240489Sgber mv_pcib_maxslots(sc->sc_dev)); 496240489Sgber if (err) 497240489Sgber goto error; 498240489Sgber 499240489Sgber device_add_child(self, "pci", -1); 500240489Sgber } else { 501240489Sgber sc->sc_devnr = 1; 502240489Sgber bus_space_write_4(sc->sc_bst, sc->sc_bsh, 503240489Sgber PCIE_REG_STATUS, 1 << PCIE_STATUS_DEV_OFFS); 504240489Sgber device_add_child(self, "pci_ep", -1); 505240489Sgber } 506240489Sgber 507240493Sgber mtx_init(&sc->sc_msi_mtx, "msi_mtx", NULL, MTX_DEF); 508240489Sgber return (bus_generic_attach(self)); 509240489Sgber 510240489Sgbererror: 511240489Sgber /* XXX SYS_RES_ should be released here */ 512240489Sgber rman_fini(&sc->sc_mem_rman); 513240489Sgber rman_fini(&sc->sc_io_rman); 514240489Sgber 515240489Sgber return (err); 516240489Sgber} 517240489Sgber 518240489Sgberstatic void 519240489Sgbermv_pcib_enable(struct mv_pcib_softc *sc, uint32_t unit) 520240489Sgber{ 521240489Sgber uint32_t val; 522240489Sgber#if !defined(SOC_MV_ARMADAXP) 523240489Sgber int timeout; 524240489Sgber 525240489Sgber /* 526240489Sgber * Check if PCIE device is enabled. 527240489Sgber */ 528240489Sgber if (read_cpu_ctrl(CPU_CONTROL) & CPU_CONTROL_PCIE_DISABLE(unit)) { 529240489Sgber write_cpu_ctrl(CPU_CONTROL, read_cpu_ctrl(CPU_CONTROL) & 530240489Sgber ~(CPU_CONTROL_PCIE_DISABLE(unit))); 531240489Sgber 532240489Sgber timeout = PCIE_LINK_TIMEOUT; 533240489Sgber val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 534240489Sgber PCIE_REG_STATUS); 535240489Sgber while (((val & PCIE_STATUS_LINK_DOWN) == 1) && (timeout > 0)) { 536240489Sgber DELAY(1000); 537240489Sgber timeout -= 1000; 538240489Sgber val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 539240489Sgber PCIE_REG_STATUS); 540240489Sgber } 541240489Sgber } 542240489Sgber#endif 543240489Sgber 544240489Sgber 545240489Sgber if (sc->sc_mode == MV_MODE_ROOT) { 546240489Sgber /* 547240489Sgber * Enable PCI bridge. 548240489Sgber */ 549240489Sgber val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND); 550240489Sgber val |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | 551240489Sgber PCIM_CMD_MEMEN | PCIM_CMD_PORTEN; 552240489Sgber bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND, val); 553240489Sgber } 554240489Sgber} 555240489Sgber 556240489Sgberstatic int 557240489Sgbermv_pcib_mem_init(struct mv_pcib_softc *sc) 558240489Sgber{ 559240489Sgber int err; 560240489Sgber 561240489Sgber /* 562240489Sgber * Memory management. 563240489Sgber */ 564209131Sraj sc->sc_mem_rman.rm_type = RMAN_ARRAY; 565209131Sraj err = rman_init(&sc->sc_mem_rman); 566186932Sraj if (err) 567186932Sraj return (err); 568186932Sraj 569209131Sraj sc->sc_io_rman.rm_type = RMAN_ARRAY; 570209131Sraj err = rman_init(&sc->sc_io_rman); 571186932Sraj if (err) { 572209131Sraj rman_fini(&sc->sc_mem_rman); 573186932Sraj return (err); 574186932Sraj } 575186932Sraj 576209131Sraj err = rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base, 577209131Sraj sc->sc_mem_base + sc->sc_mem_size - 1); 578186932Sraj if (err) 579186932Sraj goto error; 580186932Sraj 581209131Sraj err = rman_manage_region(&sc->sc_io_rman, sc->sc_io_base, 582209131Sraj sc->sc_io_base + sc->sc_io_size - 1); 583186932Sraj if (err) 584186932Sraj goto error; 585186932Sraj 586240489Sgber return (0); 587185089Sraj 588186932Srajerror: 589209131Sraj rman_fini(&sc->sc_mem_rman); 590209131Sraj rman_fini(&sc->sc_io_rman); 591240489Sgber 592186932Sraj return (err); 593185089Sraj} 594185089Sraj 595240489Sgberstatic inline uint32_t 596240489Sgberpcib_bit_get(uint32_t *map, uint32_t bit) 597240489Sgber{ 598240489Sgber uint32_t n = bit / BITS_PER_UINT32; 599240489Sgber 600240489Sgber bit = bit % BITS_PER_UINT32; 601240489Sgber return (map[n] & (1 << bit)); 602240489Sgber} 603240489Sgber 604240489Sgberstatic inline void 605240489Sgberpcib_bit_set(uint32_t *map, uint32_t bit) 606240489Sgber{ 607240489Sgber uint32_t n = bit / BITS_PER_UINT32; 608240489Sgber 609240489Sgber bit = bit % BITS_PER_UINT32; 610240489Sgber map[n] |= (1 << bit); 611240489Sgber} 612240489Sgber 613240489Sgberstatic inline uint32_t 614240489Sgberpcib_map_check(uint32_t *map, uint32_t start, uint32_t bits) 615240489Sgber{ 616240489Sgber uint32_t i; 617240489Sgber 618240489Sgber for (i = start; i < start + bits; i++) 619240489Sgber if (pcib_bit_get(map, i)) 620240489Sgber return (0); 621240489Sgber 622240489Sgber return (1); 623240489Sgber} 624240489Sgber 625240489Sgberstatic inline void 626240489Sgberpcib_map_set(uint32_t *map, uint32_t start, uint32_t bits) 627240489Sgber{ 628240489Sgber uint32_t i; 629240489Sgber 630240489Sgber for (i = start; i < start + bits; i++) 631240489Sgber pcib_bit_set(map, i); 632240489Sgber} 633240489Sgber 634240489Sgber/* 635240489Sgber * The idea of this allocator is taken from ARM No-Cache memory 636240489Sgber * management code (sys/arm/arm/vm_machdep.c). 637240489Sgber */ 638240489Sgberstatic bus_addr_t 639240489Sgberpcib_alloc(struct mv_pcib_softc *sc, uint32_t smask) 640240489Sgber{ 641240489Sgber uint32_t bits, bits_limit, i, *map, min_alloc, size; 642240489Sgber bus_addr_t addr = 0; 643240489Sgber bus_addr_t base; 644240489Sgber 645240489Sgber if (smask & 1) { 646240489Sgber base = sc->sc_io_base; 647240489Sgber min_alloc = PCI_MIN_IO_ALLOC; 648240489Sgber bits_limit = sc->sc_io_size / min_alloc; 649240489Sgber map = sc->sc_io_map; 650240489Sgber smask &= ~0x3; 651240489Sgber } else { 652240489Sgber base = sc->sc_mem_base; 653240489Sgber min_alloc = PCI_MIN_MEM_ALLOC; 654240489Sgber bits_limit = sc->sc_mem_size / min_alloc; 655240489Sgber map = sc->sc_mem_map; 656240489Sgber smask &= ~0xF; 657240489Sgber } 658240489Sgber 659240489Sgber size = ~smask + 1; 660240489Sgber bits = size / min_alloc; 661240489Sgber 662240489Sgber for (i = 0; i + bits <= bits_limit; i += bits) 663240489Sgber if (pcib_map_check(map, i, bits)) { 664240489Sgber pcib_map_set(map, i, bits); 665240489Sgber addr = base + (i * min_alloc); 666240489Sgber return (addr); 667240489Sgber } 668240489Sgber 669240489Sgber return (addr); 670240489Sgber} 671240489Sgber 672185089Srajstatic int 673209131Srajmv_pcib_init_bar(struct mv_pcib_softc *sc, int bus, int slot, int func, 674185089Sraj int barno) 675185089Sraj{ 676240489Sgber uint32_t addr, bar; 677185089Sraj int reg, width; 678185089Sraj 679185089Sraj reg = PCIR_BAR(barno); 680240489Sgber 681240489Sgber /* 682240489Sgber * Need to init the BAR register with 0xffffffff before correct 683240489Sgber * value can be read. 684240489Sgber */ 685240489Sgber mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4); 686209131Sraj bar = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4); 687185089Sraj if (bar == 0) 688185089Sraj return (1); 689185089Sraj 690185089Sraj /* Calculate BAR size: 64 or 32 bit (in 32-bit units) */ 691185089Sraj width = ((bar & 7) == 4) ? 2 : 1; 692185089Sraj 693240489Sgber addr = pcib_alloc(sc, bar); 694240489Sgber if (!addr) 695185089Sraj return (-1); 696185089Sraj 697185089Sraj if (bootverbose) 698240489Sgber printf("PCI %u:%u:%u: reg %x: smask=%08x: addr=%08x\n", 699240489Sgber bus, slot, func, reg, bar, addr); 700185089Sraj 701209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4); 702185089Sraj if (width == 2) 703209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4, 704185089Sraj 0, 4); 705185089Sraj 706185089Sraj return (width); 707185089Sraj} 708185089Sraj 709185089Srajstatic void 710209131Srajmv_pcib_init_bridge(struct mv_pcib_softc *sc, int bus, int slot, int func) 711185089Sraj{ 712185089Sraj bus_addr_t io_base, mem_base; 713185089Sraj uint32_t io_limit, mem_limit; 714185089Sraj int secbus; 715185089Sraj 716209131Sraj io_base = sc->sc_io_base; 717209131Sraj io_limit = io_base + sc->sc_io_size - 1; 718209131Sraj mem_base = sc->sc_mem_base; 719209131Sraj mem_limit = mem_base + sc->sc_mem_size - 1; 720185089Sraj 721185089Sraj /* Configure I/O decode registers */ 722209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1, 723185639Sraj io_base >> 8, 1); 724209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEH_1, 725185639Sraj io_base >> 16, 2); 726209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITL_1, 727185089Sraj io_limit >> 8, 1); 728209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITH_1, 729185089Sraj io_limit >> 16, 2); 730185089Sraj 731185089Sraj /* Configure memory decode registers */ 732209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMBASE_1, 733185089Sraj mem_base >> 16, 2); 734209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMLIMIT_1, 735185089Sraj mem_limit >> 16, 2); 736185089Sraj 737185089Sraj /* Disable memory prefetch decode */ 738209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEL_1, 739185089Sraj 0x10, 2); 740209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEH_1, 741185089Sraj 0x0, 4); 742209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITL_1, 743185089Sraj 0xF, 2); 744209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITH_1, 745185089Sraj 0x0, 4); 746185089Sraj 747209131Sraj secbus = mv_pcib_read_config(sc->sc_dev, bus, slot, func, 748185089Sraj PCIR_SECBUS_1, 1); 749185089Sraj 750185089Sraj /* Configure buses behind the bridge */ 751209131Sraj mv_pcib_init(sc, secbus, PCI_SLOTMAX); 752185089Sraj} 753185089Sraj 754185089Srajstatic int 755209131Srajmv_pcib_init(struct mv_pcib_softc *sc, int bus, int maxslot) 756185089Sraj{ 757185089Sraj int slot, func, maxfunc, error; 758185089Sraj uint8_t hdrtype, command, class, subclass; 759185089Sraj 760185089Sraj for (slot = 0; slot <= maxslot; slot++) { 761185089Sraj maxfunc = 0; 762185089Sraj for (func = 0; func <= maxfunc; func++) { 763209131Sraj hdrtype = mv_pcib_read_config(sc->sc_dev, bus, slot, 764185089Sraj func, PCIR_HDRTYPE, 1); 765185089Sraj 766185089Sraj if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 767185089Sraj continue; 768185089Sraj 769185089Sraj if (func == 0 && (hdrtype & PCIM_MFDEV)) 770185089Sraj maxfunc = PCI_FUNCMAX; 771185089Sraj 772209131Sraj command = mv_pcib_read_config(sc->sc_dev, bus, slot, 773185089Sraj func, PCIR_COMMAND, 1); 774185089Sraj command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN); 775209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, 776185089Sraj PCIR_COMMAND, command, 1); 777185089Sraj 778209131Sraj error = mv_pcib_init_all_bars(sc, bus, slot, func, 779185089Sraj hdrtype); 780185089Sraj 781185089Sraj if (error) 782185089Sraj return (error); 783185089Sraj 784185089Sraj command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | 785185089Sraj PCIM_CMD_PORTEN; 786209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, 787185089Sraj PCIR_COMMAND, command, 1); 788185089Sraj 789185089Sraj /* Handle PCI-PCI bridges */ 790209131Sraj class = mv_pcib_read_config(sc->sc_dev, bus, slot, 791185089Sraj func, PCIR_CLASS, 1); 792209131Sraj subclass = mv_pcib_read_config(sc->sc_dev, bus, slot, 793185089Sraj func, PCIR_SUBCLASS, 1); 794185089Sraj 795185089Sraj if (class != PCIC_BRIDGE || 796185089Sraj subclass != PCIS_BRIDGE_PCI) 797185089Sraj continue; 798185089Sraj 799209131Sraj mv_pcib_init_bridge(sc, bus, slot, func); 800185089Sraj } 801185089Sraj } 802185089Sraj 803185089Sraj /* Enable all ABCD interrupts */ 804185089Sraj pcib_write_irq_mask(sc, (0xF << 24)); 805185089Sraj 806185089Sraj return (0); 807185089Sraj} 808185089Sraj 809209131Srajstatic int 810209131Srajmv_pcib_init_all_bars(struct mv_pcib_softc *sc, int bus, int slot, 811209131Sraj int func, int hdrtype) 812209131Sraj{ 813209131Sraj int maxbar, bar, i; 814209131Sraj 815209131Sraj maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6; 816209131Sraj bar = 0; 817209131Sraj 818209131Sraj /* Program the base address registers */ 819209131Sraj while (bar < maxbar) { 820209131Sraj i = mv_pcib_init_bar(sc, bus, slot, func, bar); 821209131Sraj bar += i; 822209131Sraj if (i < 0) { 823209131Sraj device_printf(sc->sc_dev, 824209131Sraj "PCI IO/Memory space exhausted\n"); 825209131Sraj return (ENOMEM); 826209131Sraj } 827209131Sraj } 828209131Sraj 829209131Sraj return (0); 830209131Sraj} 831209131Sraj 832185089Srajstatic struct resource * 833209131Srajmv_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 834185089Sraj u_long start, u_long end, u_long count, u_int flags) 835185089Sraj{ 836209131Sraj struct mv_pcib_softc *sc = device_get_softc(dev); 837186932Sraj struct rman *rm = NULL; 838186932Sraj struct resource *res; 839185089Sraj 840186932Sraj switch (type) { 841186932Sraj case SYS_RES_IOPORT: 842209131Sraj rm = &sc->sc_io_rman; 843186932Sraj break; 844186932Sraj case SYS_RES_MEMORY: 845209131Sraj rm = &sc->sc_mem_rman; 846186932Sraj break; 847186932Sraj default: 848240489Sgber return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 849186932Sraj type, rid, start, end, count, flags)); 850186932Sraj }; 851186932Sraj 852240489Sgber if ((start == 0UL) && (end == ~0UL)) { 853240489Sgber start = sc->sc_mem_base; 854240489Sgber end = sc->sc_mem_base + sc->sc_mem_size - 1; 855240489Sgber count = sc->sc_mem_size; 856240489Sgber } 857240489Sgber 858240489Sgber if ((start < sc->sc_mem_base) || (start + count - 1 != end) || 859240489Sgber (end > sc->sc_mem_base + sc->sc_mem_size - 1)) 860240489Sgber return (NULL); 861240489Sgber 862186932Sraj res = rman_reserve_resource(rm, start, end, count, flags, child); 863186932Sraj if (res == NULL) 864186932Sraj return (NULL); 865186932Sraj 866186932Sraj rman_set_rid(res, *rid); 867209131Sraj rman_set_bustag(res, fdtbus_bs_tag); 868186932Sraj rman_set_bushandle(res, start); 869186932Sraj 870186932Sraj if (flags & RF_ACTIVE) 871186932Sraj if (bus_activate_resource(child, type, *rid, res)) { 872186932Sraj rman_release_resource(res); 873186932Sraj return (NULL); 874186932Sraj } 875186932Sraj 876186932Sraj return (res); 877185089Sraj} 878185089Sraj 879185089Srajstatic int 880209131Srajmv_pcib_release_resource(device_t dev, device_t child, int type, int rid, 881185089Sraj struct resource *res) 882185089Sraj{ 883185089Sraj 884186932Sraj if (type != SYS_RES_IOPORT && type != SYS_RES_MEMORY) 885186932Sraj return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 886186932Sraj type, rid, res)); 887186932Sraj 888186932Sraj return (rman_release_resource(res)); 889185089Sraj} 890185089Sraj 891185089Srajstatic int 892209131Srajmv_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 893185089Sraj{ 894209131Sraj struct mv_pcib_softc *sc = device_get_softc(dev); 895185089Sraj 896185089Sraj switch (which) { 897185089Sraj case PCIB_IVAR_BUS: 898185089Sraj *result = sc->sc_busnr; 899185089Sraj return (0); 900185089Sraj case PCIB_IVAR_DOMAIN: 901185089Sraj *result = device_get_unit(dev); 902185089Sraj return (0); 903185089Sraj } 904185089Sraj 905185089Sraj return (ENOENT); 906185089Sraj} 907185089Sraj 908185089Srajstatic int 909209131Srajmv_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 910185089Sraj{ 911209131Sraj struct mv_pcib_softc *sc = device_get_softc(dev); 912185089Sraj 913185089Sraj switch (which) { 914185089Sraj case PCIB_IVAR_BUS: 915185089Sraj sc->sc_busnr = value; 916185089Sraj return (0); 917185089Sraj } 918185089Sraj 919185089Sraj return (ENOENT); 920185089Sraj} 921209131Sraj 922209131Srajstatic inline void 923209131Srajpcib_write_irq_mask(struct mv_pcib_softc *sc, uint32_t mask) 924209131Sraj{ 925209131Sraj 926209131Sraj if (!sc->sc_type != MV_TYPE_PCI) 927209131Sraj return; 928209131Sraj 929209131Sraj bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_IRQ_MASK, mask); 930209131Sraj} 931209131Sraj 932209131Srajstatic void 933209131Srajmv_pcib_hw_cfginit(void) 934209131Sraj{ 935209131Sraj static int opened = 0; 936209131Sraj 937209131Sraj if (opened) 938209131Sraj return; 939209131Sraj 940209131Sraj mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN); 941209131Sraj opened = 1; 942209131Sraj} 943209131Sraj 944209131Srajstatic uint32_t 945209131Srajmv_pcib_hw_cfgread(struct mv_pcib_softc *sc, u_int bus, u_int slot, 946209131Sraj u_int func, u_int reg, int bytes) 947209131Sraj{ 948209131Sraj uint32_t addr, data, ca, cd; 949209131Sraj 950209131Sraj ca = (sc->sc_type != MV_TYPE_PCI) ? 951209131Sraj PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR; 952209131Sraj cd = (sc->sc_type != MV_TYPE_PCI) ? 953209131Sraj PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA; 954209131Sraj addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | 955209131Sraj PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg); 956209131Sraj 957209131Sraj mtx_lock_spin(&pcicfg_mtx); 958209131Sraj bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr); 959209131Sraj 960209131Sraj data = ~0; 961209131Sraj switch (bytes) { 962209131Sraj case 1: 963209131Sraj data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 964209131Sraj cd + (reg & 3)); 965209131Sraj break; 966209131Sraj case 2: 967209131Sraj data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh, 968209131Sraj cd + (reg & 2))); 969209131Sraj break; 970209131Sraj case 4: 971209131Sraj data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh, 972209131Sraj cd)); 973209131Sraj break; 974209131Sraj } 975209131Sraj mtx_unlock_spin(&pcicfg_mtx); 976209131Sraj return (data); 977209131Sraj} 978209131Sraj 979209131Srajstatic void 980209131Srajmv_pcib_hw_cfgwrite(struct mv_pcib_softc *sc, u_int bus, u_int slot, 981209131Sraj u_int func, u_int reg, uint32_t data, int bytes) 982209131Sraj{ 983209131Sraj uint32_t addr, ca, cd; 984209131Sraj 985209131Sraj ca = (sc->sc_type != MV_TYPE_PCI) ? 986209131Sraj PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR; 987209131Sraj cd = (sc->sc_type != MV_TYPE_PCI) ? 988209131Sraj PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA; 989209131Sraj addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | 990209131Sraj PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg); 991209131Sraj 992209131Sraj mtx_lock_spin(&pcicfg_mtx); 993209131Sraj bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr); 994209131Sraj 995209131Sraj switch (bytes) { 996209131Sraj case 1: 997209131Sraj bus_space_write_1(sc->sc_bst, sc->sc_bsh, 998209131Sraj cd + (reg & 3), data); 999209131Sraj break; 1000209131Sraj case 2: 1001209131Sraj bus_space_write_2(sc->sc_bst, sc->sc_bsh, 1002209131Sraj cd + (reg & 2), htole16(data)); 1003209131Sraj break; 1004209131Sraj case 4: 1005209131Sraj bus_space_write_4(sc->sc_bst, sc->sc_bsh, 1006209131Sraj cd, htole32(data)); 1007209131Sraj break; 1008209131Sraj } 1009209131Sraj mtx_unlock_spin(&pcicfg_mtx); 1010209131Sraj} 1011209131Sraj 1012209131Srajstatic int 1013209131Srajmv_pcib_maxslots(device_t dev) 1014209131Sraj{ 1015209131Sraj struct mv_pcib_softc *sc = device_get_softc(dev); 1016209131Sraj 1017209131Sraj return ((sc->sc_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX); 1018209131Sraj} 1019209131Sraj 1020209131Srajstatic uint32_t 1021209131Srajmv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 1022209131Sraj u_int reg, int bytes) 1023209131Sraj{ 1024209131Sraj struct mv_pcib_softc *sc = device_get_softc(dev); 1025209131Sraj 1026240489Sgber /* Return ~0 if link is inactive or trying to read from Root */ 1027240489Sgber if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) & 1028240489Sgber PCIE_STATUS_LINK_DOWN) || (slot == 0)) 1029209131Sraj return (~0U); 1030209131Sraj 1031209131Sraj return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes)); 1032209131Sraj} 1033209131Sraj 1034209131Srajstatic void 1035209131Srajmv_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 1036209131Sraj u_int reg, uint32_t val, int bytes) 1037209131Sraj{ 1038209131Sraj struct mv_pcib_softc *sc = device_get_softc(dev); 1039209131Sraj 1040240489Sgber /* Return if link is inactive or trying to write to Root */ 1041240489Sgber if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) & 1042240489Sgber PCIE_STATUS_LINK_DOWN) || (slot == 0)) 1043209131Sraj return; 1044209131Sraj 1045209131Sraj mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes); 1046209131Sraj} 1047209131Sraj 1048209131Srajstatic int 1049266020Sianmv_pcib_route_interrupt(device_t bus, device_t dev, int pin) 1050209131Sraj{ 1051209131Sraj struct mv_pcib_softc *sc; 1052266020Sian struct ofw_pci_register reg; 1053266128Sian uint32_t pintr, mintr[4]; 1054266128Sian int icells; 1055266020Sian phandle_t iparent; 1056209131Sraj 1057266020Sian sc = device_get_softc(bus); 1058266020Sian pintr = pin; 1059209131Sraj 1060266020Sian /* Fabricate imap information in case this isn't an OFW device */ 1061266020Sian bzero(®, sizeof(reg)); 1062266020Sian reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) | 1063266020Sian (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) | 1064266020Sian (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT); 1065209131Sraj 1066266128Sian icells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, 1067266128Sian ®, sizeof(reg), &pintr, sizeof(pintr), mintr, sizeof(mintr), 1068266128Sian &iparent); 1069266128Sian if (icells > 0) 1070266128Sian return (ofw_bus_map_intr(dev, iparent, icells, mintr)); 1071266020Sian 1072266020Sian /* Maybe it's a real interrupt, not an intpin */ 1073266020Sian if (pin > 4) 1074266020Sian return (pin); 1075266020Sian 1076266020Sian device_printf(bus, "could not route pin %d for device %d.%d\n", 1077209131Sraj pin, pci_get_slot(dev), pci_get_function(dev)); 1078209131Sraj return (PCI_INVALID_IRQ); 1079209131Sraj} 1080209131Sraj 1081209131Srajstatic int 1082209131Srajmv_pcib_decode_win(phandle_t node, struct mv_pcib_softc *sc) 1083209131Sraj{ 1084266084Sian struct mv_pci_range io_space, mem_space; 1085209131Sraj device_t dev; 1086209131Sraj int error; 1087209131Sraj 1088209131Sraj dev = sc->sc_dev; 1089209131Sraj 1090266084Sian if ((error = mv_pci_ranges(node, &io_space, &mem_space)) != 0) { 1091209131Sraj device_printf(dev, "could not retrieve 'ranges' data\n"); 1092209131Sraj return (error); 1093209131Sraj } 1094209131Sraj 1095209131Sraj /* Configure CPU decoding windows */ 1096240489Sgber error = decode_win_cpu_set(sc->sc_win_target, 1097240489Sgber sc->sc_io_win_attr, io_space.base_parent, io_space.len, ~0); 1098209131Sraj if (error < 0) { 1099209131Sraj device_printf(dev, "could not set up CPU decode " 1100209131Sraj "window for PCI IO\n"); 1101209131Sraj return (ENXIO); 1102209131Sraj } 1103240489Sgber error = decode_win_cpu_set(sc->sc_win_target, 1104240489Sgber sc->sc_mem_win_attr, mem_space.base_parent, mem_space.len, 1105240489Sgber mem_space.base_parent); 1106209131Sraj if (error < 0) { 1107209131Sraj device_printf(dev, "could not set up CPU decode " 1108209131Sraj "windows for PCI MEM\n"); 1109209131Sraj return (ENXIO); 1110209131Sraj } 1111209131Sraj 1112209131Sraj sc->sc_io_base = io_space.base_parent; 1113209131Sraj sc->sc_io_size = io_space.len; 1114209131Sraj 1115209131Sraj sc->sc_mem_base = mem_space.base_parent; 1116209131Sraj sc->sc_mem_size = mem_space.len; 1117209131Sraj 1118209131Sraj return (0); 1119209131Sraj} 1120209131Sraj 1121240493Sgber#if defined(SOC_MV_ARMADAXP) 1122240493Sgberstatic int 1123240493Sgbermv_pcib_map_msi(device_t dev, device_t child, int irq, uint64_t *addr, 1124240493Sgber uint32_t *data) 1125240493Sgber{ 1126240493Sgber struct mv_pcib_softc *sc; 1127240493Sgber 1128240493Sgber sc = device_get_softc(dev); 1129240493Sgber irq = irq - MSI_IRQ; 1130240493Sgber 1131240493Sgber /* validate parameters */ 1132240493Sgber if (isclr(&sc->sc_msi_bitmap, irq)) { 1133240493Sgber device_printf(dev, "invalid MSI 0x%x\n", irq); 1134240493Sgber return (EINVAL); 1135240493Sgber } 1136240493Sgber 1137240493Sgber mv_msi_data(irq, addr, data); 1138240493Sgber 1139240493Sgber debugf("%s: irq: %d addr: %jx data: %x\n", 1140240493Sgber __func__, irq, *addr, *data); 1141240493Sgber 1142240493Sgber return (0); 1143240493Sgber} 1144240493Sgber 1145240493Sgberstatic int 1146240493Sgbermv_pcib_alloc_msi(device_t dev, device_t child, int count, 1147240493Sgber int maxcount __unused, int *irqs) 1148240493Sgber{ 1149240493Sgber struct mv_pcib_softc *sc; 1150240493Sgber u_int start = 0, i; 1151240493Sgber 1152240493Sgber if (powerof2(count) == 0 || count > MSI_IRQ_NUM) 1153240493Sgber return (EINVAL); 1154240493Sgber 1155240493Sgber sc = device_get_softc(dev); 1156240493Sgber mtx_lock(&sc->sc_msi_mtx); 1157240493Sgber 1158240493Sgber for (start = 0; (start + count) < MSI_IRQ_NUM; start++) { 1159240493Sgber for (i = start; i < start + count; i++) { 1160240493Sgber if (isset(&sc->sc_msi_bitmap, i)) 1161240493Sgber break; 1162240493Sgber } 1163240493Sgber if (i == start + count) 1164240493Sgber break; 1165240493Sgber } 1166240493Sgber 1167240493Sgber if ((start + count) == MSI_IRQ_NUM) { 1168240493Sgber mtx_unlock(&sc->sc_msi_mtx); 1169240493Sgber return (ENXIO); 1170240493Sgber } 1171240493Sgber 1172240493Sgber for (i = start; i < start + count; i++) { 1173240493Sgber setbit(&sc->sc_msi_bitmap, i); 1174240493Sgber irqs[i] = MSI_IRQ + i; 1175240493Sgber } 1176240493Sgber debugf("%s: start: %x count: %x\n", __func__, start, count); 1177240493Sgber 1178240493Sgber mtx_unlock(&sc->sc_msi_mtx); 1179240493Sgber return (0); 1180240493Sgber} 1181240493Sgber 1182240493Sgberstatic int 1183240493Sgbermv_pcib_release_msi(device_t dev, device_t child, int count, int *irqs) 1184240493Sgber{ 1185240493Sgber struct mv_pcib_softc *sc; 1186240493Sgber u_int i; 1187240493Sgber 1188240493Sgber sc = device_get_softc(dev); 1189240493Sgber mtx_lock(&sc->sc_msi_mtx); 1190240493Sgber 1191240493Sgber for (i = 0; i < count; i++) 1192240493Sgber clrbit(&sc->sc_msi_bitmap, irqs[i] - MSI_IRQ); 1193240493Sgber 1194240493Sgber mtx_unlock(&sc->sc_msi_mtx); 1195240493Sgber return (0); 1196240493Sgber} 1197240493Sgber#endif 1198266084Sian 1199