uart_dev_at91usart.c revision 157023
1/*- 2 * Copyright (c) 2005 M. Warner Losh 3 * Copyright (c) 2005 cognet 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/arm/at91/uart_dev_at91usart.c 157023 2006-03-22 21:16:09Z cognet $"); 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/bus.h> 34#include <sys/conf.h> 35#include <sys/cons.h> 36#include <sys/tty.h> 37#include <machine/bus.h> 38 39#include <dev/uart/uart.h> 40#include <dev/uart/uart_cpu.h> 41#include <dev/uart/uart_bus.h> 42#include <arm/at91/at91rm92reg.h> 43#include <arm/at91/at91_usartreg.h> 44 45#include "uart_if.h" 46 47#define DEFAULT_RCLK AT91C_MASTER_CLOCK 48 49#define SIGCHG(c, i, s, d) \ 50 do { \ 51 if (c) { \ 52 i |= (i & s) ? s : s | d; \ 53 } else { \ 54 i = (i & s) ? (i & ~s) | d : i; \ 55 } \ 56 } while (0); 57 58/* 59 * Low-level UART interface. 60 */ 61static int at91_usart_probe(struct uart_bas *bas); 62static void at91_usart_init(struct uart_bas *bas, int, int, int, int); 63static void at91_usart_term(struct uart_bas *bas); 64static void at91_usart_putc(struct uart_bas *bas, int); 65static int at91_usart_poll(struct uart_bas *bas); 66static int at91_usart_getc(struct uart_bas *bas); 67 68extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs; 69 70static int 71at91_usart_param(struct uart_bas *bas, int baudrate, int databits, 72 int stopbits, int parity) 73{ 74 uint32_t mr; 75 76 /* 77 * Assume 3-write RS-232 configuration. 78 * XXX Not sure how uart will present the other modes to us, so 79 * XXX they are unimplemented. maybe ioctl? 80 */ 81 mr = USART_MR_MODE_NORMAL; 82 mr |= USART_MR_USCLKS_MCK; /* Assume MCK */ 83 84 /* 85 * Or in the databits requested 86 */ 87 if (databits < 9) 88 mr &= ~USART_MR_MODE9; 89 switch (databits) { 90 case 5: 91 mr |= USART_MR_CHRL_5BITS; 92 break; 93 case 6: 94 mr |= USART_MR_CHRL_6BITS; 95 break; 96 case 7: 97 mr |= USART_MR_CHRL_7BITS; 98 break; 99 case 8: 100 mr |= USART_MR_CHRL_8BITS; 101 break; 102 case 9: 103 mr |= USART_MR_CHRL_8BITS | USART_MR_MODE9; 104 break; 105 default: 106 return (EINVAL); 107 } 108 109 /* 110 * Or in the parity 111 */ 112 switch (parity) { 113 case UART_PARITY_NONE: 114 mr |= USART_MR_PAR_NONE; 115 break; 116 case UART_PARITY_ODD: 117 mr |= USART_MR_PAR_ODD; 118 break; 119 case UART_PARITY_EVEN: 120 mr |= USART_MR_PAR_EVEN; 121 break; 122 case UART_PARITY_MARK: 123 mr |= USART_MR_PAR_MARK; 124 break; 125 case UART_PARITY_SPACE: 126 mr |= USART_MR_PAR_SPACE; 127 break; 128 default: 129 return (EINVAL); 130 } 131 132 /* 133 * Or in the stop bits. Note: The hardware supports 134 * 1.5 stop bits in async mode, but there's no way to 135 * specify that AFAICT. 136 */ 137 if (stopbits > 1) 138 mr |= USART_MR_NBSTOP_2; 139 else 140 mr |= USART_MR_NBSTOP_2; 141 /* else if (stopbits == 1.5) 142 mr |= USART_MR_NBSTOP_1_5; */ 143 144 /* 145 * We want normal plumbing mode too, none of this fancy 146 * loopback or echo mode. 147 */ 148 mr |= USART_MR_CHMODE_NORMAL; 149 150 mr &= ~USART_MR_MSBF; /* lsb first */ 151 mr &= ~USART_MR_CKLO_SCK; /* Don't drive SCK */ 152 153 /* XXX Need to take possible synchronous mode into account */ 154 return (0); 155} 156 157struct uart_ops at91_usart_ops = { 158 .probe = at91_usart_probe, 159 .init = at91_usart_init, 160 .term = at91_usart_term, 161 .putc = at91_usart_putc, 162 .poll = at91_usart_poll, 163 .getc = at91_usart_getc, 164}; 165 166static int 167at91_usart_probe(struct uart_bas *bas) 168{ 169 /* We know that this is always here */ 170 return (0); 171} 172 173/* 174 * Initialize this device (I think as the console) 175 */ 176static void 177at91_usart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 178 int parity) 179{ 180 int cr; 181 182 at91_usart_param(bas, baudrate, databits, stopbits, parity); 183 184 /* Turn on rx and tx */ 185 cr = USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX; 186 uart_setreg(bas, USART_CR, cr); 187 uart_setreg(bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN); 188 uart_setreg(bas, USART_IER, USART_CSR_TXRDY | USART_CSR_RXRDY | 189 USART_CSR_RXBRK); 190} 191 192/* 193 * Free resources now that we're no longer the console. This appears to 194 * be never called, and I'm unsure quite what to do if I am called. 195 */ 196static void 197at91_usart_term(struct uart_bas *bas) 198{ 199 /* XXX */ 200} 201 202/* 203 * Put a character of console output (so we do it here polling rather than 204 * interrutp driven). 205 */ 206static void 207at91_usart_putc(struct uart_bas *bas, int c) 208{ 209 210 while (!(uart_getreg(bas, USART_CSR) & 211 USART_CSR_TXRDY)); 212 uart_setreg(bas, USART_THR, c); 213} 214 215/* 216 * Poll for a character available 217 */ 218static int 219at91_usart_poll(struct uart_bas *bas) 220{ 221 222 if (!(uart_getreg(bas, USART_CSR) & USART_CSR_RXRDY)) 223 return (-1); 224 return (uart_getreg(bas, USART_RHR) & 0xff); 225} 226 227/* 228 * Block waiting for a character. 229 */ 230static int 231at91_usart_getc(struct uart_bas *bas) 232{ 233 int c; 234 235 while (!(uart_getreg(bas, USART_CSR) & USART_CSR_RXRDY)) 236 ; 237 c = uart_getreg(bas, USART_RHR); 238 c &= 0xff; 239 return (c); 240} 241 242static int at91_usart_bus_probe(struct uart_softc *sc); 243static int at91_usart_bus_attach(struct uart_softc *sc); 244static int at91_usart_bus_flush(struct uart_softc *, int); 245static int at91_usart_bus_getsig(struct uart_softc *); 246static int at91_usart_bus_ioctl(struct uart_softc *, int, intptr_t); 247static int at91_usart_bus_ipend(struct uart_softc *); 248static int at91_usart_bus_param(struct uart_softc *, int, int, int, int); 249static int at91_usart_bus_receive(struct uart_softc *); 250static int at91_usart_bus_setsig(struct uart_softc *, int); 251static int at91_usart_bus_transmit(struct uart_softc *); 252 253static kobj_method_t at91_usart_methods[] = { 254 KOBJMETHOD(uart_probe, at91_usart_bus_probe), 255 KOBJMETHOD(uart_attach, at91_usart_bus_attach), 256 KOBJMETHOD(uart_flush, at91_usart_bus_flush), 257 KOBJMETHOD(uart_getsig, at91_usart_bus_getsig), 258 KOBJMETHOD(uart_ioctl, at91_usart_bus_ioctl), 259 KOBJMETHOD(uart_ipend, at91_usart_bus_ipend), 260 KOBJMETHOD(uart_param, at91_usart_bus_param), 261 KOBJMETHOD(uart_receive, at91_usart_bus_receive), 262 KOBJMETHOD(uart_setsig, at91_usart_bus_setsig), 263 KOBJMETHOD(uart_transmit, at91_usart_bus_transmit), 264 265 { 0, 0 } 266}; 267 268int 269at91_usart_bus_probe(struct uart_softc *sc) 270{ 271 return (0); 272} 273 274static int 275at91_usart_bus_attach(struct uart_softc *sc) 276{ 277 sc->sc_txfifosz = 1; 278 sc->sc_rxfifosz = 1; 279 sc->sc_hwiflow = 0; 280 return (0); 281} 282static int 283at91_usart_bus_transmit(struct uart_softc *sc) 284{ 285 int i; 286 287 /* XXX VERY sub-optimial */ 288 mtx_lock_spin(&sc->sc_hwmtx); 289 sc->sc_txbusy = 1; 290 for (i = 0; i < sc->sc_txdatasz; i++) 291 at91_usart_putc(&sc->sc_bas, sc->sc_txbuf[i]); 292 mtx_unlock_spin(&sc->sc_hwmtx); 293#ifdef USART0_CONSOLE 294 /* 295 * XXX: Gross hack : Skyeye doesn't raise an interrupt once the 296 * transfer is done, so simulate it. 297 */ 298 uart_setreg(&sc->sc_bas, USART_IER, USART_CSR_TXRDY); 299#endif 300 return (0); 301} 302static int 303at91_usart_bus_setsig(struct uart_softc *sc, int sig) 304{ 305 uint32_t new, old, cr; 306 struct uart_bas *bas; 307 308 do { 309 old = sc->sc_hwsig; 310 new = old; 311 if (sig & SER_DDTR) 312 SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR); 313 if (sig & SER_DRTS) 314 SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS); 315 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 316 bas = &sc->sc_bas; 317 mtx_lock_spin(&sc->sc_hwmtx); 318 cr = uart_getreg(bas, USART_CR); 319 cr &= ~(USART_CR_DTREN | USART_CR_DTRDIS | USART_CR_RTSEN | 320 USART_CR_RTSDIS); 321 if (new & SER_DTR) 322 cr |= USART_CR_DTREN; 323 else 324 cr |= USART_CR_DTRDIS; 325 if (new & SER_RTS) 326 cr |= USART_CR_RTSEN; 327 else 328 cr |= USART_CR_RTSDIS; 329 uart_setreg(bas, USART_CR, cr); 330 mtx_unlock_spin(&sc->sc_hwmtx); 331 return (0); 332} 333static int 334at91_usart_bus_receive(struct uart_softc *sc) 335{ 336 337 mtx_lock_spin(&sc->sc_hwmtx); 338 uart_rx_put(sc, at91_usart_getc(&sc->sc_bas)); 339 mtx_unlock_spin(&sc->sc_hwmtx); 340 return (0); 341} 342static int 343at91_usart_bus_param(struct uart_softc *sc, int baudrate, int databits, 344 int stopbits, int parity) 345{ 346 return (at91_usart_param(&sc->sc_bas, baudrate, databits, stopbits, 347 parity)); 348} 349static int 350at91_usart_bus_ipend(struct uart_softc *sc) 351{ 352 int csr = uart_getreg(&sc->sc_bas, USART_CSR); 353 int ipend = 0; 354 355#ifdef USART0_CONSOLE 356 /* 357 * XXX: We have to cheat for skyeye, as it will return 0xff for all 358 * the devices it doesn't emulate. 359 */ 360 if (sc->sc_bas.chan != 1) 361 return (0); 362#endif 363 364 mtx_lock_spin(&sc->sc_hwmtx); 365 if (csr & USART_CSR_TXRDY && sc->sc_txbusy) 366 ipend |= SER_INT_TXIDLE; 367 if (csr & USART_CSR_RXRDY) 368 ipend |= SER_INT_RXREADY; 369 if (csr & USART_CSR_RXBRK) { 370 unsigned int cr = USART_CR_RSTSTA; 371 372 ipend |= SER_INT_BREAK; 373 uart_setreg(&sc->sc_bas, USART_CR, cr); 374 } 375 mtx_unlock_spin(&sc->sc_hwmtx); 376 return (ipend); 377} 378static int 379at91_usart_bus_flush(struct uart_softc *sc, int what) 380{ 381 return (0); 382} 383 384static int 385at91_usart_bus_getsig(struct uart_softc *sc) 386{ 387 uint32_t new, sig; 388 uint8_t csr; 389 390 mtx_lock_spin(&sc->sc_hwmtx); 391 csr = uart_getreg(&sc->sc_bas, USART_CSR); 392 sig = 0; 393 if (csr & USART_CSR_CTS) 394 sig |= SER_CTS; 395 if (csr & USART_CSR_DCD) 396 sig |= SER_DCD; 397 if (csr & USART_CSR_DSR) 398 sig |= SER_DSR; 399 if (csr & USART_CSR_RI) 400 sig |= SER_RI; 401 new = sig & ~SER_MASK_DELTA; 402 sc->sc_hwsig = new; 403 mtx_unlock_spin(&sc->sc_hwmtx); 404 return (sig); 405} 406 407static int 408at91_usart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 409{ 410 return (EINVAL); 411} 412struct uart_class at91_usart_class = { 413 "at91_usart class", 414 at91_usart_methods, 415 1, 416 .uc_range = 8, 417 .uc_rclk = DEFAULT_RCLK 418}; 419