if_macbreg.h revision 210040
1210040Scognet/* 2210040Scognet * $FreeBSD: head/sys/arm/at91/if_macbreg.h 210040 2010-07-14 00:48:53Z cognet $ 3210040Scognet */ 4210040Scognet 5210040Scognet#ifndef MACB_REG_H 6210040Scognet#define MACB_REG_H 7210040Scognet 8210040Scognet#define EMAC_NCR 0x00 9210040Scognet#define EMAC_NCFGR 0x04 10210040Scognet#define EMAC_TSR 0x14 11210040Scognet#define EMAC_RSR 0x20 12210040Scognet#define EMAC_ISR 0x24 13210040Scognet#define EMAC_IER 0x28 14210040Scognet#define EMAC_IDR 0x2C 15210040Scognet#define EMAC_IMR 0x30 16210040Scognet 17210040Scognet 18210040Scognet 19210040Scognet#define EMAC_RBQP 0x18 20210040Scognet#define EMAC_TBQP 0x1C 21210040Scognet 22210040Scognet#define EMAC_HRB 0x90 23210040Scognet#define EMAC_HRT 0x94 24210040Scognet 25210040Scognet#define EMAC_SA1B 0x98 26210040Scognet#define EMAC_SA1T 0x9C 27210040Scognet 28210040Scognet#define EMAC_USRIO 0xC0 29210040Scognet 30210040Scognet#define EMAC_MAN 0x34 /* EMAC PHY Maintenance Register */ 31210040Scognet#define EMAC_SR 0x08 /* EMAC STatus Register */ 32210040Scognet#define EMAC_SR_LINK (1U << 0) /* Reserved! */ 33210040Scognet#define EMAC_SR_MDIO (1U << 1) /* MDIO pin status */ 34210040Scognet#define EMAC_SR_IDLE (1U << 2) /* IDLE (PHY logic) */ 35210040Scognet 36210040Scognet#define RX_ENABLE (1 << 2) 37210040Scognet#define TX_ENABLE (1 << 3) 38210040Scognet#define MPE_ENABLE (1 << 4) 39210040Scognet 40210040Scognet 41210040Scognet/* EMAC_MAN */ 42210040Scognet#define EMAC_MAN_BITS 0x40020000 /* HIGH and CODE bits */ 43210040Scognet#define EMAC_MAN_READ (2U << 28) 44210040Scognet#define EMAC_MAN_WRITE (1U << 28) 45210040Scognet#define EMAC_MAN_PHYA_BIT 23 46210040Scognet#define EMAC_MAN_REGA_BIT 18 47210040Scognet#define EMAC_MAN_VALUE_MASK 0xffffU 48210040Scognet#define EMAC_MAN_REG_WR(phy, reg, val) \ 49210040Scognet (EMAC_MAN_BITS | EMAC_MAN_WRITE | ((phy) << EMAC_MAN_PHYA_BIT) | \ 50210040Scognet ((reg) << EMAC_MAN_REGA_BIT) | ((val) & EMAC_MAN_VALUE_MASK)) 51210040Scognet 52210040Scognet#define EMAC_MAN_REG_RD(phy, reg) \ 53210040Scognet (EMAC_MAN_BITS | EMAC_MAN_READ | ((phy) << EMAC_MAN_PHYA_BIT) | \ 54210040Scognet ((reg) << EMAC_MAN_REGA_BIT)) 55210040Scognet 56210040Scognet#define RCOMP_INTERRUPT (1 << 1) 57210040Scognet#define RXUBR_INTERRUPT (1 << 2) 58210040Scognet#define TUBR_INTERRUPT (1 << 3) 59210040Scognet#define TUND_INTERRUPT (1 << 4) 60210040Scognet#define RLE_INTERRUPT (1 << 5) 61210040Scognet#define TXERR_INTERRUPT (1 << 6) 62210040Scognet#define ROVR_INTERRUPT (1 << 10) 63210040Scognet#define HRESP_INTERRUPT (1 << 11) 64210040Scognet#define TCOMP_INTERRUPT (1 << 7) 65210040Scognet 66210040Scognet#define CLEAR_STAT (1 << 5) 67210040Scognet 68210040Scognet#define TRANSMIT_START (1 << 9) 69210040Scognet#define TRANSMIT_STOP (1 << 10) 70210040Scognet 71210040Scognet/*Transmit status register flags*/ 72210040Scognet#define TSR_UND (1 << 6) 73210040Scognet#define TSR_COMP (1 << 5) 74210040Scognet#define TSR_BEX (1 << 4) 75210040Scognet#define TSR_TGO (1 << 3) 76210040Scognet#define TSR_RLE (1 << 2) 77210040Scognet#define TSR_COL (1 << 1) 78210040Scognet#define TSR_UBR (1 << 0) 79210040Scognet 80210040Scognet#define CFG_SPD (1 << 0) 81210040Scognet#define CFG_FD (1 << 1) 82210040Scognet#define CFG_CAF (1 << 4) 83210040Scognet#define CFG_NBC (1 << 5) 84210040Scognet#define CFG_MTI (1 << 6) 85210040Scognet#define CFG_UNI (1 << 7) 86210040Scognet#define CFG_BIG (1 << 8) 87210040Scognet 88210040Scognet#define CFG_CLK_8 (0) 89210040Scognet#define CFG_CLK_16 (1) 90210040Scognet#define CFG_CLK_32 (2) 91210040Scognet#define CFG_CLK_64 (3) 92210040Scognet 93210040Scognet#define CFG_PAE (1 << 13) 94210040Scognet 95210040Scognet#define CFG_RBOF_0 (0 << 14) 96210040Scognet#define CFG_RBOF_1 (1 << 14) 97210040Scognet#define CFG_RBOF_2 (2 << 14) 98210040Scognet#define CFG_RBOF_3 (3 << 14) 99210040Scognet 100210040Scognet#define CFG_DRFCS (1 << 17) 101210040Scognet 102210040Scognet#define USRIO_CLOCK (1 << 1) 103210040Scognet 104210040Scognet 105210040Scognet 106210040Scognet#endif 107