if_atereg.h revision 162129
1169Sohair/*- 22362Sohair * Copyright (c) 2006 M. Warner Losh. All rights reserved. 30Sduke * 40Sduke * Redistribution and use in source and binary forms, with or without 50Sduke * modification, are permitted provided that the following conditions 60Sduke * are met: 70Sduke * 1. Redistributions of source code must retain the above copyright 80Sduke * notice, this list of conditions and the following disclaimer. 90Sduke * 2. Redistributions in binary form must reproduce the above copyright 100Sduke * notice, this list of conditions and the following disclaimer in the 110Sduke * documentation and/or other materials provided with the distribution. 120Sduke * 130Sduke * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 140Sduke * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 150Sduke * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 160Sduke * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 170Sduke * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 180Sduke * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 192362Sohair * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 202362Sohair * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 212362Sohair * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 220Sduke * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 230Sduke */ 240Sduke 250Sduke/* $FreeBSD: head/sys/arm/at91/if_atereg.h 162129 2006-09-07 21:50:01Z imp $ */ 260Sduke 270Sduke#ifndef ARM_AT91_IF_ATEREG_H 280Sduke#define ARM_AT91_IF_ATEREG_H 290Sduke 300Sduke#define ETH_CTL 0x00 /* EMAC Control Register */ 310Sduke#define ETH_CFG 0x04 /* EMAC Configuration Register */ 32169Sohair#define ETH_SR 0x08 /* EMAC STatus Register */ 330Sduke#define ETH_TAR 0x0c /* EMAC Transmit Address Register */ 340Sduke#define ETH_TCR 0x10 /* EMAC Transmit Control Register */ 35169Sohair#define ETH_TSR 0x14 /* EMAC Transmit Status Register */ 360Sduke#define ETH_RBQP 0x18 /* EMAC Receive Buffer Queue Pointer */ 37169Sohair /* 0x1c reserved */ 380Sduke#define ETH_RSR 0x20 /* EMAC Receive Status Register */ 39#define ETH_ISR 0x24 /* EMAC Interrupt Status Register */ 40#define ETH_IER 0x28 /* EMAC Interrupt Enable Register */ 41#define ETH_IDR 0x2c /* EMAC Interrupt Disable Register */ 42#define ETH_IMR 0x30 /* EMAC Interrupt Mask Register */ 43#define ETH_MAN 0x34 /* EMAC PHY Maintenance Register */ 44 /* 0x38 reserved */ 45 /* 0x3c reserved */ 46#define ETH_FRA 0x40 /* Frames Transmitted OK Register */ 47#define ETH_SCOL 0x44 /* Single Collision Frame Register */ 48#define ETH_MCOL 0x48 /* Multiple Collision Frame Register */ 49#define ETH_OK 0x4c /* Frames Received OK Register */ 50#define ETH_SEQE 0x50 /* Frame Check Sequence Error Reg */ 51#define ETH_ALE 0x54 /* Alignment Error Register */ 52#define ETH_DTE 0x58 /* Deferred Transmittion Frame Reg */ 53#define ETH_LCOL 0x5c /* Late Collision Register */ 54#define ETH_ECOL 0x60 /* Excessive Collision Register */ 55#define ETH_TUE 0x64 /* Transmit Underrun Error Register */ 56#define ETH_CSE 0x68 /* Carrier Sense Error Register */ 57#define ETH_DRFC 0x6c /* Discarded RX Frame Register */ 58#define ETH_ROV 0x68 /* Receive Overrun Register */ 59#define ETH_CDE 0x64 /* Code Error Register */ 60#define ETH_ELR 0x78 /* Excessive Length Error Register */ 61#define ETH_RJB 0x7c /* Receive Jabber Register */ 62#define ETH_USF 0x80 /* Undersize Frame Register */ 63#define ETH_SQEE 0x84 /* SQE Test Error Register */ 64 /* 0x88 reserved */ 65 /* 0x8c reserved */ 66#define ETH_HSH 0x90 /* EMAC Hash Address High [63:32] */ 67#define ETH_HSL 0x94 /* EMAC Hash Address Low [31:0] */ 68#define ETH_SA1L 0x98 /* EMAC Specific Address 1 Low */ 69#define ETH_SA1H 0x9c /* EMAC Specific Address 1 High */ 70#define ETH_SA2L 0xa0 /* EMAC Specific Address 2 Low */ 71#define ETH_SA2H 0xa4 /* EMAC Specific Address 2 High */ 72#define ETH_SA3L 0xa8 /* EMAC Specific Address 3 Low */ 73#define ETH_SA3H 0xac /* EMAC Specific Address 3 High */ 74#define ETH_SA4L 0xb0 /* EMAC Specific Address 4 Low */ 75#define ETH_SA4H 0xb4 /* EMAC Specific Address 4 High */ 76 77 78/* ETH_CTL */ 79#define ETH_CTL_LB (1U << 0) /* LB: Loopback */ 80#define ETH_CTL_LBL (1U << 1) /* LBL: Loopback Local */ 81#define ETH_CTL_RE (1U << 2) /* RE: Receive Enable */ 82#define ETH_CTL_TE (1U << 3) /* TE: Transmit Enable */ 83#define ETH_CTL_MPE (1U << 4) /* MPE: Management Port Enable */ 84#define ETH_CTL_CSR (1U << 5) /* CSR: Clear Statistics Registers */ 85#define ETH_CTL_ISR (1U << 6) /* ISR: Incremenet Statistics Regs */ 86#define ETH_CTL_WES (1U << 7) /* WES: Write Enable Statistics regs */ 87#define ETH_CTL_BP (1U << 8) /* BP: Back Pressure */ 88 89/* ETH_CFG */ 90#define ETH_CFG_SPD (1U << 0) /* SPD: Speed 1 == 100: 0 == 10 */ 91#define ETH_CFG_FD (1U << 1) /* FD: Full duplex */ 92#define ETH_CFG_BR (1U << 2) /* BR: Bit Rate (optional?) */ 93 /* bit 3 reserved */ 94#define ETH_CFG_CAF (1U << 4) /* CAF: Copy All Frames */ 95#define ETH_CFG_NBC (1U << 5) /* NBC: No Broadcast */ 96#define ETH_CFG_MTI (1U << 6) /* MTI: Multicast Hash Enable */ 97#define ETH_CFG_UNI (1U << 7) /* UNI: Unicast Hash Enable */ 98#define ETH_CFG_BIG (1U << 8) /* BIG: Receive 1522 Bytes */ 99#define ETH_CFG_EAE (1U << 9) /* EAE: External Address Match En */ 100#define ETH_CFG_CLK_8 (0U << 10) /* CLK: Clock / 8 */ 101#define ETH_CFG_CLK_16 (1U << 10) /* CLK: Clock / 16 */ 102#define ETH_CFG_CLK_32 (2U << 10) /* CLK: Clock / 32 */ 103#define ETH_CFG_CLK_64 (3U << 10) /* CLK: Clock / 64 */ 104#define ETH_CFG_RTY (1U << 12) /* RTY: Retry Test*/ 105#define ETH_CFG_RMII (1U << 13) /* RMII: Reduce MII */ 106 107/* ETH_SR */ 108#define ETH_SR_LINK (1U << 0) /* Reserved! */ 109#define ETH_SR_MDIO (1U << 1) /* MDIO pin status */ 110#define ETH_SR_IDLE (1U << 2) /* IDLE (PHY logic) */ 111 112/* ETH_TCR */ 113#define ETH_TCR_NCRC (1U << 15) /* NCRC: No CRC */ 114 115/* ETH_TSR */ 116#define ETH_TSR_OVR (1U << 0) /* OVR: Ethernet Transmit Overrun */ 117#define ETH_TSR_COL (1U << 1) /* COL: Collision Occurred */ 118#define ETH_TSR_RLE (1U << 2) /* RLE: Retry Limit Exceeded */ 119#define ETH_TSR_IDLE (1U << 3) /* IDLE: Transmitter Idle */ 120#define ETH_TSR_BNQ (1U << 4) /* BNQ: Enet Tran Buff not Queued */ 121#define ETH_TSR_COMP (1U << 5) /* COMP: Transmit Complete */ 122#define ETH_TSR_UND (1U << 6) /* UND: Transmit Underrun */ 123#define ETH_TSR_WR_MASK (0x67) /* write 1 to clear bits */ 124 125/* ETH_RSR */ 126#define ETH_RSR_BNA (1U << 0) /* BNA: Buffer Not Available */ 127#define ETH_RSR_REC (1U << 1) /* REC: Frame Received */ 128#define ETH_RSR_OVR (1U << 2) /* OVR: RX Overrun */ 129 130/* ETH_ISR */ 131#define ETH_ISR_DONE (1U << 0) /* DONE: Management Done */ 132#define ETH_ISR_RCOM (1U << 1) /* RCOM: Receive Complete */ 133#define ETH_ISR_RBNA (1U << 2) /* RBNA: Receive Buffer Not Avail */ 134#define ETH_ISR_TOVR (1U << 3) /* TOVR: Transmit Buffer Overrun */ 135#define ETH_ISR_TUND (1U << 4) /* TUND: Transmit Buffer Underrun */ 136#define ETH_ISR_RTRY (1U << 5) /* RTRY: Retry Limit */ 137#define ETH_ISR_TBRE (1U << 6) /* TBRE: Trasnmit Buffer Reg empty */ 138#define ETH_ISR_TCOM (1U << 7) /* TCOM: Transmit Complete */ 139#define ETH_ISR_TIDLE (1U << 8) /* TIDLE: Transmit Idle */ 140#define ETH_ISR_LINK (1U << 9) /* LINK: Link pin delta (optional) */ 141#define ETH_ISR_ROVR (1U << 10) /* ROVR: RX Overrun */ 142#define ETH_ISR_ABT (1U << 11) /* ABT: Abort */ 143 144/* ETH_MAN */ 145#define ETH_MAN_BITS 0x40020000 /* HIGH and CODE bits */ 146#define ETH_MAN_READ (2U << 28) 147#define ETH_MAN_WRITE (1U << 28) 148#define ETH_MAN_PHYA_BIT 23 149#define ETH_MAN_REGA_BIT 18 150#define ETH_MAN_VALUE_MASK 0xffffU 151#define ETH_MAN_REG_WR(phy, reg, val) \ 152 (ETH_MAN_BITS | ETH_MAN_WRITE | ((phy) << ETH_MAN_PHYA_BIT) | \ 153 ((reg) << ETH_MAN_REGA_BIT) | ((val) & ETH_MAN_VALUE_MASK)) 154#define ETH_MAN_REG_RD(phy, reg) \ 155 (ETH_MAN_BITS | ETH_MAN_READ | ((phy) << ETH_MAN_PHYA_BIT) | \ 156 ((reg) << ETH_MAN_REGA_BIT)) 157 158typedef struct { 159 uint32_t addr; 160#define ETH_CPU_OWNER (1U << 0) 161#define ETH_WRAP_BIT (1U << 1) 162 uint32_t status; 163#define ETH_LEN_MASK 0x7ff 164#define ETH_MAC_LOCAL_4 (1U << 23) /* Packet matched addr 4 */ 165#define ETH_MAC_LOCAL_3 (1U << 24) /* Packet matched addr 3 */ 166#define ETH_MAC_LOCAL_2 (1U << 25) /* Packet matched addr 2 */ 167#define ETH_MAC_LOCAL_1 (1U << 26) /* Packet matched addr 1 */ 168#define ETH_MAC_UNK (1U << 27) /* Unkown source address RFU */ 169#define ETH_MAC_EXT (1U << 28) /* External Address */ 170#define ETH_MAC_UCAST (1U << 29) /* Unicast hash match */ 171#define ETH_MAC_MCAST (1U << 30) /* Multicast hash match */ 172#define ETH_MAC_ONES (1U << 31) /* Global all ones bcast addr */ 173} eth_rx_desc_t; 174 175#endif /* ARM_AT91_IF_ATEREG_H */ 176