if_ate.c revision 213894
1/*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * Copyright (c) 2009 Greg Ansley. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* TODO 28 * 29 * 1) Turn on the clock in pmc? Turn off? 30 * 2) GPIO initializtion in board setup code. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/arm/at91/if_ate.c 213894 2010-10-15 15:00:30Z marius $"); 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/bus.h> 39#include <sys/kernel.h> 40#include <sys/malloc.h> 41#include <sys/mbuf.h> 42#include <sys/module.h> 43#include <sys/rman.h> 44#include <sys/socket.h> 45#include <sys/sockio.h> 46#include <sys/sysctl.h> 47 48#include <machine/bus.h> 49 50#include <net/ethernet.h> 51#include <net/if.h> 52#include <net/if_arp.h> 53#include <net/if_dl.h> 54#include <net/if_media.h> 55#include <net/if_mib.h> 56#include <net/if_types.h> 57 58#ifdef INET 59#include <netinet/in.h> 60#include <netinet/in_systm.h> 61#include <netinet/in_var.h> 62#include <netinet/ip.h> 63#endif 64 65#include <net/bpf.h> 66#include <net/bpfdesc.h> 67 68#include <dev/mii/mii.h> 69#include <dev/mii/miivar.h> 70 71#include "opt_at91.h" 72#include <arm/at91/at91reg.h> 73#include <arm/at91/at91var.h> 74#include <arm/at91/if_atereg.h> 75 76#include "miibus_if.h" 77 78/* 79 * Driver-specific flags. 80 */ 81#define ATE_FLAG_DETACHING 0x01 82#define ATE_FLAG_MULTICAST 0x02 83 84/* 85 * Old EMAC assumes whole packet fits in one buffer; 86 * new EBACB assumes all receive buffers are 128 bytes 87 */ 88#define RX_BUF_SIZE(sc) (sc->is_emacb ? 128 : MCLBYTES) 89 90/* 91 * EMACB has an 11 bit counter for Rx/Tx Descriptors 92 * for max total of 1024 decriptors each. 93 */ 94#define ATE_MAX_RX_DESCR 1024 95#define ATE_MAX_TX_DESCR 1024 96 97/* How many buffers to allocate */ 98#define ATE_MAX_TX_BUFFERS 4 /* We have ping-pong tx buffers */ 99 100/* How much memory to use for rx buffers */ 101#define ATE_RX_MEMORY (ATE_MAX_RX_DESCR * 128) 102 103/* Actual number of descriptors we allocate */ 104#define ATE_NUM_RX_DESCR ATE_MAX_RX_DESCR 105#define ATE_NUM_TX_DESCR ATE_MAX_TX_BUFFERS 106 107#if ATE_NUM_TX_DESCR > ATE_MAX_TX_DESCR 108#error "Can't have more TX buffers that descriptors" 109#endif 110#if ATE_NUM_RX_DESCR > ATE_MAX_RX_DESCR 111#error "Can't have more RX buffers that descriptors" 112#endif 113 114/* Wrap indexes the same way the hardware does */ 115#define NEXT_RX_IDX(sc, cur) \ 116 ((sc->rx_descs[cur].addr & ETH_WRAP_BIT) ? 0 : (cur + 1)) 117 118#define NEXT_TX_IDX(sc, cur) \ 119 ((sc->tx_descs[cur].status & ETHB_TX_WRAP) ? 0 : (cur + 1)) 120 121struct ate_softc 122{ 123 struct ifnet *ifp; /* ifnet pointer */ 124 struct mtx sc_mtx; /* Basically a perimeter lock */ 125 device_t dev; /* Myself */ 126 device_t miibus; /* My child miibus */ 127 struct resource *irq_res; /* IRQ resource */ 128 struct resource *mem_res; /* Memory resource */ 129 struct callout tick_ch; /* Tick callout */ 130 struct ifmib_iso_8802_3 mibdata; /* Stuff for network mgmt */ 131 bus_dma_tag_t mtag; /* bus dma tag for mbufs */ 132 bus_dma_tag_t rx_tag; 133 bus_dma_tag_t rx_desc_tag; 134 bus_dmamap_t rx_desc_map; 135 bus_dmamap_t rx_map[ATE_MAX_RX_DESCR]; 136 bus_addr_t rx_desc_phys; /* PA of rx descriptors */ 137 eth_rx_desc_t *rx_descs; /* VA of rx descriptors */ 138 void *rx_buf[ATE_NUM_RX_DESCR]; /* RX buffer space */ 139 int rxhead; /* Current RX map/desc index */ 140 uint32_t rx_buf_size; /* Size of Rx buffers */ 141 142 bus_dma_tag_t tx_desc_tag; 143 bus_dmamap_t tx_desc_map; 144 bus_dmamap_t tx_map[ATE_MAX_TX_BUFFERS]; 145 bus_addr_t tx_desc_phys; /* PA of tx descriptors */ 146 eth_tx_desc_t *tx_descs; /* VA of tx descriptors */ 147 int txhead; /* Current TX map/desc index */ 148 int txtail; /* Current TX map/desc index */ 149 struct mbuf *sent_mbuf[ATE_MAX_TX_BUFFERS]; /* Sent mbufs */ 150 void *intrhand; /* Interrupt handle */ 151 int flags; 152 int if_flags; 153 int use_rmii; 154 int is_emacb; /* SAM9x hardware version */ 155}; 156 157static inline uint32_t 158RD4(struct ate_softc *sc, bus_size_t off) 159{ 160 161 return (bus_read_4(sc->mem_res, off)); 162} 163 164static inline void 165WR4(struct ate_softc *sc, bus_size_t off, uint32_t val) 166{ 167 168 bus_write_4(sc->mem_res, off, val); 169} 170 171static inline void 172BARRIER(struct ate_softc *sc, bus_size_t off, bus_size_t len, int flags) 173{ 174 175 bus_barrier(sc->mem_res, off, len, flags); 176} 177 178#define ATE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 179#define ATE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 180#define ATE_LOCK_INIT(_sc) \ 181 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 182 MTX_NETWORK_LOCK, MTX_DEF) 183#define ATE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 184#define ATE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 185#define ATE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 186 187static devclass_t ate_devclass; 188 189/* 190 * ifnet entry points. 191 */ 192static void ateinit_locked(void *); 193static void atestart_locked(struct ifnet *); 194 195static void ateinit(void *); 196static void atestart(struct ifnet *); 197static void atestop(struct ate_softc *); 198static int ateioctl(struct ifnet * ifp, u_long, caddr_t); 199 200/* 201 * Bus entry points. 202 */ 203static int ate_probe(device_t dev); 204static int ate_attach(device_t dev); 205static int ate_detach(device_t dev); 206static void ate_intr(void *); 207 208/* 209 * Helper routines. 210 */ 211static int ate_activate(device_t dev); 212static void ate_deactivate(struct ate_softc *sc); 213static int ate_ifmedia_upd(struct ifnet *ifp); 214static void ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 215static int ate_get_mac(struct ate_softc *sc, u_char *eaddr); 216static void ate_set_mac(struct ate_softc *sc, u_char *eaddr); 217static void ate_rxfilter(struct ate_softc *sc); 218 219static int ate_miibus_readreg(device_t dev, int phy, int reg); 220 221static int ate_miibus_writereg(device_t dev, int phy, int reg, int data); 222/* 223 * The AT91 family of products has the ethernet interface called EMAC. 224 * However, it isn't self identifying. It is anticipated that the parent bus 225 * code will take care to only add ate devices where they really are. As 226 * such, we do nothing here to identify the device and just set its name. 227 */ 228static int 229ate_probe(device_t dev) 230{ 231 232 device_set_desc(dev, "EMAC"); 233 return (0); 234} 235 236static int 237ate_attach(device_t dev) 238{ 239 struct ate_softc *sc; 240 struct ifnet *ifp = NULL; 241 struct sysctl_ctx_list *sctx; 242 struct sysctl_oid *soid; 243 u_char eaddr[ETHER_ADDR_LEN]; 244 uint32_t rnd; 245 int rid, err; 246 247 sc = device_get_softc(dev); 248 sc->dev = dev; 249 ATE_LOCK_INIT(sc); 250 251 rid = 0; 252 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 253 RF_ACTIVE); 254 if (sc->mem_res == NULL) { 255 device_printf(dev, "could not allocate memory resources.\n"); 256 err = ENOMEM; 257 goto out; 258 } 259 rid = 0; 260 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 261 RF_ACTIVE); 262 if (sc->irq_res == NULL) { 263 device_printf(dev, "could not allocate interrupt resources.\n"); 264 err = ENOMEM; 265 goto out; 266 } 267 268 /* New or old version, chooses buffer size. */ 269 sc->is_emacb = at91_is_sam9(); 270 sc->rx_buf_size = RX_BUF_SIZE(sc); 271 272 err = ate_activate(dev); 273 if (err) 274 goto out; 275 276 /* Default to what boot rom did */ 277 if (!sc->is_emacb) 278 sc->use_rmii = 279 (RD4(sc, ETH_CFG) & ETH_CFG_RMII) == ETH_CFG_RMII; 280 else 281 sc->use_rmii = 282 (RD4(sc, ETHB_UIO) & ETHB_UIO_RMII) == ETHB_UIO_RMII; 283 284#ifdef AT91_ATE_USE_RMII 285 /* Compile time override */ 286 sc->use_rmii = 1; 287#endif 288 /* Sysctls */ 289 sctx = device_get_sysctl_ctx(dev); 290 soid = device_get_sysctl_tree(dev); 291 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "rmii", 292 CTLFLAG_RW, &sc->use_rmii, 0, "rmii in use"); 293 294 /* Calling atestop before ifp is set is OK. */ 295 ATE_LOCK(sc); 296 atestop(sc); 297 ATE_UNLOCK(sc); 298 callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 299 300 if ((err = ate_get_mac(sc, eaddr)) != 0) { 301 /* No MAC address configured. Generate the random one. */ 302 if (bootverbose) 303 device_printf(dev, 304 "Generating random ethernet address.\n"); 305 rnd = arc4random(); 306 307 /* 308 * Set OUI to convenient locally assigned address. 'b' 309 * is 0x62, which has the locally assigned bit set, and 310 * the broadcast/multicast bit clear. 311 */ 312 eaddr[0] = 'b'; 313 eaddr[1] = 's'; 314 eaddr[2] = 'd'; 315 eaddr[3] = (rnd >> 16) & 0xff; 316 eaddr[4] = (rnd >> 8) & 0xff; 317 eaddr[5] = (rnd >> 0) & 0xff; 318 } 319 320 sc->ifp = ifp = if_alloc(IFT_ETHER); 321 err = mii_attach(dev, &sc->miibus, ifp, ate_ifmedia_upd, 322 ate_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 323 device_printf(dev, "Cannot find my PHY.\n"); 324 if (err != 0) { 325 device_printf(dev, "attaching PHYs failed\n"); 326 goto out; 327 } 328 /* 329 * XXX: Clear the isolate bit, or we won't get up, 330 * at least on the HL201 331 */ 332 ate_miibus_writereg(dev, 0, 0, 0x3000); 333 334 ifp->if_softc = sc; 335 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 336 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 337 ifp->if_capabilities |= IFCAP_VLAN_MTU; 338 ifp->if_capenable |= IFCAP_VLAN_MTU; /* The hw bits already set. */ 339 ifp->if_start = atestart; 340 ifp->if_ioctl = ateioctl; 341 ifp->if_init = ateinit; 342 ifp->if_baudrate = 10000000; 343 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 344 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 345 IFQ_SET_READY(&ifp->if_snd); 346 ifp->if_linkmib = &sc->mibdata; 347 ifp->if_linkmiblen = sizeof(sc->mibdata); 348 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 349 sc->if_flags = ifp->if_flags; 350 351 ether_ifattach(ifp, eaddr); 352 353 /* Activate the interrupt. */ 354 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 355 NULL, ate_intr, sc, &sc->intrhand); 356 if (err) { 357 device_printf(dev, "could not establish interrupt handler.\n"); 358 ether_ifdetach(ifp); 359 goto out; 360 } 361 362out: 363 if (err) 364 ate_detach(dev); 365 return (err); 366} 367 368static int 369ate_detach(device_t dev) 370{ 371 struct ate_softc *sc; 372 struct ifnet *ifp; 373 374 sc = device_get_softc(dev); 375 KASSERT(sc != NULL, ("[ate: %d]: sc is NULL", __LINE__)); 376 ifp = sc->ifp; 377 if (device_is_attached(dev)) { 378 ATE_LOCK(sc); 379 sc->flags |= ATE_FLAG_DETACHING; 380 atestop(sc); 381 ATE_UNLOCK(sc); 382 callout_drain(&sc->tick_ch); 383 ether_ifdetach(ifp); 384 } 385 if (sc->miibus != NULL) { 386 device_delete_child(dev, sc->miibus); 387 sc->miibus = NULL; 388 } 389 bus_generic_detach(sc->dev); 390 ate_deactivate(sc); 391 if (sc->intrhand != NULL) { 392 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 393 sc->intrhand = NULL; 394 } 395 if (ifp != NULL) { 396 if_free(ifp); 397 sc->ifp = NULL; 398 } 399 if (sc->mem_res != NULL) { 400 bus_release_resource(dev, SYS_RES_IOPORT, 401 rman_get_rid(sc->mem_res), sc->mem_res); 402 sc->mem_res = NULL; 403 } 404 if (sc->irq_res != NULL) { 405 bus_release_resource(dev, SYS_RES_IRQ, 406 rman_get_rid(sc->irq_res), sc->irq_res); 407 sc->irq_res = NULL; 408 } 409 ATE_LOCK_DESTROY(sc); 410 return (0); 411} 412 413static void 414ate_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 415{ 416 417 if (error != 0) 418 return; 419 *(bus_addr_t *)arg = segs[0].ds_addr; 420} 421 422static void 423ate_load_rx_buf(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 424{ 425 struct ate_softc *sc; 426 427 if (error != 0) 428 return; 429 sc = (struct ate_softc *)arg; 430 431 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 432 sc->rx_descs[sc->rxhead].addr = segs[0].ds_addr; 433 sc->rx_descs[sc->rxhead].status = 0; 434 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_POSTWRITE); 435} 436 437/* 438 * Compute the multicast filter for this device. 439 */ 440static int 441ate_setmcast(struct ate_softc *sc) 442{ 443 uint32_t index; 444 uint32_t mcaf[2]; 445 u_char *af = (u_char *) mcaf; 446 struct ifmultiaddr *ifma; 447 struct ifnet *ifp; 448 449 ifp = sc->ifp; 450 451 if ((ifp->if_flags & IFF_PROMISC) != 0) 452 return (0); 453 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 454 WR4(sc, ETH_HSL, 0xffffffff); 455 WR4(sc, ETH_HSH, 0xffffffff); 456 return (1); 457 } 458 459 /* Compute the multicast hash. */ 460 mcaf[0] = 0; 461 mcaf[1] = 0; 462 if_maddr_rlock(ifp); 463 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 464 if (ifma->ifma_addr->sa_family != AF_LINK) 465 continue; 466 index = ether_crc32_be(LLADDR((struct sockaddr_dl *) 467 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 468 af[index >> 3] |= 1 << (index & 7); 469 } 470 if_maddr_runlock(ifp); 471 472 /* 473 * Write the hash to the hash register. This card can also 474 * accept unicast packets as well as multicast packets using this 475 * register for easier bridging operations, but we don't take 476 * advantage of that. Locks here are to avoid LOR with the 477 * if_maddr_rlock, but might not be strictly necessary. 478 */ 479 WR4(sc, ETH_HSL, mcaf[0]); 480 WR4(sc, ETH_HSH, mcaf[1]); 481 return (mcaf[0] || mcaf[1]); 482} 483 484static int 485ate_activate(device_t dev) 486{ 487 struct ate_softc *sc; 488 int i; 489 490 sc = device_get_softc(dev); 491 492 /* Allocate DMA tags and maps for TX mbufs */ 493 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 494 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 495 1, MCLBYTES, 0, busdma_lock_mutex, &sc->sc_mtx, &sc->mtag)) 496 goto errout; 497 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 498 if ( bus_dmamap_create(sc->mtag, 0, &sc->tx_map[i])) 499 goto errout; 500 } 501 502 503 /* DMA tag and map for the RX descriptors. */ 504 if (bus_dma_tag_create(bus_get_dma_tag(dev), sizeof(eth_rx_desc_t), 505 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 506 ATE_NUM_RX_DESCR * sizeof(eth_rx_desc_t), 1, 507 ATE_NUM_RX_DESCR * sizeof(eth_rx_desc_t), 0, busdma_lock_mutex, 508 &sc->sc_mtx, &sc->rx_desc_tag)) 509 goto errout; 510 if (bus_dmamem_alloc(sc->rx_desc_tag, (void **)&sc->rx_descs, 511 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->rx_desc_map) != 0) 512 goto errout; 513 if (bus_dmamap_load(sc->rx_desc_tag, sc->rx_desc_map, 514 sc->rx_descs, ATE_NUM_RX_DESCR * sizeof(eth_rx_desc_t), 515 ate_getaddr, &sc->rx_desc_phys, 0) != 0) 516 goto errout; 517 518 /* Allocate DMA tags and maps for RX. buffers */ 519 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 520 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 521 sc->rx_buf_size, 1, sc->rx_buf_size, 0, 522 busdma_lock_mutex, &sc->sc_mtx, &sc->rx_tag)) 523 goto errout; 524 525 /* 526 * Allocate our RX buffers. 527 * This chip has a RX structure that's filled in. 528 * XXX On MACB (SAM9 part) we should receive directly into mbuf 529 * to avoid the copy. XXX 530 */ 531 sc->rxhead = 0; 532 for (sc->rxhead = 0; sc->rxhead < ATE_RX_MEMORY/sc->rx_buf_size; 533 sc->rxhead++) { 534 if (bus_dmamem_alloc(sc->rx_tag, 535 (void **)&sc->rx_buf[sc->rxhead], BUS_DMA_NOWAIT, 536 &sc->rx_map[sc->rxhead]) != 0) 537 goto errout; 538 539 if (bus_dmamap_load(sc->rx_tag, sc->rx_map[sc->rxhead], 540 sc->rx_buf[sc->rxhead], sc->rx_buf_size, 541 ate_load_rx_buf, sc, 0) != 0) { 542 printf("bus_dmamem_load\n"); 543 goto errout; 544 } 545 bus_dmamap_sync(sc->rx_tag, sc->rx_map[sc->rxhead], BUS_DMASYNC_PREREAD); 546 } 547 548 /* 549 * For the last buffer, set the wrap bit so the controller 550 * restarts from the first descriptor. 551 */ 552 sc->rx_descs[--sc->rxhead].addr |= ETH_WRAP_BIT; 553 sc->rxhead = 0; 554 555 /* Flush the memory for the EMAC rx descriptor. */ 556 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 557 558 /* Write the descriptor queue address. */ 559 WR4(sc, ETH_RBQP, sc->rx_desc_phys); 560 561 /* 562 * DMA tag and map for the TX descriptors. 563 * XXX Old EMAC (not EMACB) doesn't really need DMA'able 564 * memory. We could just malloc it. gja XXX 565 */ 566 if (bus_dma_tag_create(bus_get_dma_tag(dev), sizeof(eth_tx_desc_t), 567 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 568 ATE_MAX_TX_BUFFERS * sizeof(eth_tx_desc_t), 1, 569 ATE_MAX_TX_BUFFERS * sizeof(eth_tx_desc_t), 0, busdma_lock_mutex, 570 &sc->sc_mtx, &sc->tx_desc_tag) != 0) 571 goto errout; 572 573 if (bus_dmamem_alloc(sc->tx_desc_tag, (void **)&sc->tx_descs, 574 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->tx_desc_map) != 0) 575 goto errout; 576 577 if (bus_dmamap_load(sc->tx_desc_tag, sc->tx_desc_map, 578 sc->tx_descs, ATE_MAX_TX_BUFFERS * sizeof(eth_tx_desc_t), 579 ate_getaddr, &sc->tx_desc_phys, 0) != 0) 580 goto errout; 581 582 /* Initilize descriptors; mark all empty */ 583 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 584 sc->tx_descs[i].addr =0; 585 sc->tx_descs[i].status = ETHB_TX_USED; 586 sc->sent_mbuf[i] = NULL; 587 } 588 589 /* Mark last entry to cause wrap when indexing through */ 590 sc->tx_descs[ATE_MAX_TX_BUFFERS - 1].status = 591 ETHB_TX_WRAP | ETHB_TX_USED; 592 593 /* Flush the memory for the EMAC tx descriptor. */ 594 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, BUS_DMASYNC_PREWRITE); 595 596 sc->txhead = sc->txtail = 0; 597 if (sc->is_emacb) { 598 /* Write the descriptor queue address. */ 599 WR4(sc, ETHB_TBQP, sc->tx_desc_phys); 600 } 601 602 /* EMACB: Enable transceiver input clock */ 603 if (sc->is_emacb) 604 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) | ETHB_UIO_CLKE); 605 606 return (0); 607 608errout: 609 return (ENOMEM); 610} 611 612static void 613ate_deactivate(struct ate_softc *sc) 614{ 615 int i; 616 617 KASSERT(sc != NULL, ("[ate, %d]: sc is NULL!", __LINE__)); 618 if (sc->mtag != NULL) { 619 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 620 if (sc->sent_mbuf[i] != NULL) { 621 bus_dmamap_sync(sc->mtag, sc->tx_map[i], 622 BUS_DMASYNC_POSTWRITE); 623 bus_dmamap_unload(sc->mtag, sc->tx_map[i]); 624 m_freem(sc->sent_mbuf[i]); 625 } 626 bus_dmamap_destroy(sc->mtag, sc->tx_map[i]); 627 sc->sent_mbuf[i] = NULL; 628 sc->tx_map[i] = NULL; 629 } 630 bus_dma_tag_destroy(sc->mtag); 631 } 632 if (sc->rx_desc_tag != NULL) { 633 if (sc->rx_descs != NULL) { 634 if (sc->rx_desc_phys != 0) { 635 bus_dmamap_sync(sc->rx_desc_tag, 636 sc->rx_desc_map, BUS_DMASYNC_POSTREAD); 637 bus_dmamap_unload(sc->rx_desc_tag, 638 sc->rx_desc_map); 639 sc->rx_desc_phys = 0; 640 } 641 } 642 } 643 if (sc->rx_tag != NULL) { 644 for (i = 0; sc->rx_buf[i] != NULL; i++) { 645 if (sc->rx_descs[i].addr != 0) { 646 bus_dmamap_sync(sc->rx_tag, 647 sc->rx_map[i], 648 BUS_DMASYNC_POSTREAD); 649 bus_dmamap_unload(sc->rx_tag, 650 sc->rx_map[i]); 651 sc->rx_descs[i].addr = 0; 652 } 653 bus_dmamem_free(sc->rx_tag, sc->rx_buf[i], 654 sc->rx_map[i]); 655 sc->rx_buf[i] = NULL; 656 sc->rx_map[i] = NULL; 657 } 658 bus_dma_tag_destroy(sc->rx_tag); 659 } 660 if (sc->rx_desc_tag != NULL) { 661 if (sc->rx_descs != NULL) 662 bus_dmamem_free(sc->rx_desc_tag, sc->rx_descs, 663 sc->rx_desc_map); 664 bus_dma_tag_destroy(sc->rx_desc_tag); 665 sc->rx_descs = NULL; 666 sc->rx_desc_tag = NULL; 667 } 668 669 if (sc->is_emacb) 670 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) & ~ETHB_UIO_CLKE); 671} 672 673/* 674 * Change media according to request. 675 */ 676static int 677ate_ifmedia_upd(struct ifnet *ifp) 678{ 679 struct ate_softc *sc = ifp->if_softc; 680 struct mii_data *mii; 681 682 mii = device_get_softc(sc->miibus); 683 ATE_LOCK(sc); 684 mii_mediachg(mii); 685 ATE_UNLOCK(sc); 686 return (0); 687} 688 689/* 690 * Notify the world which media we're using. 691 */ 692static void 693ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 694{ 695 struct ate_softc *sc = ifp->if_softc; 696 struct mii_data *mii; 697 698 mii = device_get_softc(sc->miibus); 699 ATE_LOCK(sc); 700 mii_pollstat(mii); 701 ifmr->ifm_active = mii->mii_media_active; 702 ifmr->ifm_status = mii->mii_media_status; 703 ATE_UNLOCK(sc); 704} 705 706static void 707ate_stat_update(struct ate_softc *sc, int active) 708{ 709 uint32_t reg; 710 711 /* 712 * The speed and full/half-duplex state needs to be reflected 713 * in the ETH_CFG register. 714 */ 715 reg = RD4(sc, ETH_CFG); 716 reg &= ~(ETH_CFG_SPD | ETH_CFG_FD); 717 if (IFM_SUBTYPE(active) != IFM_10_T) 718 reg |= ETH_CFG_SPD; 719 if (active & IFM_FDX) 720 reg |= ETH_CFG_FD; 721 WR4(sc, ETH_CFG, reg); 722} 723 724static void 725ate_tick(void *xsc) 726{ 727 struct ate_softc *sc = xsc; 728 struct ifnet *ifp = sc->ifp; 729 struct mii_data *mii; 730 int active; 731 uint32_t c; 732 733 /* 734 * The KB920x boot loader tests ETH_SR & ETH_SR_LINK and will ask 735 * the MII if there's a link if this bit is clear. Not sure if we 736 * should do the same thing here or not. 737 */ 738 ATE_ASSERT_LOCKED(sc); 739 if (sc->miibus != NULL) { 740 mii = device_get_softc(sc->miibus); 741 active = mii->mii_media_active; 742 mii_tick(mii); 743 if (mii->mii_media_status & IFM_ACTIVE && 744 active != mii->mii_media_active) 745 ate_stat_update(sc, mii->mii_media_active); 746 } 747 748 /* 749 * Update the stats as best we can. When we're done, clear 750 * the status counters and start over. We're supposed to read these 751 * registers often enough that they won't overflow. Hopefully 752 * once a second is often enough. Some don't map well to 753 * the dot3Stats mib, so for those we just count them as general 754 * errors. Stats for iframes, ibutes, oframes and obytes are 755 * collected elsewhere. These registers zero on a read to prevent 756 * races. For all the collision stats, also update the collision 757 * stats for the interface. 758 */ 759 sc->mibdata.dot3StatsAlignmentErrors += RD4(sc, ETH_ALE); 760 sc->mibdata.dot3StatsFCSErrors += RD4(sc, ETH_SEQE); 761 c = RD4(sc, ETH_SCOL); 762 ifp->if_collisions += c; 763 sc->mibdata.dot3StatsSingleCollisionFrames += c; 764 c = RD4(sc, ETH_MCOL); 765 sc->mibdata.dot3StatsMultipleCollisionFrames += c; 766 ifp->if_collisions += c; 767 sc->mibdata.dot3StatsSQETestErrors += RD4(sc, ETH_SQEE); 768 sc->mibdata.dot3StatsDeferredTransmissions += RD4(sc, ETH_DTE); 769 c = RD4(sc, ETH_LCOL); 770 sc->mibdata.dot3StatsLateCollisions += c; 771 ifp->if_collisions += c; 772 c = RD4(sc, ETH_ECOL); 773 sc->mibdata.dot3StatsExcessiveCollisions += c; 774 ifp->if_collisions += c; 775 sc->mibdata.dot3StatsCarrierSenseErrors += RD4(sc, ETH_CSE); 776 sc->mibdata.dot3StatsFrameTooLongs += RD4(sc, ETH_ELR); 777 sc->mibdata.dot3StatsInternalMacReceiveErrors += RD4(sc, ETH_DRFC); 778 779 /* 780 * Not sure where to lump these, so count them against the errors 781 * for the interface. 782 */ 783 sc->ifp->if_oerrors += RD4(sc, ETH_TUE); 784 sc->ifp->if_ierrors += RD4(sc, ETH_CDE) + RD4(sc, ETH_RJB) + 785 RD4(sc, ETH_USF); 786 787 /* Schedule another timeout one second from now. */ 788 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 789} 790 791static void 792ate_set_mac(struct ate_softc *sc, u_char *eaddr) 793{ 794 795 WR4(sc, ETH_SA1L, (eaddr[3] << 24) | (eaddr[2] << 16) | 796 (eaddr[1] << 8) | eaddr[0]); 797 WR4(sc, ETH_SA1H, (eaddr[5] << 8) | (eaddr[4])); 798} 799 800static int 801ate_get_mac(struct ate_softc *sc, u_char *eaddr) 802{ 803 bus_size_t sa_low_reg[] = { ETH_SA1L, ETH_SA2L, ETH_SA3L, ETH_SA4L }; 804 bus_size_t sa_high_reg[] = { ETH_SA1H, ETH_SA2H, ETH_SA3H, ETH_SA4H }; 805 uint32_t low, high; 806 int i; 807 808 /* 809 * The boot loader may setup the MAC with an address(es), grab the 810 * first MAC address from the SA[1-4][HL] registers. 811 */ 812 for (i = 0; i < 4; i++) { 813 low = RD4(sc, sa_low_reg[i]); 814 high = RD4(sc, sa_high_reg[i]); 815 if ((low | (high & 0xffff)) != 0) { 816 eaddr[0] = low & 0xff; 817 eaddr[1] = (low >> 8) & 0xff; 818 eaddr[2] = (low >> 16) & 0xff; 819 eaddr[3] = (low >> 24) & 0xff; 820 eaddr[4] = high & 0xff; 821 eaddr[5] = (high >> 8) & 0xff; 822 return (0); 823 } 824 } 825 return (ENXIO); 826} 827 828static void 829ate_intr(void *xsc) 830{ 831 struct ate_softc *sc = xsc; 832 struct ifnet *ifp = sc->ifp; 833 struct mbuf *mb; 834 eth_rx_desc_t *rxdhead; 835 uint32_t status, reg, idx; 836 int remain, count, done; 837 838 status = RD4(sc, ETH_ISR); 839 if (status == 0) 840 return; 841 842 if (status & ETH_ISR_RCOM) { 843 844 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 845 BUS_DMASYNC_POSTREAD); 846 847 rxdhead = &sc->rx_descs[sc->rxhead]; 848 while (rxdhead->addr & ETH_CPU_OWNER) { 849 if (!sc->is_emacb) { 850 /* 851 * Simulate SAM9 FIRST/LAST bits for RM9200. 852 * RM9200 EMAC has only on Rx buffer per packet. 853 * But sometime we are handed a zero lenght packet. 854 */ 855 if ((rxdhead->status & ETH_LEN_MASK) == 0) 856 rxdhead->status = 0; /* Mark error */ 857 else 858 rxdhead->status |= ETH_BUF_FIRST | ETH_BUF_LAST; 859 } 860 861 if ((rxdhead->status & ETH_BUF_FIRST) == 0) { 862 /* Something went wrong during RX so 863 release back to EMAC all buffers of invalid packets. 864 */ 865 rxdhead->status = 0; 866 rxdhead->addr &= ~ETH_CPU_OWNER; 867 sc->rxhead = NEXT_RX_IDX(sc, sc->rxhead); 868 rxdhead = &sc->rx_descs[sc->rxhead]; 869 continue; 870 } 871 872 /* Find end of packet or start of next */ 873 idx = sc->rxhead; 874 if ((sc->rx_descs[idx].status & ETH_BUF_LAST) == 0) { 875 idx = NEXT_RX_IDX(sc, idx); 876 877 while ((sc->rx_descs[idx].addr & ETH_CPU_OWNER) && 878 ((sc->rx_descs[idx].status & 879 (ETH_BUF_FIRST|ETH_BUF_LAST))== 0)) 880 idx = NEXT_RX_IDX(sc, idx); 881 } 882 883 /* Packet NOT yet completely in memory; we are done */ 884 if ((sc->rx_descs[idx].addr & ETH_CPU_OWNER) == 0 || 885 ((sc->rx_descs[idx].status & (ETH_BUF_FIRST|ETH_BUF_LAST))== 0)) 886 break; 887 888 /* Packets with no end descriptor are invalid. */ 889 if ((sc->rx_descs[idx].status & ETH_BUF_LAST) == 0) { 890 rxdhead->status &= ~ETH_BUF_FIRST; 891 continue; 892 } 893 894 /* FCS is not coppied into mbuf. */ 895 remain = (sc->rx_descs[idx].status & ETH_LEN_MASK) - 4; 896 897 /* Get an appropriately sized mbuf */ 898 if (remain + ETHER_ALIGN >= MINCLSIZE) 899 mb = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 900 else 901 MGETHDR(mb, M_DONTWAIT, MT_DATA); 902 903 if (mb == NULL) { 904 sc->ifp->if_iqdrops++; 905 rxdhead->status = 0; 906 continue; 907 } 908 mb->m_data += ETHER_ALIGN; 909 mb->m_pkthdr.rcvif = ifp; 910 911 WR4(sc, ETH_RSR, RD4(sc, ETH_RSR)); /* Reset status */ 912 913 /* Now we process the buffers that make up the packet */ 914 do { 915 916 /* Last buffer may just be 1-4 bytes of FCS so remain 917 * may be zero for last decriptor. */ 918 if (remain > 0) { 919 /* Make sure we get the current bytes */ 920 bus_dmamap_sync(sc->rx_tag, sc->rx_map[sc->rxhead], 921 BUS_DMASYNC_POSTREAD); 922 923 count = MIN(remain, sc->rx_buf_size); 924 925 /* XXX Performance robbing copy. Could 926 * recieve directly to mbufs if not an 927 * RM9200. XXX */ 928 m_append(mb, count, sc->rx_buf[sc->rxhead]); 929 remain -= count; 930 } 931 932 done = (rxdhead->status & ETH_BUF_LAST) != 0; 933 934 /* Return the descriptor to the EMAC */ 935 rxdhead->status = 0; 936 rxdhead->addr &= ~ETH_CPU_OWNER; 937 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 938 BUS_DMASYNC_PREWRITE); 939 940 /* Move on to next descriptor with wrap */ 941 sc->rxhead = NEXT_RX_IDX(sc, sc->rxhead); 942 rxdhead = &sc->rx_descs[sc->rxhead]; 943 944 } while (!done); 945 946 if (mb != NULL) { 947 ifp->if_ipackets++; 948 (*ifp->if_input)(ifp, mb); 949 } 950 } 951 } 952 953 954 if (status & ETH_ISR_TCOM) { 955 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, 956 BUS_DMASYNC_POSTREAD); 957 958 ATE_LOCK(sc); 959 /* XXX TSR register should be cleared */ 960 if (!sc->is_emacb) { 961 /* Simulate Transmit descriptor table */ 962 963 /* First packet done */ 964 if (sc->txtail < sc->txhead) 965 sc->tx_descs[sc->txtail].status |= ETHB_TX_USED; 966 967 /* Second Packet done */ 968 if (sc->txtail + 1 < sc->txhead && 969 RD4(sc, ETH_TSR) & ETH_TSR_IDLE) 970 sc->tx_descs[sc->txtail + 1].status |= ETHB_TX_USED; 971 } 972 973 while (sc->txtail != sc->txhead && 974 sc->tx_descs[sc->txtail].status & ETHB_TX_USED ) { 975 976 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txtail], 977 BUS_DMASYNC_POSTWRITE); 978 bus_dmamap_unload(sc->mtag, sc->tx_map[sc->txtail]); 979 m_freem(sc->sent_mbuf[sc->txtail]); 980 sc->tx_descs[sc->txtail].addr = 0; 981 sc->sent_mbuf[sc->txtail] = NULL; 982 983 ifp->if_opackets++; 984 sc->txtail = NEXT_TX_IDX(sc, sc->txtail); 985 } 986 987 /* Flush descriptors to EMAC */ 988 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, BUS_DMASYNC_PREWRITE); 989 990 /* 991 * We're no longer busy, so clear the busy flag and call the 992 * start routine to xmit more packets. 993 */ 994 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 995 atestart_locked(sc->ifp); 996 ATE_UNLOCK(sc); 997 } 998 999 if (status & ETH_ISR_RBNA) { 1000 /* Workaround RM9200 Errata #11 */ 1001 if (bootverbose) 1002 device_printf(sc->dev, "RBNA workaround\n"); 1003 reg = RD4(sc, ETH_CTL); 1004 WR4(sc, ETH_CTL, reg & ~ETH_CTL_RE); 1005 BARRIER(sc, ETH_CTL, 4, BUS_SPACE_BARRIER_WRITE); 1006 WR4(sc, ETH_CTL, reg | ETH_CTL_RE); 1007 } 1008} 1009 1010/* 1011 * Reset and initialize the chip. 1012 */ 1013static void 1014ateinit_locked(void *xsc) 1015{ 1016 struct ate_softc *sc = xsc; 1017 struct ifnet *ifp = sc->ifp; 1018 struct mii_data *mii; 1019 uint8_t eaddr[ETHER_ADDR_LEN]; 1020 uint32_t reg; 1021 1022 ATE_ASSERT_LOCKED(sc); 1023 1024 /* 1025 * XXX TODO(3) 1026 * we need to turn on the EMAC clock in the pmc. With the 1027 * default boot loader, this is already turned on. However, we 1028 * need to think about how best to turn it on/off as the interface 1029 * is brought up/down, as well as dealing with the mii bus... 1030 * 1031 * We also need to multiplex the pins correctly (in board_xxx.c). 1032 */ 1033 1034 /* 1035 * There are two different ways that the mii bus is connected 1036 * to this chip mii or rmii. 1037 */ 1038 if (!sc->is_emacb) { 1039 /* RM9200 */ 1040 reg = RD4(sc, ETH_CFG); 1041 if (sc->use_rmii) 1042 reg |= ETH_CFG_RMII; 1043 else 1044 reg &= ~ETH_CFG_RMII; 1045 WR4(sc, ETH_CFG, reg); 1046 } else { 1047 /* SAM9 */ 1048 reg = ETHB_UIO_CLKE; 1049 reg |= (sc->use_rmii) ? ETHB_UIO_RMII : 0; 1050 WR4(sc, ETHB_UIO, reg); 1051 } 1052 1053 ate_rxfilter(sc); 1054 1055 /* 1056 * Set the chip MAC address. 1057 */ 1058 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 1059 ate_set_mac(sc, eaddr); 1060 1061 /* Make sure we know state of TX queue */ 1062 sc->txhead = sc->txtail = 0; 1063 if (sc->is_emacb) { 1064 /* Write the descriptor queue address. */ 1065 WR4(sc, ETHB_TBQP, sc->tx_desc_phys); 1066 } 1067 1068 /* 1069 * Turn on MACs and interrupt processing. 1070 */ 1071 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_TE | ETH_CTL_RE); 1072 WR4(sc, ETH_IER, ETH_ISR_RCOM | ETH_ISR_TCOM | ETH_ISR_RBNA); 1073 1074 /* Enable big packets. */ 1075 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 1076 1077 /* 1078 * Set 'running' flag, and clear output active flag 1079 * and attempt to start the output. 1080 */ 1081 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1082 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1083 1084 mii = device_get_softc(sc->miibus); 1085 mii_pollstat(mii); 1086 ate_stat_update(sc, mii->mii_media_active); 1087 atestart_locked(ifp); 1088 1089 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 1090} 1091 1092/* 1093 * Dequeue packets and transmit. 1094 */ 1095static void 1096atestart_locked(struct ifnet *ifp) 1097{ 1098 struct ate_softc *sc = ifp->if_softc; 1099 struct mbuf *m, *mdefrag; 1100 bus_dma_segment_t segs[1]; 1101 int nseg, e; 1102 1103 ATE_ASSERT_LOCKED(sc); 1104 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1105 return; 1106 1107 while (sc->tx_descs[sc->txhead].status & ETHB_TX_USED) { 1108 /* 1109 * Check to see if there's room to put another packet into the 1110 * xmit queue. The old EMAC version has a ping-pong buffer for 1111 * xmit packets. We use OACTIVE to indicate "we can stuff more 1112 * into our buffers (clear) or not (set)." 1113 */ 1114 if (!sc->is_emacb) { 1115 /* RM9200 has only two hardware entries */ 1116 if (!sc->is_emacb && (RD4(sc, ETH_TSR) & ETH_TSR_BNQ) == 0) { 1117 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1118 return; 1119 } 1120 } 1121 1122 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1123 if (m == 0) 1124 break; 1125 1126 e = bus_dmamap_load_mbuf_sg(sc->mtag, sc->tx_map[sc->txhead], m, 1127 segs, &nseg, 0); 1128 if (e == EFBIG) { 1129 mdefrag = m_defrag(m, M_DONTWAIT); 1130 if (mdefrag == NULL) { 1131 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1132 return; 1133 } 1134 m = mdefrag; 1135 e = bus_dmamap_load_mbuf_sg(sc->mtag, 1136 sc->tx_map[sc->txhead], m, segs, &nseg, 0); 1137 } 1138 if (e != 0) { 1139 m_freem(m); 1140 continue; 1141 } 1142 sc->sent_mbuf[sc->txhead] = m; 1143 1144 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txhead], 1145 BUS_DMASYNC_PREWRITE); 1146 1147 /* Tell the hardware to xmit the packet. */ 1148 if (!sc->is_emacb) { 1149 WR4(sc, ETH_TAR, segs[0].ds_addr); 1150 BARRIER(sc, ETH_TAR, 4, BUS_SPACE_BARRIER_WRITE); 1151 WR4(sc, ETH_TCR, segs[0].ds_len); 1152 } else { 1153 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, 1154 BUS_DMASYNC_POSTWRITE); 1155 sc->tx_descs[sc->txhead].addr = segs[0].ds_addr; 1156 sc->tx_descs[sc->txhead].status = segs[0].ds_len | 1157 (sc->tx_descs[sc->txhead].status & ETHB_TX_WRAP) | 1158 ETHB_TX_BUF_LAST; 1159 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, 1160 BUS_DMASYNC_PREWRITE); 1161 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETHB_CTL_TGO); 1162 } 1163 sc->txhead = NEXT_TX_IDX(sc, sc->txhead); 1164 1165 /* Tap off here if there is a bpf listener. */ 1166 BPF_MTAP(ifp, m); 1167 } 1168 1169 if ((sc->tx_descs[sc->txhead].status & ETHB_TX_USED) == 0) 1170 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1171} 1172 1173static void 1174ateinit(void *xsc) 1175{ 1176 struct ate_softc *sc = xsc; 1177 1178 ATE_LOCK(sc); 1179 ateinit_locked(sc); 1180 ATE_UNLOCK(sc); 1181} 1182 1183static void 1184atestart(struct ifnet *ifp) 1185{ 1186 struct ate_softc *sc = ifp->if_softc; 1187 1188 ATE_LOCK(sc); 1189 atestart_locked(ifp); 1190 ATE_UNLOCK(sc); 1191} 1192 1193/* 1194 * Turn off interrupts, and stop the NIC. Can be called with sc->ifp NULL, 1195 * so be careful. 1196 */ 1197static void 1198atestop(struct ate_softc *sc) 1199{ 1200 struct ifnet *ifp; 1201 int i; 1202 1203 ATE_ASSERT_LOCKED(sc); 1204 ifp = sc->ifp; 1205 if (ifp) { 1206 //ifp->if_timer = 0; 1207 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1208 } 1209 1210 callout_stop(&sc->tick_ch); 1211 1212 /* 1213 * Enable some parts of the MAC that are needed always (like the 1214 * MII bus. This turns off the RE and TE bits, which will remain 1215 * off until ateinit() is called to turn them on. With RE and TE 1216 * turned off, there's no DMA to worry about after this write. 1217 */ 1218 WR4(sc, ETH_CTL, ETH_CTL_MPE); 1219 1220 /* 1221 * Turn off all the configured options and revert to defaults. 1222 */ 1223 1224 /* Make sure thate the MDIO clk is less than 1225 * 2.5 Mhz. Can no longer default to /32 since 1226 * SAM9 family may have MCK > 80 Mhz */ 1227 if (at91_master_clock <= 2000000) 1228 WR4(sc, ETH_CFG, ETH_CFG_CLK_8); 1229 else if (at91_master_clock <= 4000000) 1230 WR4(sc, ETH_CFG, ETH_CFG_CLK_16); 1231 else if (at91_master_clock <= 800000) 1232 WR4(sc, ETH_CFG, ETH_CFG_CLK_32); 1233 else 1234 WR4(sc, ETH_CFG, ETH_CFG_CLK_64); 1235 1236 /* 1237 * Turn off all the interrupts, and ack any pending ones by reading 1238 * the ISR. 1239 */ 1240 WR4(sc, ETH_IDR, 0xffffffff); 1241 RD4(sc, ETH_ISR); 1242 1243 /* 1244 * Clear out the Transmit and Receiver Status registers of any 1245 * errors they may be reporting 1246 */ 1247 WR4(sc, ETH_TSR, 0xffffffff); 1248 WR4(sc, ETH_RSR, 0xffffffff); 1249 1250 /* Release TX resources. */ 1251 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 1252 if (sc->sent_mbuf[i] != NULL) { 1253 bus_dmamap_sync(sc->mtag, sc->tx_map[i], 1254 BUS_DMASYNC_POSTWRITE); 1255 bus_dmamap_unload(sc->mtag, sc->tx_map[i]); 1256 m_freem(sc->sent_mbuf[i]); 1257 sc->sent_mbuf[i] = NULL; 1258 } 1259 } 1260 1261 /* Turn off transeiver input clock */ 1262 if (sc->is_emacb) 1263 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) & ~ETHB_UIO_CLKE); 1264 1265 /* 1266 * XXX we should power down the EMAC if it isn't in use, after 1267 * putting it into loopback mode. This saves about 400uA according 1268 * to the datasheet. 1269 */ 1270} 1271 1272static void 1273ate_rxfilter(struct ate_softc *sc) 1274{ 1275 struct ifnet *ifp; 1276 uint32_t reg; 1277 int enabled; 1278 1279 KASSERT(sc != NULL, ("[ate, %d]: sc is NULL!", __LINE__)); 1280 ATE_ASSERT_LOCKED(sc); 1281 ifp = sc->ifp; 1282 1283 /* Wipe out old filter settings. */ 1284 reg = RD4(sc, ETH_CFG); 1285 reg &= ~(ETH_CFG_CAF | ETH_CFG_MTI | ETH_CFG_UNI); 1286 reg |= ETH_CFG_NBC; 1287 sc->flags &= ~ATE_FLAG_MULTICAST; 1288 1289 /* Set new parameters. */ 1290 if ((ifp->if_flags & IFF_BROADCAST) != 0) 1291 reg &= ~ETH_CFG_NBC; 1292 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1293 reg |= ETH_CFG_CAF; 1294 } else { 1295 enabled = ate_setmcast(sc); 1296 if (enabled != 0) { 1297 reg |= ETH_CFG_MTI; 1298 sc->flags |= ATE_FLAG_MULTICAST; 1299 } 1300 } 1301 WR4(sc, ETH_CFG, reg); 1302} 1303 1304static int 1305ateioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1306{ 1307 struct ate_softc *sc = ifp->if_softc; 1308 struct mii_data *mii; 1309 struct ifreq *ifr = (struct ifreq *)data; 1310 int drv_flags, flags; 1311 int mask, error, enabled; 1312 1313 error = 0; 1314 flags = ifp->if_flags; 1315 drv_flags = ifp->if_drv_flags; 1316 switch (cmd) { 1317 case SIOCSIFFLAGS: 1318 ATE_LOCK(sc); 1319 if ((flags & IFF_UP) != 0) { 1320 if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1321 if (((flags ^ sc->if_flags) 1322 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1323 ate_rxfilter(sc); 1324 } else { 1325 if ((sc->flags & ATE_FLAG_DETACHING) == 0) 1326 ateinit_locked(sc); 1327 } 1328 } else if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1329 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1330 atestop(sc); 1331 } 1332 sc->if_flags = flags; 1333 ATE_UNLOCK(sc); 1334 break; 1335 1336 case SIOCADDMULTI: 1337 case SIOCDELMULTI: 1338 if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1339 ATE_LOCK(sc); 1340 enabled = ate_setmcast(sc); 1341 if (enabled != (sc->flags & ATE_FLAG_MULTICAST)) 1342 ate_rxfilter(sc); 1343 ATE_UNLOCK(sc); 1344 } 1345 break; 1346 1347 case SIOCSIFMEDIA: 1348 case SIOCGIFMEDIA: 1349 mii = device_get_softc(sc->miibus); 1350 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1351 break; 1352 case SIOCSIFCAP: 1353 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1354 if (mask & IFCAP_VLAN_MTU) { 1355 ATE_LOCK(sc); 1356 if (ifr->ifr_reqcap & IFCAP_VLAN_MTU) { 1357 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 1358 ifp->if_capenable |= IFCAP_VLAN_MTU; 1359 } else { 1360 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_BIG); 1361 ifp->if_capenable &= ~IFCAP_VLAN_MTU; 1362 } 1363 ATE_UNLOCK(sc); 1364 } 1365 default: 1366 error = ether_ioctl(ifp, cmd, data); 1367 break; 1368 } 1369 return (error); 1370} 1371 1372static void 1373ate_child_detached(device_t dev, device_t child) 1374{ 1375 struct ate_softc *sc; 1376 1377 sc = device_get_softc(dev); 1378 if (child == sc->miibus) 1379 sc->miibus = NULL; 1380} 1381 1382/* 1383 * MII bus support routines. 1384 */ 1385static int 1386ate_miibus_readreg(device_t dev, int phy, int reg) 1387{ 1388 struct ate_softc *sc; 1389 int val; 1390 1391 /* 1392 * XXX if we implement agressive power savings, then we need 1393 * XXX to make sure that the clock to the emac is on here 1394 */ 1395 1396 sc = device_get_softc(dev); 1397 DELAY(1); /* Hangs w/o this delay really 30.5us atm */ 1398 WR4(sc, ETH_MAN, ETH_MAN_REG_RD(phy, reg)); 1399 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1400 continue; 1401 val = RD4(sc, ETH_MAN) & ETH_MAN_VALUE_MASK; 1402 1403 return (val); 1404} 1405 1406static int 1407ate_miibus_writereg(device_t dev, int phy, int reg, int data) 1408{ 1409 struct ate_softc *sc; 1410 1411 /* 1412 * XXX if we implement agressive power savings, then we need 1413 * XXX to make sure that the clock to the emac is on here 1414 */ 1415 1416 sc = device_get_softc(dev); 1417 WR4(sc, ETH_MAN, ETH_MAN_REG_WR(phy, reg, data)); 1418 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1419 continue; 1420 return (0); 1421} 1422 1423static device_method_t ate_methods[] = { 1424 /* Device interface */ 1425 DEVMETHOD(device_probe, ate_probe), 1426 DEVMETHOD(device_attach, ate_attach), 1427 DEVMETHOD(device_detach, ate_detach), 1428 1429 /* Bus interface */ 1430 DEVMETHOD(bus_child_detached, ate_child_detached), 1431 1432 /* MII interface */ 1433 DEVMETHOD(miibus_readreg, ate_miibus_readreg), 1434 DEVMETHOD(miibus_writereg, ate_miibus_writereg), 1435 1436 { 0, 0 } 1437}; 1438 1439static driver_t ate_driver = { 1440 "ate", 1441 ate_methods, 1442 sizeof(struct ate_softc), 1443}; 1444 1445DRIVER_MODULE(ate, atmelarm, ate_driver, ate_devclass, 0, 0); 1446DRIVER_MODULE(miibus, ate, miibus_driver, miibus_devclass, 0, 0); 1447MODULE_DEPEND(ate, miibus, 1, 1, 1); 1448MODULE_DEPEND(ate, ether, 1, 1, 1); 1449