if_ate.c revision 192063
1/*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26/* TODO 27 * 28 * 1) Turn on the clock in pmc? Turn off? 29 * 2) GPIO initializtion in board setup code. 30 */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: head/sys/arm/at91/if_ate.c 192063 2009-05-13 20:29:53Z stas $"); 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38#include <sys/kernel.h> 39#include <sys/mbuf.h> 40#include <sys/malloc.h> 41#include <sys/module.h> 42#include <sys/rman.h> 43#include <sys/socket.h> 44#include <sys/sockio.h> 45#include <sys/sysctl.h> 46#include <machine/bus.h> 47 48#include <net/ethernet.h> 49#include <net/if.h> 50#include <net/if_arp.h> 51#include <net/if_dl.h> 52#include <net/if_media.h> 53#include <net/if_mib.h> 54#include <net/if_types.h> 55 56#ifdef INET 57#include <netinet/in.h> 58#include <netinet/in_systm.h> 59#include <netinet/in_var.h> 60#include <netinet/ip.h> 61#endif 62 63#include <net/bpf.h> 64#include <net/bpfdesc.h> 65 66#include <dev/mii/mii.h> 67#include <dev/mii/miivar.h> 68#include <arm/at91/if_atereg.h> 69 70#include "miibus_if.h" 71 72#define ATE_MAX_TX_BUFFERS 2 /* We have ping-pong tx buffers */ 73#define ATE_MAX_RX_BUFFERS 64 74 75/* 76 * Driver-specific flags. 77 */ 78#define ATE_FLAG_DETACHING 0x01 79#define ATE_FLAG_MULTICAST 0x02 80 81struct ate_softc 82{ 83 struct ifnet *ifp; /* ifnet pointer */ 84 struct mtx sc_mtx; /* Basically a perimeter lock */ 85 device_t dev; /* Myself */ 86 device_t miibus; /* My child miibus */ 87 struct resource *irq_res; /* IRQ resource */ 88 struct resource *mem_res; /* Memory resource */ 89 struct callout tick_ch; /* Tick callout */ 90 struct ifmib_iso_8802_3 mibdata; /* Stuff for network mgmt */ 91 struct mbuf *sent_mbuf[ATE_MAX_TX_BUFFERS]; /* Sent mbufs */ 92 bus_dma_tag_t mtag; /* bus dma tag for mbufs */ 93 bus_dma_tag_t rxtag; 94 bus_dma_tag_t rx_desc_tag; 95 bus_dmamap_t rx_desc_map; 96 bus_dmamap_t rx_map[ATE_MAX_RX_BUFFERS]; 97 bus_dmamap_t tx_map[ATE_MAX_TX_BUFFERS]; 98 bus_addr_t rx_desc_phys; 99 eth_rx_desc_t *rx_descs; 100 void *rx_buf[ATE_MAX_RX_BUFFERS]; /* RX buffer space */ 101 void *intrhand; /* Interrupt handle */ 102 int flags; 103 int if_flags; 104 int rx_buf_ptr; 105 int txcur; /* Current TX map pointer */ 106 int use_rmii; 107}; 108 109static inline uint32_t 110RD4(struct ate_softc *sc, bus_size_t off) 111{ 112 113 return (bus_read_4(sc->mem_res, off)); 114} 115 116static inline void 117WR4(struct ate_softc *sc, bus_size_t off, uint32_t val) 118{ 119 120 bus_write_4(sc->mem_res, off, val); 121} 122 123static inline void 124BARRIER(struct ate_softc *sc, bus_size_t off, bus_size_t len, int flags) 125{ 126 127 bus_barrier(sc->mem_res, off, len, flags); 128} 129 130#define ATE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 131#define ATE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 132#define ATE_LOCK_INIT(_sc) \ 133 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 134 MTX_NETWORK_LOCK, MTX_DEF) 135#define ATE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 136#define ATE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 137#define ATE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 138 139static devclass_t ate_devclass; 140 141/* 142 * ifnet entry points. 143 */ 144static void ateinit_locked(void *); 145static void atestart_locked(struct ifnet *); 146 147static void ateinit(void *); 148static void atestart(struct ifnet *); 149static void atestop(struct ate_softc *); 150static int ateioctl(struct ifnet * ifp, u_long, caddr_t); 151 152/* 153 * Bus entry points. 154 */ 155static int ate_probe(device_t dev); 156static int ate_attach(device_t dev); 157static int ate_detach(device_t dev); 158static void ate_intr(void *); 159 160/* 161 * Helper routines. 162 */ 163static int ate_activate(device_t dev); 164static void ate_deactivate(struct ate_softc *sc); 165static int ate_ifmedia_upd(struct ifnet *ifp); 166static void ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 167static int ate_get_mac(struct ate_softc *sc, u_char *eaddr); 168static void ate_set_mac(struct ate_softc *sc, u_char *eaddr); 169static void ate_rxfilter(struct ate_softc *sc); 170 171/* 172 * The AT91 family of products has the ethernet called EMAC. However, 173 * it isn't self identifying. It is anticipated that the parent bus 174 * code will take care to only add ate devices where they really are. As 175 * such, we do nothing here to identify the device and just set its name. 176 */ 177static int 178ate_probe(device_t dev) 179{ 180 181 device_set_desc(dev, "EMAC"); 182 return (0); 183} 184 185static int 186ate_attach(device_t dev) 187{ 188 struct ate_softc *sc; 189 struct ifnet *ifp = NULL; 190 struct sysctl_ctx_list *sctx; 191 struct sysctl_oid *soid; 192 u_char eaddr[ETHER_ADDR_LEN]; 193 uint32_t rnd; 194 int rid, err; 195 196 sc = device_get_softc(dev); 197 sc->dev = dev; 198 ATE_LOCK_INIT(sc); 199 200 /* 201 * Allocate resources. 202 */ 203 rid = 0; 204 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 205 RF_ACTIVE); 206 if (sc->mem_res == NULL) { 207 device_printf(dev, "could not allocate memory resources.\n"); 208 err = ENOMEM; 209 goto out; 210 } 211 rid = 0; 212 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 213 RF_ACTIVE); 214 if (sc->irq_res == NULL) { 215 device_printf(dev, "could not allocate interrupt resources.\n"); 216 err = ENOMEM; 217 goto out; 218 } 219 220 err = ate_activate(dev); 221 if (err) 222 goto out; 223 224 sc->use_rmii = (RD4(sc, ETH_CFG) & ETH_CFG_RMII) == ETH_CFG_RMII; 225 226 /* Sysctls */ 227 sctx = device_get_sysctl_ctx(dev); 228 soid = device_get_sysctl_tree(dev); 229 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "rmii", 230 CTLFLAG_RD, &sc->use_rmii, 0, "rmii in use"); 231 232 /* Calling atestop before ifp is set is OK. */ 233 ATE_LOCK(sc); 234 atestop(sc); 235 ATE_UNLOCK(sc); 236 callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 237 238 if ((err = ate_get_mac(sc, eaddr)) != 0) { 239 /* 240 * No MAC address configured. Generate the random one. 241 */ 242 if (bootverbose) 243 device_printf(dev, 244 "Generating random ethernet address.\n"); 245 rnd = arc4random(); 246 247 /* 248 * Set OUI to convenient locally assigned address. 'b' 249 * is 0x62, which has the locally assigned bit set, and 250 * the broadcast/multicast bit clear. 251 */ 252 eaddr[0] = 'b'; 253 eaddr[1] = 's'; 254 eaddr[2] = 'd'; 255 eaddr[3] = (rnd >> 16) & 0xff; 256 eaddr[4] = (rnd >> 8) & 0xff; 257 eaddr[5] = rnd & 0xff; 258 } 259 ate_set_mac(sc, eaddr); 260 261 sc->ifp = ifp = if_alloc(IFT_ETHER); 262 if (mii_phy_probe(dev, &sc->miibus, ate_ifmedia_upd, ate_ifmedia_sts)) { 263 device_printf(dev, "Cannot find my PHY.\n"); 264 err = ENXIO; 265 goto out; 266 } 267 268 ifp->if_softc = sc; 269 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 270 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 271 ifp->if_capabilities |= IFCAP_VLAN_MTU; 272 ifp->if_capenable |= IFCAP_VLAN_MTU; /* The hw bits already set. */ 273 ifp->if_start = atestart; 274 ifp->if_ioctl = ateioctl; 275 ifp->if_init = ateinit; 276 ifp->if_baudrate = 10000000; 277 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 278 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 279 IFQ_SET_READY(&ifp->if_snd); 280 ifp->if_timer = 0; 281 ifp->if_linkmib = &sc->mibdata; 282 ifp->if_linkmiblen = sizeof(sc->mibdata); 283 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 284 sc->if_flags = ifp->if_flags; 285 286 ether_ifattach(ifp, eaddr); 287 288 /* 289 * Activate the interrupt. 290 */ 291 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 292 NULL, ate_intr, sc, &sc->intrhand); 293 if (err) { 294 device_printf(dev, "could not establish interrupt handler.\n"); 295 ether_ifdetach(ifp); 296 goto out; 297 } 298 299out: 300 if (err) 301 ate_detach(dev); 302 return (err); 303} 304 305static int 306ate_detach(device_t dev) 307{ 308 struct ate_softc *sc; 309 struct ifnet *ifp; 310 311 sc = device_get_softc(dev); 312 KASSERT(sc != NULL, ("[ate: %d]: sc is NULL", __LINE__)); 313 ifp = sc->ifp; 314 if (device_is_attached(dev)) { 315 ATE_LOCK(sc); 316 sc->flags |= ATE_FLAG_DETACHING; 317 atestop(sc); 318 ATE_UNLOCK(sc); 319 callout_drain(&sc->tick_ch); 320 ether_ifdetach(ifp); 321 } 322 if (sc->miibus != NULL) { 323 device_delete_child(dev, sc->miibus); 324 sc->miibus = NULL; 325 } 326 bus_generic_detach(sc->dev); 327 ate_deactivate(sc); 328 if (sc->intrhand != NULL) { 329 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 330 sc->intrhand = NULL; 331 } 332 if (ifp != NULL) { 333 if_free(ifp); 334 sc->ifp = NULL; 335 } 336 if (sc->mem_res != NULL) { 337 bus_release_resource(dev, SYS_RES_IOPORT, 338 rman_get_rid(sc->mem_res), sc->mem_res); 339 sc->mem_res = NULL; 340 } 341 if (sc->irq_res != NULL) { 342 bus_release_resource(dev, SYS_RES_IRQ, 343 rman_get_rid(sc->irq_res), sc->irq_res); 344 sc->irq_res = NULL; 345 } 346 ATE_LOCK_DESTROY(sc); 347 return (0); 348} 349 350static void 351ate_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 352{ 353 struct ate_softc *sc; 354 355 if (error != 0) 356 return; 357 sc = (struct ate_softc *)arg; 358 sc->rx_desc_phys = segs[0].ds_addr; 359} 360 361static void 362ate_load_rx_buf(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 363{ 364 struct ate_softc *sc; 365 int i; 366 367 if (error != 0) 368 return; 369 sc = (struct ate_softc *)arg; 370 i = sc->rx_buf_ptr; 371 372 /* 373 * For the last buffer, set the wrap bit so the controller 374 * restarts from the first descriptor. 375 */ 376 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 377 if (i == ATE_MAX_RX_BUFFERS - 1) 378 sc->rx_descs[i].addr = segs[0].ds_addr | ETH_WRAP_BIT; 379 else 380 sc->rx_descs[i].addr = segs[0].ds_addr; 381 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_POSTWRITE); 382 sc->rx_descs[i].status = 0; 383 /* Flush the memory in the mbuf */ 384 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], BUS_DMASYNC_PREREAD); 385} 386 387/* 388 * Compute the multicast filter for this device using the standard 389 * algorithm. I wonder why this isn't in ether somewhere as a lot 390 * of different MAC chips use this method (or the reverse the bits) 391 * method. 392 */ 393static int 394ate_setmcast(struct ate_softc *sc) 395{ 396 uint32_t index; 397 uint32_t mcaf[2]; 398 u_char *af = (u_char *) mcaf; 399 struct ifmultiaddr *ifma; 400 struct ifnet *ifp; 401 402 ifp = sc->ifp; 403 404 if ((ifp->if_flags & IFF_PROMISC) != 0) 405 return (0); 406 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 407 WR4(sc, ETH_HSL, 0xffffffff); 408 WR4(sc, ETH_HSH, 0xffffffff); 409 return (1); 410 } 411 412 /* 413 * Compute the multicast hash. 414 */ 415 mcaf[0] = 0; 416 mcaf[1] = 0; 417 IF_ADDR_LOCK(ifp); 418 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 419 if (ifma->ifma_addr->sa_family != AF_LINK) 420 continue; 421 index = ether_crc32_be(LLADDR((struct sockaddr_dl *) 422 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 423 af[index >> 3] |= 1 << (index & 7); 424 } 425 IF_ADDR_UNLOCK(ifp); 426 427 /* 428 * Write the hash to the hash register. This card can also 429 * accept unicast packets as well as multicast packets using this 430 * register for easier bridging operations, but we don't take 431 * advantage of that. Locks here are to avoid LOR with the 432 * IF_ADDR_LOCK, but might not be strictly necessary. 433 */ 434 WR4(sc, ETH_HSL, mcaf[0]); 435 WR4(sc, ETH_HSH, mcaf[1]); 436 return (mcaf[0] || mcaf[1]); 437} 438 439static int 440ate_activate(device_t dev) 441{ 442 struct ate_softc *sc; 443 int err, i; 444 445 sc = device_get_softc(dev); 446 447 /* 448 * Allocate DMA tags and maps. 449 */ 450 err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 451 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 452 1, MCLBYTES, 0, busdma_lock_mutex, &sc->sc_mtx, &sc->mtag); 453 if (err != 0) 454 goto errout; 455 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 456 err = bus_dmamap_create(sc->mtag, 0, &sc->tx_map[i]); 457 if (err != 0) 458 goto errout; 459 } 460 461 /* 462 * Allocate DMA tags and maps for RX. 463 */ 464 err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 465 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 466 1, MCLBYTES, 0, busdma_lock_mutex, &sc->sc_mtx, &sc->rxtag); 467 if (err != 0) 468 goto errout; 469 470 /* 471 * DMA tag and map for the RX descriptors. 472 */ 473 err = bus_dma_tag_create(bus_get_dma_tag(dev), sizeof(eth_rx_desc_t), 474 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 475 ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 1, 476 ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 0, busdma_lock_mutex, 477 &sc->sc_mtx, &sc->rx_desc_tag); 478 if (err != 0) 479 goto errout; 480 if (bus_dmamem_alloc(sc->rx_desc_tag, (void **)&sc->rx_descs, 481 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->rx_desc_map) != 0) 482 goto errout; 483 if (bus_dmamap_load(sc->rx_desc_tag, sc->rx_desc_map, 484 sc->rx_descs, ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 485 ate_getaddr, sc, 0) != 0) 486 goto errout; 487 488 /* 489 * Allocate our RX buffers. This chip has a RX structure that's filled 490 * in. 491 */ 492 for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) { 493 sc->rx_buf_ptr = i; 494 if (bus_dmamem_alloc(sc->rxtag, (void **)&sc->rx_buf[i], 495 BUS_DMA_NOWAIT, &sc->rx_map[i]) != 0) 496 goto errout; 497 if (bus_dmamap_load(sc->rxtag, sc->rx_map[i], sc->rx_buf[i], 498 MCLBYTES, ate_load_rx_buf, sc, 0) != 0) 499 goto errout; 500 } 501 sc->rx_buf_ptr = 0; 502 /* Flush the memory for the EMAC rx descriptor. */ 503 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 504 /* Write the descriptor queue address. */ 505 WR4(sc, ETH_RBQP, sc->rx_desc_phys); 506 return (0); 507 508errout: 509 return (ENOMEM); 510} 511 512static void 513ate_deactivate(struct ate_softc *sc) 514{ 515 int i; 516 517 KASSERT(sc != NULL, ("[ate, %d]: sc is NULL!", __LINE__)); 518 if (sc->mtag != NULL) { 519 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 520 if (sc->sent_mbuf[i] != NULL) { 521 bus_dmamap_sync(sc->mtag, sc->tx_map[i], 522 BUS_DMASYNC_POSTWRITE); 523 bus_dmamap_unload(sc->mtag, sc->tx_map[i]); 524 m_freem(sc->sent_mbuf[i]); 525 } 526 bus_dmamap_destroy(sc->mtag, sc->tx_map[i]); 527 sc->sent_mbuf[i] = NULL; 528 sc->tx_map[i] = NULL; 529 } 530 bus_dma_tag_destroy(sc->mtag); 531 } 532 if (sc->rx_desc_tag != NULL) { 533 if (sc->rx_descs != NULL) { 534 if (sc->rx_desc_phys != 0) { 535 bus_dmamap_sync(sc->rx_desc_tag, 536 sc->rx_desc_map, BUS_DMASYNC_POSTREAD); 537 bus_dmamap_unload(sc->rx_desc_tag, 538 sc->rx_desc_map); 539 sc->rx_desc_phys = 0; 540 } 541 } 542 } 543 if (sc->rxtag != NULL) { 544 for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) { 545 if (sc->rx_buf[i] != NULL) { 546 if (sc->rx_descs[i].addr != 0) { 547 bus_dmamap_sync(sc->rxtag, 548 sc->rx_map[i], 549 BUS_DMASYNC_POSTREAD); 550 bus_dmamap_unload(sc->rxtag, 551 sc->rx_map[i]); 552 sc->rx_descs[i].addr = 0; 553 } 554 bus_dmamem_free(sc->rxtag, sc->rx_buf[i], 555 sc->rx_map[i]); 556 sc->rx_buf[i] = NULL; 557 sc->rx_map[i] = NULL; 558 } 559 } 560 bus_dma_tag_destroy(sc->rxtag); 561 } 562 if (sc->rx_desc_tag != NULL) { 563 if (sc->rx_descs != NULL) 564 bus_dmamem_free(sc->rx_desc_tag, sc->rx_descs, 565 sc->rx_desc_map); 566 bus_dma_tag_destroy(sc->rx_desc_tag); 567 sc->rx_descs = NULL; 568 sc->rx_desc_tag = NULL; 569 } 570} 571 572/* 573 * Change media according to request. 574 */ 575static int 576ate_ifmedia_upd(struct ifnet *ifp) 577{ 578 struct ate_softc *sc = ifp->if_softc; 579 struct mii_data *mii; 580 581 mii = device_get_softc(sc->miibus); 582 ATE_LOCK(sc); 583 mii_mediachg(mii); 584 ATE_UNLOCK(sc); 585 return (0); 586} 587 588/* 589 * Notify the world which media we're using. 590 */ 591static void 592ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 593{ 594 struct ate_softc *sc = ifp->if_softc; 595 struct mii_data *mii; 596 597 mii = device_get_softc(sc->miibus); 598 ATE_LOCK(sc); 599 mii_pollstat(mii); 600 ifmr->ifm_active = mii->mii_media_active; 601 ifmr->ifm_status = mii->mii_media_status; 602 ATE_UNLOCK(sc); 603} 604 605static void 606ate_stat_update(struct ate_softc *sc, int active) 607{ 608 uint32_t reg; 609 610 /* 611 * The speed and full/half-duplex state needs to be reflected 612 * in the ETH_CFG register. 613 */ 614 reg = RD4(sc, ETH_CFG); 615 reg &= ~(ETH_CFG_SPD | ETH_CFG_FD); 616 if (IFM_SUBTYPE(active) != IFM_10_T) 617 reg |= ETH_CFG_SPD; 618 if (active & IFM_FDX) 619 reg |= ETH_CFG_FD; 620 WR4(sc, ETH_CFG, reg); 621} 622 623static void 624ate_tick(void *xsc) 625{ 626 struct ate_softc *sc = xsc; 627 struct ifnet *ifp = sc->ifp; 628 struct mii_data *mii; 629 int active; 630 uint32_t c; 631 632 /* 633 * The KB920x boot loader tests ETH_SR & ETH_SR_LINK and will ask 634 * the MII if there's a link if this bit is clear. Not sure if we 635 * should do the same thing here or not. 636 */ 637 ATE_ASSERT_LOCKED(sc); 638 if (sc->miibus != NULL) { 639 mii = device_get_softc(sc->miibus); 640 active = mii->mii_media_active; 641 mii_tick(mii); 642 if (mii->mii_media_status & IFM_ACTIVE && 643 active != mii->mii_media_active) 644 ate_stat_update(sc, mii->mii_media_active); 645 } 646 647 /* 648 * Update the stats as best we can. When we're done, clear 649 * the status counters and start over. We're supposed to read these 650 * registers often enough that they won't overflow. Hopefully 651 * once a second is often enough. Some don't map well to 652 * the dot3Stats mib, so for those we just count them as general 653 * errors. Stats for iframes, ibutes, oframes and obytes are 654 * collected elsewhere. These registers zero on a read to prevent 655 * races. For all the collision stats, also update the collision 656 * stats for the interface. 657 */ 658 sc->mibdata.dot3StatsAlignmentErrors += RD4(sc, ETH_ALE); 659 sc->mibdata.dot3StatsFCSErrors += RD4(sc, ETH_SEQE); 660 c = RD4(sc, ETH_SCOL); 661 ifp->if_collisions += c; 662 sc->mibdata.dot3StatsSingleCollisionFrames += c; 663 c = RD4(sc, ETH_MCOL); 664 sc->mibdata.dot3StatsMultipleCollisionFrames += c; 665 ifp->if_collisions += c; 666 sc->mibdata.dot3StatsSQETestErrors += RD4(sc, ETH_SQEE); 667 sc->mibdata.dot3StatsDeferredTransmissions += RD4(sc, ETH_DTE); 668 c = RD4(sc, ETH_LCOL); 669 sc->mibdata.dot3StatsLateCollisions += c; 670 ifp->if_collisions += c; 671 c = RD4(sc, ETH_ECOL); 672 sc->mibdata.dot3StatsExcessiveCollisions += c; 673 ifp->if_collisions += c; 674 sc->mibdata.dot3StatsCarrierSenseErrors += RD4(sc, ETH_CSE); 675 sc->mibdata.dot3StatsFrameTooLongs += RD4(sc, ETH_ELR); 676 sc->mibdata.dot3StatsInternalMacReceiveErrors += RD4(sc, ETH_DRFC); 677 678 /* 679 * Not sure where to lump these, so count them against the errors 680 * for the interface. 681 */ 682 sc->ifp->if_oerrors += RD4(sc, ETH_TUE); 683 sc->ifp->if_ierrors += RD4(sc, ETH_CDE) + RD4(sc, ETH_RJB) + 684 RD4(sc, ETH_USF); 685 686 /* 687 * Schedule another timeout one second from now. 688 */ 689 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 690} 691 692static void 693ate_set_mac(struct ate_softc *sc, u_char *eaddr) 694{ 695 696 WR4(sc, ETH_SA1L, (eaddr[3] << 24) | (eaddr[2] << 16) | 697 (eaddr[1] << 8) | eaddr[0]); 698 WR4(sc, ETH_SA1H, (eaddr[5] << 8) | (eaddr[4])); 699} 700 701static int 702ate_get_mac(struct ate_softc *sc, u_char *eaddr) 703{ 704 bus_size_t sa_low_reg[] = { ETH_SA1L, ETH_SA2L, ETH_SA3L, ETH_SA4L }; 705 bus_size_t sa_high_reg[] = { ETH_SA1H, ETH_SA2H, ETH_SA3H, ETH_SA4H }; 706 uint32_t low, high; 707 int i; 708 709 /* 710 * The boot loader setup the MAC with an address, if one is set in 711 * the loader. Grab one MAC address from the SA[1-4][HL] registers. 712 */ 713 for (i = 0; i < 4; i++) { 714 low = RD4(sc, sa_low_reg[i]); 715 high = RD4(sc, sa_high_reg[i]); 716 if ((low | (high & 0xffff)) != 0) { 717 eaddr[0] = low & 0xff; 718 eaddr[1] = (low >> 8) & 0xff; 719 eaddr[2] = (low >> 16) & 0xff; 720 eaddr[3] = (low >> 24) & 0xff; 721 eaddr[4] = high & 0xff; 722 eaddr[5] = (high >> 8) & 0xff; 723 return (0); 724 } 725 } 726 return (ENXIO); 727} 728 729static void 730ate_intr(void *xsc) 731{ 732 struct ate_softc *sc = xsc; 733 struct ifnet *ifp = sc->ifp; 734 struct mbuf *mb; 735 void *bp; 736 uint32_t status, reg, rx_stat; 737 int i; 738 739 status = RD4(sc, ETH_ISR); 740 if (status == 0) 741 return; 742 if (status & ETH_ISR_RCOM) { 743 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 744 BUS_DMASYNC_POSTREAD); 745 while (sc->rx_descs[sc->rx_buf_ptr].addr & ETH_CPU_OWNER) { 746 i = sc->rx_buf_ptr; 747 sc->rx_buf_ptr = (i + 1) % ATE_MAX_RX_BUFFERS; 748 bp = sc->rx_buf[i]; 749 rx_stat = sc->rx_descs[i].status; 750 if ((rx_stat & ETH_LEN_MASK) == 0) { 751 if (bootverbose) 752 device_printf(sc->dev, "ignoring bogus zero-length packet\n"); 753 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 754 BUS_DMASYNC_PREWRITE); 755 sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 756 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 757 BUS_DMASYNC_POSTWRITE); 758 continue; 759 } 760 /* Flush memory for mbuf so we don't get stale bytes */ 761 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 762 BUS_DMASYNC_POSTREAD); 763 WR4(sc, ETH_RSR, RD4(sc, ETH_RSR)); 764 765 /* 766 * The length returned by the device includes the 767 * ethernet CRC calculation for the packet, but 768 * ifnet drivers are supposed to discard it. 769 */ 770 mb = m_devget(sc->rx_buf[i], 771 (rx_stat & ETH_LEN_MASK) - ETHER_CRC_LEN, 772 ETHER_ALIGN, ifp, NULL); 773 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 774 BUS_DMASYNC_PREWRITE); 775 sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 776 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 777 BUS_DMASYNC_POSTWRITE); 778 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 779 BUS_DMASYNC_PREREAD); 780 if (mb != NULL) { 781 ifp->if_ipackets++; 782 (*ifp->if_input)(ifp, mb); 783 } 784 785 } 786 } 787 if (status & ETH_ISR_TCOM) { 788 ATE_LOCK(sc); 789 /* XXX TSR register should be cleared */ 790 if (sc->sent_mbuf[0]) { 791 bus_dmamap_sync(sc->mtag, sc->tx_map[0], 792 BUS_DMASYNC_POSTWRITE); 793 bus_dmamap_unload(sc->mtag, sc->tx_map[0]); 794 m_freem(sc->sent_mbuf[0]); 795 ifp->if_opackets++; 796 sc->sent_mbuf[0] = NULL; 797 } 798 if (sc->sent_mbuf[1]) { 799 if (RD4(sc, ETH_TSR) & ETH_TSR_IDLE) { 800 bus_dmamap_sync(sc->mtag, sc->tx_map[1], 801 BUS_DMASYNC_POSTWRITE); 802 bus_dmamap_unload(sc->mtag, sc->tx_map[1]); 803 m_freem(sc->sent_mbuf[1]); 804 ifp->if_opackets++; 805 sc->txcur = 0; 806 sc->sent_mbuf[0] = sc->sent_mbuf[1] = NULL; 807 } else { 808 sc->sent_mbuf[0] = sc->sent_mbuf[1]; 809 sc->sent_mbuf[1] = NULL; 810 sc->txcur = 1; 811 } 812 } else { 813 sc->sent_mbuf[0] = NULL; 814 sc->txcur = 0; 815 } 816 /* 817 * We're no longer busy, so clear the busy flag and call the 818 * start routine to xmit more packets. 819 */ 820 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 821 atestart_locked(sc->ifp); 822 ATE_UNLOCK(sc); 823 } 824 if (status & ETH_ISR_RBNA) { 825 /* Workaround Errata #11 */ 826 if (bootverbose) 827 device_printf(sc->dev, "RBNA workaround\n"); 828 reg = RD4(sc, ETH_CTL); 829 WR4(sc, ETH_CTL, reg & ~ETH_CTL_RE); 830 BARRIER(sc, ETH_CTL, 4, BUS_SPACE_BARRIER_WRITE); 831 WR4(sc, ETH_CTL, reg | ETH_CTL_RE); 832 } 833} 834 835/* 836 * Reset and initialize the chip. 837 */ 838static void 839ateinit_locked(void *xsc) 840{ 841 struct ate_softc *sc = xsc; 842 struct ifnet *ifp = sc->ifp; 843 struct mii_data *mii; 844 uint32_t reg; 845 846 ATE_ASSERT_LOCKED(sc); 847 848 /* 849 * XXX TODO(3) 850 * we need to turn on the EMAC clock in the pmc. With the 851 * default boot loader, this is already turned on. However, we 852 * need to think about how best to turn it on/off as the interface 853 * is brought up/down, as well as dealing with the mii bus... 854 * 855 * We also need to multiplex the pins correctly. 856 */ 857 858 /* 859 * There are two different ways that the mii bus is connected 860 * to this chip. Select the right one based on a compile-time 861 * option. 862 */ 863 reg = RD4(sc, ETH_CFG); 864 if (sc->use_rmii) 865 reg |= ETH_CFG_RMII; 866 else 867 reg &= ~ETH_CFG_RMII; 868 WR4(sc, ETH_CFG, reg); 869 870 ate_rxfilter(sc); 871 872 /* 873 * Turn on MACs and interrupt processing. 874 */ 875 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_TE | ETH_CTL_RE); 876 WR4(sc, ETH_IER, ETH_ISR_RCOM | ETH_ISR_TCOM | ETH_ISR_RBNA); 877 878 /* 879 * Boot loader fills in MAC address. If that's not the case, then 880 * we should set SA1L and SA1H here to the appropriate value. Note: 881 * the byte order is big endian, not little endian, so we have some 882 * swapping to do. Again, if we need it (which I don't think we do). 883 */ 884 885 /* Enable big packets. */ 886 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 887 888 /* 889 * Set 'running' flag, and clear output active flag 890 * and attempt to start the output. 891 */ 892 ifp->if_drv_flags |= IFF_DRV_RUNNING; 893 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 894 895 mii = device_get_softc(sc->miibus); 896 mii_pollstat(mii); 897 ate_stat_update(sc, mii->mii_media_active); 898 atestart_locked(ifp); 899 900 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 901} 902 903/* 904 * Dequeue packets and transmit. 905 */ 906static void 907atestart_locked(struct ifnet *ifp) 908{ 909 struct ate_softc *sc = ifp->if_softc; 910 struct mbuf *m, *mdefrag; 911 bus_dma_segment_t segs[1]; 912 int nseg, e; 913 914 ATE_ASSERT_LOCKED(sc); 915 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 916 return; 917 918 while (sc->txcur < ATE_MAX_TX_BUFFERS) { 919 /* 920 * Check to see if there's room to put another packet into the 921 * xmit queue. The EMAC chip has a ping-pong buffer for xmit 922 * packets. We use OACTIVE to indicate "we can stuff more into 923 * our buffers (clear) or not (set)." 924 */ 925 if (!(RD4(sc, ETH_TSR) & ETH_TSR_BNQ)) { 926 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 927 return; 928 } 929 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 930 if (m == 0) { 931 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 932 return; 933 } 934 e = bus_dmamap_load_mbuf_sg(sc->mtag, sc->tx_map[sc->txcur], m, 935 segs, &nseg, 0); 936 if (e == EFBIG) { 937 mdefrag = m_defrag(m, M_DONTWAIT); 938 if (mdefrag == NULL) { 939 IFQ_DRV_PREPEND(&ifp->if_snd, m); 940 return; 941 } 942 m = mdefrag; 943 e = bus_dmamap_load_mbuf_sg(sc->mtag, 944 sc->tx_map[sc->txcur], m, segs, &nseg, 0); 945 } 946 if (e != 0) { 947 m_freem(m); 948 continue; 949 } 950 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txcur], 951 BUS_DMASYNC_PREWRITE); 952 953 /* 954 * Tell the hardware to xmit the packet. 955 */ 956 WR4(sc, ETH_TAR, segs[0].ds_addr); 957 BARRIER(sc, ETH_TAR, 8, BUS_SPACE_BARRIER_WRITE); 958 WR4(sc, ETH_TCR, segs[0].ds_len); 959 960 /* 961 * Tap off here if there is a bpf listener. 962 */ 963 BPF_MTAP(ifp, m); 964 965 sc->sent_mbuf[sc->txcur] = m; 966 sc->txcur++; 967 } 968} 969 970static void 971ateinit(void *xsc) 972{ 973 struct ate_softc *sc = xsc; 974 975 ATE_LOCK(sc); 976 ateinit_locked(sc); 977 ATE_UNLOCK(sc); 978} 979 980static void 981atestart(struct ifnet *ifp) 982{ 983 struct ate_softc *sc = ifp->if_softc; 984 985 ATE_LOCK(sc); 986 atestart_locked(ifp); 987 ATE_UNLOCK(sc); 988} 989 990/* 991 * Turn off interrupts, and stop the NIC. Can be called with sc->ifp NULL, 992 * so be careful. 993 */ 994static void 995atestop(struct ate_softc *sc) 996{ 997 struct ifnet *ifp; 998 int i; 999 1000 ATE_ASSERT_LOCKED(sc); 1001 ifp = sc->ifp; 1002 if (ifp) { 1003 ifp->if_timer = 0; 1004 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1005 } 1006 1007 callout_stop(&sc->tick_ch); 1008 1009 /* 1010 * Enable some parts of the MAC that are needed always (like the 1011 * MII bus. This turns off the RE and TE bits, which will remain 1012 * off until ateinit() is called to turn them on. With RE and TE 1013 * turned off, there's no DMA to worry about after this write. 1014 */ 1015 WR4(sc, ETH_CTL, ETH_CTL_MPE); 1016 1017 /* 1018 * Turn off all the configured options and revert to defaults. 1019 */ 1020 WR4(sc, ETH_CFG, ETH_CFG_CLK_32); 1021 1022 /* 1023 * Turn off all the interrupts, and ack any pending ones by reading 1024 * the ISR. 1025 */ 1026 WR4(sc, ETH_IDR, 0xffffffff); 1027 RD4(sc, ETH_ISR); 1028 1029 /* 1030 * Clear out the Transmit and Receiver Status registers of any 1031 * errors they may be reporting 1032 */ 1033 WR4(sc, ETH_TSR, 0xffffffff); 1034 WR4(sc, ETH_RSR, 0xffffffff); 1035 1036 /* 1037 * Release TX resources. 1038 */ 1039 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 1040 if (sc->sent_mbuf[i] != NULL) { 1041 bus_dmamap_sync(sc->mtag, sc->tx_map[i], 1042 BUS_DMASYNC_POSTWRITE); 1043 bus_dmamap_unload(sc->mtag, sc->tx_map[i]); 1044 m_freem(sc->sent_mbuf[i]); 1045 sc->sent_mbuf[i] = NULL; 1046 } 1047 } 1048 1049 /* 1050 * XXX we should power down the EMAC if it isn't in use, after 1051 * putting it into loopback mode. This saves about 400uA according 1052 * to the datasheet. 1053 */ 1054} 1055 1056static void 1057ate_rxfilter(struct ate_softc *sc) 1058{ 1059 struct ifnet *ifp; 1060 uint32_t reg; 1061 int enabled; 1062 1063 KASSERT(sc != NULL, ("[ate, %d]: sc is NULL!", __LINE__)); 1064 ATE_ASSERT_LOCKED(sc); 1065 ifp = sc->ifp; 1066 1067 /* 1068 * Wipe out old filter settings. 1069 */ 1070 reg = RD4(sc, ETH_CFG); 1071 reg &= ~(ETH_CFG_CAF | ETH_CFG_MTI | ETH_CFG_UNI); 1072 reg |= ETH_CFG_NBC; 1073 sc->flags &= ~ATE_FLAG_MULTICAST; 1074 1075 /* 1076 * Set new parameters. 1077 */ 1078 if ((ifp->if_flags & IFF_BROADCAST) != 0) 1079 reg &= ~ETH_CFG_NBC; 1080 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1081 reg |= ETH_CFG_CAF; 1082 } else { 1083 enabled = ate_setmcast(sc); 1084 if (enabled != 0) { 1085 reg |= ETH_CFG_MTI; 1086 sc->flags |= ATE_FLAG_MULTICAST; 1087 } 1088 } 1089 WR4(sc, ETH_CFG, reg); 1090} 1091 1092static int 1093ateioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1094{ 1095 struct ate_softc *sc = ifp->if_softc; 1096 struct mii_data *mii; 1097 struct ifreq *ifr = (struct ifreq *)data; 1098 int drv_flags, flags; 1099 int mask, error, enabled; 1100 1101 error = 0; 1102 flags = ifp->if_flags; 1103 drv_flags = ifp->if_drv_flags; 1104 switch (cmd) { 1105 case SIOCSIFFLAGS: 1106 ATE_LOCK(sc); 1107 if ((flags & IFF_UP) != 0) { 1108 if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1109 if (((flags ^ sc->if_flags) 1110 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1111 ate_rxfilter(sc); 1112 } else { 1113 if ((sc->flags & ATE_FLAG_DETACHING) == 0) 1114 ateinit_locked(sc); 1115 } 1116 } else if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1117 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1118 atestop(sc); 1119 } 1120 sc->if_flags = flags; 1121 ATE_UNLOCK(sc); 1122 break; 1123 1124 case SIOCADDMULTI: 1125 case SIOCDELMULTI: 1126 if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1127 ATE_LOCK(sc); 1128 enabled = ate_setmcast(sc); 1129 if (enabled != (sc->flags & ATE_FLAG_MULTICAST)) 1130 ate_rxfilter(sc); 1131 ATE_UNLOCK(sc); 1132 } 1133 break; 1134 1135 case SIOCSIFMEDIA: 1136 case SIOCGIFMEDIA: 1137 mii = device_get_softc(sc->miibus); 1138 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1139 break; 1140 case SIOCSIFCAP: 1141 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1142 if (mask & IFCAP_VLAN_MTU) { 1143 ATE_LOCK(sc); 1144 if (ifr->ifr_reqcap & IFCAP_VLAN_MTU) { 1145 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 1146 ifp->if_capenable |= IFCAP_VLAN_MTU; 1147 } else { 1148 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_BIG); 1149 ifp->if_capenable &= ~IFCAP_VLAN_MTU; 1150 } 1151 ATE_UNLOCK(sc); 1152 } 1153 default: 1154 error = ether_ioctl(ifp, cmd, data); 1155 break; 1156 } 1157 return (error); 1158} 1159 1160static void 1161ate_child_detached(device_t dev, device_t child) 1162{ 1163 struct ate_softc *sc; 1164 1165 sc = device_get_softc(dev); 1166 if (child == sc->miibus) 1167 sc->miibus = NULL; 1168} 1169 1170/* 1171 * MII bus support routines. 1172 */ 1173static int 1174ate_miibus_readreg(device_t dev, int phy, int reg) 1175{ 1176 struct ate_softc *sc; 1177 int val; 1178 1179 /* 1180 * XXX if we implement agressive power savings, then we need 1181 * XXX to make sure that the clock to the emac is on here 1182 */ 1183 1184 sc = device_get_softc(dev); 1185 DELAY(1); /* Hangs w/o this delay really 30.5us atm */ 1186 WR4(sc, ETH_MAN, ETH_MAN_REG_RD(phy, reg)); 1187 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1188 continue; 1189 val = RD4(sc, ETH_MAN) & ETH_MAN_VALUE_MASK; 1190 1191 return (val); 1192} 1193 1194static void 1195ate_miibus_writereg(device_t dev, int phy, int reg, int data) 1196{ 1197 struct ate_softc *sc; 1198 1199 /* 1200 * XXX if we implement agressive power savings, then we need 1201 * XXX to make sure that the clock to the emac is on here 1202 */ 1203 1204 sc = device_get_softc(dev); 1205 WR4(sc, ETH_MAN, ETH_MAN_REG_WR(phy, reg, data)); 1206 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1207 continue; 1208 return; 1209} 1210 1211static device_method_t ate_methods[] = { 1212 /* Device interface */ 1213 DEVMETHOD(device_probe, ate_probe), 1214 DEVMETHOD(device_attach, ate_attach), 1215 DEVMETHOD(device_detach, ate_detach), 1216 1217 /* Bus interface */ 1218 DEVMETHOD(bus_child_detached, ate_child_detached), 1219 1220 /* MII interface */ 1221 DEVMETHOD(miibus_readreg, ate_miibus_readreg), 1222 DEVMETHOD(miibus_writereg, ate_miibus_writereg), 1223 1224 { 0, 0 } 1225}; 1226 1227static driver_t ate_driver = { 1228 "ate", 1229 ate_methods, 1230 sizeof(struct ate_softc), 1231}; 1232 1233DRIVER_MODULE(ate, atmelarm, ate_driver, ate_devclass, 0, 0); 1234DRIVER_MODULE(miibus, ate, miibus_driver, miibus_devclass, 0, 0); 1235MODULE_DEPEND(ate, miibus, 1, 1, 1); 1236MODULE_DEPEND(ate, ether, 1, 1, 1); 1237