at91sam9x5.c revision 238389 
1/*-
2 * Copyright (c) 2005 Olivier Houchard.  All rights reserved.
3 * Copyright (c) 2010 Greg Ansley.  All rights reserved.
4 * Copyright (c) 2012 M. Warner Losh..  All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD: head/sys/arm/at91/at91sam9x25.c 238389 2012-07-12 02:58:45Z imp $");
30
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/bus.h>
34#include <sys/kernel.h>
35#include <sys/malloc.h>
36#include <sys/module.h>
37
38#include <machine/bus.h>
39
40#include <arm/at91/at91var.h>
41#include <arm/at91/at91reg.h>
42#include <arm/at91/at91soc.h>
43#include <arm/at91/at91_aicreg.h>
44#include <arm/at91/at91sam9x25reg.h>
45#include <arm/at91/at91_pitreg.h>
46#include <arm/at91/at91_pmcreg.h>
47#include <arm/at91/at91_pmcvar.h>
48#include <arm/at91/at91_rstreg.h>
49
50struct at91sam9x25_softc {
51	device_t dev;
52	bus_space_tag_t sc_st;
53	bus_space_handle_t sc_sh;
54};
55
56/*
57 * Standard priority levels for the system.  0 is lowest and 7 is highest.
58 * These values are the ones Atmel uses for its Linux port
59 */
60static const int at91_irq_prio[32] =
61{
62	7,	/* Advanced Interrupt Controller (FIQ) */
63	7,	/* System Peripherals */
64	1,	/* Parallel IO Controller A and B */
65	1,	/* Parallel IO Controller C and D */
66	4,	/* Soft Modem */
67	5,	/* USART 0 */
68	5,	/* USART 1 */
69	5,	/* USART 2 */
70	5,	/* USART 3 */
71	6,	/* Two-Wire Interface 0 */
72	6,	/* Two-Wire Interface 1 */
73	6,	/* Two-Wire Interface 2 */
74	0,	/* Multimedia Card Interface 0 */
75	5,	/* Serial Peripheral Interface 0 */
76	5,	/* Serial Peripheral Interface 1 */
77	5,	/* UART 0 */
78	5,	/* UART 1 */
79	0,	/* Timer Counter 0, 1, 2, 3, 4 and 5 */
80	0,	/* Pulse Width Modulation Controller */
81	0,	/* ADC Controller */
82	0,	/* DMA Controller 0 */
83	0,	/* DMA Controller 1 */
84	2,	/* USB Host High Speed port */
85	2,	/* USB Device High speed port */
86	3,	/* Ethernet MAC 0 */
87	3,	/* LDC Controller or Image Sensor Interface */
88	0,	/* Multimedia Card Interface 1 */
89	3,	/* Ethernet MAC 1 */
90	4,	/* Synchronous Serial Interface */
91	4,	/* CAN Controller 0 */
92	4,	/* CAN Controller 1 */
93	0,	/* Advanced Interrupt Controller (IRQ0) */
94};
95
96#define DEVICE(_name, _id, _unit)		\
97	{					\
98		_name, _unit,			\
99		AT91SAM9X25_ ## _id ##_BASE,	\
100		AT91SAM9X25_ ## _id ## _SIZE,	\
101		AT91SAM9X25_IRQ_ ## _id		\
102	}
103
104static const struct cpu_devs at91_devs[] =
105{
106	DEVICE("at91_pmc", PMC,  0),
107	DEVICE("at91_wdt", WDT,  0),
108	DEVICE("at91_rst", RSTC, 0),
109	DEVICE("at91_pit", PIT,  0),
110	DEVICE("at91_pio", PIOA, 0),
111	DEVICE("at91_pio", PIOB, 1),
112	DEVICE("at91_pio", PIOC, 2),
113	DEVICE("at91_pio", PIOD, 3),
114	DEVICE("at91_twi", TWI0, 0),
115	DEVICE("at91_twi", TWI1, 1),
116	DEVICE("at91_twi", TWI2, 2),
117	DEVICE("at91_mci", HSMCI0, 0),
118	DEVICE("at91_mci", HSMCI1, 1),
119	DEVICE("uart", DBGU,   0),
120	DEVICE("uart", USART0, 1),
121	DEVICE("uart", USART1, 2),
122	DEVICE("uart", USART2, 3),
123	DEVICE("uart", USART3, 4),
124	DEVICE("spi",  SPI0,   0),
125	DEVICE("spi",  SPI1,   1),
126	DEVICE("macb", EMAC0,  0),
127	DEVICE("macb", EMAC1,  0),
128	DEVICE("nand", NAND,   0),
129	DEVICE("ohci", OHCI,   0),
130	DEVICE("ehci", EHCI,   0),
131	{ 0, 0, 0, 0, 0 }
132};
133
134static void
135at91_cpu_add_builtin_children(device_t dev)
136{
137	int i;
138	const struct cpu_devs *walker;
139
140	for (i = 1, walker = at91_devs; walker->name; i++, walker++) {
141		at91_add_child(dev, i, walker->name, walker->unit,
142		    walker->mem_base, walker->mem_len, walker->irq0,
143		    walker->irq1, walker->irq2);
144	}
145}
146
147static uint32_t
148at91_pll_outa(int freq)
149{
150
151	switch (freq / 10000000) {
152		case 747 ... 801: return ((1 << 29) | (0 << 14));
153		case 697 ... 746: return ((1 << 29) | (1 << 14));
154		case 647 ... 696: return ((1 << 29) | (2 << 14));
155		case 597 ... 646: return ((1 << 29) | (3 << 14));
156		case 547 ... 596: return ((1 << 29) | (1 << 14));
157		case 497 ... 546: return ((1 << 29) | (2 << 14));
158		case 447 ... 496: return ((1 << 29) | (3 << 14));
159		case 397 ... 446: return ((1 << 29) | (4 << 14));
160		default: return (1 << 29);
161	}
162}
163
164static uint32_t
165at91_pll_outb(int freq)
166{
167
168	return (0);
169}
170
171static void
172at91_identify(driver_t *drv, device_t parent)
173{
174
175	if (soc_info.type == AT91_T_SAM9X5 && soc_info.subtype == AT91_ST_SAM9X25) {
176		at91_add_child(parent, 0, "at91sam9x25", 0, 0, 0, -1, 0, 0);
177		at91_cpu_add_builtin_children(parent);
178	}
179}
180
181static int
182at91_probe(device_t dev)
183{
184
185	device_set_desc(dev, "AT91SAM9X25");
186	return (0);
187}
188
189static int
190at91_attach(device_t dev)
191{
192	struct at91_pmc_clock *clk;
193	struct at91sam9x25_softc *sc = device_get_softc(dev);
194	struct at91_softc *at91sc = device_get_softc(device_get_parent(dev));
195
196	sc->sc_st = at91sc->sc_st;
197	sc->sc_sh = at91sc->sc_sh;
198	sc->dev = dev;
199
200	/* Update USB device port clock info */
201	clk = at91_pmc_clock_ref("udpck");
202	clk->pmc_mask  = PMC_SCER_UDP_SAM9;
203	at91_pmc_clock_deref(clk);
204
205	/* Update USB host port clock info */
206	clk = at91_pmc_clock_ref("uhpck");
207	clk->pmc_mask  = PMC_SCER_UHP_SAM9;
208	at91_pmc_clock_deref(clk);
209
210	/* Each SOC has different PLL contraints */
211	clk = at91_pmc_clock_ref("plla");
212	clk->pll_min_in    = SAM9X25_PLL_A_MIN_IN_FREQ;		/*   2 MHz */
213	clk->pll_max_in    = SAM9X25_PLL_A_MAX_IN_FREQ;		/*  32 MHz */
214	clk->pll_min_out   = SAM9X25_PLL_A_MIN_OUT_FREQ;	/* 400 MHz */
215	clk->pll_max_out   = SAM9X25_PLL_A_MAX_OUT_FREQ;	/* 800 MHz */
216	clk->pll_mul_shift = SAM9X25_PLL_A_MUL_SHIFT;
217	clk->pll_mul_mask  = SAM9X25_PLL_A_MUL_MASK;
218	clk->pll_div_shift = SAM9X25_PLL_A_DIV_SHIFT;
219	clk->pll_div_mask  = SAM9X25_PLL_A_DIV_MASK;
220	clk->set_outb      = at91_pll_outa;
221	at91_pmc_clock_deref(clk);
222
223	clk = at91_pmc_clock_ref("pllb");
224	clk->pll_min_in    = SAM9X25_PLL_B_MIN_IN_FREQ;		/*   2 MHz */
225	clk->pll_max_in    = SAM9X25_PLL_B_MAX_IN_FREQ;		/*  32 MHz */
226	clk->pll_min_out   = SAM9X25_PLL_B_MIN_OUT_FREQ;	/*  30 MHz */
227	clk->pll_max_out   = SAM9X25_PLL_B_MAX_OUT_FREQ;	/* 100 MHz */
228	clk->pll_mul_shift = SAM9X25_PLL_B_MUL_SHIFT;
229	clk->pll_mul_mask  = SAM9X25_PLL_B_MUL_MASK;
230	clk->pll_div_shift = SAM9X25_PLL_B_DIV_SHIFT;
231	clk->pll_div_mask  = SAM9X25_PLL_B_DIV_MASK;
232	clk->set_outb      = at91_pll_outb;
233	at91_pmc_clock_deref(clk);
234	return (0);
235}
236
237static device_method_t at91sam9x25_methods[] = {
238	DEVMETHOD(device_probe, at91_probe),
239	DEVMETHOD(device_attach, at91_attach),
240	DEVMETHOD(device_identify, at91_identify),
241	{0, 0},
242};
243
244static driver_t at91sam9x25_driver = {
245	"at91sam9x25",
246	at91sam9x25_methods,
247	sizeof(struct at91sam9x25_softc),
248};
249
250static devclass_t at91sam9x25_devclass;
251
252DRIVER_MODULE(at91sam9x25, atmelarm, at91sam9x25_driver, at91sam9x25_devclass, 0, 0);
253
254static struct at91_soc_data soc_data = {
255	.soc_delay = at91_pit_delay,
256	.soc_reset = at91_rst_cpu_reset,
257	.soc_irq_prio = at91_irq_prio,
258};
259
260AT91_SOC_SUB(AT91_T_SAM9X5, AT91_ST_SAM9X25, &soc_data);
261