at91sam9g45.c revision 266087
1/*- 2 * Copyright (c) 2005 Olivier Houchard. All rights reserved. 3 * Copyright (c) 2010 Greg Ansley. All rights reserved. 4 * Copyright (c) 2012 Andrew Turner. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: stable/10/sys/arm/at91/at91sam9g45.c 266087 2014-05-14 20:31:54Z ian $"); 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/bus.h> 34#include <sys/kernel.h> 35#include <sys/malloc.h> 36#include <sys/module.h> 37 38#define _ARM32_BUS_DMA_PRIVATE 39#include <machine/bus.h> 40 41#include <arm/at91/at91var.h> 42#include <arm/at91/at91reg.h> 43#include <arm/at91/at91soc.h> 44#include <arm/at91/at91_aicreg.h> 45#include <arm/at91/at91sam9g45reg.h> 46#include <arm/at91/at91_pitreg.h> 47#include <arm/at91/at91_pmcreg.h> 48#include <arm/at91/at91_pmcvar.h> 49#include <arm/at91/at91_rstreg.h> 50 51/* 52 * Standard priority levels for the system. 0 is lowest and 7 is highest. 53 * These values are the ones Atmel uses for its Linux port 54 */ 55static const int at91_irq_prio[32] = 56{ 57 7, /* Advanced Interrupt Controller */ 58 7, /* System Peripherals */ 59 1, /* Parallel IO Controller A */ 60 1, /* Parallel IO Controller B */ 61 1, /* Parallel IO Controller C */ 62 1, /* Parallel IO Controller D and E */ 63 0, 64 5, /* USART 0 */ 65 5, /* USART 1 */ 66 5, /* USART 2 */ 67 5, /* USART 3 */ 68 0, /* Multimedia Card Interface 0 */ 69 6, /* Two-Wire Interface 0 */ 70 6, /* Two-Wire Interface 1 */ 71 5, /* Serial Peripheral Interface 0 */ 72 5, /* Serial Peripheral Interface 1 */ 73 4, /* Serial Synchronous Controller 0 */ 74 4, /* Serial Synchronous Controller 1 */ 75 0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */ 76 0, /* Pulse Width Modulation Controller */ 77 0, /* Touch Screen Controller */ 78 0, /* DMA Controller */ 79 2, /* USB Host High Speed port */ 80 3, /* LCD Controller */ 81 5, /* AC97 Controller */ 82 3, /* Ethernet */ 83 0, /* Image Sensor Interface */ 84 2, /* USB Device High Speed port */ 85 0, /* (reserved) */ 86 0, /* Multimedia Card Interface 1 */ 87 0, /* (reserved) */ 88 0, /* Advanced Interrupt Controller IRQ0 */ 89}; 90 91static const uint32_t at91_pio_base[] = { 92 AT91SAM9G45_PIOA_BASE, 93 AT91SAM9G45_PIOB_BASE, 94 AT91SAM9G45_PIOC_BASE, 95 AT91SAM9G45_PIOD_BASE, 96 AT91SAM9G45_PIOE_BASE, 97}; 98 99#define DEVICE(_name, _id, _unit) \ 100 { \ 101 _name, _unit, \ 102 AT91SAM9G45_ ## _id ##_BASE, \ 103 AT91SAM9G45_ ## _id ## _SIZE, \ 104 AT91SAM9G45_IRQ_ ## _id \ 105 } 106 107static const struct cpu_devs at91_devs[] = 108{ 109 DEVICE("at91_pmc", PMC, 0), 110 DEVICE("at91_wdt", WDT, 0), 111 DEVICE("at91_rst", RSTC, 0), 112 DEVICE("at91_pit", PIT, 0), 113 DEVICE("at91_pio", PIOA, 0), 114 DEVICE("at91_pio", PIOB, 1), 115 DEVICE("at91_pio", PIOC, 2), 116 DEVICE("at91_pio", PIOD, 3), 117 DEVICE("at91_pio", PIOE, 4), 118 DEVICE("at91_twi", TWI0, 0), 119 DEVICE("at91_twi", TWI1, 1), 120 DEVICE("at91_mci", HSMCI0, 0), 121 DEVICE("at91_mci", HSMCI1, 1), 122 DEVICE("uart", DBGU, 0), 123 DEVICE("uart", USART0, 1), 124 DEVICE("uart", USART1, 2), 125 DEVICE("uart", USART2, 3), 126 DEVICE("uart", USART3, 4), 127 DEVICE("spi", SPI0, 0), 128 DEVICE("spi", SPI1, 1), 129 DEVICE("ate", EMAC, 0), 130 DEVICE("macb", EMAC, 0), 131 DEVICE("nand", NAND, 0), 132 DEVICE("ohci", OHCI, 0), 133 { 0, 0, 0, 0, 0 } 134}; 135 136static void 137at91_clock_init(void) 138{ 139 struct at91_pmc_clock *clk; 140 141 /* Update USB host port clock info */ 142 clk = at91_pmc_clock_ref("uhpck"); 143 clk->pmc_mask = PMC_SCER_UHP_SAM9; 144 at91_pmc_clock_deref(clk); 145 146 /* Each SOC has different PLL contraints */ 147 clk = at91_pmc_clock_ref("plla"); 148 clk->pll_min_in = SAM9G45_PLL_A_MIN_IN_FREQ; /* 2 MHz */ 149 clk->pll_max_in = SAM9G45_PLL_A_MAX_IN_FREQ; /* 32 MHz */ 150 clk->pll_min_out = SAM9G45_PLL_A_MIN_OUT_FREQ; /* 400 MHz */ 151 clk->pll_max_out = SAM9G45_PLL_A_MAX_OUT_FREQ; /* 800 MHz */ 152 clk->pll_mul_shift = SAM9G45_PLL_A_MUL_SHIFT; 153 clk->pll_mul_mask = SAM9G45_PLL_A_MUL_MASK; 154 clk->pll_div_shift = SAM9G45_PLL_A_DIV_SHIFT; 155 clk->pll_div_mask = SAM9G45_PLL_A_DIV_MASK; 156 clk->set_outb = at91_pmc_800mhz_plla_outb; 157 at91_pmc_clock_deref(clk); 158} 159 160static struct at91_soc_data soc_data = { 161 .soc_delay = at91_pit_delay, 162 .soc_reset = at91_rst_cpu_reset, 163 .soc_clock_init = at91_clock_init, 164 .soc_irq_prio = at91_irq_prio, 165 .soc_children = at91_devs, 166 .soc_pio_base = at91_pio_base, 167 .soc_pio_count = nitems(at91_pio_base), 168}; 169 170AT91_SOC(AT91_T_SAM9G45, &soc_data); 171