at91sam9g45.c revision 239190 
1/*-
2 * Copyright (c) 2005 Olivier Houchard.  All rights reserved.
3 * Copyright (c) 2010 Greg Ansley.  All rights reserved.
4 * Copyright (c) 2012 Andrew Turner.  All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD: head/sys/arm/at91/at91sam9g45.c 239190 2012-08-11 05:45:19Z imp $");
30
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/bus.h>
34#include <sys/kernel.h>
35#include <sys/malloc.h>
36#include <sys/module.h>
37
38#define	_ARM32_BUS_DMA_PRIVATE
39#include <machine/bus.h>
40
41#include <arm/at91/at91var.h>
42#include <arm/at91/at91reg.h>
43#include <arm/at91/at91soc.h>
44#include <arm/at91/at91_aicreg.h>
45#include <arm/at91/at91sam9g45reg.h>
46#include <arm/at91/at91_pitreg.h>
47#include <arm/at91/at91_pmcreg.h>
48#include <arm/at91/at91_pmcvar.h>
49#include <arm/at91/at91_rstreg.h>
50
51/*
52 * Standard priority levels for the system.  0 is lowest and 7 is highest.
53 * These values are the ones Atmel uses for its Linux port
54 */
55static const int at91_irq_prio[32] =
56{
57	7,	/* Advanced Interrupt Controller */
58	7,	/* System Peripherals */
59	1,	/* Parallel IO Controller A */
60	1,	/* Parallel IO Controller B */
61	1,	/* Parallel IO Controller C */
62	1,	/* Parallel IO Controller D and E */
63	0,
64	5,	/* USART 0 */
65	5,	/* USART 1 */
66	5,	/* USART 2 */
67	5,	/* USART 3 */
68	0,	/* Multimedia Card Interface 0 */
69	6,	/* Two-Wire Interface 0 */
70	6,	/* Two-Wire Interface 1 */
71	5,	/* Serial Peripheral Interface 0 */
72	5,	/* Serial Peripheral Interface 1 */
73	4,	/* Serial Synchronous Controller 0 */
74	4,	/* Serial Synchronous Controller 1 */
75	0,	/* Timer Counter 0, 1, 2, 3, 4 and 5 */
76	0,	/* Pulse Width Modulation Controller */
77	0,	/* Touch Screen Controller */
78	0,	/* DMA Controller */
79	2,	/* USB Host High Speed port */
80	3,	/* LCD Controller */
81	5,	/* AC97 Controller */
82	3,	/* Ethernet */
83	0,	/* Image Sensor Interface */
84	2,	/* USB Device High Speed port */
85	0,	/* (reserved) */
86	0,	/* Multimedia Card Interface 1 */
87	0,	/* (reserved) */
88	0,	/* Advanced Interrupt Controller IRQ0 */
89};
90
91#define DEVICE(_name, _id, _unit)		\
92	{					\
93		_name, _unit,			\
94		AT91SAM9G45_ ## _id ##_BASE,	\
95		AT91SAM9G45_ ## _id ## _SIZE,	\
96		AT91SAM9G45_IRQ_ ## _id		\
97	}
98
99static const struct cpu_devs at91_devs[] =
100{
101	DEVICE("at91_pmc", PMC,  0),
102	DEVICE("at91_wdt", WDT,  0),
103	DEVICE("at91_rst", RSTC, 0),
104	DEVICE("at91_pit", PIT,  0),
105	DEVICE("at91_pio", PIOA, 0),
106	DEVICE("at91_pio", PIOB, 1),
107	DEVICE("at91_pio", PIOC, 2),
108	DEVICE("at91_pio", PIOD, 3),
109	DEVICE("at91_pio", PIOE, 4),
110	DEVICE("at91_twi", TWI0, 0),
111	DEVICE("at91_twi", TWI1, 1),
112	DEVICE("at91_mci", HSMCI0, 0),
113	DEVICE("at91_mci", HSMCI1, 1),
114	DEVICE("uart", DBGU,   0),
115	DEVICE("uart", USART0, 1),
116	DEVICE("uart", USART1, 2),
117	DEVICE("uart", USART2, 3),
118	DEVICE("uart", USART3, 4),
119	DEVICE("spi",  SPI0,   0),
120	DEVICE("spi",  SPI1,   1),
121	DEVICE("ate",  EMAC,   0),
122	DEVICE("macb", EMAC,   0),
123	DEVICE("nand", NAND,   0),
124	DEVICE("ohci", OHCI,   0),
125	{ 0, 0, 0, 0, 0 }
126};
127
128static void
129at91_clock_init(void)
130{
131	struct at91_pmc_clock *clk;
132
133	/* Update USB host port clock info */
134	clk = at91_pmc_clock_ref("uhpck");
135	clk->pmc_mask  = PMC_SCER_UHP_SAM9;
136	at91_pmc_clock_deref(clk);
137
138	/* Each SOC has different PLL contraints */
139	clk = at91_pmc_clock_ref("plla");
140	clk->pll_min_in    = SAM9G45_PLL_A_MIN_IN_FREQ;		/*   2 MHz */
141	clk->pll_max_in    = SAM9G45_PLL_A_MAX_IN_FREQ;		/*  32 MHz */
142	clk->pll_min_out   = SAM9G45_PLL_A_MIN_OUT_FREQ;	/* 400 MHz */
143	clk->pll_max_out   = SAM9G45_PLL_A_MAX_OUT_FREQ;	/* 800 MHz */
144	clk->pll_mul_shift = SAM9G45_PLL_A_MUL_SHIFT;
145	clk->pll_mul_mask  = SAM9G45_PLL_A_MUL_MASK;
146	clk->pll_div_shift = SAM9G45_PLL_A_DIV_SHIFT;
147	clk->pll_div_mask  = SAM9G45_PLL_A_DIV_MASK;
148	clk->set_outb      = at91_pmc_800mhz_plla_outb;
149	at91_pmc_clock_deref(clk);
150}
151
152static struct at91_soc_data soc_data = {
153	.soc_delay = at91_pit_delay,
154	.soc_reset = at91_rst_cpu_reset,
155	.soc_clock_init = at91_clock_init,
156	.soc_irq_prio = at91_irq_prio,
157	.soc_children = at91_devs,
158};
159
160AT91_SOC(AT91_T_SAM9G45, &soc_data);
161