at91sam9g45.c revision 238788
1238788Sandrew/*- 2238788Sandrew * Copyright (c) 2005 Olivier Houchard. All rights reserved. 3238788Sandrew * Copyright (c) 2010 Greg Ansley. All rights reserved. 4238788Sandrew * Copyright (c) 2012 Andrew Turner. All rights reserved. 5238788Sandrew * 6238788Sandrew * Redistribution and use in source and binary forms, with or without 7238788Sandrew * modification, are permitted provided that the following conditions 8238788Sandrew * are met: 9238788Sandrew * 1. Redistributions of source code must retain the above copyright 10238788Sandrew * notice, this list of conditions and the following disclaimer. 11238788Sandrew * 2. Redistributions in binary form must reproduce the above copyright 12238788Sandrew * notice, this list of conditions and the following disclaimer in the 13238788Sandrew * documentation and/or other materials provided with the distribution. 14238788Sandrew * 15238788Sandrew * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16238788Sandrew * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17238788Sandrew * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18238788Sandrew * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19238788Sandrew * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20238788Sandrew * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21238788Sandrew * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22238788Sandrew * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23238788Sandrew * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24238788Sandrew * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25238788Sandrew * SUCH DAMAGE. 26238788Sandrew */ 27238788Sandrew 28238788Sandrew#include <sys/cdefs.h> 29238788Sandrew__FBSDID("$FreeBSD: head/sys/arm/at91/at91sam9g45.c 238788 2012-07-26 08:01:25Z andrew $"); 30238788Sandrew 31238788Sandrew#include <sys/param.h> 32238788Sandrew#include <sys/systm.h> 33238788Sandrew#include <sys/bus.h> 34238788Sandrew#include <sys/kernel.h> 35238788Sandrew#include <sys/malloc.h> 36238788Sandrew#include <sys/module.h> 37238788Sandrew 38238788Sandrew#define _ARM32_BUS_DMA_PRIVATE 39238788Sandrew#include <machine/bus.h> 40238788Sandrew 41238788Sandrew#include <arm/at91/at91var.h> 42238788Sandrew#include <arm/at91/at91reg.h> 43238788Sandrew#include <arm/at91/at91soc.h> 44238788Sandrew#include <arm/at91/at91_aicreg.h> 45238788Sandrew#include <arm/at91/at91sam9g45reg.h> 46238788Sandrew#include <arm/at91/at91_pitreg.h> 47238788Sandrew#include <arm/at91/at91_pmcreg.h> 48238788Sandrew#include <arm/at91/at91_pmcvar.h> 49238788Sandrew#include <arm/at91/at91_rstreg.h> 50238788Sandrew 51238788Sandrew/* 52238788Sandrew * Standard priority levels for the system. 0 is lowest and 7 is highest. 53238788Sandrew * These values are the ones Atmel uses for its Linux port 54238788Sandrew */ 55238788Sandrewstatic const int at91_irq_prio[32] = 56238788Sandrew{ 57238788Sandrew 7, /* Advanced Interrupt Controller */ 58238788Sandrew 7, /* System Peripherals */ 59238788Sandrew 1, /* Parallel IO Controller A */ 60238788Sandrew 1, /* Parallel IO Controller B */ 61238788Sandrew 1, /* Parallel IO Controller C */ 62238788Sandrew 1, /* Parallel IO Controller D and E */ 63238788Sandrew 0, 64238788Sandrew 5, /* USART 0 */ 65238788Sandrew 5, /* USART 1 */ 66238788Sandrew 5, /* USART 2 */ 67238788Sandrew 5, /* USART 3 */ 68238788Sandrew 0, /* Multimedia Card Interface 0 */ 69238788Sandrew 6, /* Two-Wire Interface 0 */ 70238788Sandrew 6, /* Two-Wire Interface 1 */ 71238788Sandrew 5, /* Serial Peripheral Interface 0 */ 72238788Sandrew 5, /* Serial Peripheral Interface 1 */ 73238788Sandrew 4, /* Serial Synchronous Controller 0 */ 74238788Sandrew 4, /* Serial Synchronous Controller 1 */ 75238788Sandrew 0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */ 76238788Sandrew 0, /* Pulse Width Modulation Controller */ 77238788Sandrew 0, /* Touch Screen Controller */ 78238788Sandrew 0, /* DMA Controller */ 79238788Sandrew 2, /* USB Host High Speed port */ 80238788Sandrew 3, /* LCD Controller */ 81238788Sandrew 5, /* AC97 Controller */ 82238788Sandrew 3, /* Ethernet */ 83238788Sandrew 0, /* Image Sensor Interface */ 84238788Sandrew 2, /* USB Device High Speed port */ 85238788Sandrew 0, /* (reserved) */ 86238788Sandrew 0, /* Multimedia Card Interface 1 */ 87238788Sandrew 0, /* (reserved) */ 88238788Sandrew 0, /* Advanced Interrupt Controller IRQ0 */ 89238788Sandrew}; 90238788Sandrew 91238788Sandrew#define DEVICE(_name, _id, _unit) \ 92238788Sandrew { \ 93238788Sandrew _name, _unit, \ 94238788Sandrew AT91SAM9G45_ ## _id ##_BASE, \ 95238788Sandrew AT91SAM9G45_ ## _id ## _SIZE, \ 96238788Sandrew AT91SAM9G45_IRQ_ ## _id \ 97238788Sandrew } 98238788Sandrew 99238788Sandrewstatic const struct cpu_devs at91_devs[] = 100238788Sandrew{ 101238788Sandrew DEVICE("at91_pmc", PMC, 0), 102238788Sandrew DEVICE("at91_wdt", WDT, 0), 103238788Sandrew DEVICE("at91_rst", RSTC, 0), 104238788Sandrew DEVICE("at91_pit", PIT, 0), 105238788Sandrew DEVICE("at91_pio", PIOA, 0), 106238788Sandrew DEVICE("at91_pio", PIOB, 1), 107238788Sandrew DEVICE("at91_pio", PIOC, 2), 108238788Sandrew DEVICE("at91_pio", PIOD, 3), 109238788Sandrew DEVICE("at91_pio", PIOE, 4), 110238788Sandrew DEVICE("at91_twi", TWI0, 0), 111238788Sandrew DEVICE("at91_twi", TWI1, 1), 112238788Sandrew DEVICE("at91_mci", HSMCI0, 0), 113238788Sandrew DEVICE("at91_mci", HSMCI1, 1), 114238788Sandrew DEVICE("uart", DBGU, 0), 115238788Sandrew DEVICE("uart", USART0, 1), 116238788Sandrew DEVICE("uart", USART1, 2), 117238788Sandrew DEVICE("uart", USART2, 3), 118238788Sandrew DEVICE("uart", USART3, 4), 119238788Sandrew DEVICE("spi", SPI0, 0), 120238788Sandrew DEVICE("spi", SPI1, 1), 121238788Sandrew DEVICE("ate", EMAC, 0), 122238788Sandrew DEVICE("macb", EMAC, 0), 123238788Sandrew DEVICE("nand", NAND, 0), 124238788Sandrew DEVICE("ohci", OHCI, 0), 125238788Sandrew { 0, 0, 0, 0, 0 } 126238788Sandrew}; 127238788Sandrew 128238788Sandrewstatic uint32_t 129238788Sandrewat91_pll_outa(int freq) 130238788Sandrew{ 131238788Sandrew 132238788Sandrew switch (freq / 10000000) { 133238788Sandrew case 747 ... 801: return ((1 << 29) | (0 << 14)); 134238788Sandrew case 697 ... 746: return ((1 << 29) | (1 << 14)); 135238788Sandrew case 647 ... 696: return ((1 << 29) | (2 << 14)); 136238788Sandrew case 597 ... 646: return ((1 << 29) | (3 << 14)); 137238788Sandrew case 547 ... 596: return ((1 << 29) | (4 << 14)); 138238788Sandrew case 497 ... 546: return ((1 << 29) | (5 << 14)); 139238788Sandrew case 447 ... 496: return ((1 << 29) | (6 << 14)); 140238788Sandrew case 397 ... 446: return ((1 << 29) | (7 << 14)); 141238788Sandrew default: return (1 << 29); 142238788Sandrew } 143238788Sandrew} 144238788Sandrew 145238788Sandrewstatic void 146238788Sandrewat91_clock_init(void) 147238788Sandrew{ 148238788Sandrew struct at91_pmc_clock *clk; 149238788Sandrew 150238788Sandrew /* Update USB host port clock info */ 151238788Sandrew clk = at91_pmc_clock_ref("uhpck"); 152238788Sandrew clk->pmc_mask = PMC_SCER_UHP_SAM9; 153238788Sandrew at91_pmc_clock_deref(clk); 154238788Sandrew 155238788Sandrew /* Each SOC has different PLL contraints */ 156238788Sandrew clk = at91_pmc_clock_ref("plla"); 157238788Sandrew clk->pll_min_in = SAM9G45_PLL_A_MIN_IN_FREQ; /* 2 MHz */ 158238788Sandrew clk->pll_max_in = SAM9G45_PLL_A_MAX_IN_FREQ; /* 32 MHz */ 159238788Sandrew clk->pll_min_out = SAM9G45_PLL_A_MIN_OUT_FREQ; /* 400 MHz */ 160238788Sandrew clk->pll_max_out = SAM9G45_PLL_A_MAX_OUT_FREQ; /* 800 MHz */ 161238788Sandrew clk->pll_mul_shift = SAM9G45_PLL_A_MUL_SHIFT; 162238788Sandrew clk->pll_mul_mask = SAM9G45_PLL_A_MUL_MASK; 163238788Sandrew clk->pll_div_shift = SAM9G45_PLL_A_DIV_SHIFT; 164238788Sandrew clk->pll_div_mask = SAM9G45_PLL_A_DIV_MASK; 165238788Sandrew clk->set_outb = at91_pll_outa; 166238788Sandrew at91_pmc_clock_deref(clk); 167238788Sandrew} 168238788Sandrew 169238788Sandrewstatic struct at91_soc_data soc_data = { 170238788Sandrew .soc_delay = at91_pit_delay, 171238788Sandrew .soc_reset = at91_rst_cpu_reset, 172238788Sandrew .soc_clock_init = at91_clock_init, 173238788Sandrew .soc_irq_prio = at91_irq_prio, 174238788Sandrew .soc_children = at91_devs, 175238788Sandrew}; 176238788Sandrew 177238788SandrewAT91_SOC(AT91_T_SAM9G45, &soc_data); 178